HT27LC512(32PLCC-A) [HOLTEK]
Memory IC;
| 型号： | HT27LC512(32PLCC-A) |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Memory IC |
| 文件： | 总14页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT27LC512
CMOS 64K´8-Bit OTP EPROM
Features
·
·
Fast programming algorithm
64K´8-bit organization
·
·
Read access time: 90ns
Single +3.3V power supply
·
·
Programming voltage
Programming time 75ms typ.
·
-
High-reliability CMOS technology
VPP=12.2V±0.2V
-
·
VCC=5.8V±0.2V
Latch-up immunity to 100mA from -1.0V to VCC+1.0V
·
Low power consumption
·
Two line control (OE & CE)
-
Active: 15mA max.
·
Standard product identification code
-
Standby: 1mA typ.
·
Commercial temperature ranges (0°C to +70°C)
·
Fast read access time: 120ns
·
28-pin DIP/SOP/TSOP, 32-pin PLCC package
·
CMOS and TTL compatible I/O
·
Commercial and industrial temperature range
General Description
The HT27LC512 chip family is a low-power, 512K bit,
+3.3V electrically one-time programmable (OTP)
read-only memories (EPROM). Organized into 64K
words with 8 bits per word, it features a fast single ad-
dress location programming, typically at 75ms per byte.
Any byte can be accessed in less than 90ns with respect
to Spec. This eliminates the need for WAIT states in
high-performance microprocessor systems. The
HT27LC512 has separate Output Enable(OE) and Chip
Enable (CE) controls which eliminate bus contention is-
sues.
Block Diagram
R
o
w
C
e
l
l
A
r
r
a
y
X
-
D
e
c
o
d
e
r
A
d
d
r
e
s
s
V
C
C
C
o
l
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n
G
N
D
Y
-
G
a
t
i
n
g
Y
-
D
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o
d
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r
A
d
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s
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C
E
S
A
C
K
T
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E
&
O
E
&
&
O
E
/
V
P
P
P
G
M
&
T
E
S
T
D
Q
0
~
D
Q
7
O
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B
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c
Rev. 1.40
1
December 9, 2003
HT27LC512
Pin Assignment
A
A
1
1
5
1
2
3
4
5
6
7
8
9
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
V
C
C
2
7
6
5
4
3
2
1
0
0
1
2
A
1
4
3
A
A
A
A
A
A
A
A
A
1
A
8
9
1
A
A
1
2
2
1
1
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
0
9
8
O
E
/
V
P
P
2
2
A
C
D
D
D
D
D
G
D
D
D
A
A
A
1
0
O
E
/
V
P
P
2
2
2
2
2
2
1
2
3
4
5
6
7
3
4
5
6
7
8
A
1
1
E
Q
Q
Q
Q
Q
A
A
9
8
7
6
5
4
3
D
2
1
0
A
1
0
A
A
1
1
3
4
C
D
D
D
D
D
E
Q
Q
Q
Q
Q
0
1
2
3
4
7
6
5
4
3
V
C
C
A
A
1
1
5
2
N
D
D
D
Q
Q
Q
Q
Q
Q
A
A
A
A
A
7
6
5
4
3
0
1
2
G
N
D
H
T
2
7
L
C
5
1
2
H
T
2
7
L
C
5
1
2
2
8
D
I
P
-
A
/
S
O
P
-
A
2
8
T
S
O
P
-
A
A
7
A
A
1
1
4
2
2
2
2
2
2
2
2
2
9
8
7
6
5
4
3
2
1
2
9
A
A
A
A
A
A
A
6
5
4
3
2
1
0
5
6
7
8
9
5
A
8
2
8
6
7
8
9
3
A
9
A
A
A
A
A
A
A
6
5
4
3
2
1
0
0
A
8
2
2
2
2
2
2
2
7
6
5
4
3
2
1
A
1
1
A
9
N
C
H
T
2
7
L
C
5
1
2
H
T
2
7
L
C
5
1
2
A
1
1
O
E
/
V
P
P
3
2
P
L
C
C
-
A
3
2
P
L
C
C
-
B
1
1
1
1
0
1
2
3
1
1
1
1
0
1
2
3
O
E
/
V
P
P
A
C
D
D
1
0
A
C
D
1
0
E
Q
Q
N
C
E
7
D
Q
0
D
Q
Q
7
6
Pin Description
Pin Name
A0~A15
DQ0~DQ7
CE
I/O/C/P
Description
I
Address inputs
Data inputs/outputs
Chip enable
I/O
C
OE/VPP
NC
C/P
¾
Output enable/program voltage supply
No connection
Absolute Maximum Ratings
Operation Temperature Commercial..........................................................................................................0°C to +70°C
Storage Temperature.............................................................................................................................-65°C to 125 °C
Applied VCC Voltage with Respect to GND .................................................................................................0.6V to 7.0V
Applied Voltage on Input Pin with Respect to GND ......................................................................................0.6V to 7.0V
Applied Voltage on Output Pin with Respect to GND ...........................................................................0.6V to VCC+0.5V
Applied Voltage on A9 Pin with Respect to GND ........................................................................................0.6V to 13.5V
Applied VPP Voltage with Respect to GND................................................................................................0.6V to 13.5V
Applied READ Voltage (Functionality is guaranteed between these limits) .................................................+3V to +3.6V
Note: These are stress ratings only. Stresses exceeding the range specified under. ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 1.40
2
December 9, 2003
HT27LC512
D.C. Characteristics
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Read Operation
VOH
VOL
VIH
VIL
Output High Level
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
2.4
¾
2.0
0.3
5
V
V
IOH=-0.4mA
¾
¾
¾
¾
¾
¾
¾
1.0
¾
¾
¾
0.45
VCC+0.5
0.8
IOL=2.0mA
Output Low Level
Input High Level
V
¾
¾
Input Low Level
V
ILI
VIN=0 to 3.6V
VOUT=0 to 3.6V
CE=VIL, f=5MHz, IOUT=0mA
Input Leakage Current
Output Leakage Current
VCC Active Current
Standby Current (CMOS)
Standby Current (TTL)
VPP Read/Standby Current
5
mA
mA
mA
mA
mA
mA
ILO
10
¾
¾
¾
¾
10
ICC
ISB1
ISB2
IPP
15
10
CE=VCC±0.3V
CE=VIH
0.6
CE=OE=VIL, VPP=VCC
100
Programming Operation
VOH
VOL
VIH
VIL
ILI
IOH=0.4mA
IOL=2.1mA
Output High Level
Output Low Level
Input High Level
5.8V
5.8V
5.8V
5.8V
5.8V
5.8V
5.8V
5.8V
2.4
V
V
¾
¾
¾
¾
¾
¾
¾
¾
¾
0.45
¾
0.7VCC
V
CC+0.5
0.8
V
¾
¾
Input Low Level
V
-0.5
¾
VIN=VIL, VIH
Input Load Current
A9 Product ID Voltage
VCC Supply Current
VPP Supply Current
5.0
mA
V
VH
11.5
¾
12.5
40
¾
¾
ICC
IPP
Capacitance
mA
mA
CE=VIL
10
¾
CIN
VIN=0V
Input Capacitance
Output Capacitance
VPP Capacitance
3.3V
3.3V
3.3V
8
8
12
12
25
pF
pF
pF
¾
¾
¾
COUT
CVPP
VOUT=0V
VPP=0V
18
A.C. Characteristics
Ta=+25°C±5°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Read Operation
tACC
tCE
CE=OE=VIL
OE=VIL
Address to Output Delay
3.3V
3.3V
90
90
45
ns
ns
ns
¾
¾
¾
¾
¾
¾
Chip Enable to Output Delay
tOE
CE=VIL
Output Enable to Output Delay 3.3V
CE or OE High to Output Float,
3.3V
tDF
40
ns
ns
¾
¾
¾
¾
¾
Whichever Occurred First
Output Hold from Address, CE or
3.3V
tOH
0
¾
OE, Whichever Occurred First
Rev. 1.40
3
December 9, 2003
HT27LC512
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VCC
Programming Operation
tAS
Address Setup Time
CE/VPP Setup Time
OE/VPP Hold Time
Data Setup Time
5.8V
5.8V
5.8V
5.8V
5.8V
5.8V
2
2
2
2
0
2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
ms
ms
ms
ms
ms
ms
tOES
tOEH
tDS
tAH
Address Hold Time
Data Hold Time
tDH
Output Enable to Output Float
Delay
tDFP
5.8V
0
130
ns
¾
¾
tPW
tVCS
tDV
PGM Program Pulse Width
VCC Setup Time
5.8V
5.8V
5.8V
5.8V
30
2
75
¾
¾
¾
105
¾
¾
¾
¾
¾
ms
ms
ns
ms
Data Valid From CE
150
¾
¾
2
tVR
OE/VPP Recovery Time
Test Waveforms and Measurements
2
.
4
V
2
.
0
V
A
M
L
C
A
C
D
r
i
v
i
n
g
e
a
s
u
r
e
m
e
n
t
L
e
v
e
l
s
e
v
e
l
0
.
8
V
0
.
4
5
V
tR, tF< 20ns (10% to 90%)
Output Test Load
1
.
3
V
(
1
N
9
1
4
)
3
.
3
k
O
u
t
p
u
t
P
i
n
C
L
Note: CL=100pF including jig capacitance
Product Identification Code
Pins
Hex
Data
Code
A0
0
A1
1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
Manufacturer
Device Type
0
1
0
0
0
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
0
1
1
1
1C
83
7F
7F
1
1
0
0
Continuation
1
0
Rev. 1.40
4
December 9, 2003
HT27LC512
Functional Description
Operation Mode
All the operation modes are shown in the table following.
Mode
CE
VIL
OE/VPP
VIL
A0
X (2)
X
A9
Output
Dout
Read
X
Output Disable
Standby (TTL)
Standby (CMOS)
Program
VIL
VIH
X
X
High Z
High Z
High Z
DIN
VIH
X
X
X
X
X
V
CC± 0.3V
VIL
VPP
VIL
X
X
Program Verify
Product Inhibit
Manufacturer Code (3)
Device Code (3)
VIL
X
X
DOUT
High Z
1C
VIH
VPP
VIL
X
X
VIL
VIL
VIH
VH (1)
VH (1)
VIL
VIL
83
Note:
(1) VH = 12.0V±0.5V
(2) X=Either VIH or VIL
(3) For Manufacturer Code and Device Code, A1=VIH, When A1=VIL, both codes will read 7F
Programming of the HT27LC512
high-level CE input inhibits the other HT27LC512 from
being programmed.
When the HT27LC512 is delivered, the chip has all
512K bits in the ²ONE² or HIGH state. ²ZEROs² are
loaded into the HT27LC512 through the procedure of
programming.
Program Verify Mode
Verification should be performed on the programmed
bits to determine whether they were correctly pro-
grammed. The verification should be performed with
OE/VPP and CE at VIL. Data should be verified at tDV af-
ter the falling edge of CE.
The programming mode is entered when 12.2±0.2V is
applied to the OE/VPP pin and CE is at VIL. For pro-
gramming, the data to be programmed is applied with 8
bits in parallel to the data pins.
Auto Product Identification
The programming flowchart in Figure 3. shows the fast
interactive programming algorithm. The interactive al-
gorithm reduces programming time by using 30ms to
105ms programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data is
not verified, additional pulses are given until it is verified
or until the maximum number of pulses is reached. This
process is repeated while sequencing through each ad-
dress of the HT27LC512. This part of the programming
algorithm is carried at VCC=5.8V to assure that each
EPROM bit is programmed to a sufficiently high thresh-
old voltage. This ensures that all bits have sufficient
margin. After the final address is completed, the entire
EPROM memory is read at VCC=VPP=3.3±0.3V to verify
the entire memory.
The Auto Product Identification mode allows the reading
out of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for use by
the programming equipment for the purpose of automat-
ically matching the device to be programmed with its
corresponding programming algorithm. This mode is
functional in the 25°C±5°C ambient temperature range
that is required when programming the HT27LC512.
To activate this mode, the programming equipment must
force 12.0±0.5V on the address line A9 of the
HT27LC512. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from VIL to VIH, when A1=VIH. All other address
lines must be held at VIH during Auto Product Identifica-
tion mode.
Byte 0 (A0=VIL) represents the manufacturer code, and
byte 1 (A0=VIH), the device code. For HT27LC512, these
two identifier bytes are shown in the Mode Select Table.
All identifiers for the manufacturer and device codes will
possess odd parity, with the MSB (DQ7) defined as the
parity bit. When A1=VIL, the HT27LC512 will read out the
binary code of 7F, continuation code, to signify the un-
availability of manufacturer ID codes.
Program Inhibit Mode
Programming of multiple HT27LC512 in parallel with dif-
ferent data is also easily accomplished by using the Pro-
gram Inhibit Mode. Except for CE, all like inputs of the
parallel HT27LC512 may be common. A TTL low-level
program pulse applied to an HT27LC512 CE input with
OE/VPP=12.2±0.2V will program that HT27LC512. A
Rev. 1.40
5
December 9, 2003
HT27LC512
·
·
Read Mode
Low memory power consumption
Assurance that output bus contention will not occur.
The HT27LC512 has two control functions, both of
which must be logically satisfied in order to obtain data
at outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and should be used to gate data to
the output pins, independent of device selection. As-
suming that addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE). Data
is available at the outputs (tOE) after the falling edge of
OE, assuming the CE has been LOW and addresses
It is recommended that CE be decoded and used as the
primary device-selection function, while OE be made a
common connection to all devices in the array and con-
nected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the output pins
are only active when data is desired from a particular
memory device.
have been stable for at least tACC-tOE
.
System Considerations
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1mF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VPP to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM ar-
rays, a 4.7mF bulk electrolytic capacitor should be used
between VCC and VPP for each eight devices. The lo-
cation of the capacitor should be close to where the
power supply is connected to the array.
Standby Mode
The HT27LC512 has CMOS standby mode which re-
duces the maximum VCC current to 10mA. It is placed in
CMOS standby when CE is at VCC±0.3V. The
HT27LC512 also has a TTL-standby mode which re-
duces the maximum VCC current to 0.6mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state, inde-
pendent of the OE input.
Two-line Output Control Function
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
A
d
d
r
e
s
s
A
d
d
r
e
s
s
V
a
l
i
d
t
C E
C
E
t
D F
t
O E
O
E
t
A C C
t
O H
O
u
t
p
u
t
V
a
l
i
d
O
u
t
p
u
t
H
I
G
H
Z
Figure 1. A.C. Waveforms for Read Operation
R
e
a
d
P
r
o
g
r
a
m
(
V
e
r
i
f
y
)
V
I
H
A
d
d
r
e
s
s
A
d
d
r
e
s
s
S
t
a
b
l
e
V
I
L
t
A H
t
A
S
t
D V
V
I
H
D
a
t
a
O
u
t
D
a
t
a
I
n
D
a
t
a
V
a
l
i
d
V
I
L
t
D
S
t
D H
5
5
.
.
8
0
V
V
t
D F P
V
C
C
t
V C S
1
2
.
2
V
t
O E S
O
E
/
V
P
P
V
I
L
t
O
E
H
t
P R T
t
V R
V
I
H
C
E
V
I
L
t
P W
Figure 2. Programming Waveforms
Rev. 1.40
6
December 9, 2003
HT27LC512
S
T
A
R
T
A
d
d
r
e
s
s
=
F
i
r
s
t
L
o
c
a
t
i
o
n
V
C
C
= 5 . 8 V
V
P
P
X
=
0
P
r
o
g
r
a
m
o
n
e
7
5
m
s
P
u
l
s
e
I
n
t
e
r
a
c
t
i
v
e
S
e
c
t
i
o
n
I
n
c
r
e
m
e
n
t
X
Y
e
s
X
=
2
5
?
N
o
F
a
i
l
V
e
r
i
f
y
B
y
t
e
?
P
a
s
s
L
a
s
t
F
a
i
l
N
o
I
n
c
r
e
m
e
n
t
A
d
d
r
e
s
s
A
d
d
r
e
s
s
Y
e
s
V
C
C
=
3
.
3
V
V
e
r
i
f
y
S
e
c
t
i
o
n
F
a
i
l
V
e
r
i
f
y
a
l
l
D
e
v
i
c
e
F
a
i
l
e
d
B
y
t
e
s
?
P
a
s
s
D
e
v
i
c
e
P
a
s
s
e
d
N
m
m
Figure 3. Fast Programming Flowchart
Rev. 1.40
7
December 9, 2003
HT27LC512
Package Information
28-pin DIP (600mil) Outline Dimensions
A
2
8
1
5
B
1
1
4
H
C
D
I
a
E
F
G
Dimensions in mil
Nom.
Symbol
Min.
1445
535
145
125
16
Max.
1465
555
155
145
20
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
50
70
¾
100
¾
¾
¾
595
635
0°
615
670
15°
¾
a
¾
Rev. 1.40
8
December 9, 2003
HT27LC512
28-pin SOP (300mil) Outline Dimensions
2
8
1
5
A
B
1
1
4
C
C
'
G
H
D
a
E
F
Dimensions in mil
Nom.
Symbol
Min.
394
290
14
697
92
¾
Max.
419
300
20
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
713
104
¾
4
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.40
9
December 9, 2003
HT27LC512
28-pin TSOP (8´13.4) Outline Dimensions
H
D
1
2
8
q
E
0
.
0
1
0
L
D
e
t
a
i
l
F
1
4
1
5
D
A
2
A
A
1
S
e
e
D
e
t
a
i
l
F
L
1
S
b
e
y
S
e
a
t
i
n
g
P
l
a
n
e
Dimensions in mm
Nom.
Symbol
Min.
¾
Max.
1.25
0.18
1.05
¾
A
A1
A2
b
¾
¾
0.08
0.95
¾
¾
0.20
¾
D
11.70
13.20
7.90
¾
11.90
13.60
8.10
¾
HD
E
¾
¾
e
0.55
0.50
0.8
¾
L
¾
¾
L1
q
¾
¾
0°
5°
Rev. 1.40
10
December 9, 2003
HT27LC512
32-pin PLCC Outline Dimensions
A
B
4
1
3
2
3
0
5
2
9
D
C
1
3
2
1
1
4
2
0
K
E
F
J
G
H
I
Dimensions in mil
Nom.
Symbol
Min.
485
445
585
545
105
¾
Max.
495
455
595
555
115
140
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
15
¾
¾
16
22
J
24
32
K
a
8
12
0°
10°
Rev. 1.40
11
December 9, 2003
HT27LC512
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
B
Reel Outer Diameter
Reel Inner Diameter
330±1.0
62±1.5
13.0+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2.0±0.5
24.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
PLCC 32
Symbol
Description
Dimensions in mm
330±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
62±1.5
13.0+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2.0±0.5
24.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
Rev. 1.40
12
December 9, 2003
HT27LC512
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
24.0±0.3
12.0±0.1
1.75±0.1
11.5±0.1
1.5+0.1
W
P
Carrier Tape Width
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
D1
P0
P1
A0
B0
K0
t
1.5+0.25
4.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
10.85±0.1
18.34±0.1
2.97±0.1
0.35±0.01
21.3
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
PLCC 32
Symbol
Description
Carrier Tape Width
Dimensions in mm
24.0±0.3
W
P
E
F
Cavity Pitch
18.0±0.1
Perforation Position
1.75±0.1
Cavity to Perforation (Width Direction)
Perforation Diameter
11.5±0.1
D
1.5+0.1
1.55+1.0
D1
Cavity Hole Diameter
-0.05
P0
P1
A0
B0
K0
t
Perforation Pitch
4.0±0.1
2.0±0.1
13.1±0.1
15.5±0.1
3.9±0.1
0.30±0.05
21.3
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
Rev. 1.40
13
December 9, 2003
HT27LC512
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor (Hong Kong) Ltd.
Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holmate Semiconductor, Inc.
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2003 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
14
December 9, 2003
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