概述
数据手册HT46C62 概述
A/D with LCD Type 8-Bit MCU A / D with LCD型8位MCU
HT46C62 数据手册
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PDF下载HT46R62/HT46C62
A/D with LCD Type 8-Bit MCU
Technical Document
·
·
·
Tools Information
FAQs
Application Note
-
-
-
-
HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
HA0004E HT48 & HT46 MCU UART Software Implementation Method
HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
HA0047E An PWM application example using the HT46 series of MCUs
Features
·
·
·
·
·
Operating voltage:
Watchdog Timer
f
f
SYS=4MHz: 2.2V~5.5V
SYS=8MHz: 3.3V~5.5V
Buzzer output
On-chip crystal, RC and 32768Hz crystal oscillator
·
20 bidirectional I/O lines
HALT function and wake-up feature reduce power
consumption
(PA, PB0~PB5, PD0~PD2, PD4~PD6)
·
·
Two external interrupt input
·
·
·
·
·
·
·
·
·
·
6-level subroutine nesting
One 8-bit programmable timer/event counter with
PFD (programmable frequency divider) function
6 channels 9-bit resolution A/D converter
3-channel 8-bit PWM output shared with 3 I/O lines
Bit manipulation instruction
·
LCD driver with 20´3 or 19´4 segments
(logical output option for SEG0~SEG15)
16-bit table read instruction
·
·
·
·
·
2K´14 program memory
88´8 data memory RAM
Supports PFD for sound generation
Real Time Clock (RTC)
Up to 0.5ms instruction cycle with 8MHz system clock
63 powerful instructions
All instructions in 1 or 2 machine cycles
Low voltage reset/detector function
52-pin QFP, 56-pin SSOP packages
8-bit prescaler for RTC
General Description
The HT46R62/HT46C62 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D product applications that interface di-
rectly to analog signals and which require LCD Inter-
face. The mask version HT46C62 is fully pin and
functionally compatible with the OTP version HT46R62
device.
Converter, Pulse Width Modulation function, HALT and
wake-up functions, in addition to a flexible and
configurable LCD interface enhance the versatility of
these devices to control a wide range of applications re-
quiring analog signal processing and LCD interfacing,
such as electronic metering, environmental monitoring,
handheld measurement tools, motor driving, etc., for
both industrial and home appliance application areas.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, multi-channel A/D
Rev. 1.60
1
July 14, 2005
HT46R62/HT46C62
Block Diagram
I
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S Y S
P
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C
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3
4
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P
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r
P
P
P
P
D
D
D
D
0
4
5
6
/
/
/
/
P
I
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W
M
0
0
~
P
D
2
/
P
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M
2
P
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P
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A
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A
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B
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P
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B
P
B
0
/
A
N
0
~
P
B
5
/
A
N
5
A
C
C
O
S
C
2
O
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C
1
P
B
O
S
C
4
R
E
S
V
D
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P
A
0
/
/
B
B
Z
Z
L
C
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V
O
S
S
M
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m
o
r
y
P
A
1
P
A
C
P
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t
A
S
C
3
P
A
2
P
A
P
P
A
A
3
4
/
~
P
F
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L
C
D
D
R
I
V
E
R
P
A
7
E
N
/
D
I
S
H
A
L
T
L
V
D
/
L
V
R
C
O
O
M
0
~
C
O
M
3
/
S
S
E
G
0
1
~
C
M
2
S
E
G
1
9
E
G
8
Rev. 1.60
2
July 14, 2005
HT46R62/HT46C62
Pin Assignment
P
P
A
A
0
1
/
/
B
B
Z
Z
R
O
O
V
O
O
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
C
C
C
E
S
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
S
S
C
C
1
2
P
A
2
P
A
3
/
P
F
D
D
D
P
P
P
P
A
A
A
A
4
5
6
7
0
1
2
3
4
5
S
S
C
C
3
4
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
0
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
B
B
B
B
B
B
0
1
2
3
4
5
/
/
/
/
/
/
A
A
A
A
A
A
N
N
N
N
N
N
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
3
3
3
3
3
9
8
7
6
5
4
S
S
S
S
S
S
S
S
S
S
S
S
S
E
E
E
E
E
E
E
E
E
E
E
E
E
G
G
G
G
G
G
G
G
G
G
G
G
G
3
4
5
6
7
8
9
1
1
1
1
1
1
1
2
3
4
5
6
7
8
9
1
1
1
1
P
A
5
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
P
P
A
A
6
7
P
B
0
/
A
N
0
P
B
1
/
A
N
1
P
B
2
/
A
N
2
H
T
4
6
R
6
2
/
H
T
4
6
C
6
2
P
B
3
/
A
N
3
3
3
3
3
2
2
2
3
2
1
0
9
8
7
V
S
S
5
2
Q
F
P
-
A
P
P
B
B
4
5
/
/
A
A
N
N
4
5
0
1
2
3
4
5
P
P
P
D
D
D
0
1
2
/
/
/
P
P
P
4
5
6
W
W
W
M
M
M
0
1
2
0
1
V
S
S
0
1
2
3
0
1
2
3
4
5
6
7
8
P
D
0
/
P
W
M
0
P
P
D
D
1
2
/
/
P
P
W
W
M
M
1
2
P
P
P
D
D
D
/
/
/
I
I
T
N
N
T
T
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
M
R
D
V
L
C
V
M
A
X
V
V
1
2
1
2
0
O
O
O
M
M
M
3
2
1
/
S
E
G
1
9
C
C
C
O
M
H
T
4
6
R
6
2
/
H
T
4
6
C
6
2
5
6
S
S
O
P
-
A
Note: The 52-pin QFP package does not support the charge pump (C type bias) of the LCD. The LCD bias type must
select the R type by option.
Rev. 1.60
3
July 14, 2005
HT46R62/HT46C62
Pin Description
Pin Name
I/O
Options
Description
PA0/BZ
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by option. Software instructions determine the CMOS output or
Schmitt Trigger input with or without pull-high resistor (determined by
pull-high options: bit option). The BZ, BZ and PFD are pin-shared with
PA0, PA1 and PA3, respectively.
Wake-up
Pull-high
Buzzer
PFD
PA1/BZ
PA2
I/O
I/O
PA3/PFD
PA4~PA7
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
Bidirectional 6-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (de-
termined by pull-high option: bit option) or A/D input. Once a PB line is se-
lected as an A/D input (by using software control), the I/O function and
pull-high resistor are disabled automatically.
Pull-high
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (de-
termined by pull-high option: bit option). The PWM0/PWM1/PWM2 output
function are pin-shared with PD0/PD1/PD2 (dependent on PWM options).
PD0/PWM0
PD1/PWM1
PD2/PWM2
Pull-high
PWM
I/O
I/O
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (de-
termined by pull-high option: bit option). The INT0, INT1 and TMR are
pin-shared with PD4/PD5/PD6.
PD4/INT0
PD5/INT1
PD6/TMR
Pull-high
VSS
Negative power supply, ground
LCD power supply
¾
¾
¾
¾
¾
VLCD
I
I
I
VMAX
IC maximum voltage connect to VDD, VLCD or V1
Voltage pump
V1, V2, C1, C2
COM0~COM2
COM3/SEG19
1/2, 1/3 or 1/4 SEG19 can be set as a segment or as a common output driver for LCD
O
O
Duty
panel by options. COM0~COM2 are outputs for LCD panel plate.
LCD driver outputs for LCD panel segments. SEG0~SEG15 can be
optioned as logical outputs.
SEG0~SEG18
Logical Output
OSC1 and OSC2 are connected to an RC network or a crystal (by options)
for the internal system clock. In the case of RC operation, OSC2 is the out-
OSC1
OSC2
I
Crystal or RC put terminal for 1/4 system clock. The system clock may come from the
RTC oscillator. If the system clock comes from RTCOSC, these two pins
can be floating.
O
Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz
OSC3
OSC4
I
RTC or
crystal oscillator for timing purposes or to a system clock source (depend-
O
System Clock
ing on the options). No built-in capacitor
VDD
RES
Positive power supply
¾
¾
¾
I
Schmitt trigger reset input, active low
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Rev. 1.60
4
July 14, 2005
HT46R62/HT46C62
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
fSYS=4MHz
2.2
3.3
¾
5.5
5.5
2
V
V
¾
¾
1
VDD
Operating Voltage
f
SYS=8MHz
¾
3V
5V
mA
mA
No load, ADC Off,
SYS=4MHz
Operating Current
IDD1
IDD2
IDD3
f
(Crystal OSC, RC OSC)
3
5
¾
Operating Current
No load, ADC Off,
fSYS=8MHz
5V
4
8
mA
¾
(Crystal OSC, RC OSC)
3V
5V
3V
5V
3V
5V
3V
5V
0.3
0.6
¾
¾
2.5
10
2
0.6
1
mA
mA
mA
mA
mA
mA
mA
mA
¾
¾
¾
¾
¾
¾
¾
¾
Operating Current
(fSYS=32768Hz)
No load, ADC Off
1
Standby Current
(*fS=T1)
No load, system HALT,
LCD Off at HALT
ISTB1
ISTB2
ISTB3
2
5
Standby Current
(*fS=RTC OSC)
No load, system HALT,
LCD On at HALT, C type
20
5
Standby Current
(*fS=WDT OSC)
No load, system HALT,
LCD On at HALT, C type
6
10
No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VLCD=VDD
17
34
13
28
14
26
10
19
30
60
¾
¾
¾
¾
¾
¾
¾
¾
0
mA
mA
mA
mA
mA
mA
mA
mA
V
3V
5V
Standby Current
(*fS=RTC OSC)
ISTB4
ISTB5
ISTB6
ISTB7
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VLCD=VDD
25
3V
5V
Standby Current
(*fS=RTC OSC)
50
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/2 bias, VLCD=VDD
25
3V
5V
Standby Current
(*fS=WDT OSC)
50
(Low bias current option)
No load, system HALT,
LCD On at HALT, R type,
1/3 bias, VLCD=VDD
20
3V
5V
Standby Current
(*fS=WDT OSC)
40
(Low bias current option)
Input Low Voltage for I/O Ports,
TMR, INT0, INT1
VIL1
0.3VDD
¾
¾
¾
¾
¾
¾
Input High Voltage for I/O Ports,
TMR, INT0, INT1
VIH1
0.7VDD
VDD
V
VIL2
0.4VDD
VDD
3.3
3.6
¾
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset Voltage
Low Voltage Detector Voltage
0
0.9VDD
2.7
3.0
6
V
V
¾
¾
¾
¾
¾
¾
¾
¾
VIH2
VLVR
VLVD
3.0
3.3
12
25
-4
-8
V
¾
V
¾
3V
5V
3V
5V
mA
mA
mA
mA
I/O Port Segment Logic Output
Sink Current
IOL1
V
V
OL=0.1VDD
OH=0.9VDD
10
¾
-2
¾
I/O Port Segment Logic Output
Source Current
IOH1
-5
¾
Rev. 1.60
5
July 14, 2005
HT46R62/HT46C62
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
3V
5V
3V
5V
3V
5V
¾
210
350
-80
-180
20
420
700
-160
-360
60
¾
¾
mA
mA
mA
mA
kW
kW
V
LCD Common and Segment
Current
IOL2
V
V
OL=0.1VDD
OH=0.9VDD
¾
LCD Common and Segment
Current
IOH2
¾
100
50
¾
¾
¾
Pull-high Resistance of I/O Ports
and INT0, INT1
RPH
10
30
VAD
EAD
VDD
A/D Input Voltage
0
¾
A/D Conversion Integral
Nonlinearity Error
LSB
¾
¾
¾
¾
±0.5
±1
3V
5V
0.5
1.5
1
3
mA
mA
¾
¾
Additional Power Consumption
if A/D Converter is Used
IADC
Note:
²*fS² please refer to clock option of Watchdog Timer
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
2.2V~5.5V
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
400
400
4000
8000
kHz
kHz
¾
¾
fSYS1
System Clock
3.3V~5.5V
¾
System Clock
fSYS2
2.2V~5.5V
32768
Hz
¾
¾
¾
(32768Hz Crystal OSC)
fRTCOSC
RTC Frequency
32768
¾
Hz
kHz
kHz
ms
¾
¾
¾
3V
5V
¾
¾
¾
0
¾
4000
8000
180
130
¾
2.2V~5.5V
fTIMER
Timer I/P Frequency
3.3V~5.5V
0
¾
45
32
1
90
¾
¾
¾
tWDTOSC
Watchdog Oscillator Period
65
ms
tRES
tSST
tLVR
tINT
External Reset Low Pulse Width
System Start-up Timer Period
¾
ms
Power-up or wake-up from
HALT
tSYS
ms
1024
¾
¾
¾
Low Voltage Width to Reset
Interrupt Pulse Width
A/D Clock Period
1
1
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
76
32
¾
¾
¾
¾
¾
ms
ms
tAD
1
tADC
tADCS
tAD
tAD
A/D Conversion Time
A/D Sampling Time
¾
¾
Note: tSYS= 1/fSYS
Rev. 1.60
6
July 14, 2005
HT46R62/HT46C62
Functional Description
Execution Flow
specify a maximum of 2048 addresses.
The system clock is derived from either a crystal or an
RC oscillator or a 32768Hz crystal oscillator. It is inter-
nally divided into four non-overlapping clocks. One in-
struction cycle consists of four system clock cycles.
After accessing a program memory word to fetch an in-
struction code, the value of the PC is incremented by 1.
The PC then points to the memory word containing the
next instruction code.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
The pipelining scheme makes it possible for each in-
struction to be effectively executed in a cycle. If an in-
struction changes the value of the program counter, two
cycles are required to complete the instruction.
When executing a jump instruction, conditional skip ex-
ecution, loading a PCL register, a subroutine call, an ini-
tial reset, an internal interrupt, an external interrupt, or
returning from a subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get a proper instruction; oth-
erwise proceed to the next instruction.
Program Counter - PC
The program counter (PC) is 11 bits wide and it controls
the sequence in which the instructions stored in the pro-
gram ROM are executed. The contents of the PC can
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
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4
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P
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P
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1
P
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+
2
P
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(
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(
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-
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Execution Flow
Program Counter
Mode
*10
0
*9
0
0
0
0
0
0
*8
0
0
0
0
0
0
*7
0
0
0
0
0
0
*6
0
0
0
0
0
0
*5
0
0
0
0
0
0
*4
0
0
0
0
1
1
*3
0
0
1
1
0
1
*2
0
1
0
1
1
0
*1
0
0
0
0
0
0
*0
0
0
0
0
0
0
Initial Reset
External Interrupt 0
External Interrupt 1
0
0
Timer/Event Counter Overflow
Time Base Interrupt
RTC Interrupt
0
0
0
Skip
Program Counter+2
Loading PCL
*10
*9
*8
#8
S8
@7
#7
@6
#6
@5
#5
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
Jump, Call Branch
Return From Subroutine
#10
S10
#9
S9
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *10~*0: Program counter bits
#10~#0: Instruction code bits
S10~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.60
7
July 14, 2005
HT46R62/HT46C62
·
·
Location 008H
The lower byte of the PC (PCL) is a readable and
writeable register (06H). Moving data into the PCL per-
forms a short jump. The destination is within 256 loca-
tions.
Location 008H is reserved for the external interrupt
service program also. If the INT1 input pin is activated,
and the interrupt is enabled, and the stack is not full,
the program begins execution at location 008H.
When a control transfer takes place, an additional
dummy cycle is required.
Location 00CH
Location 00CH is reserved for the Timer/Event Coun-
ter interrupt service program. If a timer interrupt re-
sults from a Timer/Event Counter overflow, and if the
interrupt is enabled and the stack is not full, the pro-
gram begins execution at location 00CH.
Program Memory - EPROM
The program memory (EPROM) is used to store the pro-
gram instructions which are to be executed. It also con-
tains data, table, and interrupt entries, and is organized
into 2048´14 bits which are addressed by the program
counter and table pointer.
·
·
·
Location 014H
Location 014H is reserved for the Time Base interrupt
service program. If a Time Base interrupt occurs, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 014H.
Certain locations in the ROM are reserved for special
usage:
Location 018H
·
·
Location 000H
Location 018H is reserved for the real time clock inter-
rupt service program. If a real time clock interrupt oc-
curs, and the interrupt is enabled, and the stack is not
full, the program begins execution at location 018H.
Location 000H is reserved for program initialization.
After chip reset, the program always begins execution
at this location.
Location 004H
Table location
Location 004H is reserved for the external interrupt
service program. If the INT0 input pin is activated, and
the interrupt is enabled, and the stack is not full, the
program begins execution at location 004H.
Any location in the ROM can be used as a look-up ta-
ble. The instructions ²TABRDC [m]² (the current page,
1 page=256 words) and ²TABRDL [m]² (the last page)
transfer the contents of the lower-order byte to the
specified data memory, and the contents of the
higher-order byte to TBLH (Table Higher-order byte
register) (08H). Only the destination of the lower-order
byte in the table is well-defined; the other bits of the ta-
ble word are all transferred to the lower portion of
TBLH and the remaining 1 bit is read as ²0². The
TBLH is read only, and the table pointer (TBLP) is a
read/write register (07H), indicating the table location.
Before accessing the table, the location should be
placed in TBLP. All the table related instructions re-
quire 2 cycles to complete the operation. These areas
may function as a normal ROM depending upon the
user¢s requirements.
0
0
0
0
0
0
0
4
8
H
H
H
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7
Program Memory
Table Location
Instruction(s)
*10
P10
1
*9
P9
1
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Table Location
P10~P8: Current program counter bits
Note: *10~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.60
8
July 14, 2005
HT46R62/HT46C62
Stack Register - STACK
decrement and rotate operations directly. Except for
some dedicated bits, each bit in the data memory can be
set and reset by ²SET [m].i² and ²CLR [m].i². They are
also indirectly accessible through memory pointer regis-
ters (MP0;01H/MP1;03H). The space before 28H is
overlapping in each bank.
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 6 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At the
start of a subroutine call or an interrupt acknowledg-
ment, the contents of the program counter is pushed
onto the stack. At the end of the subroutine or interrupt
routine, signaled by a return instruction (RET or RETI),
the contents of the program counter is restored to its
previous value from the stack. After chip reset, the SP
will point to the top of the stack.
I
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c
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A
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0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
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1
P
1
B
P
A
C
C
P
C
L
T
B
L
P
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent sixteen return addresses are stored).
T
B
L
H
R
T
C
C
0
0
A
B
H
H
S
T
A
T
U
S
I
N
T
C
0
0
0
C
D
H
H
T
M
R
0
E
H
T
M
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C
0
F
H
H
H
H
H
H
H
H
H
H
H
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
P
P
A
B
Data Memory - RAM
P
P
A
B
C
C
S
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P
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The data memory (RAM) is designed with 116´8 bits,
and is divided into two functional groups, namely; spe-
cial function registers 28´8 bit and general purpose data
memory, 88´8 bit most of which are readable/writable,
although some are read only. The special function regis-
ter are overlapped in any banks.
D
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y
P
D
P
D
C
1
1
A
B
H
H
P
P
P
W
W
W
M
M
M
0
1
2
Of the two types of functional groups, the special func-
tion registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indi-
rect addressing register 1 (02H), a Memory pointer reg-
ister 1 (MP1;03H), a Bank pointer (BP;04H), an
Accumulator (ACC;05H), a Program counter
lower-order byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), Interrupt control
register 1 (INTC1;1EH) , PWM data register
(PWM0;1AH, PWM1;1BH, PWM2;1CH), the A/D result
lower-order byte register (ADRL;24H), the A/D result
higher-order byte register (ADRH;25H), the A/D control
register (ADCR;26H), the A/D clock setting register
(ACSR;27H), I/O registers (PA;12H, PB;14H, PD;18H)
and I/O control registers (PAC;13H, PBC;15H,
PDC;19H). The space before 28H is overlapping in each
bank. The general purpose data memory, addressed
from 28H to 7FH, is used for data and control informa-
tion under instruction commands. All of the data mem-
ory areas can handle arithmetic, logic, increment,
1
1
C
D
H
H
1
E
H
I
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T
C
1
1
F
H
2
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
8
H
H
H
H
H
H
H
H
H
A
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A
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7
F
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RAM Mapping
Rev. 1.60
9
July 14, 2005
HT46R62/HT46C62
Indirect Addressing Register
Status Register - STATUS
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1(03H) respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The status register (0AH) is 8 bits wide and contains, a
carry flag (C), an auxiliary carry flag (AC), a zero flag (Z),
an overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PDF flags, bits in the status reg-
ister can be altered by instructions similar to other reg-
isters. Data written into the status register does not alter
the TO or PDF flags. Operations related to the status
register, however, may yield different results from those
intended. The TO and PDF flags can only be changed
by a Watchdog Timer overflow, chip power-up, or clear-
ing the Watchdog Timer and executing the ²HALT² in-
struction. The Z, OV, AC, and C flags reflect the status of
the latest operations.
The function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 7-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. The bit 7 of MP0 and MP1 are al-
ways ²1². MP0 can only be applied to data memory,
while MP1 can be applied to data memory and LCD dis-
play memory.
Accumulator - ACC
On entering the interrupt sequence or executing the
subroutine call, the status register will not be automati-
cally pushed onto the stack. If the contents of the status
is important, and if the subroutine is likely to corrupt the
status register, the programmer should take precautions
and save it properly.
The accumulator (ACC) is related to the ALU opera-
tions. It is also mapped to location 05H of the RAM and
is capable of operating with immediate data. The data
movement between two data memory locations must
pass through the ACC.
Arithmetic and Logic Unit - ALU
Interrupts
This circuit performs 8-bit arithmetic and logic opera-
tions and provides the following functions:
The device provides two external interrupts, one internal
timer/event counter interrupts, an internal time base in-
terrupt, and an internal real time clock interrupt. The in-
terrupt control register 0 (INTC0;0BH) and interrupt
control register 1 (INTC1;1EH) both contain the interrupt
control bits that are used to set the enable/disable status
and interrupt request flags.
·
·
·
·
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ etc.)
The ALU not only saves the results of a data operation
but also changes the status register.
Bit No.
Label
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
0
C
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is
set by executing the ²HALT² instruction.
4
PDF
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO
is set by a WDT time-out.
5
TO
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 1.60
10
July 14, 2005
HT46R62/HT46C62
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may take place during this interval,
but only the interrupt request flag will be recorded. If a
certain interrupt requires servicing within the service
routine, the EMI bit and the corresponding bit of the
INTC0 or of INTC1 may be set in order to allow interrupt
nesting. Once the stack is full, the interrupt request will
not be acknowledged, even if the related interrupt is en-
abled, until the SP is decremented. If immediate service
is desired, the stack should be prevented from becom-
ing full.
tion 04H or 08H occurs. The interrupt request flag (EIF0
or EIF1) and EMI bits are all cleared to disable other
maskable interrupts.
The internal Timer/Event Counter interrupt is initialized
by setting the Timer/Event Counter interrupt request flag
(TF; bit 6 of INTC0), which is normally caused by a timer
overflow. After the interrupt is enabled, and the stack is
not full, and the TF bit is set, a subroutine call to location
0CH occurs. The related interrupt request flag (TF) is re-
set, and the EMI bit is cleared to disable further interrupts.
The time base interrupt is initialized by setting the time
base interrupt request flag (TBF; bit 5 of INTC1), that is
caused by a regular time base signal. After the interrupt
is enabled, and the stack is not full, and the TBF bit is
set, a subroutine call to location 14H occurs. The related
interrupt request flag (TBF) is reset and the EMI bit is
cleared to disable further maskable interrupts.
All these interrupts can support a wake-up function. As
an interrupt is serviced, a control transfer occurs by
pushing the contents of the program counter onto the
stack followed by a branch to a subroutine at the speci-
fied location in the ROM. Only the contents of the pro-
gram counter is pushed onto the stack. If the contents of
the register or of the status register (STATUS) is altered
by the interrupt service program which corrupts the de-
sired control sequence, the contents should be saved in
advance.
The real time clock interrupt is initialized by setting the
real time clock interrupt request flag (RTF; bit 6 of
INTC1), that is caused by a regular real time clock sig-
nal. After the interrupt is enabled, and the stack is not
full, and the RTF bit is set, a subroutine call to location
18H occurs. The related interrupt request flag (RTF) is
reset and the EMI bit is cleared to disable further inter-
rupts.
External interrupts are triggered by a an edge transition
of INT0 or INT1 (option: high to low, low to high, low to
high or high to low), and the related interrupt request flag
(EIF0; bit 4 of INTC0, EIF1; bit 5 of INTC0) is set as well.
After the interrupt is enabled, the stack is not full, and
the external interrupt is active, a subroutine call to loca-
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are all held until the ²RETI²
instruction is executed or the EMI bit and the related in-
Bit No.
Label
EMI
Function
0
1
2
3
4
5
6
Control the master (global) interrupt (1=enabled; 0=disabled)
EEI0
EEI1
ETI
Control the external interrupt 0 (1=enabled; 0=disabled)
Control the external interrupt 1 (1=enabled; 0=disabled)
Control the Timer/Event Counter interrupt (1=enabled; 0=disabled)
External interrupt 0 request flag (1=active; 0=inactive)
External interrupt 1 request flag (1=active; 0=inactive)
Internal Timer/Event Counter request flag (1=enable; 0=disable)
EIF0
EIF1
TF
For test mode used only.
7
¾
Must be written as ²0²; otherwise may result in unpredictable operation.
INTC0 (0BH) Register
Bit No.
Label
¾
Function
0
1
Unused bit, read as ²0²
ETBI
ERTI
¾
Control the time base interrupt (1=enabled; 0:disabled)
Control the real time clock interrupt (1=enabled; 0:disabled)
Unused bit, read as ²0²
2
3, 4
5
TBF
RTF
¾
Time base request flag (1=active; 0=inactive)
Real time clock request flag (1=active; 0=inactive)
Unused bit, read as ²0²
6
7
INTC1 (1EH) Register
Rev. 1.60
11
July 14, 2005
HT46R62/HT46C62
terrupt control bit are set both to 1 (if the stack is not full).
To return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI sets the EMI bit and enables an
interrupt service, but RET does not.
oscillator is selected as the system oscillator, the system
oscillator is not stopped; but the instruction execution is
stopped. Since the 32768Hz oscillator is also designed
for timing purposes, the internal timing (RTC, time base,
WDT) operation still runs even if the system enters the
HALT mode.
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Of the three oscillators, if the RC oscillator is used, an
external resistor between OSC1 and VSS is required,
and the range of the resistance should be from 30kW to
750kW. The system clock, divided by 4, is available on
OSC2 with pull-high resistor, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
the oscillation may vary with VDD, temperature, and the
chip itself due to process variations. It is therefore, not
suitable for timing sensitive operations where accurate
oscillator frequency is desired.
Interrupt Source
External interrupt 0
Priority Vector
1
2
3
4
5
04H
08H
0CH
14H
18H
External interrupt 1
Timer/Event Counter overflow
Time base interrupt
Real time clock interrupt
On the other hand, if the crystal oscillator is selected, a
crystal across OSC1 and OSC2 is needed to provide the
feedback and phase shift required for the oscillator, and
no other external components are required. A resonator
may be connected between OSC1 and OSC2 to replace
the crystal and to get a frequency reference, but two ex-
ternal capacitors in OSC1 and OSC2 are required.
The Timer/Event Counter interrupt request flag (TF), ex-
ternal interrupt 1 request flag (EIF1), external interrupt 0
request flag (EIF0), enable Timer/Event Counter inter-
rupt bit (ETI), enable external interrupt 1 bit (EEI1), en-
able external interrupt 0 bit (EEI0) and enable master
interrupt bit (EMI) make up of the Interrupt Control regis-
ter 0 (INTC0) which is located at 0BH in the RAM. The
real time clock interrupt request flag (RTF), time base in-
terrupt request flag (TBF), enable real time clock inter-
rupt bit (ERTI), and enable time base interrupt bit
(ETBI), on the other hand, constitute the Interrupt Con-
trol register 1 (INTC1) which is located at 1EH in the
RAM. EMI, EEI0, EEI1, ETI, ET1I, ETBI and ERTI are all
used to control the enable/disable status of interrupts.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (RTF, TBF,
TF, EIF1, EIF0) are all set, they remain in the INTC1 or
INTC0 respectively until the interrupts are serviced or
cleared by a software instruction.
There is another oscillator circuit designed for the real
time clock. In this case, only the 32.768kHz crystal oscil-
lator can be applied. The crystal should be connected
between OSC3 and OSC4.
V
D
D
4
7
0
p
F
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C
1
O
S
C
1
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2
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It is recommended that a program should not use the
²CALL subroutine² within the interrupt subroutine. It¢s be-
cause interrupts often occur in an unpredictable manner
or require to be serviced immediately in some applica-
tions. During that period, if only one stack is left, and en-
abling the interrupt is not well controlled, operation of
the ²call² in the interrupt subroutine may damage the
original control sequence.
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3
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6
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System Oscillator
Note: 32768Hz crystal enable condition: For WDT
clock source or for system clock source.
Oscillator Configuration
The external resistor and capacitor components
connected to the 32768Hz crystal are not neces-
sary to provide oscillation. For applications
where precise RTC frequencies are essential,
these components may be required to provide
frequency compensation due to different crystal
manufacturing tolerances.
The device provides three oscillator circuits for system
clocks, i.e., RC oscillator, crystal oscillator and 32768Hz
crystal oscillator, determined by options. No matter what
type of oscillator is selected, the signal is used for the
system clock. The HALT mode stops the system oscilla-
tor (RC and crystal oscillator only) and ignores external
signal in order to conserve power. The 32768Hz crystal
oscillator still runs at HALT mode. If the 32768Hz crystal
Rev. 1.60
12
July 14, 2005
HT46R62/HT46C62
The RTC oscillator circuit can be controlled to oscillate
quickly by setting the ²QOSC² bit (bit 4 of RTCC). It is
recommended to turn on the quick oscillating function
upon power on, and then turn it off after 2 seconds.
two types of software instructions; ²CLR WDT² and the
other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instruction, only one type of instruction can
be active at a time depending on the options - ²CLR
WDT² times selection option. If the ²CLR WDT² is se-
lected (i.e., CLR WDT times equal one), any execution
of the ²CLR WDT² instruction clears the WDT. In the
case that ²CLR WDT1² and ²CLR WDT2² are chosen
(i.e., CLR WDT times equal two), these two instructions
have to be executed to clear the WDT; otherwise, the
WDT may reset the chip due to time-out.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Although
the system enters the power down mode, the system
clock stops, and the WDT oscillator still works with a pe-
riod of approximately 65ms@5V. The WDT oscillator can
be disabled by options to conserve power.
Watchdog Timer - WDT
Multi-function Timer
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC os-
cillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by options. But if the WDT is disabled, all exe-
cutions related to the WDT lead to no operation.
The HT46R62/HT46C62 provides a multi-function timer
for the WDT, time base and RTC but with different
time-out periods. The multi-function timer consists of an
8-stage divider and a 7-bit prescaler, with the clock
source coming from the WDT OSC or RTC OSC or the
instruction clock (i.e., system clock divided by 4). The
multi-function timer also provides a selectable fre-
quency signal (ranges from fS/22 to fS/28) for LCD driver
circuits, and a selectable frequency signal (ranging from
fS/22 to fS/29) for the buzzer output by options. It is rec-
ommended to select a nearly 4kHz signal for the LCD
driver circuits to have proper display.
Once an internal WDT oscillator (RC oscillator with pe-
riod 65ms@5V normally) is selected, it is divided by
212~215 (by option to get the WDT time-out period). The
minimum period of WDT time-out period is about
300ms~600ms. This time-out period may vary with tem-
perature, VDD and process variations. By selection the
WDT option, longer time-out periods can be realized. If
the WDT time-out is selected 215, the maximum time-out
period is divided by 215~216about 2.1s~4.3s. If the WDT
oscillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the halt state the WDT may stop counting
and lose its protecting purpose. In this situation the logic
can only be restarted by external logic. If the device op-
erates in a noisy environment, using the on-chip RC os-
cillator (WDT OSC) is strongly recommended, since the
HALT will stop the system clock.
Time Base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
ranges from 212/fS to 215fS selected by options. If time
base time-out occurs, the related interrupt request flag
(TBF; bit 5 of INTC1) is set. But if the interrupt is en-
abled, and the stack is not full, a subroutine call to loca-
tion 14H occurs.
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The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the program counter and SP are reset to zero. To clear
the contents of the WDT, there are three methods to be
adopted, i.e., external reset (a low level to RES), soft-
ware instruction, and a ²HALT² instruction. There are
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Watchdog Timer
Rev. 1.60
13
July 14, 2005
HT46R62/HT46C62
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Real Time Clock
Real Time Clock - RTC
struction, and is set by executing the ²HALT² instruction.
On the other hand, the TO flag is set if WDT time-out oc-
curs, and causes a wake-up that only resets the program
counter and SP, and leaves the others at their original
state.
The real time clock (RTC) is operated in the same man-
ner as the time base that is used to supply a regular in-
ternal interrupt. Its time-out period ranges from fS/28 to
fS/215 by software programming. Writing data to RT2,
RT1 and RT0 (bit 2, 1, 0 of RTCC;09H) yields various
time-out periods. If the RTC time-out occurs, the related
interrupt request flag (RTF; bit 6 of INTC1) is set. But if
the interrupt is enabled, and the stack is not full, a sub-
routine call to location 18H occurs.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by options. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two se-
quence may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the in-
terrupt is enabled, and the stack is not full, the regular in-
terrupt response takes place.
RT2
0
RT1
0
RT0 RTC Clock Divided Factor
0
1
0
1
0
1
0
1
28*
29*
0
0
0
1
210
211
*
0
1
*
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awakened using
that interrupt.
1
0
212
213
214
215
1
0
If wake-up events occur, it takes 1024 tSYS (system
clock period) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
1
1
1
1
Note: ²*² not recommended to be used
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
·
The system oscillator turns off but the WDT oscillator
keeps running (if the WDT oscillator or the real time
clock is selected).
Reset
·
·
The contents of the on-chip RAM and of the registers
remain unchanged.
There are three ways in which reset may occur.
·
·
·
RES is reset during normal operation
RES is reset during HALT
The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time
clock oscillator).
WDT time-out is reset during normal operation
·
·
·
All I/O ports maintain their original status.
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the program counter and SP and leaves the
other circuits at their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the ²initial condition² once the re-
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
The PDF flag is set but the TO flag is cleared.
LCD driver is still running
(if the WDT OSC or RTC OSC is selected).
The system quits the HALT mode by an external reset,
an interrupt, an external falling edge signal on port A, or
a WDT overflow. An external reset causes device initial-
ization, and the WDT overflow performs a ²warm reset².
After examining the TO and PDF flags, the reason for
chip reset can be determined. The PDF flag is cleared by
system power-up or by executing the ²CLR WDT² in-
Rev. 1.60
14
July 14, 2005
HT46R62/HT46C62
H
A
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T
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES Wake-up HALT
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WDT time-out during normal operation
WDT Wake-up HALT
1
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Note: ²u² stands for unchanged
Reset Configuration
Timer/Event Counter
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state or during power up.
Awaking from the HALT state or system power-up, the
SST delay is added.
One timer/event counters (TMR) are implemented in the
microcontroller. The Timer/Event Counter contains a
8-bit programmable count-up counter and the clock may
come from an external source or an internal clock
source. An internal clock source comes from fSYS. The
external clock input allows the user to count external
events, measure time intervals or pulse widths, or to
generate an accurate time base.
An extra SST delay is added during the power-up pe-
riod, and any wake-up from HALT may enable only the
SST delay.
The functional unit chip reset status is shown below.
Program Counter
Interrupt
000H
There are two registers related to the Timer/Event
Counter; TMR ([0DH]) and TMRC ([0EH]). Two physical
registers are mapped to TMR location; writing TMR puts
the starting value in the Timer/Event Counter register
and reading TMR takes the contents of the Timer/Event
Counter. The TMRC is a timer/event counter control reg-
ister, which defines some options counting enable or
disable and an active edge.
Disabled
Cleared
Prescaler, Divider
Cleared. After master reset,
WDT starts counting
WDT, RTC, Time Base
Timer/event Counter
Input/output Ports
Stack Pointer
Off
Input mode
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the internal selected
clock source. Finally, the pulse width measurement
mode can be used to count the high or low level duration
of the external signal (TMR), and the counting is based
on the internal selected clock source.
Points to the top of the stack
V
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0 . 0 1 F *
1
0
0
k
R
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S
1
0
k
In the event count or timer mode, the timer/event coun-
ter starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt re-
quest flag (TF; bit 6 of INTC0). In the pulse width mea-
surement mode with the values of the TON and TE bits
equal to 1, after the TMR has received a transient from
low to high (or high to low if the TE bit is ²0²), it will start
counting until the TMR returns to the original level and
resets the TON. The measured result remains in the
timer/event counter even if the activated transient oc-
curs again. In other words, only 1-cycle measurement
can be made until the TON is set. The cycle measure-
ment will re-function as long as it receives further tran-
sient pulse. In this operation mode, the timer/event
counter begins counting not according to the logic level
but to the transient edges. In the case of counter over-
m
0 . 1 F *
Reset Circuit
Note:
²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
V
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S S T
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Reset Timing Chart
Rev. 1.60
15
July 14, 2005
HT46R62/HT46C62
The register states are summarized below:
Reset
WDT Time-out
RES Reset
RES Reset
(HALT)
WDT Time-out
(HALT)*
Register
MP0
(Power On) (Normal Operation) (Normal Operation)
1xxx xxxx
1xxx xxxx
0000 0000
xxxx xxxx
0000H
1uuu uuuu
1uuu uuuu
0000 0000
uuuu uuuu
0000H
1uuu uuuu
1uuu uuuu
0000 0000
uuuu uuuu
0000H
1uuu uuuu
1uuu uuuu
0000 0000
uuuu uuuu
0000H
1uuu uuuu
1uuu uuuu
uuuu uuuu
uuuu uuuu
0000H
MP1
BP
ACC
Program Counter
TBLP
TBLH
RTCC
STATUS
INTC0
TMR
xxxx xxxx
--xx xxxx
--00 0111
--00 xxxx
-000 0000
xxxx xxxx
00-0 1000
1111 1111
1111 1111
--11 1111
--11 1111
-111 -111
-111 -111
xxxx xxxx
xxxx xxxx
xxxx xxxx
-00- -00-
x--- ----
uuuu uuuu
--uu uuuu
--00 0111
--1u uuuu
-000 0000
xxxx xxxx
00-0 1000
1111 1111
1111 1111
--11 1111
--11 1111
-111 -111
-111 -111
xxxx xxxx
xxxx xxxx
xxxx xxxx
-00- -00-
uuuu uuuu
--uu uuuu
--00 0111
--uu uuuu
-000 0000
xxxx xxxx
00-0 1000
1111 1111
1111 1111
--11 1111
--11 1111
-111 -111
-111 -111
xxxx xxxx
xxxx xxxx
xxxx xxxx
-00- -00-
uuuu uuuu
--uu uuuu
--00 0111
--01 uuuu
-000 0000
xxxx xxxx
00-0 1000
1111 1111
1111 1111
--11 1111
--11 1111
-111 -111
-111 -111
xxxx xxxx
xxxx xxxx
xxxx xxxx
-00- -00-
uuuu uuuu
--uu uuuu
--uu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
-uuu -uuu
-uuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uu- -uu-
TMRC
PA
PAC
PB
PBC
PD
PDC
PWM0
PWM1
PWM2
INTC1
ADRL
ADRH
ADCR
ACSR
x--- ----
x--- ----
x--- ----
u--- ----
xxxx xxxx
0100 0000
1--- --00
xxxx xxxx
0100 0000
1--- --00
xxxx xxxx
0100 0000
1--- --00
xxxx xxxx
0100 0000
1--- --00
uuuu uuuu
uuuu uuuu
1--- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.60
16
July 14, 2005
HT46R62/HT46C62
flows, the counter is reloaded from the timer/event coun-
ter register and issues an interrupt request, as in the
other two modes, i.e., event and timer modes.
to ETI disables the related interrupt service. When the
PFD function is selected, executing ²SET [PA].3² in-
struction to enable PFD output and executing ²CLR
[PA].3² instruction to disable PFD output.
To enable the counting operation, the Timer ON bit
(TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the TON can only be reset by in-
structions. The overflow of the Timer/Event Counter is
one of the wake-up sources and can also be applied to a
PFD (Programmable Frequency Divider) output at PA3
by options. Only one PFD can be applied to PA3 by op-
tions . No matter what the operation mode is, writing a 0
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR) is read,
the clock is blocked to avoid errors, as this may results
Bit No.
Label
Function
To define the prescaler stages.
PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
010: fINT=fSYS/4
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
0
1
2
PSC0
PSC1
PSC2
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
3
TE
0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
5
TON
Enable/disable timer counting (0=disabled; 1=enabled)
¾
Unused bit, read as ²0²
Defines the operating mode (TM1, TM0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
6
7
TM0
TM1
11= Pulse Width measurement mode (External clock)
00= Unused
TMRC (0EH) Register
P
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(
6
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7
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P
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Timer/Event Counter
Rev. 1.60
17
July 14, 2005
HT46R62/HT46C62
in a counting error. Blocking of the clock should be taken
into account by the programmer. It is strongly recom-
mended to load a desired value into the TMR register
first, before turning on the related timer/event counter,
for proper operation since the initial value of TMR is un-
known. Due to the timer/event scheme, the programmer
should pay special attention on the instruction to enable
then disable the timer for the first time, whenever there
is a need to use the timer/event function, to avoid unpre-
dictable result. After this procedure, the timer/event
function can be operated normally.
Each line of port A has the capability of waking-up the
device. Each I/O port has a pull-high option. Once the
pull-high option is selected, the I/O port has a pull-high
resistor, otherwise, there¢s none. Take note that a
non-pull-high I/O port operating in input mode will cause
a floating state.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by timer/event
counter overflow signal. The input mode always retain
its original functions. Once the PFD option is selected,
the PFD output signal is controlled by PA3 data register
only. Writing ²1² to PA3 data register will enable the PFD
output function and writing 0 will force the PA3 to remain
at ²0². The I/O functions of PA3 are shown below.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter. The definitions are as shown. The
overflow signal of timer/event counter can be used to
generate the PFD signal. The timer prescaler is also
used as the PWM counter.
I/O
I/P
O/P
I/P
O/P
Mode (Normal) (Normal) (PFD)
(PFD)
Input/Output Ports
Logical
Input
Logical
Output
Logical
PFD
PA3
Input (Timer on)
There are 20 bidirectional input/output lines in the
microcontroller, labeled as PA, PB0~PB5, PD0~PD2
and PD4~PD6, which are mapped to the data memory
of [12H], [14H] and [18H] respectively. All of these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, that is, the
inputs must be ready at the T2 rising edge of instruction
²MOV A,[m]² (m=12H, 14H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Note: The PFD frequency is the timer/event counter
overflowfrequencydividedby2.
The PA0, PA1, PA3, PD4, PD5 and PD6 are pin-shared
with BZ, BZ, PFD, INT0, INT1 and TMR pins respec-
tively.
The PA0 and PA1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ option is selected, the output
signal in output mode of PA0/PA1 will be the buzzer sig-
nal generated by multi-function timer. The input mode
always remain in its original function. Once the BZ/BZ
option is selected, the buzzer output signal are con-
trolled by the PA0, PA1 data register only.
Each I/O line has its own control register (PAC, PBC,
PDC) to control the input/output configuration. With this
control register, CMOS output or Schmitt Trigger input
with or without pull-high resistor structures can be re-
configured dynamically under software control. To func-
tion as an input, the corresponding latch of the control
register must write ²1². The input source also depends
on the control register. If the control register bit is ²1²,
the input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the inter-
nal bus. The latter is possible in the ²read-modify-write²
instruction.
The I/O function of PA0/PA1 are shown below.
PA0 I/O
I
I
I
O
I
O
I
O
I
O
O
O
O
B
C
0
O
O
B
C
1
O
O
B
B
0
O
O
B
B
1
PA1 I/O
O
X
C
X
D
I
PA0 Mode
PA1 Mode
PA0 Data
X
X
X
X
I
C
X
D
X
D
I
B
X
0
X
0
I
B
X
1
C
C
D0
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 19H.
PA1 Data
X D1 D
D
B
D
X
0
X
B
B
PA0 Pad Status
PA1 Pad Status
B
I
D0
D1
0
I
D
D
0
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or
18H) instructions.
Note:
²I² input; ²O² output
²D, D0, D1² Data
²B² buzzer option, BZ or BZ
²X² don¢t care
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
²C² CMOS output
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1/PD2. If the PWM function
is enabled, the PWM0/PWM1/PWM2 signal will appear
Rev. 1.60
18
July 14, 2005
HT46R62/HT46C62
V
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Input/Output Ports
PWM
on PD0/PD1/PD2 (if PD0/PD1/PD2 is operating in out-
put mode). The I/O functions of PD0/PD1/PD2 are as
shown.
The microcontroller provides 3 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0/PD1/PD2. The PWM channels have their data reg-
isters denoted as PWM0 (1AH), PWM1 (1BH) and
PWM2 (1CH). The frequency source of the PWM coun-
ter comes from fSYS. The PWM registers are three 8-bit
registers. The waveforms of PWM outputs are as
shown. Once the PD0/PD1/PD2 are selected as the
PWM outputs and the output function of PD0/PD1/PD2
are enabled (PDC.0/PDC.1/ PDC.2=²0²), writing ²1² to
PD0/PD1/PD2 data register will enable the PWM output
function and writing ²0² will force the PD0/PD1/PD2 to
stay at ²0².
I/O
I/P
O/P
I/P
O/P
Mode (Normal) (Normal) (PWM)
(PWM)
PD0
PWM0
PWM1
PWM2
Logical
Input
Logical
Output
Logical
Input
PD1
PD2
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The definitions of PFD control signal and PFD output
frequency are listed in the following table.
A (6+2) bits mode PWM cycle is divided into four modu-
lation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2. The group 2 is denoted by AC which is
the value of PWM.1~PWM.0.
Timer
PA3 Data PA3 Pad
PFD
Timer Preload
Value
Register
State
Frequency
OFF
OFF
ON
X
X
N
N
0
1
0
1
0
U
X
X
0
X
ON
PFD
f
TMR/[2´(M-N)]
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Note:
²X² stands for unused
²U² stands for unknown
²M² is ²256² for PFD
Parameter
AC (0~3)
Duty Cycle
DC+ 1
64
i<AC
²N² is preload value for timer/event counter
²fTMR² is input clock frequency for timer/event
counter
Modulation cycle i
(i=0~3)
DC
64
i³AC
Rev. 1.60
19
July 14, 2005
HT46R62/HT46C62
A (7+1) bits mode PWM cycle is divided into two modu-
lation cycles (modulation cycle0~modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1. The group 2 is denoted by AC which is
the value of PWM.0.
PWM
PWM Cycle PWM Cycle
Modulation Frequency Frequency
Duty
fSYS/64 for (6+2) bits mode
f
SYS/256
[PWM]/256
f
SYS/128 for (7+1) bits mode
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~1)
Duty Cycle
DC+ 1
128
i<AC
Modulation cycle i
(i=0~1)
DC
i³AC
128
S
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Rev. 1.60
20
July 14, 2005
HT46R62/HT46C62
A/D Converter
converter circuit is powered-on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and fall-
ing edge means that the A/D conversion has started. In
order to ensure that the A/D conversion is completed,
the START should remain at ²0² until the EOCB is
cleared to ²0² (end of A/D conversion).
The 6 channels and 9 bits resolution A/D converter are
implemented in this microcontroller. The reference volt-
age is VDD. The A/D converter contains 4 special regis-
ters which are; ADRL (24H), ADRH (25H), ADCR (26H)
and ACSR (27H). The ADRH and ADRL are A/D result
register higher-order byte and lower-order byte and are
read-only. After the A/D conversion is completed, the
ADRH and ADRL should be read to get the conversion
result data. The ADCR is an A/D converter control regis-
ter, which defines the A/D channel number, analog
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an
A/D conversion, define PB configuration, select the con-
verted analog channel, and give START bit a rising edge
and falling edge (0®1®0). At the end of A/D conver-
sion, the EOCB bit is cleared. The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the applica-
tion program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
When the A/D conversion has completed, the A/D inter-
rupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D con-
verter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an un-
defined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selec-
tion bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initial-
ization is not required.
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of six
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
Bit No. Label
Function
Selects the A/D converter clock source
00= system clock/2
0
1
ADCS0
ADCS1
01= system clock/8
10= system clock/32
11= undefined
2~6
7
¾
Unused bit, read as ²0²
TEST For test mode used only
ACSR (27H) Register
Bit No. Label
Function
0
1
2
ACS0
ACS1 Defines the analog channel select.
ACS2
3
4
5
PCR0
Defines the port B configuration select. If PCR0, PCR1 and PCR2 are all zero, the ADC circuit is
power off to reduce power consumption
PCR1
PCR2
Indicates end of A/D conversion. (0 = end of A/D conversion)
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, other-
wise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
6
7
EOCB
START
Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)
ADCR (26H) Register
Rev. 1.60
21
July 14, 2005
HT46R62/HT46C62
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PB5
PB5
PB5
PB5
PB5
PB5
AN5
AN5
PB4
PB4
PB4
PB4
PB4
AN4
AN4
AN4
PB3
PB3
PB3
PB3
AN3
AN3
AN3
AN3
PB2
PB2
PB2
AN2
AN2
AN2
AN2
AN2
PB1
PB1
AN1
AN1
AN1
AN1
AN1
AN1
PB0
AN0
AN0
AN0
AN0
AN0
AN0
AN0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
Port B Configuration
ACS2
ACS1
ACS0
Analog Channel
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN5
AN5
Analog Input Channel Selection
Register
Bit7
D0
Bit6
Bit5
¾
Bit4
¾
Bit3
¾
Bit2
¾
Bit1
Bit0
¾
ADRL (24H)
ADRH (25H)
¾
¾
D8
D7
D6
D5
D4
D3
D2
D1
Note: D0~D8 is A/D conversion result data bit LSB~MSB.
ADRL (24H), ADRH (25H) Register
The following programming example illustrates how to setup and implement an A/D conversion. The method of poll-
ing the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete.
Example: using EOCB Polling Method to detect end of conversion
clr
EADI
; disable ADC interrupt
mov
mov
mov
mov
a,00000001B
ACSR,a
; setup the ACSR register to select fSYS/8 as the A/D clock
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
a,00100000B
ADCR,a
:
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
set
clr
START
START
START
; reset A/D
; start A/D
Polling_EOC:
sz
EOCB
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
jmp
mov
polling_EOC
a,ADRH
; read conversion result high byte value from the ADRH register
Rev. 1.60
22
July 14, 2005
HT46R62/HT46C62
mov
mov
mov
adrh_buffer,a
; save result to user defined memory
a,ADRL
; read conversion result low byte value from the ADRL register
; save result to user defined memory
adrl_buffer,a
:
:
jmp
start_conversion
; start next A/D conversion
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1
B
0
1
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S
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:
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t
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t
A
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C
t
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s
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A
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c
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N
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:
A
/
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c
l
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k
m
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b
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f
S
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S
S
Y
S
S
Y
S
t
t
A
D
C
S
A
D
A
D
C
A
D
A/D Conversion Timing
LCD Display Memory
LCD Driver Output
The device provides an area of embedded data memory
for LCD display. This area is located from 40H to 53H of
the RAM at Bank 1. Bank pointer (BP; located at 04H of
the RAM) is the switch between the RAM and the LCD
display memory. When the BP is set as ²1², any data
written into 40H~53H will effect the LCD display. When
the BP is cleared to ²0², any data written into 40H~53H
means to access the general purpose data memory.
The LCD display memory can be read and written to
only by indirect addressing mode using MP1. When
data is written into the display data area, it is automati-
cally read by the LCD driver which then generates the
corresponding LCD driving signals. To turn the display
on or off, a ²1² or a ²0² is written to the corresponding bit
of the display memory, respectively. The figure illus-
trates the mapping between the display memory and
LCD pattern for the device.
The output number of the device LCD driver can be 20´2
or 20´3 or 19´4 by option (i.e., 1/2 duty, 1/3 duty or 1/4
duty). The bias type LCD driver can be ²R² type or ²C²
type. If the ²R² bias type is selected, no external capaci-
tor is required. If the ²C² bias type is selected, a capaci-
tor mounted between C1 and C2 pins is needed. The
LCD driver bias voltage can be 1/2 bias or 1/3 bias by
option. If 1/2 bias is selected, a capacitor mounted be-
tween V2 pin and ground is required. If 1/3 bias is se-
lected, two capacitors are needed for V1 and V2 pins.
Refer to application diagram.
Option
Condition
Low Bias Current High Bias Current
(Typ.)
(Typ.)
1/3 Bias
1/2 Bias
(VLCD/4.5)´15mA
(VLCD/3)´15mA
(VLCD/4.5)´45mA
(VLCD/3)´45mA
C
O
M
4
0
H
4
1
H
4
2
H
4
3
H
5
1
H
5
2
H
5
3
H
B
i
t
²R² Type Bias Current
0
1
2
3
0
Note: The 52-pin QFP package does not support the
charge pump (C type bias) of the LCD. The LCD
bias type must select the R type by option.
1
2
3
S
E
G
M
E
N
T
0
1
2
3
1
7
1
8
1
9
Display Memory
Rev. 1.60
23
July 14, 2005
HT46R62/HT46C62
D
u
r
i
n
g
a
R
e
s
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t
P
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1
V
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C
C
D
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C
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M
0
,
C
O
M
1
,
C
O
M
2
/
/
2
2
L
L
C
C
D
D
S
L
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S
V
1
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V
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1
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2
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1
2
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2
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1
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2
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d
.
LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type)
Rev. 1.60
24
July 14, 2005
HT46R62/HT46C62
V
V
A
B
V
V
V
C
S
A
C
O
M
0
S
S
S
S
S
V
V
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C
C
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M
1
V
V
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A
V
V
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C
C
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2
V
V
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A
V
V
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C
C
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3
V
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:
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d
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:
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1
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1
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3
V
L
C
D
LCD Driver Output
LCD Segments as Logical Output
The SEG0~SEG15 also can be optioned as logical output, once an LCD segment is optioned as a logical output, the
content of bit 0 of the related segment address in LCD RAM will appear on the segment.
SEG0~SEG7 is together byte optioned as logical output, SEG8~SEG15 are bit individually optioned as logical outputs.
LCD Type
R Type
1/2 bias 1/3 bias
C Type
1/3 bias
LCD Bias Type
1/2 bias
3
2
If VDD
>
V
LCD, then VMAX connect to VDD
,
If VDD>VLCD, then VMAX connect to VDD,
else VMAX connect to VLCD
VMAX
else VMAX connect to V1
Rev. 1.60
25
July 14, 2005
HT46R62/HT46C62
Low Voltage Reset/Detector Functions
There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These
two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to
enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5; otherwise, the LVD function is
disabled.
The RTCC register definitions are listed below.
Bit No.
0~2
3
Label
Function
RT0~RT2 8 to 1 multiplexer control inputs to select the real clock prescaler output
LVDC
LVD enable/disable (1/0)
32768Hz OSC quick start-up oscillating
0/1: quickly/slowly start
4
QOSC
LVD detection output (1/0)
5
LVDO
1: low voltage detected, read only
6, 7
¾
Unused bit, read as ²0²
RTCC (09H) Register
The LVR has the same effect or function with the exter-
nal RES signal which performs chip reset. During HALT
state, LVR is disabled both LVR and LVD are disabled.
The relationship between VDD and VLVR is shown below.
V
D
D
V
O P R
5
.
5
V
5
.
5
V
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
V
L
V
R
3
.
0
V
2
.
2
V
The LVR includes the following specifications:
·
The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
0
.
9
V
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
·
The LVR uses the ²OR² function with the external RES
signal to perform chip reset.
V
D
D
5
.
5
V
L
V
R
D
e
t
e
c
t
V
o
l
t
a
g
e
V
L
V
R
0
.
9
0
V
V
R
e
s
e
t
S
i
g
n
a
l
R
e
s
e
t
N
o
r
m
a
l
O
p
e
r
a
t
i
o
n
R
e
s
e
t
*
1
*
2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
Rev. 1.60
26
July 14, 2005
HT46R62/HT46C62
Options
The following shows the options in the device. All these options should be defined in order to ensure proper functioning
system.
Options
OSC type selection.
This option is to decide if an RC or crystal or 32768Hz crystal oscillator is chosen as system clock.
WDT, RTC and time base clock source selection.
There are three types of selections: system clock/4 or RTC OSC or WDT OSC.
WDT enable/disable selection.
WDT can be enabled or disabled by option.
WDT time-out period selection.
There are four types of selection: WDT clock source divided by 212/fS~213/fS, 213/fS~214/fS, 214/fS~215/fS or
215/fS~216/fS.
CLR WDT times selection.
This option defines the method to clear the WDT by instruction. ²One time² means that the ²CLR WDT² can clear the
WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, the WDT can be
cleared.
Time Base time-out period selection.
The Time Base time-out period ranges from 212/fS to 215/fS. ²fS² means the clock source selected by options.
Buzzer output frequency selection.
There are eight types of frequency signals for buzzer output: fS/22~fS/29. ²fS² means the clock source selected by op-
tions.
Wake-up selection.
This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip
from a HALT by a falling edge (bit option).
Pull-high selection.
This option is to decide whether the pull-high resistance is visible or not in the input mode of the I/O ports. PA, PB and
PD can be independently selected (bit option).
I/O pins share with other function selections.
PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.
LCD common selection.
There are three types of selections: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4
common is selected, the segment output pin ²SEG19² will be set as a common output.
LCD bias power supply selection.
There are two types of selections: 1/2 bias or 1/3 bias
LCD bias type selection.
This option is to determine what kind of bias is selected, R type or C type.
LCD driver clock frequency selection.
There are seven types of frequency signals for the LCD driver circuits: fS/22~fS/28. ²fS² stands for the clock source se-
lection by options.
LCD ON/OFF at HALT selection.
LCD Segments as logical output selection, (byte, bit, bit, bit, bit, bit, bit, bit, bit option)
[SEG0~SEG7], SEG8, SEG9, SEG10, SEG11, SEG12, SEG13, SEG14 or SEG15
LVR selection.
LVR has enable or disable options
LVD selection.
LVD has enable or disable options
PFD selection.
If PA3 is set as PFD output, PFD is the timer overflow signal of the Timer/Event Counter respectively.
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
PD2: level output or PWM2 output
INT0 or INT1 triggering edge selection: disable; high to low; low to high; low to high or high to low.
Rev. 1.60
27
July 14, 2005
HT46R62/HT46C62
Application Circuits
V
D
D
C
O
M
0
~
C
O
M
2
9
m
0 . 0 1 F *
L
C
D
V
R
D
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C
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M
3
/
S
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G
1
P
A
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L
S
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0
~
S
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G
1
8
1
0
0
k
m
0 . 1 F
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1
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m
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C
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1
2
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7
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1
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2
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2
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1
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4
P
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3
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4
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1
3
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2
7
6
8
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B
0
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A
N
0
5
P
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4
5
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I
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0
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2
6
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2
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4
6
R
6
2
/
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T
4
6
C
6
2
O
S
C
C
i
r
c
u
i
t
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
4MHz Crystal
C1, C2
0pF
R1
10kW
12kW
10kW
10kW
10kW
27kW
9.1kW
10kW
10kW
4MHz Resonator
10pF
0pF
3.58MHz Crystal
3.58MHz Resonator
2MHz Crystal & Resonator
1MHz Crystal
25pF
25pF
35pF
300pF
300pF
300pF
480kHz Resonator
455kHz Resonator
429kHz Resonator
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage condi-
tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
²VMAX² connect to VDD or VLCD or V1 refer to the table.
LCD Type
R Type
1/2 bias 1/3 bias
C Type
1/3 bias
LCD bias type
1/2 bias
If VDD>VLCD, then VMAX connect to VDD
,
If VDD > 3/2VLCD, then VMAX connect to VDD
,
VMAX
else VMAX connect to VLCD
else VMAX connect to V1
Rev. 1.60
28
July 14, 2005
HT46R62/HT46C62
Instruction Set Summary
Instruction
Cycle
Flag
Mnemonic
Arithmetic
Description
Affected
ADD A,[m]
ADDM A,[m]
ADD A,x
Add data memory to ACC
1
1(1)
1
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
Add ACC to data memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add data memory to ACC with carry
1
1(1)
Add ACC to data memory with carry
Subtract immediate data from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Subtract data memory from ACC
1
1(1)
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1(1)
Logic Operation
AND A,[m]
OR A,[m]
AND data memory to ACC
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
OR data memory to ACC
XOR A,[m]
ANDM A,[m]
ORM A,[m]
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
1
1(1)
1(1)
1(1)
1
XORM A,[m] Exclusive-OR ACC to data memory
AND A,x
OR A,x
AND immediate data to ACC
OR immediate data to ACC
1
XOR A,x
CPL [m]
CPLA [m]
Exclusive-OR immediate data to ACC
Complement data memory
1
1(1)
Complement data memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment data memory with result in ACC
1
Z
Z
Z
Z
Increment data memory
1(1)
DECA [m]
DEC [m]
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
Rotate
RRA [m]
RR [m]
Rotate data memory right with result in ACC
Rotate data memory right
1
1(1)
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
1(1)
C
1
None
None
C
1(1)
1
RLCA [m]
RLC [m]
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1(1)
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Rev. 1.60
29
July 14, 2005
HT46R62/HT46C62
Instruction
Cycle
Flag
Mnemonic
Branch
Description
Affected
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if data memory is zero
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
Miscellaneous
NOP
No operation
1
1(1)
1(1)
1
None
None
CLR [m]
Clear data memory
SET [m]
Set data memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1
1(1)
1
None
1
TO,PDF
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2): If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(1) and (2)
(3)
:
(4): The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
Rev. 1.60
30
July 14, 2005
HT46R62/HT46C62
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
Rev. 1.60
31
July 14, 2005
HT46R62/HT46C62
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
Operation
The contents of the specified data memory are cleared to 0.
[m] ¬ 00H
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.60
32
July 14, 2005
HT46R62/HT46C62
CLR [m].i
Clear bit of data memory
Description
Operation
The bit i of the specified data memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
0
PDF
0
OV
Z
AC
C
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
0*
PDF
0*
OV
Z
AC
C
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
0*
PDF
0*
OV
Z
AC
C
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.60
33
July 14, 2005
HT46R62/HT46C62
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Operation
Data in the specified data memory is decremented by 1.
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.60
34
July 14, 2005
HT46R62/HT46C62
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
0
PDF
1
OV
Z
AC
C
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Operation
Data in the specified data memory is incremented by 1
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Description
Operation
Move data memory to the accumulator
The contents of the specified data memory are copied to the accumulator.
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.60
35
July 14, 2005
HT46R62/HT46C62
MOV A,x
Move immediate data to the accumulator
Description
Operation
The 8-bit data specified by the code is loaded into the accumulator.
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
Program Counter ¬ Program Counter+1
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.60
36
July 14, 2005
HT46R62/HT46C62
RET
Return from subroutine
Description
Operation
Affected flag(s)
The program counter is restored from the stack. This is a 2-cycle instruction.
Program Counter ¬ Stack
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
Operation
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.60
37
July 14, 2005
HT46R62/HT46C62
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
Operation
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
Rev. 1.60
38
July 14, 2005
HT46R62/HT46C62
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.60
39
July 14, 2005
HT46R62/HT46C62
SET [m]
Set data memory
Description
Operation
Each bit of the specified data memory is set to 1.
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Operation
Bit i of the specified data memory is set to 1.
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.60
40
July 14, 2005
HT46R62/HT46C62
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.60
41
July 14, 2005
HT46R62/HT46C62
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.60
42
July 14, 2005
HT46R62/HT46C62
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.60
43
July 14, 2005
HT46R62/HT46C62
Package Information
52-pin QFP (14´14) Outline Dimensions
C
H
D
G
3
9
2
7
I
4
0
2
6
F
A
B
E
1
4
5
2
K
J
1
1
3
Dimensions in mm
Symbol
Min.
17.3
13.9
17.3
13.9
¾
Nom.
¾
Max.
17.5
14.1
17.5
14.1
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
1
0.4
¾
¾
2.5
¾
3.1
¾
¾
0.1
¾
¾
¾
3.4
¾
¾
J
0.73
0.1
0°
1.03
0.2
K
a
7°
Rev. 1.60
44
July 14, 2005
HT46R62/HT46C62
56-pin SSOP (300mil) Outline Dimensions
2
2
9
8
5
6
A
B
1
C
C
'
G
H
D
a
E
F
Dimensions in mil
Symbol
Min.
395
291
8
Nom.
¾
Max.
420
299
12
A
B
C
C¢
D
E
F
¾
¾
720
89
¾
730
99
¾
¾
25
¾
4
10
¾
¾
¾
¾
G
H
a
25
4
35
12
0°
8°
Rev. 1.60
45
July 14, 2005
HT46R62/HT46C62
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.60
46
July 14, 2005
HT46C62 相关器件
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| HT46C62(52QFP) | HOLTEK | Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PQFP52 | 获取价格 |
|
| HT46C62(52QFP-A) | HOLTEK | Microcontroller, 8-Bit, MROM, 8MHz, CMOS, PQFP52 | 获取价格 |
|
| HT46C62(56SSOP) | HOLTEK | Microcontroller, 8-Bit, MROM, 8MHz, CMOS, PDSO56 | 获取价格 |
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| HT46C62(56SSOP-A) | HOLTEK | Microcontroller, 8-Bit, MROM, 8MHz, CMOS, PDSO56 | 获取价格 |
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| HT46C63 | HOLTEK | A/D with LCD Type 8-Bit MCU | 获取价格 |
|
| HT46C63(100QFP) | ETC | Microcontroller | 获取价格 |
|
| HT46C63(100QFP-A) | HOLTEK | Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PQFP100 | 获取价格 |
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| HT46C63(56SSOP-A) | HOLTEK | Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO56 | 获取价格 |
|
| HT46C63-100QEP-A | HOLTEK | A/D with LCD Type 8-Bit MCU | 获取价格 |
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