HT48R10A-1(24SOP-A)_技术文档

HT48R10A-1/HT48C10-1

I/O Type 8-Bit MCU

Technical Document

·

Tools Information

FAQs

Application Note

-

HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM

HA0004E HT48 & HT46 MCU UART Software Implementation Method

HA0013E HT48 & HT46 LCM Interface Design

HA0021E Using the I/O Ports on the HT48 MCU Series

HA0085E 8-bit Pseudo-Random Number Generator

Features

·

Operating voltage:

64´8 data memory RAM

f

_SYS=4MHz: 2.2V~5.5V

_SYS=8MHz: 3.3V~5.5V

Buzzer driving pair and PFD supported

HALT function and wake-up feature reduce power

consumption

·

Low voltage reset function

21 bidirectional I/O lines (max.)

1 interrupt input shared with an I/O line

·

Up to 0.5ms instruction cycle with 8MHz system clock

at V_DD=5V

8-bit programmable timer/event counter with over-

flow interrupt and 8-stage prescaler

·

All instructions in one or two machine cycles

14-bit table read instruction

4-level subroutine nesting

·

On-chip external crystal, RC oscillator and internal

RC oscillator

Bit manipulation instruction

63 powerful instructions

·

32768Hz crystal oscillator for timing purposes only

Watchdog Timer

24-pin SKDIP/SOP package

1024´14 program memory ROM

General Description

The HT48R10A-1/HT48C10-1 are 8-bit high perfor-

mance, RISC architecture microcontroller devices spe-

cifically designed for multiple I/O control product

applications. The mask version HT48C10-1 is fully pin

and functionally compatible with the OTP version

HT48R10A-1 device.

The advantages of low power consumption, I/O flexibil-

ity, timer functions, oscillator options, HALT and

wake-up functions, watchdog timer, buzzer driver, as

well as low cost, enhance the versatility of these devices

to suit a wide range of application possibilities such as

industrial control, consumer products, subsystem con-

trollers, etc.

Rev. 2.01

1

January 9, 2009

HT48R10A-1/HT48C10-1

Block Diagram

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Pin Assignment

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Rev. 2.01

2

January 9, 2009

HT48R10A-1/HT48C10-1

Pin Description

Pin Name I/O

Options

Description

Pull-high*

Wake-up

Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input

by options. Software instructions determine the CMOS output or Schmitt trigger

PA0~PA7

I/O

CMOS/Schmitt or CMOS (dependent on options) input with a pull-high resistor (determined by

trigger Input pull-high options).

Bidirectional 8-bit input/output port. Software instructions determine the CMOS

output or Schmitt trigger input with a pull-high resistor (determined by pull-high

PB0/BZ

PB1/BZ

PB2~PB7

Pull-high*

options).

I/O or BZ/BZ The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the PB0

and PB1 are selected as buzzer driving outputs, the output signals come from an

internal PFD generator (shared with timer/event counter).

VSS

Negative power supply, ground

¾

Bidirectional I/O lines. Software instructions determine the CMOS output or

Schmitt trigger input with a pull-high resistor (determined by pull-high options).

The external interrupt and timer input are pin-shared with the PC0 and PC1, re-

spectively. The external interrupt input is activated on a high to low transition.

PC0/INT

PC1/TMR

PC2

I/O

Pull-high*

RES

VDD

I

Schmitt trigger reset input. Active low

Positive power supply

¾

OSC1, OSC2 are connected to an RC network or Crystal (determined by options)

for the internal system clock. In the case of RC operation, OSC2 is the output ter-

minal for 1/4 system clock. These two pins also can be optioned as an RTC oscil-

lator (32768Hz) or I/O lines. In these two cases, the system clock comes from an

internal RC oscillator whose frequency has 4 options (3.2MHz, 1.6MHz, 800kHz,

400kHz). If the I/O option is selected, the pull-high options also be enabled. Oth-

erwise the PC3 and PC4 are used as internal registers (pull-high resistors always

disabled).

Crystal or RC

or Int. RC+I/O

or Int. RC+RTC

OSC1/PC3

OSC2/PC4

I

O

* The pull-high resistors of each I/O port (PA, PB, PC) are controlled by an option bit.

Absolute Maximum Ratings

Supply Voltage...........................V_SS-0.3V to V_SS+6.0V

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

Storage Temperature............................-50°C to 125°C

Operating Temperature...........................-40°C to 85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

Rev. 2.01

3

January 9, 2009

HT48R10A-1/HT48C10-1

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

¾

f

_SYS=4MHz

2.2

3.3

¾

5.5

1.5

4

V

¾

V_DD

Operating Voltage

f

_SYS=8MHz

V

¾

3V

5V

3V

5V

0.6

2

mA

I_DD1

No load, f_SYS=4MHz

Operating Current (Crystal OSC)

Operating Current (RC OSC)

¾

0.8

2.5

1.5

4

¾

I_DD2

I_DD3

I_STB1

No load, f_SYS=4MHz

No load, f_SYS=8MHz

No load, system HALT

¾

Operating Current

5V

4

8

mA

¾

(Crystal OSC, RC OSC)

3V

5V

3V

5V

3V

5V

¾

5

10

¾

3.0

8

mA

V

Standby Current

(WDT Enabled RTC Off)

1

¾

Standby Current

I_STB2

No load, system HALT

(WDT Disabled RTC Off)

2

¾

5

¾

Standby Current

I_STB3

(WDT Disabled, RTC On)

10

¾

V_IL1

V_IH1

V_IL2

V_IH2

V_LVR

0.3V_DD

V_DD

0.4V_DD

V_DD

3.3

¾

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES)

Input High Voltage (RES)

Low Voltage Reset

0

¾

0.7V_DD

0

V

¾

V

¾

0.9V_DD

2.7

4

V

¾

LVRenabled

V

¾

V

_OL=0.1V_DD

3V

5V

3V

5V

3V

5V

mA

kW

I_OL

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance

V

10

20

-4

-10

60

30

¾

V_OH=0.9V_DD

_OH=0.9V_DD

-2

¾

I_OH

V

-5

¾

20

100

50

R_PH

¾

10

Rev. 2.01

4

January 9, 2009

HT48R10A-1/HT48C10-1

A.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

¾

2.2V~5.5V

3.3V~5.5V

2.2V~5.5V

3.3V~5.5V

3.2MHz

1.6MHz

800kHz

400kHz

2.2V~5.5V

3.3V~5.5V

¾

400

1800

900

450

225

0

4000

8000

4000

8000

5400

2700

1350

675

kHz

¾

90

65

23

17

f_SYS1

System Clock (Crystal OSC)

System Clock (RC OSC)

¾

f_SYS2

¾

f_SYS3

System Clock (Internal RC OSC)

5V

4000

8000

180

¾

f_TIMER

Timer I/P Frequency (TMR)

Watchdog Oscillator Period

0

3V

5V

3V

5V

45

ms

t_WDTOSC

32

130

¾

11

46

ms

Watchdog Time-out Period

(WDT OSC)

t_WDT1

Without WDT prescaler

8

33

Watchdog Time-out Period

(System Clock)

t_WDT2

t_SYS

ms

Without WDT prescaler

1024

¾

Watchdog Time-out Period

(RTC OSC)

t_WDT3

7.812

t_RES

t_SST

t_INT

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

1

¾

1

¾

Wake-up from HALT

¾

1024

¾

ms

t_SYS

ms

Rev. 2.01

5

January 9, 2009

HT48R10A-1/HT48C10-1

Functional Description

Execution Flow

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call, initial re-

set, internal interrupt, external interrupt or return from

subroutine, the PC manipulates the program transfer by

loading the address corresponding to each instruction.

The system clock for the microcontroller is derived from

either a crystal or an RC oscillator. The system clock is

internally divided into four non-overlapping clocks. One

instruction cycle consists of four system clock cycles.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get the proper instruction.

Otherwise proceed with the next instruction.

Instruction fetching and execution are pipelined in such

a way that a fetch takes an instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to effectively execute in a cycle. If an instruction

changes the program counter, two cycles are required to

complete the instruction.

The lower byte of the program counter (PCL) is a read-

able and writable register (06H). Moving data into the

PCL performs a short jump. The destination will be

within 256 locations.

Program Counter - PC

The program counter (PC) controls the sequence in

which the instructions stored in program ROM are exe-

cuted and its contents specify full range of program

memory.

When a control transfer takes place, an additional

dummy cycle is required.

Program Memory - ROM

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by one. The program counter then points to

the memory word containing the next instruction code.

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

1024´14 bits, addressed by the program counter and ta-

ble pointer.

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Execution Flow

Program Counter

Mode

*9

0

*8

0

*7

0

*6

0

*5

0

*4

0

*3

0

*2

0

*1

0

*0

0

Initial Reset

External Interrupt

0

1

0

Timer/Event Counter Overflow

Skip

0

1

0

Program Counter+2

Loading PCL

*9

*8

@7

#7

@6

#6

@5

#5

@4

#4

@3

#3

@2

#2

@1

#1

@0

#0

Jump, Call Branch

Return from Subroutine

#9

S9

#8

S8

S7

S6

S5

S4

S3

S2

S1

S0

Program Counter

Note: *9~*0: Program counter bits

#9~#0: Instruction code bits

S9~S0: Stack register bits

@7~@0: PCL bits

Rev. 2.01

6

January 9, 2009

HT48R10A-1/HT48C10-1

Certain locations in the program memory are reserved

for special usage:

ferred to the lower portion of TBLH, and the remaining

2 bits are read as ²0². The Table Higher-order byte

register (TBLH) is read only. The table pointer (TBLP)

is a read/write register (07H), which indicates the table

location. Before accessing the table, the location must

be placed in TBLP. The TBLH is read only and cannot

be restored. If the main routine and the ISR (Interrupt

Service Routine) both employ the table read instruc-

tion, the contents of the TBLH in the main routine are

likely to be changed by the table read instruction used

in the ISR. Errors can occur. In other words, using the

table read instruction in the main routine and the ISR

simultaneously should be avoided. However, if the ta-

ble read instruction has to be applied in both the main

routine and the ISR, the interrupt is supposed to be

disabled prior to the table read instruction. It will not be

enabled until the TBLH has been backed up. All table

related instructions require two cycles to complete the

operation. These areas may function as normal pro-

gram memory depending upon the requirements.

·

Location 000H

This area is reserved for program initialization. After

chip reset, the program always begins execution at lo-

cation 000H.

·

Location 004H

This area is reserved for the external interrupt service

program. If the INT input pin is activated, the interrupt

is enabled and the stack is not full, the program begins

execution at location 004H.

·

Location 008H

This area is reserved for the timer/event counter inter-

rupt service program. If a timer interrupt results from a

timer/event counter overflow, and if the interrupt is en-

abled and the stack is not full, the program begins ex-

ecution at location 008H.

Table location

Any location in the ROM space can be used as

look-up tables. The instructions ²TABRDC [m]² (the

current page, one page=256 words) and ²TABRDL

[m]² (the last page) transfer the contents of the

lower-order byte to the specified data memory, and

the higher-order byte to TBLH (08H). Only the desti-

nation of the lower-order byte in the table is

well-defined, the other bits of the table word are trans-

Stack Register - STACK

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 4 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledgment, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

0

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If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledgment will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 4 return ad-

dresses are stored).

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Program Memory

Table Location

Instruction

*9

P9

1

*8

P8

1

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

@7

@6

@5

@4

@3

@2

@1

@0

Table Location

P9, P8: Current program counter bits

Note: *9~*0: Table location bits

@7~@0: Table pointer bits

Rev. 2.01

7

January 9, 2009

HT48R10A-1/HT48C10-1

panded usage and reading these locations will get

²00H². The general purpose data memory, addressed

from 40H to 7FH, is used for data and control informa-

tion under instruction commands.

Data Memory - RAM

The data memory is designed with 81´8 bits. The data

memory is divided into two functional groups: special

function registers and general purpose data memory

(64´8). Most are read/write, but some are read only.

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer register (MP;01H).

The special function registers include the indirect ad-

dressing register (00H), timer/event counter

(TMR;0DH), timer/event counter control register

(TMRC;0EH), program counter lower-order byte regis-

ter (PCL;06H), memory pointer register (MP;01H), ac-

cumulator (ACC;05H), table pointer (TBLP;07H), table

higher-order byte register (TBLH;08H), status register

(STATUS;0AH), interrupt control register (INTC;0BH),

Watchdog Timer option setting register (WDTS;09H),

I/O registers (PA;12H, PB;14H, PC;16H) and I/O control

registers (PAC;13H, PBC;15H, PCC;17H). The remain-

ing space before the 40H is reserved for future ex-

Indirect Addressing Register

Location 00H is an indirect addressing register that is

not physically implemented. Any read/write operation of

[00H] accesses data memory pointed to by MP (01H).

Reading location 00H itself indirectly will return the re-

sult 00H. Writing indirectly results in no operation.

The memory pointer register MP (01H) is a 7-bit register.

The bit 7 of MP is undefined and reading will return the re-

sult ²1². Any writing operation to MP will only transfer the

lower 7-bit data to MP.

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1

2

3

4

5

6

7

8

9

H

M

P

Accumulator

A

C

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

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C

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T

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Arithmetic and Logic Unit - ALU

D

A

T

A

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Y

0

C

D

H

T

M

R

This circuit performs 8-bit arithmetic and logic opera-

tions. The ALU provides the following functions:

0

E

H

T

M

R

C

0

F

H

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

1

0

1

2

3

4

5

6

7

8

9

P

A

P

A

C

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

P

B

P

B

C

The ALU not only saves the results of a data operation

but also changes the status register.

P

C

P

C

Status Register - STATUS

:

U

n

u

s

e

d

This 8-bit register (0AH) contains the zero flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PDF), and watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

1

A

B

H

R

e

a

d

a

s

"

0

"

1

C

D

H

1

E

H

1

F

H

With the exception of the TO and PDF flags, bits in

the status register can be altered by instructions like

most other registers. Any data written into the status

register will not change the TO or PDF flag. In addi-

tion operations related to the status register may give

different results from those intended. The TO flag

can be affected only by system power-up, a WDT

time-out or executing the ²CLR WDT² or ²HALT² in-

struction. The PDF flag can be affected only by exe-

2

0

H

3

F

H

4

0

G

e

n

e

r

a

l

P

E

u

r

p

o

s

e

D

A

T

A

M

O

R

Y

(

6

4

B

y

t

e

s

)

7

F

H

RAM Mapping

Rev. 2.01

8

January 9, 2009

HT48R10A-1/HT48C10-1

(STATUS) are altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents should be saved in advance.

cuting the ²HALT² or ²CLR WDT² instruction or a

system power-up.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

External interrupts are triggered by a high to low transi-

tion of INT and the related interrupt request flag (EIF; bit

4 of INTC) will be set. When the interrupt is enabled, the

stack is not full and the external interrupt is active, a sub-

routine call to location 04H will occur. The interrupt re-

quest flag (EIF) and EMI bits will be cleared to disable

other interrupts.

In addition, on entering the interrupt sequence or exe-

cuting the subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status are important and if the subroutine can cor-

rupt the status register, precautions must be taken to

save it properly.

The internal timer/event counter interrupt is initialized by

setting the timer/event counter interrupt request flag

(TF; bit 5 of INTC), caused by a timer overflow. When

the interrupt is enabled, the stack is not full and the TF

bit is set, a subroutine call to location 08H will occur. The

related interrupt request flag (TF) will be reset and the

EMI bit cleared to disable further interrupts.

Interrupt

The device provides an external interrupt and internal

timer/event counter interrupts. The Interrupt Control

Register (INTC;0BH) contains the interrupt control bits

to set the enable or disable and the interrupt request

flags.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (of course, if the stack is

not full). To return from the interrupt subroutine, ²RET² or

²RETI² may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt requires servicing within the service routine, the

EMI bit and the corresponding bit of INTC may be set to

allow interrupt nesting. If the stack is full, the interrupt re-

quest will not be acknowledged, even if the related inter-

rupt is enabled, until the SP is decremented. If immediate

service is desired, the stack must be prevented from be-

coming full.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

No.

a

Interrupt Source

External Interrupt

Timer/Event Counter Overflow

Priority Vector

1

2

04H

08H

b

Bit No.

Label

Function

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

0

C

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

1

2

3

AC

Z

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

OV

PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by

executing the ²HALT² instruction.

4

5

PDF

TO

TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

6

7

¾

Unused bit, read as ²0²

Status (0AH) Register

Rev. 2.01

9

January 9, 2009

HT48R10A-1/HT48C10-1

Bit No.

Label

EMI

EEI

ETI

¾

Function

0

1

2

3

4

5

6

7

Controls the master (global) interrupt (1= enabled; 0= disabled)

Controls the external interrupt (1= enabled; 0= disabled)

Controls the timer/event counter interrupt (1= enabled; 0= disabled)

Unused bit, read as ²0²

EIF

TF

External interrupt request flag (1= active; 0= inactive)

Internal timer/event counter request flag (1= active; 0= inactive)

Unused bit, read as ²0²

¾

Unused bit, read as ²0²

INTC (0BH) Register

If an RC oscillator is used, an external resistor between

OSC1 and VDD is required and the resistance must

range from 24kW to 1MW. The system clock, divided by

4, is available on OSC2, which can be used to synchro-

nize external logic. The RC oscillator provides the most

cost effective solution. However, the frequency of oscil-

lation may vary with VDD, temperatures and the chip it-

self due to process variations. It is, therefore, not

suitable for timing sensitive operations where an accu-

rate oscillator frequency is desired.

The timer/event counter interrupt request flag (TF), ex-

ternal interrupt request flag (EIF), enable timer/event

counter bit (ETI), enable external interrupt bit (EEI) and

enable master interrupt bit (EMI) constitute an interrupt

control register (INTC) which is located at 0BH in the

data memory. EMI, EEI, ETI are used to control the en-

abling/disabling of interrupts. These bits prevent the re-

quested interrupt from being serviced. Once the

interrupt request flags (TF, EIF) are set, they will remain

in the INTC register until the interrupts are serviced or

cleared by a software instruction.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift required for the oscillator, and no other external

components are required. Instead of a crystal, a resona-

tor can also be connected between OSC1 and OSC2 to

get a frequency reference, but two external capacitors in

OSC1 and OSC2 are required. If the internal RC oscilla-

tor is used, the OSC1 and OSC2 can be selected as

general I/O lines or an 32768Hz crystal oscillator (RTC

OSC). Also, the frequencies of the internal RC oscillator

can be 3.2MHz, 1.6MHz, 800kHz and 400kHz (de-

pended by options).

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. In-

terrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications.

If only one stack is left and enabling the interrupt is not

well controlled, the original control sequence will be dam-

aged once the ²CALL² operates in the interrupt subrou-

tine.

Oscillator Configuration

There are 3 oscillator circuits in the microcontroller.

The WDT oscillator is a free running on-chip RC oscillator,

and no external components are required. Even if the sys-

tem enters the power down mode, the system clock is

stopped, but the WDT oscillator still works with a period of

approximately 65ms@5V. The WDT oscillator can be dis-

abled by options to conserve power.

V

D

O

S

C

1

O

S

C

1

4

7

0

p

F

S

Y

S

O

S

C

2

O

S

C

2

Watchdog Timer - WDT

N

M

O

S

O

p

e

n

D

r

a

i

n

C

r

y

s

t

a

l

O

s

c

i

l

a

t

o

r

R

C

O

s

c

i

l

a

t

o

r

The clock source of WDT is implemented by a dedicated

RC oscillator (WDT oscillator), RTC clock or instruction

clock (system clock divided by 4), decided by options.

This timer is designed to prevent a software malfunction

or sequence from jumping to an unknown location with

unpredictable results. The Watchdog Timer can be dis-

abled by an option. If the Watchdog Timer is disabled, all

the executions related to the WDT result in no operation.

The RTC clock is enabled only in the internal RC+RTC

mode.

(

I

n

c

l

u

d

e

3

2

7

6

8

H

z

)

System Oscillator

All of them are designed for system clocks, namely the

external RC oscillator, the external Crystal oscillator and

the internal RC oscillator, which are determined by the

options. No matter what oscillator type is selected, the

signal provides the system clock. The HALT mode stops

the system oscillator and ignores an external signal to

conserve power.

Rev. 2.01

10

January 9, 2009

HT48R10A-1/HT48C10-1

S

y

s

t

e

m

C

l

o

c

k

/

4

W

D

T

P

r

e

s

c

a

l

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r

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T

C

O

S

C

O

p

t

i

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n

8

-

b

i

t

C

o

u

n

t

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r

7

-

b

i

t

C

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t

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t

W

D

T

O

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8

-

t

o

-

1

M

U

X

W

S

0

~

W

S

2

W

D

T

i

m

e

-

o

u

t

Watchdog Timer

Once the internal WDT oscillator (RC oscillator with a

period of 65ms@5V normally) is selected, it is first di-

vided by 256 (8-stage) to get the nominal time-out pe-

riod of approximately 17ms@5V. This time-out period

may vary with temperatures, VDD and process varia-

tions. By invoking the WDT prescaler, longer time-out

periods can be realized. Writing data to WS2, WS1,

WS0 (bit 2,1,0 of the WDTS) can give different time-out

periods. If WS2, WS1, and WS0 are all equal to 1, the divi-

sion ratio is up to 1:128, and the maximum time-out period

is 2.1s@5V seconds. If the WDT oscillator is disabled, the

WDT clock may still come from the instruction clock and

operate in the same manner except that in the HALT state

the WDT may stop counting and lose its protecting pur-

pose. In this situation the logic can only be restarted by ex-

ternal logic. The high nibble and bit 3 of the WDTS are

reserved for user's defined flags, which can be used to in-

dicate some specified status.

one), any execution of the ²CLR WDT² instruction will

clear the WDT. In the case that ²CLR WDT1² and ²CLR

WDT2² are chosen (i.e. CLRWDT times equal two),

these two instructions must be executed to clear the

WDT; otherwise, the WDT may reset the chip as a result

of time-out.

Power Down Operation - HALT

The HALT mode is initialized by the ²HALT² instruction

and results in the following.

·

The system oscillator will be turned off but the WDT

oscillator keeps running (if the WDT oscillator is se-

lected).

·

The contents of the on chip RAM and registers remain

unchanged.

WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) or 32kHz crystal oscilla-

tor (RTC OSC) is strongly recommended, since the HALT

will stop the system clock.

·

All of the I/O ports maintain their original status.

The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a ²warm reset². After the TO and PDF flags are

examined, the reason for chip reset can be determined.

The PDF flag is cleared by system power-up or execut-

ing the ²CLR² WDT instruction and is set when execut-

ing the ²HALT² instruction. The TO flag is set if the WDT

time-out occurs, and causes a wake-up that only resets

the Program Counter and SP; the others keep their orig-

inal status.

WS2

WS1

WS0

Division Ratio

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake up the

device by the options. Awakening from an I/O port stim-

ulus, the program will resume execution of the next in-

struction. If it is awakening from an interrupt, two

sequences may happen. If the related interrupt is dis-

abled or the interrupt is enabled but the stack is full, the

program will resume execution at the next instruction. If

the interrupt is enabled and the stack is not full, the regu-

lar interrupt response takes place. If an interrupt request

flag is set to ²1² before entering the HALT mode, the

wake-up function of the related interrupt will be disabled.

Once a wake-up event occurs, it takes 1024 t_SYS(sys-

tem clock period) to resume normal operation. In other

WDTS (09H) Register

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit ²TO². But in the HALT

mode, the overflow will initialize a ²warm reset² and only

the Program Counter and SP are reset to zero. To clear

the contents of WDT (including the WDT prescaler),

three methods are adopted; external reset (a low level to

RES), software instruction and a ²HALT² instruction.

The software instruction include ²CLR WDT² and the

other set - ²CLR WDT1² and ²CLR WDT2². Of these

two types of instruction, only one can be active depend-

ing on the option - ²CLR WDT times selection option². If

the ²CLR WDT² is selected (i.e. CLRWDT times equal

Rev. 2.01

11

January 9, 2009

HT48R10A-1/HT48C10-1

words, a dummy period will be inserted after wake-up. If

the wake-up results from an interrupt acknowledgment,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

V

D

R

E

S

t

S S T

S

T

i

m

e

-

o

u

t

C

h

i

p

R

e

s

e

t

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

The RTC oscillator is still running in the HALT mode (If

the RTC oscillator is enabled).

Reset Timing Chart

V

D

m

0 . 0 1 F *

Reset

1

0

k

There are three ways in which a reset can occur:

R

E

S

·

RES reset during normal operation

RES reset during HALT

1

0

k

m

0 . 1 F *

WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the Program Counter and SP, leav-

ing the other circuits in their original state. Some regis-

ters remain unchanged during other reset conditions.

Most registers are reset to the ²initial condition² when

the reset conditions are met. By examining the PDF and

TO flags, the program can distinguish between different

²chip resets².

Reset Circuit

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

H

A

L

T

W

a

r

m

R

e

s

e

t

W

D

T

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

R

E

S

0

u

0

1

0

u

1

u

1

C

o

l

d

R

e

s

e

t

S

T

1

0

-

b

i

t

R

i

p

l

e

O

S

C

1

C

o

u

n

t

e

r

WDT time-out during normal operation

WDT wake-up HALT

S

y

s

t

e

m

R

e

s

e

t

Reset Configuration

The functional unit chip reset status are shown below.

Note: ²u² means ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem reset (power-up, WDT time-out or RES reset) or the

system awakes from the HALT state.

Program Counter

Interrupt

000H

Disable

Clear

Prescaler

Clear. After master reset,

WDT begins counting

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

WDT

Timer/Event Counter Off

Input/Output Ports

SP

Input mode

Points to the top of the stack

An extra option load time delay is added during system

reset (power-up, WDT time-out at normal mode or RES

reset).

Rev. 2.01

12

January 9, 2009

HT48R10A-1/HT48C10-1

The states of the registers is summarized in the table.

Reset

WDT time-out

RES Reset

(Power On) (Normal Operation) (Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

Register

TMR

xxxx xxxx

00-0 1000

xxxx xxxx

00-0 1000

xxxx xxxx

00-0 1000

xxxx xxxx

00-0 1000

uuuu uuuu

uu-u uuuu

TMRC

Program

Counter

000H

MP

-xxx xxxx

xxxx xxxx

--xx xxxx

-uuu uuuu

uuuu uuuu

--uu uuuu

--1u uuuu

--00 -000

-uuu uuuu

uuuu uuuu

--uu uuuu

--00 -000

-uuu uuuu

uuuu uuuu

--uu uuuu

--01 uuuu

--00 -000

-uuu uuuu

uuuu uuuu

--uu uuuu

--11 uuuu

--uu -uuu

ACC

TBLP

TBLH

STATUS

INTC

WDTS

PA

--00 xxxx

--00 -000

0000 0111

1111 1111

---1 1111

0000 0111

1111 1111

---1 1111

0000 0111

1111 1111

---1 1111

0000 0111

1111 1111

---1 1111

uuuu uuuu

---u uuuu

PAC

PB

PBC

PC

PCC

---1 1111

---u uuuu

Note:

²*² means ²warm reset²

²u² means ²unchanged²

²x² means ²unknown²

time-bases for timer/event counter. The internal clock

source can be selected as coming from (can always be

optioned) or f_RTC(enabled only system oscillator in the

Int. RC+RTC mode) by options. Using external clock in-

put allows the user to count external events, measure

time internals or pulse widths, or generate an accurate

time base. While using the internal clock allows the user

to generate an accurate time base.

Timer/Event Counter

A timer/event counters (TMR) is implemented in the

microcontroller. The timer/event counter contains an

8-bit programmable count-up counter and the clock may

come from an external source or from the system clock

or RTC.

Using the internal clock sources, there are 2 reference

Bit No.

Label

Function

To define the prescaler stages, PSC2, PSC1, PSC0=

000: f_INT=f_SYS/2 or f_RTC/2

001: f_INT=f_SYS/4 or f_RTC/4

010: f_INT=f_SYS/8 or f_RTC/8

0~2

PSC0~PSC2 011: f_INT=f_SYS/16 or f_RTC/16

100: f_INT=f_SYS/32 or f_RTC/32

101: f_INT=f_SYS/64 or f_RTC/64

110: f_INT=f_SYS/128 or f_RTC/128

111: f_INT=f_SYS/256 or f_RTC/256

To define the TMR active edge of timer/event counter

3

TE

(0=active on low to high; 1=active on high to low)

To enable or disable timer counting (0=disabled; 1=enabled)

Unused bit, read as ²0²

4

5

TON

¾

To define the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

6

7

TM0

TM1

TMRC (0EH) Register

Rev. 2.01

13

January 9, 2009

HT48R10A-1/HT48C10-1

(

1

/

2

~

1

P

/

2

5

6

)

f

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0

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2

~

P

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0

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Z

Timer/Event Counter

The timer/event counter can generate PFD signal by us-

ing external or internal clock and PFD frequency is de-

termine by the equation f_INT/[2´(256-N)].

But in the other two modes the TON can only be reset by

instructions. The overflow of the timer/event counter is

one of the wake-up sources. No matter what the opera-

tion mode is, writing a 0 to ETI can disable the interrupt

service.

There are 2 registers related to the timer/event counter;

TMR ([0DH]), TMRC ([0EH]). Two physical registers are

mapped to TMR location; writing TMR makes the start-

ing value be placed in the timer/event counter preload

register and reading TMR gets the contents of the

timer/event counter. The TMRC is a timer/event counter

control register, which defines some options.

In the case of timer/event counter OFF condition, writ-

ing data to the timer/event counter preload register will

also reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow oc-

curs. When the timer/event counter (reading TMR) is read,

the clock will be blocked to avoid errors. As clock blocking

may results in a counting error, this must be taken into con-

sideration by the programmer.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR) pin. The timer mode functions as a normal timer

with the clock source coming from the f_INTclock. The

pulse width measurement mode can be used to count

the high or low level duration of the external signal

(TMR). The counting is based on the f_INTclock.

The bit0~bit2 of the TMRC can be used to define the

pre-scaling stages of the internal clock sources of

timer/event counter. The definitions are as shown. The

overflow signal of timer/event counter can be used to

generate PFD signals for buzzer driving.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFH. Once over-

flow occurs, the counter is reloaded from the timer/event

counter preload register and generates the interrupt re-

quest flag (TF; bit 5 of INTC) at the same time.

Input/Output Ports

There are 21 bidirectional input/output lines in the

microcontroller, labeled from PA to PC, which are

mapped to the data memory of [12H], [14H] and [16H]

respectively. All of these I/O ports can be used for input

and output operations. For input operation, these ports

are non-latching, that is, the inputs must be ready at the

T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H

or 16H). For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

In the pulse width measurement mode with the TON

and TE bits equal to one, once the TMR has received a

transient from low to high (or high to low if the TE bits is

²0²) it will start counting until the TMR returns to the orig-

inal level and resets the TON. The measured result will

remain in the timer/event counter even if the activated

transient occurs again. In other words, only one cycle

measurement can be done. Until setting the TON, the

cycle measurement will function again as long as it re-

ceives further transient pulse. Note that, in this operat-

ing mode, the timer/event counter starts counting not

according to the logic level but according to the transient

edges. In the case of counter overflows, the counter is

reloaded from the timer/event counter preload register

and issues the interrupt request just like the other two

modes. To enable the counting operation, the timer ON

bit (TON; bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON will be cleared au-

tomatically after the measurement cycle is completed.

Each I/O line has its own control register (PAC, PBC,

PCC) to control the input/output configuration. With this

control register, CMOS output or Schmitt trigger input

with or without pull-high resistor structures can be re-

configured dynamically (i.e. on-the-fly) under software

control. To function as an input, the corresponding latch

of the control register must write ²1². The input source

also depends on the control register. If the control regis-

ter bit is ²1², the input will read the pad state. If the con-

trol register bit is ²0², the contents of the latches will

move to the internal bus. The latter is possible in the

²read-modify-write² instruction.

Rev. 2.01

14

January 9, 2009

HT48R10A-1/HT48C10-1

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H and 17H.

mented; on reading them a ²0² is returned whereas writing

then results in a no-operation. See Application note.

There is a pull-high option available for all I/O ports (byte

option). Once the pull-high option of an I/O port is se-

lected, all I/O lines have pull-high resistors. Otherwise,

the pull-high resistors are absent. It should be noted that

a non-pull-high I/O line operating in input mode will

cause a floating state.

After a chip reset, these input/output lines remain at high

levels or floating state (dependent on pull-high options).

Each bit of these input/output latches can be set or

cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or

16H) instructions.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

The PB0 and PB1 are pin-shared with BZ and BZ signal,

respectively. If the BZ/BZ option is selected, the output

signal in output mode of PB0/PB1 will be the PFD signal

generated by timer/event counter overflow signal. The

input mode always remaining its original functions.

Once the BZ/BZ option is selected, the buzzer output

signals are controlled by PB0 data register only. The I/O

functions of PB0/PB1 are shown below.

Each line of port A has the capability of waking-up the de-

vice. The highest 3-bit of port C are not physically imple-

PB0 I/O

I

O

x

B

0

x

I

O

x

O

I

O

I

O

I

O

B

C

0

O

B

C

1

O

B

0

O

B

1

PB1 I/O

O

x

PB0 Mode

PB1 Mode

PB0 Data

x

I

C

x

B

x

0

x

0

I

B

x

1

x

B

I

C

x

B

1

x

C

D

x

D₀

D₁

D₀

D₁

PB1 Data

D

I

D

0

D

B

D

x

PB0 Pad Status

PB1 Pad Status

I

D

I

0

B

I

D

0

B

D

0

Note:

²I² input, ²O² output, ²D, D₀, D₁² data,

²B² buzzer option, BZ or BZ, ²x² don't care

²C² CMOS output

V

D

P

C

3

/

P

C

4

I

/

O

M

o

d

e

O

n

l

y

C

o

n

t

r

o

l

B

i

t

P

U

D

a

t

a

B

u

s

D

C

Q

K

W

r

i

t

e

C

o

n

t

r

o

l

R

e

g

i

s

t

e

r

S

C

h

i

p

R

e

s

e

t

P

A

B

C

0

~

P

A

7

0

~

P

B

7

0

~

P

C

4

R

e

a

d

C

o

n

t

r

o

l

R

e

g

i

s

t

e

r

D

a

t

a

B

i

t

D

C

Q

K

Q

W

r

i

t

e

D

a

t

a

R

e

g

i

s

t

e

r

S

M

U

P

B

0

(

P

B

0

,

P

B

1

O

n

l

y

)

X

B

Z

/

B

Z

B

Z

E

N

M

(

P

B

0

,

P

B

1

O

n

l

y

)

U

X

R

e

a

d

D

a

t

a

R

e

g

i

s

t

e

r

S

y

s

t

e

m

W

a

k

e

-

u

p

O

P

0

~

O

P

7

(

P

A

o

n

l

y

)

I

N

T

f

o

r

P

C

0

O

n

l

y

T

M

R

f

o

r

P

C

1

O

n

l

y

Input/Output Ports

Rev. 2.01

15

January 9, 2009

HT48R10A-1/HT48C10-1

·

The PC0 and PC1 are pin-shared with INT, TMR and

pins respectively.

The LVR uses the ²OR² function with the external

RES signal to perform chip reset.

The relationship between V_DDand V_LVRis shown below.

In case of ²Internal RC+I/O² system oscillator, the PC3

and PC4 are pin-shared with OSC1 and OSC2 pins.

Once the ²Internal RC+I/O² mode is selected, the PC3

and PC4 can be used as general purpose I/O lines. Oth-

erwise, the pull-high resistors and I/O functions of PC3

and PC4 will be disabled.

V

D

V

O

P

R

5

.

5

V

5

.

5

V

L

V

R

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

3

.

0

V

2

.

2

V

Low Voltage Reset - LVR

0

.

9

V

The microcontroller provides low voltage reset circuit in

order to monitor the supply voltage of the device. If the

supply voltage of the device is within the range

0.9V~V_LVR, such as changing a battery, the LVR will au-

tomatically reset the device internally.

Note: V_OPRis the voltage range for proper chip opera-

tion at 4MHz system clock.

The LVR includes the following specifications:

·

The low voltage (0.9V~V_LVR) has to remain in their

original state to exceed 1ms. If the low voltage state

does not exceed 1ms, the LVR will ignore it and do not

perform a reset function.

V

D

5

.

5

V

L

V

R

D

e

t

e

c

t

V

o

l

t

a

g

e

V

L

V

R

0

.

9

0

V

R

e

s

e

t

S

i

g

n

a

l

R

e

s

e

t

N

o

r

m

a

l

O

p

e

r

a

t

i

o

n

R

e

s

e

t

*

1

*

2

Low Voltage Reset

Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system

clock pulses before entering the normal operation.

*2: Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms delay enter the

reset mode.

Rev. 2.01

16

January 9, 2009

HT48R10A-1/HT48C10-1

Options

The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper

system functioning.

Items

Options

WDT clock source: WDT oscillator or f_SYS/4 or RTC oscillator or disable

CLRWDT instructions: 1 or 2 instructions

Timer/event counter clock sources: f_SYSor RTCOSC

PA bit wake-up enable or disable

1

2

3

4

5

6

7

8

PA CMOS or Schmitt input

PA, PB, PC pull-high enable or disable (By port)

BZ/BZ enable or disable

LVR enable or disable

System oscillator

9

Ext.RC, Ext.crystal, Int.RC+RTC or Int.RC+PC3/PC4

10

Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz

Rev. 2.01

17

January 9, 2009

HT48R10A-1/HT48C10-1

Application Circuits

V

D

R

O

S

C

R

C

S

y

s

t

e

m

O

s

c

i

l

a

t

o

r

2

4

k

W

O

S

C

W

O

S

C

1

2

4

7

0

p

F

N

M

O

S

o

p

e

n

d

r

a

i

n

V

D

C

1

O

S

C

1

2

m

0 . 0 1 F *

V

R

D

P

A

B

0

2

~

P

A

B

7

C

F

s

r

y

s

t

a

l

S

y

s

t

e

m

O

s

c

i

l

a

t

o

r

o

r

t

h

e

v

a

l

u

e

s

,

1

0

k

C

2

e

t

a

b

l

e

b

e

l

o

w

m

0 . 1 F

P

C

2

E

S

R

1

0

k

P

B

0

1

/

B

Z

m

0 . 1 F *

O

S

C

1

2

V

S

I

O

n

t

e

r

n

a

l

R

C

O

s

c

i

l

a

t

o

r

S

C

1

a

n

d

O

S

C

2

l

e

f

t

u

n

c

o

n

e

c

t

e

d

O

S

C

1

2

O

S

C

i

r

c

u

i

t

O

S

C

1

2

S

e

R

i

g

h

t

S

i

d

e

I

w

n

t

e

r

n

a

l

R

C

O

s

c

i

l

a

t

o

r

1

0

p

F

3

2

7

6

8

H

S

z

i

t

h

R

T

C

P

C

0

1

/

I

T

N

T

M

R

H

T

4

8

R

1

0

A

-

1

/

H

T

4

8

C

1

0

-

1

O

S

C

i

r

c

u

i

t

Note: The resistance and capacitance for reset circuit should be designed to ensure that the VDD is stable and re-

mains in a valid range of the operating voltage before bringing RES to high.

²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise

interference.

The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For refer-

ence only)

Crystal or Resonator

4MHz Crystal

C1, C2

0pF

R1

10kW

12kW

10kW

27kW

9.1kW

10kW

4MHz Resonator

10pF

0pF

3.58MHz Crystal

3.58MHz Resonator

2MHz Crystal & Resonator

1MHz Crystal

25pF

35pF

300pF

480kHz Resonator

455kHz Resonator

429kHz Resonator

The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage condi-

tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the

MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.

Rev. 2.01

18

January 9, 2009

HT48R10A-1/HT48C10-1

Instruction Set

Introduction

subtract instruction mnemonics to enable the necessary

arithmetic to be carried out. Care must be taken to en-

sure correct handling of carry and borrow data when re-

sults exceed 255 for addition and less than 0 for

subtraction. The increment and decrement instructions

INC, INCA, DEC and DECA provide a simple means of

increasing or decreasing by a value of one of the values

in the destination specified.

Central to the successful operation of any

microcontroller is its instruction set, which is a set of pro-

gram instruction codes that directs the microcontroller to

perform certain operations. In the case of Holtek

microcontrollers, a comprehensive and flexible set of

over 60 instructions is provided to enable programmers

to implement their application with the minimum of pro-

gramming overheads.

Logical and Rotate Operations

For easier understanding of the various instruction

codes, they have been subdivided into several func-

tional groupings.

The standard logical operations such as AND, OR, XOR

and CPL all have their own instruction within the Holtek

microcontroller instruction set. As with the case of most

instructions involving data manipulation, data must pass

through the Accumulator which may involve additional

programming steps. In all logical data operations, the

zero flag may be set if the result of the operation is zero.

Another form of logical data manipulation comes from

the rotate instructions such as RR, RL, RRC and RLC

which provide a simple means of rotating one bit right or

left. Different rotate instructions exist depending on pro-

gram requirements. Rotate instructions are useful for

serial port programming applications where data can be

rotated from an internal register into the Carry bit from

where it can be examined and the necessary serial bit

set high or low. Another application where rotate data

operations are used is to implement multiplication and

division calculations.

Instruction Timing

Most instructions are implemented within one instruc-

tion cycle. The exceptions to this are branch, call, or ta-

ble read instructions where two instruction cycles are

required. One instruction cycle is equal to 4 system

clock cycles, therefore in the case of an 8MHz system

oscillator, most instructions would be implemented

within 0.5ms and branch or call instructions would be im-

plemented within 1ms. Although instructions which re-

quire one more cycle to implement are generally limited

to the JMP, CALL, RET, RETI and table read instruc-

tions, it is important to realize that any other instructions

which involve manipulation of the Program Counter Low

register or PCL will also take one more cycle to imple-

ment. As instructions which change the contents of the

PCL will imply a direct jump to that new address, one

more cycle will be required. Examples of such instruc-

tions would be ²CLR PCL² or ²MOV PCL, A². For the

case of skip instructions, it must be noted that if the re-

sult of the comparison involves a skip operation then

this will also take one more cycle, if no skip is involved

then only one cycle is required.

Branches and Control Transfer

Program branching takes the form of either jumps to

specified locations using the JMP instruction or to a sub-

routine using the CALL instruction. They differ in the

sense that in the case of a subroutine call, the program

must return to the instruction immediately when the sub-

routine has been carried out. This is done by placing a

return instruction RET in the subroutine which will cause

the program to jump back to the address right after the

CALL instruction. In the case of a JMP instruction, the

program simply jumps to the desired location. There is

no requirement to jump back to the original jumping off

point as in the case of the CALL instruction. One special

and extremely useful set of branch instructions are the

conditional branches. Here a decision is first made re-

garding the condition of a certain data memory or indi-

vidual bits. Depending upon the conditions, the program

will continue with the next instruction or skip over it and

jump to the following instruction. These instructions are

the key to decision making and branching within the pro-

gram perhaps determined by the condition of certain in-

put switches or by the condition of internal data bits.

Moving and Transferring Data

The transfer of data within the microcontroller program

is one of the most frequently used operations. Making

use of three kinds of MOV instructions, data can be

transferred from registers to the Accumulator and

vice-versa as well as being able to move specific imme-

diate data directly into the Accumulator. One of the most

important data transfer applications is to receive data

from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and

data manipulation is a necessary feature of most

microcontroller applications. Within the Holtek

microcontroller instruction set are a range of add and

Rev. 2.01

19

January 9, 2009

HT48R10A-1/HT48C10-1

Bit Operations

Other Operations

The ability to provide single bit operations on Data Mem-

ory is an extremely flexible feature of all Holtek

microcontrollers. This feature is especially useful for

output port bit programming where individual bits or port

pins can be directly set high or low using either the ²SET

[m].i² or ²CLR [m].i² instructions respectively. The fea-

ture removes the need for programmers to first read the

8-bit output port, manipulate the input data to ensure

that other bits are not changed and then output the port

with the correct new data. This read-modify-write pro-

cess is taken care of automatically when these bit oper-

ation instructions are used.

In addition to the above functional instructions, a range

of other instructions also exist such as the ²HALT² in-

struction for Power-down operations and instructions to

control the operation of the Watchdog Timer for reliable

program operations under extreme electric or electro-

magnetic environments. For their relevant operations,

refer to the functional related sections.

Instruction Set Summary

The following table depicts a summary of the instruction

set categorised according to function and can be con-

sulted as a basic instruction reference using the follow-

ing listed conventions.

Table Read Operations

Table conventions:

Data storage is normally implemented by using regis-

ters. However, when working with large amounts of

fixed data, the volume involved often makes it inconve-

nient to store the fixed data in the Data Memory. To over-

come this problem, Holtek microcontrollers allow an

area of Program Memory to be setup as a table where

data can be directly stored. A set of easy to use instruc-

tions provides the means by which this fixed data can be

referenced and retrieved from the Program Memory.

x: Bits immediate data

m: Data Memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Mnemonic

Arithmetic

Description

Cycles Flag Affected

ADD A,[m]

ADDM A,[m]

ADD A,x

Add Data Memory to ACC

1

1^Note

1

Z, C, AC, OV

C

Add ACC to Data Memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add Data Memory to ACC with Carry

1

1^Note

Add ACC to Data memory with Carry

Subtract immediate data from the ACC

Subtract Data Memory from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

1

1^Note

Subtract Data Memory from ACC with result in Data Memory

Subtract Data Memory from ACC with Carry

Subtract Data Memory from ACC with Carry, result in Data Memory

Decimal adjust ACC for Addition with result in Data Memory

1

1^Note

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

Logical AND Data Memory to ACC

Logical OR Data Memory to ACC

Logical XOR Data Memory to ACC

Logical AND ACC to Data Memory

Logical OR ACC to Data Memory

Logical XOR ACC to Data Memory

Logical AND immediate Data to ACC

Logical OR immediate Data to ACC

Logical XOR immediate Data to ACC

Complement Data Memory

1

Z

1

1^Note

1

OR A,x

1

XOR A,x

1

1^Note

CPL [m]

CPLA [m]

Complement Data Memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment Data Memory with result in ACC

1

Z

Increment Data Memory

1^Note

DECA [m]

DEC [m]

Decrement Data Memory with result in ACC

Decrement Data Memory

1

1^Note

Rev. 2.01

20

January 9, 2009

HT48R10A-1/HT48C10-1

Mnemonic

Rotate

Description

Cycles Flag Affected

RRA [m]

RR [m]

Rotate Data Memory right with result in ACC

Rotate Data Memory right

1

1^Note

1

1^Note

1

1^Note

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate Data Memory right through Carry with result in ACC

Rotate Data Memory right through Carry

Rotate Data Memory left with result in ACC

Rotate Data Memory left

C

None

C

RLCA [m]

RLC [m]

Rotate Data Memory left through Carry with result in ACC

Rotate Data Memory left through Carry

1

1^Note

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move Data Memory to ACC

Move ACC to Data Memory

Move immediate data to ACC

1

1^Note

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of Data Memory

Set bit of Data Memory

1^Note

None

Branch

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if Data Memory is zero

1^Note

1^note

1^Note

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if Data Memory is zero with data movement to ACC

Skip if bit i of Data Memory is zero

Skip if bit i of Data Memory is not zero

Skip if increment Data Memory is zero

Skip if decrement Data Memory is zero

Skip if increment Data Memory is zero with result in ACC

Skip if decrement Data Memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m]

TABRDL [m]

Read table (current page) to TBLH and Data Memory

Read table (last page) to TBLH and Data Memory

2^Note

None

Miscellaneous

NOP

No operation

1

1^Note

1

None

CLR [m]

Clear Data Memory

SET [m]

Set Data Memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO, PDF

None

Pre-clear Watchdog Timer

Swap nibbles of Data Memory

Swap nibbles of Data Memory with result in ACC

Enter power down mode

1

1^Note

1

None

1

TO, PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by

the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and

²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags

remain unchanged.

Rev. 2.01

21

January 9, 2009

HT48R10A-1/HT48C10-1

Instruction Definition

ADC A,[m]

Add Data Memory to ACC with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the Accumulator.

Operation

ACC ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADCM A,[m]

Add ACC to Data Memory with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADD A,[m]

Add Data Memory to ACC

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

ADD A,x

Add immediate data to ACC

Description

The contents of the Accumulator and the specified immediate data are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + x

Affected flag(s)

OV, Z, AC, C

ADDM A,[m]

Add ACC to Data Memory

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

AND A,[m]

Logical AND Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

Z

AND A,x

Logical AND immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical AND

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

Z

ANDM A,[m]

Logical AND ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

Z

Rev. 2.01

22

January 9, 2009

HT48R10A-1/HT48C10-1

CALL addr

Subroutine call

Description

Unconditionally calls a subroutine at the specified address. The Program Counter then in-

crements by 1 to obtain the address of the next instruction which is then pushed onto the

stack. The specified address is then loaded and the program continues execution from this

new address. As this instruction requires an additional operation, it is a two cycle instruc-

tion.

Operation

Stack ¬ Program Counter + 1

Program Counter ¬ addr

Affected flag(s)

None

CLR [m]

Clear Data Memory

Description

Operation

Each bit of the specified Data Memory is cleared to 0.

[m] ¬ 00H

Affected flag(s)

None

CLR [m].i

Clear bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

None

CLR WDT

Description

Operation

Clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared.

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT1

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT2 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT2

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT1 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

Rev. 2.01

23

January 9, 2009

HT48R10A-1/HT48C10-1

CPL [m]

Complement Data Memory

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa.

Operation

[m] ¬ [m]

Affected flag(s)

Z

CPLA [m]

Complement Data Memory with result in ACC

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa. The complemented result

is stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

Z

DAA [m]

Decimal-Adjust ACC for addition with result in Data Memory

Description

Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-

sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or

if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble

remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of

6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-

ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C

flag may be affected by this instruction which indicates that if the original BCD sum is

greater than 100, it allows multiple precision decimal addition.

Operation

[m] ¬ ACC + 00H or

[m] ¬ ACC + 06H or

[m] ¬ ACC + 60H or

[m] ¬ ACC + 66H

Affected flag(s)

C

DEC [m]

Decrement Data Memory

Description

Operation

Data in the specified Data Memory is decremented by 1.

[m] ¬ [m] - 1

Affected flag(s)

Z

DECA [m]

Decrement Data Memory with result in ACC

Description

Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-

mulator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] - 1

Affected flag(s)

Z

HALT

Enter power down mode

Description

This instruction stops the program execution and turns off the system clock. The contents

of the Data Memory and registers are retained. The WDT and prescaler are cleared. The

power down flag PDF is set and the WDT time-out flag TO is cleared.

Operation

TO ¬ 0

PDF ¬ 1

Affected flag(s)

TO, PDF

Rev. 2.01

24

January 9, 2009

HT48R10A-1/HT48C10-1

INC [m]

Increment Data Memory

Description

Operation

Data in the specified Data Memory is incremented by 1.

[m] ¬ [m] + 1

Affected flag(s)

Z

INCA [m]

Increment Data Memory with result in ACC

Description

Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-

lator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] + 1

Affected flag(s)

Z

JMP addr

Jump unconditionally

Description

The contents of the Program Counter are replaced with the specified address. Program

execution then continues from this new address. As this requires the insertion of a dummy

instruction while the new address is loaded, it is a two cycle instruction.

Operation

Program Counter ¬ addr

Affected flag(s)

None

MOV A,[m]

Description

Operation

Move Data Memory to ACC

The contents of the specified Data Memory are copied to the Accumulator.

ACC ¬ [m]

Affected flag(s)

None

MOV A,x

Move immediate data to ACC

Description

Operation

The immediate data specified is loaded into the Accumulator.

ACC ¬ x

Affected flag(s)

None

MOV [m],A

Description

Operation

Move ACC to Data Memory

The contents of the Accumulator are copied to the specified Data Memory.

[m] ¬ ACC

Affected flag(s)

None

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

No operation

None

OR A,[m]

Logical OR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-

ation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

Z

Rev. 2.01

25

January 9, 2009

HT48R10A-1/HT48C10-1

OR A,x

Logical OR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

Z

ORM A,[m]

Logical OR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-

ation. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²OR² [m]

Affected flag(s)

Z

RET

Return from subroutine

Description

The Program Counter is restored from the stack. Program execution continues at the re-

stored address.

Operation

Program Counter ¬ Stack

Affected flag(s)

None

RET A,x

Return from subroutine and load immediate data to ACC

Description

The Program Counter is restored from the stack and the Accumulator loaded with the

specified immediate data. Program execution continues at the restored address.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

None

RETI

Return from interrupt

Description

The Program Counter is restored from the stack and the interrupts are re-enabled by set-

ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending

when the RETI instruction is executed, the pending Interrupt routine will be processed be-

fore returning to the main program.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

None

RL [m]

Rotate Data Memory left

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ [m].7

Affected flag(s)

None

RLA [m]

Rotate Data Memory left with result in ACC

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-

main unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ [m].7

Affected flag(s)

None

Rev. 2.01

26

January 9, 2009

HT48R10A-1/HT48C10-1

RLC [m]

Rotate Data Memory left through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7

replaces the Carry bit and the original carry flag is rotated into bit 0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RLCA [m]

Rotate Data Memory left through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces

the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in

the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RR [m]

Rotate Data Memory right

Description

The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into

bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ [m].0

Affected flag(s)

None

RRA [m]

Rotate Data Memory right with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-

tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data

Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ [m].0

Affected flag(s)

None

RRC [m]

Rotate Data Memory right through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0

replaces the Carry bit and the original carry flag is rotated into bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

C

RRCA [m]

Rotate Data Memory right through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-

places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is

stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

C

Rev. 2.01

27

January 9, 2009

HT48R10A-1/HT48C10-1

SBC A,[m]

Subtract Data Memory from ACC with Carry

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result

of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or

zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SBCM A,[m]

Subtract Data Memory from ACC with Carry and result in Data Memory

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-

sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is

positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SDZ [m]

Skip if decrement Data Memory is 0

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0 the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] - 1

Skip if [m] = 0

Affected flag(s)

None

SDZA [m]

Skip if decrement Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0, the program proceeds with the following instruction.

Operation

ACC ¬ [m] - 1

Skip if ACC = 0

Affected flag(s)

None

SET [m]

Set Data Memory

Description

Operation

Each bit of the specified Data Memory is set to 1.

[m] ¬ FFH

Affected flag(s)

None

SET [m].i

Set bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is set to 1.

[m].i ¬ 1

Affected flag(s)

None

Rev. 2.01

28

January 9, 2009

HT48R10A-1/HT48C10-1

SIZ [m]

Skip if increment Data Memory is 0

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] + 1

Skip if [m] = 0

Affected flag(s)

None

SIZA [m]

Skip if increment Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0 the program proceeds with the following instruction.

Operation

ACC ¬ [m] + 1

Skip if ACC = 0

Affected flag(s)

None

SNZ [m].i

Skip if bit i of Data Memory is not 0

Description

If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is 0 the program proceeds with the following instruction.

Operation

Skip if [m].i ¹ 0

Affected flag(s)

None

SUB A,[m]

Subtract Data Memory from ACC

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUBM A,[m]

Subtract Data Memory from ACC with result in Data Memory

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUB A,x

Subtract immediate data from ACC

Description

The immediate data specified by the code is subtracted from the contents of the Accumu-

lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-

tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will

be set to 1.

Operation

ACC ¬ ACC - x

Affected flag(s)

OV, Z, AC, C

Rev. 2.01

29

January 9, 2009

HT48R10A-1/HT48C10-1

SWAP [m]

Description

Operation

Swap nibbles of Data Memory

The low-order and high-order nibbles of the specified Data Memory are interchanged.

[m].3~[m].0 « [m].7 ~ [m].4

Affected flag(s)

None

SWAPA [m]

Swap nibbles of Data Memory with result in ACC

Description

The low-order and high-order nibbles of the specified Data Memory are interchanged. The

result is stored in the Accumulator. The contents of the Data Memory remain unchanged.

Operation

ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4

ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0

Affected flag(s)

None

SZ [m]

Skip if Data Memory is 0

Description

If the contents of the specified Data Memory is 0, the following instruction is skipped. As

this requires the insertion of a dummy instruction while the next instruction is fetched, it is a

two cycle instruction. If the result is not 0 the program proceeds with the following instruc-

tion.

Operation

Skip if [m] = 0

None

Affected flag(s)

SZA [m]

Skip if Data Memory is 0 with data movement to ACC

Description

The contents of the specified Data Memory are copied to the Accumulator. If the value is

zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-

tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the

program proceeds with the following instruction.

Operation

ACC ¬ [m]

Skip if [m] = 0

Affected flag(s)

None

SZ [m].i

Skip if bit i of Data Memory is 0

Description

If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is not 0, the program proceeds with the following instruction.

Operation

Skip if [m].i = 0

None

Affected flag(s)

TABRDC [m]

Read table (current page) to TBLH and Data Memory

Description

The low byte of the program code (current page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

TABRDL [m]

Read table (last page) to TBLH and Data Memory

Description

The low byte of the program code (last page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

Rev. 2.01

30

January 9, 2009

HT48R10A-1/HT48C10-1

XOR A,[m]

Logical XOR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XORM A,[m]

Logical XOR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XOR A,x

Logical XOR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical XOR

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

Z

Rev. 2.01

31

January 9, 2009

HT48R10A-1/HT48C10-1

Package Information

24-pin SKDIP (300mil) Outline Dimensions

A

2

4

1

3

2

1

3

2

4

B

1

H

C

D

C

D

I

E

F

G

E

F

G

Fig2. 1/2 Lead Packages

Fig1. Full Lead Packages

·

MS-001d (see fig1)

Dimensions in mil

Nom.

Symbol

Min.

1230

240

115

14

Max.

1280

280

195

150

22

A

B

C

D

E

F

G

H

I

¾

45

70

¾

100

¾

300

¾

325

430

¾

·

MS-001d (see fig2)

Dimensions in mil

Nom.

Symbol

Min.

1160

240

115

14

Max.

1195

280

195

150

22

A

B

C

D

E

F

G

H

I

¾

45

70

¾

100

¾

300

¾

325

430

¾

Rev. 2.01

32

January 9, 2009

HT48R10A-1/HT48C10-1

·

MO-095a (see fig2)

Dimensions in mil

Symbol

Min.

1145

275

120

110

14

Nom.

¾

Max.

1185

295

150

22

A

B

C

D

E

F

G

H

I

¾

45

60

¾

100

¾

300

¾

325

430

¾

Rev. 2.01

33

January 9, 2009

HT48R10A-1/HT48C10-1

24-pin SOP (300mil) Outline Dimensions

2

4

1

3

A

B

1

2

C

'

G

H

D

a

E

F

·

MS-013

Dimensions in mil

Nom.

Symbol

Min.

393

256

12

598

¾

Max.

419

300

20

A

B

C

C¢

D

E

F

¾

50

¾

613

104

¾

4

12

G

H

a

16

8

50

13

0°

8°

Rev. 2.01

34

January 9, 2009

HT48R10A-1/HT48C10-1

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SOP 24W

Symbol

Description

Dimensions in mm

A

B

Reel Outer Diameter

Reel Inner Diameter

Spindle Hole Diameter

Key Slit Width

330.0±1.0

100.0±1.5

13.0^+0.5/-0.2

C

D

2.0±0.5

24.8^+0.3/-0.2

T1

T2

Space Between Flange

Reel Thickness

30.2±0.2

Rev. 2.01

35

January 9, 2009

HT48R10A-1/HT48C10-1

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

W

B

0

C

D

1

P

K

0

A

0

R

e

l

H

o

l

e

I

C

p

a

c

k

a

g

e

p

i

n

1

a

n

d

t

h

e

r

e

l

h

o

l

e

s

a

r

e

l

o

c

a

t

e

d

o

n

t

h

e

s

a

m

e

s

i

d

e

.

SOP 24W

Symbol

Description

Dimensions in mm

24.0±0.3

12.0±0.1

1.75±0.1

11.5±0.1

1.55+0.1

1.5+0.25

4.0±0.1

W

P

Carrier Tape Width

Cavity Pitch

E

Perforation Position

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

2.0±0.1

10.9±0.1

15.9±0.1

3.1±0.1

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

0.35±0.05

21.3

C

Rev. 2.01

36

January 9, 2009

HT48R10A-1/HT48C10-1

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103

Tel: 86-21-5422-4590

Fax: 86-21-5422-4705

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057

Tel: 86-755-8616-9908, 86-755-8616-9308

Fax: 86-755-8616-9722

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752

Fax: 86-10-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016

Tel: 86-28-6653-6590

Fax: 86-28-6653-6591

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538

Tel: 1-510-252-9880

Fax: 1-510-252-9885

http://www.holtek.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 2.01

37

January 9, 2009


型号：	HT48R10A-1(24SOP-A)
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Microcontroller, 8-Bit, MROM, 8MHz, CMOS, PDSO24 微控制器光电二极管
文件：	总37页 (文件大小：247K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT48R10A-1(24SOP-A) [HOLTEK]

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