HT48R54A_10
更新时间：2024-09-18 11:30:02
品牌：HOLTEK
描述：I/O Type 8-Bit OTP MCU with 1616 High Current LED Driver
概述
数据手册HT48R54A_10 概述
I/O Type 8-Bit OTP MCU with 1616 High Current LED Driver I / O型8位OTP MCU与16'16高电流LED驱动器
HT48R54A_10 数据手册
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PDF下载HT48R54A
I/O Type 8-Bit OTP MCU with 16´ 16 High Current LED Driver
Technical Document
·
Tools Information
·
FAQs
·
Application Note
-
HA0002E Reading Larger than Usual MCU Tables
-
-
-
-
HA0007E Using the MCU Look Up Table Instructions
HA0019E Using the Watchdog Timer in the HT48 MCU Series
HA0020E Using the Timer/Event Counter in the HT48 MCU Series
HA0075E MCU Reset and Oscillator Circuits Application Note
Features
·
·
·
·
Operating voltage:
PFD/Buzzer driver output
fSYS=32768Hz: 2.2V~5.5V
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
RC/XTAL and 32768Hz crystal oscillator
Dual clock system offers three operating modes
-
Normal mode: Both RC/XTAL and 32768Hz clock
·
·
·
·
·
·
·
·
·
·
·
·
·
4k´15 program memory ROM
192´8 data memory RAM
8 bidirectional I/O lines
active
-
Slow mode: 32768Hz clock only
-
Idle mode: Periodical wake-up by watchdog timer
overflow
Max. 16´16 LED driver output
8 LED shared I/O lines
·
HALT function and wake-up feature reduce power
consumption
24 LED shared output
·
·
·
·
·
·
·
15-bit table read instructions
One external interrupt input
Two internal interrupt
63 powerful instructions
One instruction cycle: 4 system clock periods
All instructions in 1 or 2 instruction cycles
Bit manipulation instructions
Two 8 bit programmable timer/event counter
32768 Real Time Clock function
6-level subroutine nesting
Watchdog Timer (WDT)
Up to 0.5ms instruction cycle with 8MHz system clock
44/52-pin QFP and 44-pin LQFP packages
Low voltage reset (LVR)
General Description
This device is an 8-bit high performance, RISC architec-
ture microcontroller specifically designed for multiple
I/O control product applications. The advantages of low
power consumption, I/O flexibility, timer functions, oscil-
lator options, HALT and wake-up functions, watchdog
timer, as well as low cost, enhance the versatility of
these devices to suit a wide range of application possi-
bilities such as industrial control, consumer products,
subsystem controllers, etc.
Rev. 1.20
1
April 28, 2010
HT48R54A
Block Diagram
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Rev. 1.20
2
April 28, 2010
HT48R54A
Pin Assignment
4
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4
5
6
7
4
4
4
4
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1
Pin Description
Pin Name I/O
Options
Description
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt trigger input. A pull-high resistor can be con-
nected via configuration option. Each pin can be setup to be a wake-up input
via configuration options.
PA0/BZ
PA1/BZ
Pull-high
Wake-up
Buzzer
PFD
PA2/TMR0
I/O
The PA0 and PA1 are pin-shared with the BZ and BZ, respectively.
The timer input TMR0 is pin-shared with PA2.
PA3/TMR1
PA4~PA6
PA7/PFD
The timer input TMR1 is pin-shared with PA3.
The PFD function is pin-shared with PA7 which is determined by configuration
option.
Bidirectional 8-bit input/output port. When used as output port, they are config-
ured as PMOS output pins.
PB0~PB7
PC0~PC7
PD0/INT
I/O
O
¾
¾
¾
PC0~PC7 are PMOS output pins.
External interrupt input. Pin-shared with PD0 and activated on a high to low or
low to high transition. PD0 is NMOS type output pin.
I/O
PD1~PD7
PE0~PE7
RES
O
O
I
PD1~PD7 are NMOS output pins.
¾
¾
¾
PE0~PE7 are NMOS output pins.
Schmitt trigger reset input. Active low.
OSC1 and OSC2 are connected to an RC network or a crystal (by options) for
OSC1
OSC2
I
RC or Crystal the internal system clock. In the case of RC operation, OSC2 is the output ter-
minal for 1/4 system clock.
O
OSC3
OSC4
I
Real time clock oscillator. OSC3 and OSC4 are connected to a 32768Hz crys-
¾
O
tal oscillator for system clock timing purposes.
VDD
Positive power supply
¾
¾
¾
¾
¾
VDDB
VDDC
VSS
PB port positive power supply
¾
PC port positive power supply
¾
Negative Power supply, ground
¾
VSSD,
VSSE
PD & PE port negative power supply, ground
¾
¾
Rev. 1.20
3
April 28, 2010
HT48R54A
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
I
OL Total ..............................................................300mA
I
OH Total............................................................-200mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
f
SYS=4MHz
2.2
3.3
2.2
¾
5.5
5.5
5.5
2
¾
¾
VDD
fSYS=8MHz
Operating Voltage
V
¾
fSYS=32768Hz
¾
¾
3V
5V
1.2
2.5
Operating Current
IDD1
No load, fSYS=4MHz
No load, fSYS=8MHz
mA
mA
(Crystal OSC, RC OSC)
5
¾
Operating Current
IDD2
5V
4
8
¾
(Crystal OSC, RC OSC)
Operating Current
3V
5V
20
50
40
¾
¾
No load,
IDD3
(*RTC OSC Enabled, Crystal OSC
Disabled, RC OSC Disabled)
mA
fSYS=32768Hz
100
3V
5V
3V
5V
3V
5V
3V
5V
¾
3
6
1
2
2
4
5
10
¾
¾
Standby Current
No load,
ISTB1
ISTB2
ISTB3
ISTB4
mA
mA
mA
mA
(WDT OSC, *RTC OSC Enabled)
system HALT
2
¾
Standby Current (WDT OSC Disabled,
*RTC OSC Enabled)
No load,
system HALT
4
¾
4
¾
Standby Current (WDT OSC Enabled,
RTC OSC Disabled)
No load,
system HALT
8
¾
1
¾
¾
¾
Standby Current
No load,
(WDT OSC, RTC OSC Disabled)
system HALT
2
¾
VIL1
VIH1
VIL2
VIH2
0.3VDD
VDD
0.4VDD
VDD
2.22
3.32
4.42
¾
Input Low Voltage for I/O Ports
Input High Voltage for I/O Ports
Input Low Voltage (RES)
0
V
V
V
V
V
V
V
¾
¾
¾
0.7VDD
¾
¾
0
0.9VDD
1.98
2.98
3.98
4
¾
¾
¾
Input High Voltage (RES)
¾
¾
¾
2.1V option
3.15V option
4.2V option
2.1
3.15
4.2
8
VLVR
Low Voltage Reset
¾
3V
5V
3V
5V
IOL1
V
V
OL=0.1VDD
OL=0.1VDD
I/O Port Sink Current for PA
mA
mA
10
20
16
40
¾
8
¾
IOL2
I/O Port Sink Current for PD, PE
20
¾
Rev. 1.20
4
April 28, 2010
HT48R54A
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
mA
mA
kW
VDD
3V
5V
3V
5V
3V
5V
-2
-5
-4
-10
-8
¾
¾
IOH1
V
V
OH=0.9VDD
OH=0.9VDD
¾
I/O Port Source Current for PA
I/O Port Source Current for PB, PC
Pull-high Resistance
-4
¾
IOH2
-10
20
-20
60
¾
100
50
RPH
10
30
Note: * RTC OSC in slow start oscillating
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ. Max.
Unit
VDD
¾
2.2V~5.5V
3.3V~5.5V
2.2V~5.5V
3.3V~5.5V
¾
400
400
0
4000
¾
System Clock
fSYS
kHz
kHz
(Crystal OSC, RC OSC)
8000
¾
¾
4000
¾
¾
fTIMER
Timer I/P Frequency
0
8000
¾
¾
3V
5V
45
32
90
65
180
130
ms
ms
tWDTOSC
Watchdog Oscillator Period
¾
fSP Time-out Period Clock Source
from WDT
With prescaler
(fS/4096)
221
tFSP1
tWDTOSC
¾
¾
¾
fSP Time-out Period Clock Source
from RTC Oscillator
With prescaler
(fS/4096)
221
¾
tFSP2
tRES
tSST
*tRTC
¾
¾
¾
¾
1
¾
¾
¾
External Reset Low Pulse Width
System Start-up Timer Period
¾
ms
Power-up or wake-up
from HALT
tSYS
1024
¾
tLVR
tINT
Low Voltage Width to Reset
Interrupt Pulse Width
0.25
1
1
2
ms
¾
¾
¾
¾
¾
¾
ms
Note: tSYS=1/fSYS
*tRTC@30.5ms
Rev. 1.20
5
April 28, 2010
HT48R54A
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
a crystal oscillator or an RC oscillator or a RTC oscilla-
tor. The system clock is internally divided into four
non-overlapping clocks. One instruction cycle consists
of four system clock cycles.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call or return
from subroutine, initial reset, internal interrupt, external
interrupt or return from interrupt, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of pro-
gram memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
T
1
T
2
T
3
T
1
T
4
T
2
T
3
T
1
T
4
T
2
T
3
T
4
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2
(
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C
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)
P
C
P
C
+
1
P
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+
2
P
C
F
e
t
c
h
I
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T
(
P
C
)
E
x
e
c
u
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T
(
P
C
-
1
)
S T
F
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c
h
I
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(
P
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+
1
)
E
x
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c
u
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I
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T
(
P
C
)
N
F
e
t
c
h
I
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution Flow
Program Counter
Mode
*10
0
*9
0
*8
0
*7
0
*6
0
*5
0
*4
0
*3
0
*2
0
*1
0
*0
0
*11
0
Initial Reset
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Skip
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Program Counter+2
@7 @6 @5 @4 @3 @2 @1 @0
Loading PCL
*11
*10
*9
#9
S9
*8
#8
S8
Jump, Call Branch
#11 #10
S11 S10
#7
S7
#6
S6
#5
S5
#4
S4
#3
S3
#2
S2
#1
S1
#0
S0
Return from Subroutine
Program Counter
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
S11~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.20
6
April 28, 2010
HT48R54A
TBLH is read only and cannot be restored. If the main
routine and the ISR (Interrupt Service Routine) both
employ the table read instruction, the contents of the
TBLH in the main routine are likely to be changed by
the table read instruction used in the ISR, therefore
errors may occur. In other words, using the table read
instruction in the main routine and the ISR simulta-
neously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt should be disabled prior to
using the table read instruction. It should not be en-
abled until the TBLH has been backed up. All table re-
lated instructions require two cycles to complete the
operation. These areas may function as normal pro-
gram memory depending upon the requirements.
Program Memory - ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and ta-
ble pointer.
Certain locations in the program memory are reserved
for special usage:
·
Location 000H
This area is reserved for program initialisation. After a
chip reset, the program always begins execution at lo-
cation 000H.
·
Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
0
0
0
H
D
e
v
i
c
e
I
n
i
t
i
a
l
i
z
a
t
i
o
0
0
0
0
4
8
H
H
E
x
t
e
r
n
a
l
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p
t
T
i
m
e
r
/
E
v
e
n
t
C
o
u
n
t
e
r
0
·
Location 008H
This area is reserved for the timer/event counter 0 inter-
rupt service program. If a timer interrupt results from a
timer/event counter 0 overflow, and if the interrupt is en-
abled and the stack is not full, the program begins exe-
cution at location 008H.
0
0
C
T
H
i
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r
/
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v
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n
t
C
o
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n
t
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r
1
n
0
0
H
P
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M
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m
n
F
F
H
L
o
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k
-
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p
T
a
b
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e
(
2
5
6
·
Location 00CH
This area is reserved for the timer/event counter 1 inter-
rupt service program. If a timer interrupt results from a
timer/event counter 1 overflow, and if the interrupt is en-
abled and the stack is not full, the program begins exe-
cution at location 00CH.
F
0
0
H
L
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k
-
u
p
T
a
b
l
e
(
2
5
6
F
F
F
H
1
5
b
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t
s
N
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e
:
n
r
a
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g
e
s
f
r
o
m
0
Program Memory
Stack Register - STACK
·
Table location
Any location in the program memory space can be
used as look-up tables. The instructions ²TABRDC
[m]² (the current page, one page=256 words) and
²TABRDL [m]² (the last page) transfer the contents of
the lower-order byte to the specified data memory,
and the higher-order byte to TBLH (08H). Only the
destination of the lower-order byte in the table is
well-defined, the other bits of the table word are trans-
ferred to the lower portion of the TBLH, and the re-
maining 1-bit words are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The ta-
ble pointer (TBLP) is a read/write register (07H),
which indicates the table location. Before accessing
the table, the location must be placed in the TBLP. The
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction, RET or RETI, the pro-
gram counter is restored to its previous value from the
stack. After a chip reset, the stack pointer will point to
the top of the stack.
Table Location
Instruction
*11
P11
1
*10
P10
1
*9
P9
1
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Table Location
P11~P8: Current program counter bits
Note: *11~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.20
7
April 28, 2010
HT48R54A
I
I
A
A
R
R
0
1
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
If the stack is full and a non-masked interrupt takes place,
the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented, by RET or RET, the interrupt will
be serviced. This feature prevents stack overflow
allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is
subsequently executed, a stack overflow occurs and the
first entry will be lost. Only the most recent 6 return
addresses are stored.
M
M
P
P
0
1
A
C
C
P
C
L
T
B
L
P
T
B
L
H
0
0
A
B
H
S
T
A
T
U
S
H
I
N
T
C
0
1
Data Memory - RAM
0
0
C
D
H
H
H
The data memory is divided into two functional groups,
namely, function registers and general purpose data
memory (192´8). Most are read/write, but some are
read only.
T
M
R
0
0
E
T
M
R
C
0
F
H
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
T
M
R
1
S
p
e
c
i
a
l
T
M
R
C
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
the memory pointer registers.
D
a
t
a
M
e
P
P
A
B
P
P
A
B
C
C
P
P
C
D
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] ([02H]) will access the data memory
pointed to by MP0 (MP1). Reading location 00H (02H)
itself indirectly will return the result ²00H². Writing indi-
rectly results in no operation.
1
1
A
B
H
P
E
H
1
1
C
D
H
H
H
1
E
1
F
H
The memory pointer registers, MP0 and MP1, are 8-bit
registers.
2
0
H
M
O
D
E
Accumulator
4
0
H
G
e
n
e
r
a
l
P
u
r
p
o
s
e
:
U
n
u
s
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
D
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M
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1
9
2
B
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F
F
H
RAM Mapping
Arithmetic and Logic Unit - ALU
(TO). It also records the status information and controls
the operation sequence.
This circuit performs 8-bit arithmetic and logic opera-
tions. The ALU provides the following functions:
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
tion, operations related to the status register may
give different results from those intended. The TO
flag can be affected only by a system power-up, a
WDT time-out or executing the ²CLR WDT² or
²HALT² instruction. The PDF flag can be affected
only by executing the ²HALT² or ²CLR WDT² instruc-
tion or during a system power-up.
·
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
·
Logic operations (AND, OR, XOR, CPL)
·
Rotation (RL, RR, RLC, RRC)
·
Increment and Decrement (INC, DEC)
·
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Rev. 1.20
8
April 28, 2010
HT48R54A
Bit No.
Label
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a
rotate through carry instruction.
0
C
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow
from the high nibble into the low nibble in subtraction, otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa, otherwise OV is cleared.
OV
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
4
PDF
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
5
TO
TO is set by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
STATUS (0AH) Register
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status register are important and if the subroutine
can corrupt the status register, precautions must be
taken to save it properly.
All interrupts have a wake-up capability. When an inter-
rupt is serviced, a control transfer occurs by pushing the
program counter onto the stack, followed by a branch to
a subroutine at specified location in the program mem-
ory. Only the program counter is pushed onto the stack.
If the contents of the register or status register are al-
tered by the interrupt service program, an action which
may corrupt the desired control sequence, the contents
should be saved in advance.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupt. The Interrupt Control Reg-
ister (INTC;0BH) contains the interrupt control bits to set
the enable or disable bits and the interrupt request flags.
An external interrupt is triggered either on a high to low
or low to high transition on the INT pin. The related inter-
rupt request flag, EIF; bit 4 of the INTC register will then
be set. When the interrupt is enabled, the stack is not full
and the external interrupt is active, a subroutine call to
location 04H will occur. The interrupt request flag (EIF)
and EMI bits will be cleared to disable other interrupts.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related in-
terrupt is enabled, until the SP is decremented. If immedi-
ate service is desired, the stack must be prevented from
becoming full.
The internal timer/event counter 0 interrupt is initialised
by setting the timer/event counter 0 interrupt request
flag, T0F; bit 5 of the INTC register. This will be caused
by a timer 0 overflow. When the interrupt is enabled, the
stack is not full and the T0F bit is set, a subroutine call to
location 08H will occur. The related interrupt request
flag, T0F, will then be reset and the EMI bit cleared to
disable further interrupts.
Bit No.
Label
EMI
EEI
Function
0
1
2
3
4
5
6
7
Controls the master (global) interrupt (1=enable; 0=disable)
Controls the external interrupt (1=enable; 0=disable)
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
External interrupt request flag (1=active; 0=inactive)
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
Unused bit, read as ²0²
ET0I
ET1I
EIF
T0F
T1F
¾
INTC (0BH) Register
Rev. 1.20
9
April 28, 2010
HT48R54A
The internal timer/event counter 1 interrupt is initialised
by setting the timer/event counter 1 interrupt request
flag, T1F; bit 6 of the INTC register. This will be caused
by a timer 1 overflow. When the interrupt is enabled, the
stack is not full and the T1F bit is set, a subroutine call to
location 0CH will occur. The related interrupt request
flag, T1F, will then be reset and the EMI bit cleared to
disable further interrupts.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Inter-
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well con-
trolled, the original control sequence will be damaged if a
²CALL² is executed in the interrupt subroutine.
Oscillator Configuration
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the ²RETI² in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1, if the stack is not full. To
return from the interrupt subroutine, a ²RET² or ²RETI²
instruction may be invoked. RETI will set the EMI bit to
enable an interrupt service, but RET will not.
These devices provide three types of system oscillator
circuits, an crystal oscillator, an RC oscillator and a
32768Hz crystal oscillator, the choice crystal or RC os-
cillator is determined by configuration option.
If an RC oscillator is used, an external resistor, whose
resistance must range from 130kW to 2.5MW, should be
connected between OSC1 and VSS. The RC oscillator
provides the most cost effective solution, however, the
frequency of oscillation may vary with VDD, tempera-
tures and the chip itself due to process variations. It is,
therefore, not suitable for timing sensitive operations
where an accurate oscillator frequency is desired.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The other oscillator circuit is designed for the real time
clock. For this device, only a 32768Hz crystal oscillator
can be used. The crystal should be connected between
OSC3 and OSC4.
Interrupt Source
External Interrupt
Priority Vector
1
2
3
04H
08H
0CH
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
The RTC oscillator circuit can be controlled to start up
quickly by setting the ²QOSC² bit (bit 4 of mode). It is
recommended to turn on the quick oscillating function at
power on until the RTC oscillator is stable, and then turn
it off after 2 seconds to reduce power consumption.
The timer/event counter 0 interrupt request flag (T0F),
The timer/event counter 1 interrupt request flag (T1F),
external interrupt request flag (EIF); enable timer/event
counter 0 interrupt bit (ET0I), enable timer/event coun-
ter 1 interrupt bit (ET1I), enable external interrupt bit
(EEI), enable master interrupt bit (EMI) constitute an in-
terrupt control register (INTC) which is located at 0BH in
the data memory. EMI, EEI, ET0I, ET1I are used to con-
trol the enabling/disabling of interrupts. These bits pre-
vent the requested interrupt from being serviced. Once
the interrupt request flags, T0F, T1F and EIF, are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and requires no external components. Although
when the system enters the power down mode, the sys-
tem clock stops, the WDT oscillator will keep running
with a period of approximately 65ms at 5V. The WDT os-
cillator can be disabled by a configuration option to con-
serve power.
V
D
D
4
7
0
p
F
O
S
C
1
O
S
C
3
O
S
C
1
1
0
p
F
R
O
S
C
O
S
C
4
O
S
C
2
f
S
Y
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S
4
O
S
C
2
R
C
O
s
c
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l
a
t
o
r
3
2
7
6
8
H
z
C
r
y
s
t
a
l
O
s
c
i
l
l
C
r
y
s
t
a
l
O
s
c
i
l
l
a
t
o
r
System Oscillator
Rev. 1.20
10
April 28, 2010
HT48R54A
Watchdog Timer - WDT
The WDT time-out under normal mode or slow mode will
initialize a ²chip reset² and set the status bit ²TO². But in
the idle mode, that is after a HALT instruction is exe-
cuted, the time-out will initialize a ²warm reset² and only
the program counter and stack pointer are reset to 0.
The WDT clock source is implemented by a internal WDT
OSC, the external 32768Hz (fRTC) or the instruction clock
(system clock divided by 4), the choice of which is deter-
mined by configuration option. This timer is designed to
prevent software malfunctions or sequences jumping to
an unknown location with unpredictable results. The
Watchdog can be disabled by a configuration option. If
the Watchdog Timer is disabled, all the executions re-
lated to WDT will result in no operation.
To clear the WDT contents (not including the 4-bit di-
vider and the 8-stage prescaler), three methods are
adopted; an external reset (a low level to RES pin), soft-
ware instruction and a ²HALT² instruction.
The software instruction includes a ²CLR WDT² instruc-
tion, and the instruction pair ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one can
be active depending on the configuration option ²WDT²
instruction. If the ²CLR WDT² is selected (i.e. One clear
instruction), any execution of the CLR WDT instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. two clear instructions),
these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip as a result
of a time-out.
If the device operates in a noisy environment, using the
on-chip WDT OSC or 32768Hz crystal oscillator is
strongly recommended.
When the WDT clock source is selected, it will be first di-
vided by 16 (4-stage), and then divided by the TMR0C
prescaler (8-stage), after that, divided by 512 (9-stage)
to get the nominal time-out period. By using the TMR0C
prescaler, longer time-out periods can be realized. Writ-
ing data to PSC2, PSC1, PSC0 can give different
time-out periods. The WDT OSC period is 65ms. This
time-out period may vary with temperature, VDD and
process variations. The WDT OSC keep running in any
operation mode.
Operation Mode
The device support two system clocks and three opera-
tion modes. The system clock can be either an RC/XTAL
oscillator or a 32768Hz RTC. The three operational
modes are, Normal, Slow, or Idle mode. These are all
selected by software.
If the instruction clock (system clock/4) is selected as
the WDT clock source, the WDT operates in the same
manner.
If the WDT clock source is the 32768Hz, the WDT also
operates in the same manner.
S
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m
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4
f
S
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3
2
7
6
8
H
z
4
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8
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2
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P
S
C
8
-
0
t
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-
1
M
9
U
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B
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T
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Watchdog Timer
Bit No.
Label
Function
System clock high/low mode select bit
0= RC/XTAL system clock select
1= 32768Hz system clock select and RC/XTAL system clock stop
0
MODS
Note that if the 32768Hz system clock is selected, then the WDT clock source configura-
tion option must also select the 32768Hz oscillator as its clock source, otherwise unpre-
dictable system operation may occur.
1, 2, 3
4
¾
QOSC
¾
Unused bit, read as ²0²
32768Hz OSC quick start-up
0=quick start; 1=slow start
5, 6, 7
Unused bit, read as ²0²
MODE (20H) Register
Rev. 1.20
11
April 28, 2010
HT48R54A
Mode
Normal
Slow
System Clock
RC/XTAL oscillator
32768Hz
HALT Instruction
No Executed
No Executed
Be executed
MODS
RC Oscillator
32768Hz
On
0
1
x
On
Off
Off
On
Idle
HALT
On
Operation Mode
Power Down Operation - HALT
The RTC oscillator will keep running when the device is
in the HALT mode, if the RTC oscillator is enabled.
The HALT mode is entered using the ²HALT² instruction
and results in the following:
Reset
·
The system oscillator will be turned off but the WDT
Therearethreewaysinwhicharesetcanoccur:
remains operational if its clock source is the internal
WDT oscillator.
·
RES reset during normal operation
·
RES reset during HALT
·
The contents of the on chip RAM and registers remain
·
unchanged.
WDT time-out reset during normal operation
·
The WDT will be cleared. The WDT will resume count-
A the time-out during a HALT is different from the other
chip reset conditions, since it can perform a ²warm re -
set² that resets only the program counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to their ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
ing, if the WDT clock souce is the internal WDT oscil-
lator.
·
All of the I/O ports will maintain their original status.
·
The PDF flag will be set and the TO flag will be cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². After the TO and PDF flags are
examined, the reason behind the reset can be deter-
mined. The PDF flag is cleared by a system power-up or
executing the ²CLR WDT² instruction and is set when
executing the ²HALT² instruction. The TO flag is set if
the WDT time-out occurs, and causes a wake-up that
only resets the program counter and stack pointer, the
other circuits remain in their original status.
TO PDF
RESET Conditions
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
0
u
0
1
1
0
u
1
u
1
WDT time-out during normal operation
WDT wake-up HALT
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each port
A pin can be independently selected to wake up the de-
vice via configuration options. If awakened by an I/O
port stimulus, the program will resume execution at the
next instruction. If awakened by an interrupt, two se-
quences may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
will resume execution at the next instruction. If the inter-
rupt is enabled and the stack is not full, the regular inter-
rupt response takes place. If an interrupt request flag is
set to ²1² before entering the HALT mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 system clock peri-
ods to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
Note: ²u² stands for ²unchanged²
V
D
D
R
E
S
t
S
S
T
S
S
T
T
i
m
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-
o
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t
C
h
i
p
R
e
s
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t
Reset Timing Chart
H
A
L
T
W
a
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m
R
W
D
T
R
E
S
C
o
l
d
R
e
s
S
S
T
1
1
0
-
b
i
t
R
i
p
p
l
e
O
S
C
C
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t
e
r
S
y
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e
m
R
e
s
e
t
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset Configuration
Rev. 1.20
12
April 28, 2010
HT48R54A
V
D
D
V
D
D
To guarantee that the system oscillator is running and
stable, the SST (System Start-up Timer) provides an ex-
tra delay of 1024 system clock pulses when the system
reset (power-up, WDT time-out or RES reset) or when
the system awakes from the HALT state.
0
.
m
0
F
1
1
0
W
0
k
1
0
W
0
k
R
E
S
R
E
S
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en-
able the SST delay.
0
m
. F 1
1
0
W
k
B
a
s
i
c
H
i
-
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An extra option load time delay is added during a system
reset (power-up, WDT time-out at normal mode or RES
reset).
Reset Circuit
Note: Most applications can use the Basic Reset Circuit
as shown, however for applications with extensive noise,
it is recommended to use the Hi-noise Reset Circuit.
The functional unit chip reset status are shown below.
Program Counter
Interrupt
000H
Disable
Clear
Prescaler
Clear. After master reset,
WDT begins counting
WDT
Timer/Event Counter Off
Input/Output Ports
Stack Pointer
Input mode
Points to the top of the stack
The states of the registers are summarised in the table.
Reset
(Power On)
WDT Time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
Register
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
-xxx xxxx
--00 xxxx
--00 -000
xxxx xxxx
00-0 1000
xxxx xxxx
0000 1000
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
---0 ---0
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
-uuu uuuu
--1u uuuu
--00 -000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
-uuu uuuu
--uu uuuu
--00 -000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
-uuu uuuu
--01 uuuu
--00 -000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
-uuu uuuu
--11 uuuu
--uu -uuu
MP1
ACC
PCL
TBLP
TBLH
STATUS
INTC
TMR0
TMR0C
TMR1
TMR1C
PA
xxxx xxxx
00-0 1000
xxxx xxxx
0000 1000
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
---0 ---0
xxxx xxxx
00-0 1000
xxxx xxxx
0000 1000
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
---0 ---0
xxxx xxxx
00-0 1000
xxxx xxxx
0000 1000
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
1111 1111
1111 1111
---0 ---0
uuuu uuuu
uu-u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u ---u
PAC
PB
PBC
PC
PD
PE
MODE
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Rev. 1.20
13
April 28, 2010
HT48R54A
occurs, the counter is reloaded from the timer/event
counter 0 preload register and at the same time gener-
ates the interrupt request flag, T0F; bit 5 of the INTC.
Timer/Event Counter 0
Two Timer/event counters are implemented in the
microcontroller. The timer/event counter 0 contains an
8-bit programmable count-up counter whose clock may
be sourced from an external source or from the system
In the pulse width measurement mode with the T0ON
and T0E bits equal to one, once it goes from low to high
(or high to low if the T0E bits is ²0²) it will start counting
until the TMR0 returns to the original level and resets the
T0ON. The measured result will remain in the
timer/event counter 0 even if the activated transient oc-
curs again. In other words, only one cycle measurement
can be done. Until setting the T0ON, the cycle measure-
ment will function again as long as it receives further
transient pulse. Note that, in this operating mode, the
timer/event counter 0 starts counting not according to
the logic level but according to the transient edges. In
the case of counter overflows, the counter is reloaded
from the timer/event counter 0 preload register and is-
sues the interrupt request just like the other two modes.
To enable the counting operation, the timer 0 ON bit
(T0ON; bit 4 of the TMR0C) should be set to ²1². In the
pulse width measurement mode, the T0ON will be
cleared automatically after the measurement cycle is
completed. But in the other two modes the T0ON can
only be reset by instructions. The overflow of the
timer/event counter 0 is one of the wake-up sources. No
matter what the operation mode is, writing a ²0² to ET0I
can disable the corresponding interrupt services.
clock/4 or fSP
.
The fSP clock source is implemented by the WDT OSC,
an external 32768Hz (fRTC) or an instruction clock (sys-
tem clock divided by 4), determined by configuration op-
tion. If one of these three source is selected, it will be
first divided by 16 (4-stage), and then divided by the
TMR0C prescaler (8-stage) to get an fSP output period.
By using the TMR0C prescaler, longer time-out periods
can be realized. Writing data to P0SC2, P0SC1, P0SC0
can give different fSP output periods.
Using internal clock sources, there are 2 reference
time-bases for the timer/event counter 0. The internal
clock source can be sourced from fSYS/4 or fSP via a con-
figuration options. Using an external clock input allows
the user to count external events, measure time
intervals or pulse widths, or generate an accurate time
base, while using the internal clock allows the user to
generate an accurate time base.
There are two registers related to the timer/event coun-
ter 0; TMR0 ([0DH]) and TMR0C ([0EH]). Writing to
TMR0 places the start value in the timer/event counter 0
preload register while reading the TMR0 register re-
trieves the contents of the timer/event counter 0. The
TMR0C register is a timer/event counter 0 control regis-
ter which defines some options.
In the case of timer/event counter 0 OFF condition, writ-
ing data to the timer/event counter 0 preload register will
also reload that data to the timer/event counter 0. But if
the timer/event counter 0 is turned on, data written to it
will only be kept in the timer/event counter 0 preload reg-
ister. The timer/event counter 0 will still operate until
overflow occurs (a timer/event counter 0 reloading will
occur at the same time). When the timer/event counter 0
(reading TMR0) is read, the clock will be blocked to
avoid errors. As clock blocking may result in a counting
error, this must be taken into consideration by the pro-
grammer. The bit2~bit0 of the TMR0C can be used to
define the pre-scaling stages of the internal clock
sources of the timer/event counter 0. The definitions are
as shown.
The T0M0, T0M1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source must comes from the ex-
ternal timer pin, TMR0. The timer mode functions as a
normal timer with the clock source coming from the fINT
clock. The pulse width measurement mode can be used
to count the duration of a high or low-level signal on the
external timer pin, TMR0. The counting is based on the
f
INT clock.
In the event count or timer mode, once the timer/event
counter 0 is enabled, it begins counting form the value
placed in the timer/event counter 0. From this initial
value it will count up to a value of FFH. Once an overflow
(
1
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Rev. 1.20
14
April 28, 2010
HT48R54A
Bit No.
Label
Function
Define the prescaler stages, P0SC2, P0SC1, P0SC0=
000: fSP=fS/32
001: fSP=fS/64
0
1
2
P0SC0
P0SC1
P0SC2
010: fSP=fS/128
011: fSP=fS/256
100: fSP=fS/512
101: fSP=fS/1024
110: fSP=fS/2048
111: fSP=fS/4096
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
3
T0E
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
To enable or disable timer 0 counting
(0=disable; 1=enable)
4
5
T0ON
¾
Unused bit, read as ²0²
Define the operating mode, T0M1, T0M0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
T0M0
T0M1
TMR0C (0EH) Register
Timer/Event Counter 1
flow occurs, the counter is reloaded from the timer/event
counter 1 preload register and generates the corre-
sponding interrupt request flag (T1F; bit 6 of INTC) at
the same time.
Using the internal clock sources, there are 2 reference
time-bases for timer/event counter 1. The internal clock
source can be selected as coming from fSYS or fRTC (se-
lected by T1S bit). The external clock input allows the
user to count external events, measure time intervals or
pulse widths, or to generate an accurate time base and
PFD signals.
In pulse width measurement mode with the T1ON and
T1E bits are equal to one, once the TMR1 has received
a transition from low to high (or high to low if the T1E bit
is 0) it will start counting until the TMR1 returns to the
original level and reset the T1ON. The measured result
will remain in the timer/event counter 1 even if the acti-
vated transition occurs again. In other words, only one
cycle measurement can be done. Until setting the
T1ON, the cycle measurement will function again as
long as it receives further transition pulse. Note that, in
this operating mode, the timer/event counter 1 starts
counting not according to the logic level but according to
the transition edges. In the case of counter overflows,
the counter 1 is reloaded from the timer/event counter 1
pre-load register and issues the interrupt request just
like the other two modes.
There are 2 registers related to timer/event counter 1;
TMR1(10H), TMR1C(11H). In timer/event counter 1
counting mode (T1ON=1), writing TMR1 will only put the
written data to pre-load register (8 bits). The timer/event
counter 1 pre-load register is changed by each writing
TMR1 operations. Reading TMR1 will also latch the
TMR1 to the destination. The TMR1C is the timer/event
counter 1 control register, which defines the operating
mode, counting enable or disable and active edge.
The T1M0, T1M1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR1) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT1 clock. The
pulse width measurement mode can be used to count
the high or low level duration of the external signal
(TMR1). The counting is based on the fINT1 clock.
To enable the counting operation, the timer ON
bit(T1ON; bit 4 of TMR1C) should be set to 1. In the
pulse width measurement mode, the T1ON will be
cleared automatically after the measurement cycle is
complete. But in the other two modes the T1ON can only
be reset by instructions. The overflow of the timer/event
counter 1 is one of the wake-up sources. No matter what
the operation mode is, writing a 0 to ET1I can disabled
the corresponding interrupt service.
In the event count or timer mode, once the timer/event
counter 1 starts counting, it will count from the current
contents in the timer/event counter 1 to FFH. Once over-
Rev. 1.20
15
April 28, 2010
HT48R54A
In the case of timer/event counter 1 OFF condition, writ-
ing data to the timer/event counter 1 pre-load register
will also load the data to timer/event counter 1. But if the
timer/event counter 1 is turned on, data written to the
timer/event counter 1 will only be kept in the timer/event
counter 1 pre-load register. The timer/event counter 1
will still operate until the overflow occurs (a timer/event
counter 1 reloading will occur at the same time).
When the timer/event counter 1 (reading TMR1) is read,
the clock will be blocked to avoid errors. As this may re-
sults in a counting error, this must be taken into consid-
eration by the programmer.
The bit 0~2 of the TMR1C can be used to define the
pre-scaling stages of the internal clock sources of
timer/event counter 1. The definitions are as shown.
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Timer/Event Counter 1
Bit No.
Label
Function
Define the prescaler stages, P1SC2, P1SC1, P1SC0=
000: fINT1=fS1/2
001: fINT1=fS1/4
0
1
2
P1SC0
P1SC1
P1SC2
010: fINT1=fS1/8
011: fINT1=fS1/16
100: fINT1=fS1/32
101: fINT1=fS1/64
110: fINT1=fS1/128
111: fINT1=fS1/256
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
3
T1E
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4
5
T1ON
T1S
To enable or disable timer 1 counting (0=disable; 1=enable)
Select clock source of TMR1 (0=fSYS; 1=fRTC
)
Define the operating mode, T1M1, T1M0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
T1M0
T1M1
TMR1C (11H) Register
Rev. 1.20
16
April 28, 2010
HT48R54A
Input/Output Ports
The PD and PE can be used for output operation only.
Setting its output register high which effectively places
its NMOS output transistor in high impedance state. Re-
setting output register to low will force to output low
state.
There are 16 bidirectional input/output (PA, PB) lines
and 8 PMOS (PC), 16 NMOS (PD, PE) output lines in
the microcontroller, labeled from PA to PE, which are
mapped to the data memory of [12H], [14H], [16H],
[18H] and [1AH] respectively. All pins on PA~PB can be
used for both input and output operations.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set
or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H, 18H or 1AH) instructions.
For the input operation, these ports are non-latching,
that is, the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]² (m=12H, 14H). For output oper-
ation, all the data is latched and remains unchanged un-
til the output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²LR [m].i²,
²CPL [m]², ²CPLA [m]² read the entire port states into
the CPU, execute the defined operations (bit-operation),
and then write the results back to the latches or the ac-
cumulator.
The PA and PB have their own control registers (PAC,
PBC) to control the input/output configuration. These
two control registers are mapped to locations 13H and
15H. CMOS/PMOS output or Schmitt trigger input with
structures can be reconfigured dynamically under soft-
ware control. The control registers specifies which pin
are set as input and which are set as outputs. To setup a
pin as an input the corresponding bit of the control regis-
ter must be set high, for an output it must be set low.
Each line of port A has the capability of waking-up the
device.
There is a pull-high option available for PA0~PA7 lines
(port option). Once the pull-high option of an I/O line is
selected, the I/O line have pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PC can be used for output operation only. Resetting
its output register to low will effectively places its PMOS
output transistor in high impedance state. Setting output
register to high will force PC to output high state.
The external interrupt pin INT is pin-shard with output
pin PD0.
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PA Input/Output Ports
Rev. 1.20
17
April 28, 2010
HT48R54A
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PB Input/Output Ports
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PC Output Ports
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PD0 Input/Output Port
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t
a
R
K
e
g
i
s
t
e
r
S
C
h
i
p
R
e
s
e
t
R
e
a
d
D
a
t
a
R
e
g
i
s
t
e
r
PD1~PD7, PE Output Ports
Rev. 1.20
18
April 28, 2010
HT48R54A
Buzzer Output
The PA0 and PA1 are pin-shared with BZ and BZ signal, respectively. If the BZ/BZ option is selected, the output signal
in output mode of PA0/PA1 will be the buzzer signal generated by Multi-function timer. The input mode is always re-
mained in its original functions. Once the BZ/BZ option is selected, the buzzer output signals are controlled by the PA0
data register only.
The I/O functions of PA0/PA1 are shown below.
PAC Register
PAC0
PAC Register
PAC1
PA Data Register PA Data Register
PA0 PA1
Output Function
PA0=BZ, PA1=BZ
0
0
0
0
1
1
0
0
1
1
0
1
1
0
1
0
x
x
x
x
PA0=0, PA1=0
x
PA0=BZ, PA1=input
PA0=0, PA1=input
PA0=input, PA1=0
PA0=input, PA1=input
x
D
x
Note:
²x² stands for don¢t care
²D² stands for Data ²0² or ²1²
PFD Output
The PA7 is pin-shared with the PFD signal. If the PFD option is selected, the output signal in output mode of PA7 will be
the PFD signal generated by timer/event counter 1 overflow signal. The input mode is always remaining its original
functions. Once the PFD option is selected, the PFD output signal is controlled by PA7 data register only. The I/O func-
tions of PA7 are shown below.
I/O Mode
I/P (Normal)
O/P (Normal)
I/P (PFD)
O/P (PFD)
PA7
Logical Input
Logical Output
Logical Input
PFD (Timer on)
Note: ThePFDfrequencyisthetimer/eventcounter1overflowfrequencydividedby2.
The definitions of the PFD control signal and PFD output frequency are listed in the following table.
Timer
OFF
OFF
ON
Timer Preload Value
PA7 Data Register
PA7 Pad State
PFD Frequency
X
X
N
N
0
1
0
1
0
U
X
X
0
X
ON
PFD
fTMR1/[2´(M-N)]
Note:
²X² stands for unused
²U² stands for unknown
²M² is ²65536² for PFD
²N² is the preload value for the timer/event counter 1
²fTMR1² is input clock frequency for timer/event counter 1
Rev. 1.20
19
April 28, 2010
HT48R54A
Low Voltage Reset - LVR
The LVR includes the following specifications:
·
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will au-
tomatically reset the device internally.
The low voltage (0.9V~VLVR) has to remain in their
original state for more than 1ms. If the low voltage
state does not exceed 1ms, the LVR will ignore it and
do not perform a reset function.
·
The LVR uses the ²OR² function with the external
RES signal to perform a chip reset.
The relationship between VDD and VLVR is shown below.
V
D
D
V
O
P
R
V
D
D
V
O
P
R
V
D
D
V
O
P
R
5
.
5
5
V
.
5
V
5
.
5
5
V
.
5
V
5
.
5
5
V
.
5
V
V
L
V
R
V
L
V
R
V
L
V
R
2
.
1
V
2
.
2
V
3
.
1
5
V
4
.
2
V
2
.
2
V
2
.
2
V
0
.
9
V
0
.
9
V
0
.
9
V
Note: VOPR is the voltage range for proper chip operation at 4MHz system clock.
V
D
D
5
.
5
V
L
V
R
D
e
t
e
c
t
V
L
V
R
0
.
9
V
0
V
R
e
s
e
t
S
i
g
n
a
l
R
e
s
e
t
N
o
r
m
a
l
O
p
e
r
a
t
i
o
n
R
e
s
e
t
*
1
*
2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2: Since a low voltage has to be maintained for more than 1ms, therefore a 1ms delay is provided before
entering the reset mode.
Rev. 1.20
20
April 28, 2010
HT48R54A
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure having
a proper functioning system.
Items
Options
1
2
OSC type selection: RC or crystal
PA0~PA7 bit wake-up enable or disable (by bit)
PA pull-high enable or disable (by port)
WDT clock source: WDT oscillator or fSYS/4 or 32768Hz oscillator
WDT enable or disable
3
4
5
6
CLRWDT instructions: 1 or 2 instructions
Timer/event counter 0 clock sources: fSYS/4 or fSP
LVR enable or disable
7
8
9
LVR voltage: 2.1V or 3.15V or 4.2V
10
11
12
Buzzer function: single BZ enable or both BZ and BZ or both disable
Buzzer frequency: fS/2, fS/4, fS/8, fS/16
PA7: Normal I/O or PFD output
Rev. 1.20
21
April 28, 2010
HT48R54A
Application Circuits
V
D
D
P
A
0
/
B
Z
V
D
D
P
A
1
/
B
Z
P
A
2
/
T
M
R
0
P A
t
P
3
/
T
M
R
1
R
e
s
e
1
0
W
0
k
A
B
4
0
~
~
P
P
A
B
6
7
C
i
r
c
u
i
t
P
A
7
/
P
F
D
0
m
. F 1
R
E
S
P
V
D
D
R
C
S
y
s
t
e
m
0
m
. F 1
1
3
W
0
<
k
O
R
S
<
C
2
.
W
4
M
P
P
C
D
0
1
~
~
P
P
C
D
7
7
4
7
0
p
F
O
O
S
S
C
C
1
2
P
D
0
/
I
N
T
V
S
S
R
O
S
C
f
S
Y
S
P
E
0
~
P
E
7
O
O
S
S
C
C
1
2
C
1
O
S
C
O
O
S
S
C
C
1
2
C
i
r
c
u
i
t
C
S
r
y
s
t
a
l
/
R
e
s
y
s
t
e
m
O
s
c
R
1
3
2
7
6
8
H
z
F
o
r
R
1
,
C
1
,
O
S
C
3
C
2
1
0
p
F
O
S
C
C
i
r
c
u
i
t
O
S
C
4
H
T
4
8
R
5
4
A
Note: 1. Crystal/resonator system oscillators
For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For
resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is
not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator
when VDD falls below its operating range, it is recommended that R1 is added. The values of C1 and C2
should be selected in consultation with the crystal/resonator manufacturer specifications.
2. Reset circuit
The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and re-
mains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of
the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.
3. For applications where noise may interfere with the reset circuit and for details on the oscillator external
components, refer to Application Note HA0075E for more information.
Rev. 1.20
22
April 28, 2010
HT48R54A
Instruction Set
Introduction
sure correct handling of carry and borrow data when re-
sults exceed 255 for addition and less than 0 for sub-
traction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Central to the successful operation of any
microcontroller is its instruction set, which is a set of pro-
gram instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of pro-
gramming overheads.
Logical and Rotate Operations
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on pro-
gram requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
For easier understanding of the various instruction
codes, they have been subdivided into several func-
tional groupings.
Instruction Timing
Most instructions are implemented within one instruc-
tion cycle. The exceptions to this are branch, call, or ta-
ble read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be im-
plemented within 1ms. Although instructions which re-
quire one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instruc-
tions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to imple-
ment. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instruc-
tions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the re-
sult of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a sub-
routine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the sub-
routine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made re-
garding the condition of a certain data memory or indi-
vidual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the pro-
gram perhaps determined by the condition of certain in-
put switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific imme-
diate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to en-
Rev. 1.20
23
April 28, 2010
HT48R54A
Bit Operations
Other Operations
The ability to provide single bit operations on Data Mem-
ory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The fea-
ture removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write pro-
cess is taken care of automatically when these bit oper-
ation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² in-
struction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electro-
magnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be con-
sulted as a basic instruction reference using the follow-
ing listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using regis-
ters. However, when working with large amounts of
fixed data, the volume involved often makes it inconve-
nient to store the fixed data in the Data Memory. To over-
come this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instruc-
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Arithmetic
Description
Cycles Flag Affected
ADD A,[m]
ADDM A,[m]
ADD A,x
Add Data Memory to ACC
1
1Note
1
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
Add ACC to Data Memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add Data Memory to ACC with Carry
1
1Note
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
1
1Note
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1Note
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1Note
1Note
1
OR A,x
1
XOR A,x
1
1Note
CPL [m]
CPLA [m]
Complement Data Memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment Data Memory with result in ACC
1
Z
Z
Z
Z
Increment Data Memory
1Note
DECA [m]
DEC [m]
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
Rev. 1.20
24
April 28, 2010
HT48R54A
Mnemonic
Rotate
Description
Cycles Flag Affected
RRA [m]
RR [m]
Rotate Data Memory right with result in ACC
Rotate Data Memory right
1
1Note
1
1Note
1
1Note
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
C
None
None
C
RLCA [m]
RLC [m]
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Branch
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if Data Memory is zero
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m]
TABRDL [m]
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
Miscellaneous
NOP
No operation
1
1Note
1Note
1
None
None
CLR [m]
Clear Data Memory
SET [m]
Set Data Memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO, PDF
TO, PDF
TO, PDF
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1
1Note
1
None
1
TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.20
25
April 28, 2010
HT48R54A
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.20
26
April 28, 2010
HT48R54A
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then in-
crements by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruc-
tion.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Operation
Each bit of the specified Data Memory is cleared to 0.
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Description
Operation
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.20
27
April 28, 2010
HT48R54A
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Operation
Data in the specified Data Memory is decremented by 1.
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
mulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.20
28
April 28, 2010
HT48R54A
INC [m]
Increment Data Memory
Description
Operation
Data in the specified Data Memory is incremented by 1.
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
lator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Description
Operation
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
Operation
The immediate data specified is loaded into the Accumulator.
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Description
Operation
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
ation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.20
29
April 28, 2010
HT48R54A
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
ation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the re-
stored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by set-
ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed be-
fore returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
main unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.20
30
April 28, 2010
HT48R54A
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.20
31
April 28, 2010
HT48R54A
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Operation
Each bit of the specified Data Memory is set to 1.
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is set to 1.
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.20
32
April 28, 2010
HT48R54A
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumu-
lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.20
33
April 28, 2010
HT48R54A
SWAP [m]
Description
Operation
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
tion.
Operation
Skip if [m] = 0
None
Affected flag(s)
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
None
Affected flag(s)
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.20
34
April 28, 2010
HT48R54A
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.20
35
April 28, 2010
HT48R54A
Package Information
44-pin QFP (10mm´10mm) Outline Dimensions
C
H
D
G
3
3
2
3
I
3
4
2
2
L
F
A
B
E
1
2
4
4
a
K
J
1
1
1
Dimensions in inch
Nom.
Symbol
Min.
0.512
0.390
0.512
0.390
¾
Max.
0.528
0.398
0.528
0.398
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
0.031
0.012
¾
¾
¾
0.075
¾
0.087
0.106
0.020
0.037
0.008
¾
¾
0.010
0.029
0.004
¾
¾
J
¾
K
L
¾
0.004
¾
a
0°
7°
Dimensions in mm
Nom.
Symbol
Min.
13.00
9.90
13.00
9.90
¾
Max.
13.40
10.10
13.40
10.10
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
0.80
0.30
¾
¾
¾
1.90
¾
2.20
2.70
0.50
0.93
0.20
¾
¾
0.25
0.73
0.10
¾
¾
J
¾
K
L
¾
0.10
¾
a
0°
7°
Rev. 1.20
36
April 28, 2010
HT48R54A
44-pin LQFP (10mm´10mm) (FP3.2mm) Outline Dimensions
C
H
D
G
3
3
2
3
I
3
4
2
2
F
A
B
E
1
2
4
4
a
K
J
1
1
1
Dimensions in inch
Symbol
Min.
0.512
0.390
0.512
0.390
¾
Nom.
0.520
0.394
0.520
0.394
0.031
Max.
0.528
0.398
0.528
0.398
¾
A
B
C
D
E
F
G
H
I
0.012
0.055
¾
¾
¾
0.053
¾
0.057
0.063
0.010
0.053
0.008
0.004
0.041
0.004
¾
J
0.047
¾
K
a
0°
¾
7°
Dimensions in mm
Symbol
Min.
13.00
9.90
13.00
9.90
¾
Nom.
13.20
10.00
13.20
10.00
0.80
Max.
13.40
10.10
13.40
10.10
¾
A
B
C
D
E
F
G
H
I
0.30
1.40
¾
¾
¾
1.35
¾
1.45
1.60
0.25
1.35
0.25
0.10
1.05
0.10
¾
J
1.20
¾
K
a
0°
¾
7°
Rev. 1.20
37
April 28, 2010
HT48R54A
52-pin QFP (14mm´14mm) Outline Dimensions
C
H
D
G
3
9
2
7
I
4
0
2
6
F
A
B
E
1
4
5
2
K
J
1
1
3
Dimensions in inch
Nom.
Symbol
Min.
0.681
0.547
0.681
0.547
¾
Max.
0.689
0.555
0.689
0.555
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
0.039
0.016
¾
¾
¾
0.098
¾
0.122
0.134
¾
¾
0.004
¾
¾
J
0.029
0.004
¾
0.041
0.008
¾
K
L
¾
0.004
¾
a
0°
7°
Dimensions in mm
Nom.
Symbol
Min.
17.30
13.90
17.30
13.90
¾
Max.
17.50
14.10
17.50
14.10
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
1.00
0.40
¾
¾
¾
2.50
¾
3.10
3.40
¾
¾
0.10
¾
¾
J
0.73
0.10
0°
1.03
0.20
7°
K
a
¾
¾
Rev. 1.20
38
April 28, 2010
HT48R54A
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
39
April 28, 2010
HT48R54A_10 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| HT48R70A-1 | HOLTEK | I/O Type 8-Bit MCU | 获取价格 |
|
| HT48R70A-1(48SSOP) | HOLTEK | Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO48 | 获取价格 |
|
| HT48R70A-1_07 | HOLTEK | I/O Type 8-Bit MCU | 获取价格 |
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| HT48RA0 | HOLTEK | Remote Type 8-Bit MCU | 获取价格 |
|
| HT48RA0(20DIP-A) | HOLTEK | Microcontroller, 8-Bit, UVPROM, 4MHz, CMOS, PDIP20 | 获取价格 |
|
| HT48RA0(20SOIC-A) | HOLTEK | Microcontroller, 8-Bit, UVPROM, 4MHz, CMOS, PDSO20 | 获取价格 |
|
| HT48RA0(20SOP-A) | HOLTEK | Microcontroller | 获取价格 |
|
| HT48RA0(24SOIC-A) | HOLTEK | Microcontroller, 8-Bit, UVPROM, 4MHz, CMOS, PDSO24 | 获取价格 |
|
| HT48RA0(24SOP-A) | HOLTEK | Microcontroller | 获取价格 |
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| HT48RA0-1 | HOLTEK | Remote Type 8-Bit MCU | 获取价格 |
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