HT48RU80(48SSOP-A)_技术文档

HT48RU80/HT48CU80

I/O Type 8-Bit MCU

Technical Document

·

Tools Information

FAQs

Application Note

-

HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM

HA0004E HT48 & HT46 MCU UART Software Implementation Method

HA0013E HT48 & HT46 LCM Interface Design

HA0021E Using the I/O Ports on the HT48 MCU Series

Features

·

Operating voltage:

576´8 data memory RAM

f

_SYS=4MHz: 2.2V~5.5V

_SYS=8MHz: 3.3V~5.5V

Universal Asynchronous Receiver/Transmitter

(UART)

f

·

Low voltage reset function

56 bidirectional I/O lines (max.)

Two interrupt input

·

HALT function and wake-up feature reduce power

consumption

·

16-level subroutine nesting

16-bit´2 programmable timer/event counter and

overflow interrupts with PFD outputs

Up to 0.5ms instruction cycle with 8MHz system clock

at V_DD=5V

·

8-bit´1 programmable timer/event counter

Bit manipulation instruction

On-chip RC oscillator, external crystal and RC oscil-

lator

16-bit table read instruction

63 powerful instructions

·

32768Hz crystal oscillator for timing purposes only

Watchdog Timer

All instructions in one or two machine cycles

48-pin SSOP, 64-pin LQFP package

16K´16 program memory ROM

General Description

The HT48RU80/HT48CU80 are 8-bit high performance,

RISC architecture microcontroller devices specifically

designed for multiple I/O control product applications.

The mask version HT48CU80 is fully pin and function-

ally compatible with the OTP version HT48RU80 de-

vice.

wake-up functions, watchdog timer, buzzer driver, as

well as low cost, enhance the versatility of these devices

to suit a wide range of application possibilities such as

industrial control, consumer products, subsystem con-

trollers, etc.

The HT48CU80 is under development and will be avail-

able soon.

The advantages of low power consumption, I/O flexibil-

ity, timer functions, oscillator options, HALT and

Rev. 1.30

1

January 7, 2009

HT48RU80/HT48CU80

Block Diagram

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Rev. 1.30

2

January 7, 2009

HT48RU80/HT48CU80

Pin Assignment

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Pin Description

Pin Name I/O

Options

Description

Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up

input by configuration option. Software instructions determine if the pin is a

CMOS output or input. Configuration options determine if all pins on this port

Pull-high

Wake-up

PA0~PA7

I/O

Schmitt Trigger have pull-high resistors and if the inputs are Schmitt trigger or non Schmitt

trigger.

PB0/BZ

PB1/BZ

PB2/INT1

PB3/TMR2

PB4~PB7

PC0/TX

Bidirectional 8-bit input/output ports. Software instructions determine if the

pin is a CMOS output or Schmitt trigger input. A configuration option for each

Pull-high

port determines if all pins on the relevant port have pull-high resistors. Pins

PB0, PB1, PB2 and PB3 are pin-shared with BZ, BZ, INT1 and TMR2, re-

spectively.

I/O

PC1/RX

I/O or BZ/BZ

PC2~PC7

PD0~PD7

PE0~PE7

PF0~PF7

PG0~PG7

Pins PC0 and PC1 are pin-shared with the UART pins TX and RX.

External interrupt Schmitt trigger input. Edge triggered on high to low transi-

tion.

INT0

I

¾

TMR0

TMR1

I

Schmitt trigger input for Timer/Event Counter 0

Schmitt trigger input for Timer/Event Counter 1

¾

Rev. 1.30

3

January 7, 2009

HT48RU80/HT48CU80

Pin Name I/O

Options

Description

OSC1, OSC2 are connected to an external RC network or external Crystal

(determined by configuration option) for the internal system clock. For exter-

nal RC system clock operation, OSC2 is an output pin for 1/4 system clock.

These two pins also can be optioned as an RTC oscillator (32768Hz). In this

case, the system clock comes from an internal RC oscillator whose nominal

frequency at 5V has 4 options, 3.2MHz, 1.6MHz, 800kHz, 400kHz.

Crystal or RC

or Int.

OSC1

OSC2

I

O

RC+RTC

RES

VDD

VSS

I

Schmitt trigger reset input. Active low.

Positive power supply

¾

Negative power supply, ground.

Note: Each pin on PAcan be programmed through a configuration option to have a wake-up function.

Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for a partic-

ular port, then all input pins on this port will be connected to pull-high resistors.

Pins PE4~PE7 and pins PF4~PF7 only exist on the 64-pin package.

Port G only exists on the 64-pin package.

Absolute Maximum Ratings

Supply Voltage...........................V_SS-0.3V to V_SS+6.0V

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

Storage Temperature............................-50°C to 125°C

Operating Temperature...........................-40°C to 85°C

I_OHTotal............................................................-100mA

I

_OLTotal ..............................................................150mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

¾

f

_SYS=4MHz

2.2

3.3

¾

5.5

1.5

4

V

¾

V_DD

Operating Voltage

f

_SYS=8MHz

V

¾

3V

5V

3V

5V

3V

5V

0.6

2

mA

Operating Current

(Crystal OSC)

No load, f_SYS=4MHz,

UART disable

I_DD1

I_DD2

I_DD3

0.8

2.5

1.5

3

1.5

4

Operating Current

(RC OSC)

No load, f_SYS=4MHz,

UART disable

3

Operating Current

No load, f_SYS=4MHz,

UART On

(Crystal OSC, RC OSC)

6

Operating Current

No load, f_SYS=8MHz,

UART Off

I_DD4

5V

3

5

mA

¾

(Crystal OSC, RC OSC)

Operating Current

No load, f_SYS=8MHz,

UART On

I_DD5

10

(Crystal OSC, RC OSC)

3V

5V

3V

5V

5

10

1

¾

mA

Standby Current

I_STB1

No load, system HALT

(WDTOSC On, RTC Off)

Standby Current

I_STB2

(WDTOSC Off, RTC Off)

2

Rev. 1.30

4

January 7, 2009

HT48RU80/HT48CU80

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

3V

5V

¾

5

10

¾

mA

V

Standby Current

I_STB3

No load, system HALT

(WDTOSC Off, RTC On)

V_IL1

V_IH1

V_IL2

V_IH2

V_LVR

0.3V_DD

V_DD

0.4V_DD

V_DD

3.3

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES)

Input High Voltage (RES)

Low Voltage Reset

0

¾

0.7V_DD

0

V

¾

V

¾

0.9V_DD

2.7

4

V

¾

LVRenabled

V_OL=0.1V_DD

V_OH=0.9V_DD

3.0

8

V

¾

3V

5V

3V

5V

3V

5V

mA

kW

¾

I_OL

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance

10

20

-4

-10

60

30

¾

-2

¾

I_OH

V

_OH=0.9V_DD

-5

¾

20

100

50

R_PH

¾

10

A.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

¾

2.2V~5.5V

3.3V~5.5V

2.2V~5.5V

3.3V~5.5V

3.2MHz

400

1800

900

450

225

0

4000

8000

4000

8000

5400

2700

1350

675

kHz

¾

90

65

23

17

System Clock

(Crystal OSC)

f_SYS1

¾

System Clock

(RC OSC)

f_SYS2

¾

1.6MHz

System Clock

f_SYS3

5V

(Internal RC OSC)

800kHz

400kHz

2.2V~5.5V

3.3V~5.5V

4000

8000

180

¾

Timer I/P Frequency

(TMR)

f_TIMER

0

3V

5V

3V

5V

45

¾

ms

t_WDTOSC

Watchdog Oscillator Period

32

130

11

46

ms

Watchdog Time-out Period

(WDT OSC)

t_WDT1

Without WDT prescaler

8

33

Watchdog Time-out Period

(System Clock)

t_WDT2

t_SYS

ms

Without WDT prescaler

1024

¾

Watchdog Time-out Period

(RTC OSC)

t_WDT3

7.812

t_RES

t_SST

t_INT

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

1

¾

1

¾

Wake-up from HALT

¾

1024

¾

ms

t_SYS

ms

Rev. 1.30

5

January 7, 2009

HT48RU80/HT48CU80

Functional Description

Execution Flow

When executing a jump instruction, conditional skip ex-

ecution, loading register, subroutine call or return from

subroutine, initial reset, internal interrupt, external inter-

rupt or return from interrupts, the PC manages the pro-

gram transfer by loading the address corresponding to

each instruction.

The system clock for the microcontroller is derived from

either a crystal or an RC oscillator. The system clock is

internally divided into four non-overlapping clocks. One

instruction cycle consists of four system clock cycles.

Instruction fetching and execution are pipelined in such

a way that a fetch takes an instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to be effectively executed in a cycle. If an instruction

changes the program counter, two cycles are required to

complete the instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get the proper instruction.

Otherwise proceed with the next instruction.

The lower byte of the program counter (PCL) is a read-

able and writeable register (06H). Moving data into the

PCL performs a short jump. The destination will be

within the current program ROM page.

Program Counter - PC

The program counter (PC) controls the sequence in

which the instructions stored in the program ROM are

executed and its contents specify a full range of pro-

gram memory.

When a control transfer takes place, an additional

dummy cycle is required.

Program Memory - ROM

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by one. The program counter then points to

the memory word containing the next instruction code.

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

S

y

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C

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O

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2

(

R

C

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P

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P

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+

1

P

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+

2

P

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F

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(

P

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)

E

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(

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+

2

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+

1

)

Execution Flow

Program Counter

Mode

*13 *12 *11 *10 *9

*8

0

*7

0

*6

0

*5

0

*4

0

1

*3

0

1

0

*2

0

1

0

1

0

1

*1

0

*0

0

Initial Reset

External Interrupt 0

0

Timer/Event Counter 0 Overflow

Timer/Event Counter 1 Overflow

Timer/Event Counter 2 Overflow

External Interrupt 1

UART Interrupt

Skip

Program Counter+2

*8 @7 @6 @5 @4 @3 @2 @1 @0

Loading PCL

*13 *12 *11 *10 *9

Jump, Call Branch

BP.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Return (RET, RETI)

Program Counter

Note: *13~*0: Program counter bits

#13~#0: Instruction code bits

S13~S0: Stack register bits

@7~@0: PCL bits

Rev. 1.30

6

January 7, 2009

HT48RU80/HT48CU80

·

Location 000H

8192´16 bits´2 banks, addressed by the Program

Counter and table pointer.

This area is reserved for program initialization. After a

chip reset, the program always begins execution at lo-

cation 000H.

The BP register bit5 is used to select the ROM bank.

When the BP¢s bit5=0, the ROM bank 0 ranges from

0000H to 1FFFH. When the BP¢s bit5=1, the ROM

bank1 ranges from 2000H to 3FFFH.

Location 004H

This area is reserved for the external interrupt 0 ser-

vice program. If the INT0 interrupt pin is activated, the

interrupt enabled and the stack is not full, the program

begins execution at location 004H.

The ²CALL² and ²JMP² instruction provide only 13 bits

of address to allow branching within any 8K program

memory bank. When doing a ²CALL² or ²JMP² instruc-

tion, the upper 1 bit of the address is provided by BP5.

When doing a ²CALL² or ²JMP² instruction, user must

ensure that the bank select bit is programmed so that

the desired program memory bank is addressed. If a re-

turn from ²CALL² instruction (or interrupt) is executed,

the entire 14-bit Program Counter is popped off the

stack.

·

Location 008H

This area is reserved for the Timer/Event Counter 0 in-

terrupt service program. If a timer interrupt results from a

Timer/Event Counter 0 overflow, and if the interrupt is

enabled and the stack is not full, the program begins ex-

ecution at location 008H.

Location 00CH

This location is reserved for the Timer/Event Counter

1 interrupt service program. If a timer interrupt results

from a Timer/Event Counter 1 overflow, and the inter-

rupt is enabled and the stack is not full, the program

begins execution at location 00CH.

Certain locations in the program memory are reserved

for special usage:

0

4

8

H

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·

Location 010H

T

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e

r

/

E

v

p

e

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t

C

o

u

n

t

e

r

0

This area is reserved for the external interrupt 1 ser-

vice program. If the INT1 interrupt pin is activated, the

interrupt enabled and the stack is not full, the program

begins execution at location 010H.

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n

t

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t

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u

b

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Location 014H

This area is reserved for the UART interrupt service

program. If a UART interrupt results from a UART TX

or RX, and the interrupt is enabled and the stack is not

full, the program begins execution at location 014H.

0

1

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Location 018H

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This location is reserved for the Timer/Event Counter

2 interrupt service program. If a timer interrupt results

from a Timer/Event Counter 2 overflow, and the inter-

rupt is enabled and the stack is not full, the program

begins execution at location 018H.

1

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1

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2

0

H

·

Table location

Any location in the ROM can be used as a look-up ta-

ble. The instructions ²TABRDC [m]² (page specified

by TBHP) and ²TABRDL [m]² (the last page) transfer

the contents of the lower-order byte to the specified

data memory, and the contents of the higher-order

byte to TBLH (Table Higher-order byte register) (08H).

3

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Program Memory

Table Location

Instruction

*13~*8

TBHP

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

@7

@6

@5

@4

@3

@2

@1

@0

111111

Table Location

TBHP: Table pointer higher-order bits

Note: *13~*0: Table location bits

@7~@0: Table pointer bits

Rev. 1.30

7

January 7, 2009

HT48RU80/HT48CU80

Only the destination of the lower-order byte in the ta-

ble is well-defined; the other bits of the table word are

all transferred to the lower portion of TBLH. The TBLH

is read only, the higher-order byte table pointer TBHP

(1FH) and the lower-order byte table pointer TBLP

(07H) are read/write registers, indicating the table lo-

cation. Before accessing the table, the location the lo-

cation has to be placed in TBHP and TBLP. All the

table related instructions require 2 cycles to complete

the operation. These areas may function as a normal

ROM depending upon the user¢s requirements.

Bank pointer (BP;04H), an Accumulator (ACC;05H), a

Program counter lower-order byte register (PCL;06H), a

lower-order byte table pointer (TBLP;07H), a Table

higher-order byte register (TBLH;08H), a Watchdog

Timer option setting register (WDTS;09H), a Status reg-

ister (STATUS;0AH), an Interrupt control register 0

(INTC0;0BH), a Timer/Event Counter 0 higher order

byte register (TMR0H;0CH), a Timer/Event Counter 0

lower order byte register (TMR0L;0DH), a Timer/Event

Counter 0 control register (TMR0C;0EH), a Timer/Event

Counter 1 higher order byte register (TMR1H;0FH), a

Timer/Event Counter 1 lower order byte register

(TMR1L;10H), a Timer/Event Counter 1 control register

(TMR1C;11H), I/O registers (PA;12H, PB;14H, PC;16H,

PD;18H, PE;1AH, PF;1CH, PG;25H) and I/O control

registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H,

PEC;1BH, PFC;1DH, PGC;26H), a Timer/Event Coun-

ter 2 (TMR2;21H), a Timer/Event Counter 2 control reg-

ister (TMR2C;22H), a higher-order byte table pointer

Stack Register - STACK

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 16 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledge signal, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

(TBHP;1FH), an Interrupt control register

1

(INTC1;1EH), a UART Status register (USR;28H), a

UART Control register 1 (UCR1;29H), a UART Control

register 2 (UCR2;2AH), a UART TX/RX Buffer register

(TXR/RXR;2BH), and a UART Baud Rate generator

prescaler register (BRG;2CH). On the other hand, the

general purpose data memory, addressed from 40H to

FFH (bank0~2), is used for data and control information

under instruction commands.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 16 return ad-

dresses are stored).

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP0 or MP1).

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] ([02H]) will access data memory pointed

to by MP0 (MP1). Reading location 00H (02H) itself indi-

rectly will return the result 00H. Writing indirectly results

in no operation. The memory pointer registers (MP0 and

MP1) are 8-bit registers.

Data Memory - RAM

The data memory (RAM) is designed with 617´8 bits,

and is divided into two functional groups, namely, spe-

cial function registers and general purpose data mem-

ory (192´8bits´3banks), most of which are readable/

writeable, although some are read only.

[BP REG] Bit1~Bit0

RAM Bank

Accumulator - ACC

00

01

10

0

1

2

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

The special function registers consist of an Indirect ad-

dressing register 0 (IAR0;00H), a Memory pointer regis-

ter 0 (MP0;01H), an Indirect addressing register 1

(IAR1;02H), a Memory pointer register 1 (MP1;03H), a

Rev. 1.30

8

January 7, 2009

HT48RU80/HT48CU80

0

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RAM Mapping

Status Register - STATUS

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic operations.

The ALU provides the following functions:

This 8-bit register (0AH) contains the zero flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PDF), and watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

With the exception of the TO and PDF flags, bits in

the status register can be altered by instructions like

most other registers. Any data written into the status

register will not change the TO or PDF flag. In addi-

tion, operations related to the status register may

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ)

The ALU not only saves the results of a data operation but

also changes the status register.

Rev. 1.30

9

January 7, 2009

HT48RU80/HT48CU80

Bit No.

Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation, otherwise C is cleared. C is also affected by a ro-

tate through carry instruction.

0

C

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction, otherwise AC is cleared.

1

2

3

AC

Z

Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa, otherwise OV is cleared.

OV

PDF is cleared by a system power-up or executing the ²CLR WDT² instruction.

PDF is set by executing the ²HALT² instruction.

4

PDF

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.

TO is set by a WDT time-out.

5

TO

6~7

¾

Unused bit, read as ²0².

Status (0AH) Register

give different results from those intended. The TO

flag can be affected only by a system power-up, a

WDT time-out or executing the ²CLR WDT² or

²HALT² instruction. The PDF flag can be affected

only by executing the ²HALT² or ²CLR WDT² instruc-

tion or during a system power-up.

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

(STATUS) are altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents should be saved in advance.

External interrupts are triggered by a high to low transi-

tion of the INT0 or INT1 and the related interrupt request

flag (EIF0; bit 4 of the INTC0; EIF1; bit 4 of the INTC1)

will be set. When the interrupt is enabled, the stack is

not full and the external interrupt is active, a subroutine

call to location 04H or 10H will occur. The interrupt re-

quest flag (EIF0 or EIF1) and EMI bits will be cleared to

disable other interrupts.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

In addition, on entering the interrupt sequence or exe-

cuting a subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status are important and if the subroutine can cor-

rupt the status register, precautions must be taken to

save it properly.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F; bit 5 of the INTC0), caused by a timer 0

overflow. When the interrupt is enabled, the stack is not

full and the T0F bit is set, a subroutine call to location

08H will occur. The related interrupt request flag (T0F)

will be reset and the EMI bit cleared to disable further in-

terrupts.

Interrupt

The device provides two external interrupts, three inter-

nal timer/event counter interrupts, and a UART TX/ RX

interrupt. The Interrupt Control Register 0 (INTC0; 0BH)

and Interrupt Control Register 1 (INTC1;1EH) both con-

tain the interrupt control bits that are used to set the en-

able/disable status and interrupt request flags.

The internal Timer/Event Counter 1 interrupt is initial-

ized by setting the Timer/Event Counter 1 interrupt re-

quest flag (T1F; bit 6 of the INTC0), caused by a T 1

overflow. When the interrupt is enabled, the stack is not

full and the T1F is set, a subroutine call to location 0CH

will occur. The related interrupt request flag (T1F) will be

reset and the EMI bit cleared to disable further inter-

rupts.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt requires servicing within the service routine, the

EMI bit and the corresponding bit of the INTC0 or INTC1

may be set to allow interrupt nesting. If the stack is full,

the interrupt request will not be acknowledged, even if

the related interrupt is enabled, until the SP is decre-

mented. If immediate service is desired, the stack must

be prevented from becoming full.

The UART interrupt is initialized by setting the interrupt

request flag (URF; bit 5 of the INTC1), that is caused by

a regular UART receive signal, caused by a UART

transmit signal. After the interrupt is enabled, the stack

is not full, and the URF bit is set, a subroutine call to lo-

cation 14H occurs. The related interrupt request flag

(URF) is reset and the EMI bit is cleared to disable fur-

ther other interrupts.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

Rev. 1.30

10

January 7, 2009

HT48RU80/HT48CU80

Bit No.

Label

EMI

EEI0

ET0I

ET1I

EIF0

T0F

T1F

¾

Function

0

1

2

3

4

5

6

7

Controls the master (global) interrupt (1= enable; 0= disable)

Controls the external interrupt 0 (1= enable; 0= disable)

Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable)

Controls the Timer/Event Counter 1 interrupt (1= enable; 0= disable)

External interrupt 0 request flag (1= active; 0= inactive)

Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)

Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)

Unused bit, read as ²0²

INTC0 (0BH) Register

Bit No.

Label

EEI1

EURI

ET2I

¾

Function

0

1

Controls the external interrupt 1 (1= enable; 0= disable)

Controls the UART TX or RX interrupt (1= enable; 0= disable)

Controls the Timer/Event Counter 2 overflow interrupt (1= enable; 0= disable)

Unused bit, read as ²0²

2

3, 7

4

EIF1

URF

T2F

External interrupt 1 request flag (1= active; 0= inactive)

UART TX or RX interrupt request flag (1= active; 0= inactive)

Timer/Event Counter 2 overflow request flag (1= active; 0= inactive)

5

6

INTC1 (1EH) Register

The internal Timer/Event Counter 2 interrupt is initial-

ized by setting the Timer/Event Counter 2 interrupt re-

quest flag (T2F; bit 6 of the INTC1), caused by a T 2

overflow. When the interrupt is enabled, the stack is not

full and the T2F is set, a subroutine call to location 18H

will occur. The related interrupt request flag (T2F) will be

reset and the EMI bit cleared to disable further inter-

rupts.

These can be masked by resetting the EMI bit.

No.

a

Interrupt Source

External Interrupt 0

Priority Vector

1

2

3

4

5

04H

08H

b

Timer/Event Counter 0 Overflow

Timer/Event Counter 1 Overflow

External Interrupt 1

c

0CH

010H

014H

d

e

UART Interrupt

During the execution of an interrupt subroutine, other in-

terrupt acknowledge signals are held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, ²RET² or ²RETI²

may be invoked. RETI will set the EMI bit to enable an

interrupt service, but RET will not.

Timer/Event Counter 2 Overflow

Interrupt

f

6

018H

The Timer/Event Counter 0/1 interrupt request flag

(T0F/T1F), external interrupt 0 request flag (EIF0), en-

able Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I),

enable external interrupt 0 bit (EEI0) and enable master

interrupt bit (EMI) constitute an interrupt control register

(INTC0) which is located at 0BH in the data memory.

EMI, EEI0, ET0I and ET1I are used to control the en-

abling or disabling of interrupts. These bits prevent the

requested interrupt from being serviced. Once the inter-

rupt request flags (T0F, T1F, EIF0) are set, they will re-

main in the INTC0 register until the interrupts are

serviced or cleared by a software instruction.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

Rev. 1.30

11

January 7, 2009

HT48RU80/HT48CU80

The External Interrupt 1 request flag (EIF1), UART inter-

rupt request flag (URF), Timer/Event Counter 2 interrupt

request flag (T2F), External Interrupt 1 bit (EEI1), and

enable UART interrupt bit (EURI), enable Timer/Event

Counter 2 interrupt bit (ET2I), constitute the Interrupt

Control register 1 (INTC1) which is located at 1EH in the

data memory. EEI1, EURI and ET2I are used to control

the enabling or disabling of interrupts. These bits pre-

vent the requested interrupt from being serviced. Once

the interrupt request flags (EIF1, URF, T2F) are set, they

will remain in the INTC1 register until the interrupts are

serviced or cleared by a software instruction.

cost effective solution. However, the frequency of os-

cillation may vary with VDD, temperatures and the chip

itself due to process variations. It is, therefore, not suit-

able for timing sensitive operations where an accurate

oscillator frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift required for the oscillator. No other external compo-

nents are required. In stead of a crystal, a resonator can

also be connected between OSC1 and OSC2 to get a

frequency reference, but two external capacitors in

OSC1 and OSC2 are required. If the internal RC oscilla-

tor is used, the OSC1 and OSC2 can be selected as

32768Hz crystal oscillator (RTC OSC). Also, the fre-

quencies of the internal RC oscillator can be 3.2MHz,

1.6MHz, 800kHz and 400kHz, depending on the op-

tions.

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only

one stack is left and enabling the interrupt is not well

controlled, the original control sequence will be dam-

aged once the ²CALL² operates in the interrupt subrou-

tine.

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode, the system

clock is stopped, but the WDT oscillator still works within

a period of approximately 65ms at 5V. The WDT oscilla-

tor can be disabled by options to conserve power.

Oscillator Configuration

There are three oscillator circuits in the microcontroller.

V

D

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator), RTC clock or instruction

clock (system clock divided by 4), determines the op-

tions. This timer is designed to prevent a software mal-

function or sequence from jumping to an unknown

location with unpredictable results. The Watchdog

Timer can be disabled by options. If the Watchdog Timer

is disabled, all the executions related to the WDT result

in no operation. The RTC clock is enabled only in the in-

ternal RC+RTC mode.

O

S

C

1

O

S

C

1

4

7

0

p

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S

Y

S

O

S

C

2

O

S

C

2

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3

2

7

6

8

H

z

)

System Oscillator

All of them are designed for system clocks, namely, the

external RC oscillator, the external Crystal oscillator and

the internal RC oscillator, which are determined by op-

tions. No matter what oscillator type is selected, the sig-

nal provides the system clock. The HALT mode stops

the system oscillator and ignores an external signal to

conserve power.

Once the internal WDT oscillator (RC oscillator with a

period of 65ms at 5V normally) is selected, it is first di-

vided by 256 (8-stage) to get the nominal time-out pe-

riod of 17ms at 5V. This time-out period may vary with

temperatures, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the

WDTS) can give different time-out periods. If WS2,

WS1, and WS0 are all equal to 1, the division ratio is up

to 1:128, and the maximum time-out period is 2.1 sec-

onds at 5V. If the WDT oscillator is disabled, the WDT

If an RC oscillator is used, an external resistor between

OSC1 and VDD is required and the resistance must

range from 24kW to 1MW. The system clock, divided by

4, is available on OSC2, which can be used to synchro-

nize external logic. The RC oscillator provides the most

S

Y

S

W

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Watchdog Timer

Rev. 1.30

12

January 7, 2009

HT48RU80/HT48CU80

·

All of the I/O ports maintain their original status.

The PDF flag is set and the TO flag is cleared.

clock may still come from the instruction clock and oper-

ates in the same manner except that in the HALT state

the WDT may stop counting and lose its protecting pur-

pose. In this situation the logic can only be restarted by

external logic. The high nibbles and bit 3 of the WDTS

are reserved for users defined flags, which can be used

to indicate some specified status.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a ²warm reset². After the TO and PDF flags are

examined, the cause for a chip reset can be determined.

The PDF flag is cleared by a system power-up or exe-

cuting the ²CLR WDT² instruction and is set when exe-

cuting the ²HALT² instruction. The TO flag is set if the

WDT time-out occurs, and causes a wake-up that only

resets the Program Counter and SP; the others remain

in their original status.

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) or 32kHz crystal oscil-

lator (RTC OSC) is strongly recommended, since the

HALT will stop the system clock.

WS2

WS1

WS0

Division Ratio

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in Port A can be independently selected to wake-up the

device by options. Awakening from an I/O port stimulus,

the program will resume execution of the next instruc-

tion. If it awakens from an interrupt, two sequence may

occur. If the related interrupt is disabled or the interrupt

is enabled but the stack is full, the program will resume

execution at the next instruction. If the interrupt is en-

abled and the stack is not full, the regular interrupt re-

sponse takes place. If an interrupt request flag is set to

²1² before entering the HALT mode, the wake-up func-

tion of the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 t_SYS(system clock

period) to resume normal operation. In other words, a

dummy period will be inserted after a wake-up. If the

wake-up results from an interrupt acknowledge signal,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

1:4

1:8

1:16

1:32

1:64

1:128

WDTS Register

The WDT overflow under normal operation will initialize

a ²chip reset² and set the status bit ²TO². But in the

HALT mode, the overflow will initialize a ²warm reset²

and only the Program Counter and SP are reset to zero.

To clear the WDT contents (including the WDT

prescaler), three methods are adopted; external reset (a

low level to RES), software instruction and a ²HALT² in-

struction. The software instruction include ²CLR WDT²

and the other set - ²CLR WDT1² and ²CLR WDT2². Of

these two types of instruction, only one can be active de-

pending on the option - ²CLR WDT times selection op-

tion². If the ²CLR WDT² is selected (i.e. CLRWDT times

equal one), any execution of the ²CLR WDT² instruction

will clear the WDT. In the case that ²CLR WDT1² and

²CLR WDT2² are chosen (i.e. CLRWDT times equal

two), these two instructions must be executed to clear

the WDT, otherwise, the WDT may reset the chip as a

result of time-out.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

The RTC oscillator still runs in the HALT mode (if the

RTC oscillator is enabled).

Reset

There are three ways in which a reset can occur:

·

RES reset during normal operation

RES reset during HALT

Power Down Operation - HALT

WDT time-out reset during normal operation

The HALT mode is initialized by the ²HALT² instruction

and results in the following:

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the Program Counter and SP, leav-

ing the other circuits in their original state. Some regis-

ters remain unchanged during other reset conditions.

Most registers are reset to the ²initial condition² when

the reset conditions are met. By examining the PDF and

TO flags, the program can distinguish between different

²chip resets².

·

The system oscillator will be turned off but the WDT

oscillator remains running (if the WDT oscillator is se-

lected).

·

The contents of the on chip RAM and registers remain

unchanged.

The WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

Rev. 1.30

13

January 7, 2009

HT48RU80/HT48CU80

V

D

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

m

0 . 0 1 F *

0

u

0

1

0

u

1

u

1

0

k

R

E

S

1

0

k

WDT time-out during normal operation

WDT wake-up HALT

m

0 . 1 F *

Note: ²u² stands for ²unchanged²

Reset Circuit

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra delay of 1024 system clock pulses when the sys-

tem resets (power-up, WDT time-out or RES reset) or

the system awakes from the HALT state.

Note:

²*² Make the length of the wiring, which is con-

nected to the RES pin as short as possible, to

avoid noise interference.

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

V

D

R

E

S

t

S S T

S

T

i

m

e

-

o

u

t

An extra option load time delay is added during system

reset (power-up, WDT time-out at normal mode or RES

reset).

C

h

i

p

R

e

s

e

t

Reset Timing Chart

The functional unit chip reset status are shown below.

Program Counter

Interrupt

000H

H

A

L

T

W

a

r

m

R

e

s

e

t

Disable

Clear

W

D

T

Prescaler

Clear. After master reset,

WDT begins counting

R

E

S

WDT

C

o

l

d

R

e

s

e

t

Timer/Event Counter Off

S

T

1

0

-

b

i

t

R

i

p

l

e

O

S

C

1

C

o

u

n

t

e

r

Input/Output Ports

Stack Pointer

Input mode

Points to the top of the stack

S

y

s

t

e

m

R

e

s

e

t

Reset Configuration

Rev. 1.30

14

January 7, 2009

HT48RU80/HT48CU80

The states of the registers are summarized in the following table.

Reset WDT Time-out RES Reset

(Power On) (Normal Operation) (Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)*

Register

TMR0H

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

uuuu uuuu

uu-u u---

TMR0L

TMR0C

TMR1H

TMR1L

TMR1C

TMR2

TMR2C

Program Counter

MP0

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

uuuu uuuu

uu-u u---

xxxx xxxx

00-0 1000

000H

xxxx xxxx

00-0 1000

000H

xxxx xxxx

00-0 1000

000H

xxxx xxxx

00-0 1000

000H

uuuu uuuu

uu-u uuuu

000H

xxxx xxxx

0000 0000

xxxx xxxx

--00 xxxx

-000 0000

-000 -000

0000 0111

1111 1111

0000 1011

0000 00x0

0000 0000

xxxx xxxx

uuuu uuuu

0000 0000

uuuu uuuu

--1u uuuu

-000 0000

-000 -000

0000 0111

1111 1111

0000 1011

0000 00x0

0000 0000

xxxx xxxx

uuuu uuuu

0000 0000

uuuu uuuu

--uu uuuu

-000 0000

-000 -000

0000 0111

1111 1111

0000 1011

0000 00x0

0000 0000

xxxx xxxx

uuuu uuuu

0000 0000

uuuu uuuu

--01 uuuu

-000 0000

-000 -000

0000 0111

1111 1111

0000 1011

0000 00x0

0000 0000

xxxx xxxx

uuuu uuuu

--11 uuuu

-uuu uuuu

-uuu -uuu

uuuu uuuu

MP1

BP

ACC

TBLP

TBLH

TBHP

STATUS

INTC0

INTC1

WDTS

PA

PAC

PB

PBC

PC

PCC

PD

PDC

PE

PEC

PF

PFC

PG

PGC

USR

UCR1

UCR2

TXR/RXR

BRG

Note:

²*² stands for ²warm reset²

²u² stands for ²unchanged²

²x² stands for ²unknown²

Rev. 1.30

15

January 7, 2009

HT48RU80/HT48CU80

tions to the TMR1H. Reading from the TMR1H will latch

the contents of TMR1H and TMR1L counters to the des-

tination and the lower-order byte buffer, respectively.

Reading the TMR1L will read the contents of the

lower-order byte buffer. The TMR1C is the Timer/Event

Counter 1 control register, which defines the operating

mode, counting enable or disable and active edge.

Timer/Event Counter

Three timer/event counters (TMR0, TMR1, TMR2) are

implemented in this microcontroller.

The Timer/Event Counter 0 contains a 16-bit program-

mable count-up counter and the clock may come from

an external source or from the system clock divided by 4

or RTC.

There are two registers related to timer/event counter,

namely, TMR2 (21H) and TMR2C (22H). In the

timer/event counter counting mode (T2ON=1), writing

TMR2 will only put the written data to the preload regis-

ter (8 bits). The timer/event counter preload register is

changed by each writing operations to the TMR2. Read-

ing from the TMR2 will also latch the TMR2 to the desti-

nation. The TMR2C is the timer/event counter control

register, which defines the operating mode, counting en-

able or disable and active edge.

The Timer/Event Counter 1 contains a 16-bit program-

mable count-up counter and the clock may come from

an external source or from the system clock divided by 4

or RTC.

The Timer/Event Counter 2 contains an 8-bit program-

mable count-up counter and the clock may come from

an external source or from the system clock or RTC.

Using the internal clock sources, there are two refer-

ence time-bases for the Timer/Event Counter 0. The in-

ternal clock source can be selected as coming from

The T0M0, T0M1 (TMR0C), T1M0, T1M1 (TMR1C),

T2M0, T2M1 (TMR2C) bits define the operating mode.

The event count mode is used to count external events,

which means the clock source comes from an external

pin (TMR0/TMR1/TMR2). The timer mode functions as

a normal timer with the clock source coming from the in-

struction clock or RTC clock (Timer0/Timer1/Timer2).

The pulse width measurement mode can be used to

count the high or low level duration of the external signal

(TMR0/TMR1/TMR2). The counting is based on the in-

struction clock or RTC clock (Timer0/Timer1/Timer2).

f

_SYS/4 (can always be optioned) or RTC (enabled only

by a system oscillator in the Int. RC+RTC mode) by op-

tions.

Using the internal clock sources, there are two refer-

ence time-bases for the Timer/Event Counter 1. The in-

ternal clock source can be selected as coming from

f

_SYS/4 (can always be optioned) or RTC (enabled only

by a system oscillator in the Int. RC+RTC mode) by op-

tions.

Using external clock input allows the user to count exter-

nal events, measure time internals or pulse widths, or

generate an accurate time base. While using the inter-

nal clock allows the user to generate an accurate time

base.

In the event count or timer mode, once the Timer/Event

Counter 0/1 starts counting, it will count from the current

contents in the Timer/Event Counter 0/1 to FFFFH.

Once overflow occurs, the counter is reloaded from the

Timer/Event Counter 0/1 preload register and at the

same time generates the interrupt request flag

(T0F/T1F; bit 5/6 of the INTC0).

There are three registers related to the Timer/Event

Counter 0, namely, TMR0H ([0CH]), TMR0L ([0DH]),

and TMR0C ([0EH]). Writing to the TMR0L will only put

the written data to an internal lower-order byte buffer (8

bits) and writing to the TMR0H will transfer the specified

data and the contents of the lower-order byte buffer to

TMR0H and TMR0L preload registers, respectively. The

Timer/Event Counter 0 preload register is changed by

each writing operations to theTMR0H. Reading from the

TMR0H will latch the contents of the TMR0H and

TMR0L counters to the destination and the lower-order

byte buffer, respectively. Reading the TMR0L will read

the contents of the lower-order byte buffer. The TMR0C

is the Timer/Event Counter 0 control register, which de-

fines the operating mode, counting enable or disable

and active edge.

In the event count or timer mode, once the Timer/Event

Counter 2 starts counting, it will count from the current

contents in the timer/event counter to FFH. Once over-

flow occurs, the counter is reloaded from the

Timer/Event Counter 2 preload register and at the same

time generates the corresponding interrupt request flag

(T2F; bit 6 of the INTC1).

In the pulse width measurement mode with the T0ON/

T1ON/T2ON and T0E/T1E/T2E bits equal to one, once

the TMR0/TMR1/TMR2 has received a transient from

low to high (or high to low if the T0E/T1E/T2E bits are

²0²) it will start counting until the TMR0/TMR1/ TMR2 re-

turns to the original level and resets the T0ON/T1ON/

T2ON. The measured result will remain in the

Timer/Event Counter 0/1/2 even if the activated tran-

sient occurs again. In other words, only one cycle mea-

surement can be done. Until setting the T0ON/T1ON/

T2ON, the cycle measurement will function again as

long as it receives further transient pulse. Note that, in

this operating mode, the Timer/Event Counter 0/1/2

starts counting not according to the logic level but ac-

There are three registers related to the Timer/Event

Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).

Writing to the TMR1L will only put the written data to an

internal lower-order byte buffer (8 bits) and writing to the

TMR1H will transfer the specified data and the contents

of the lower-order byte buffer to TMR1H and TMR1L

preload registers, respectively. The Timer/Event Coun-

ter 1 preload register is changed by each writing opera-

Rev. 1.30

16

January 7, 2009

HT48RU80/HT48CU80

Bit No.

Label

Function

0~2, 5

¾

Unused bit, read as ²0²

Defines the TMR0 active edge of the Timer/Event Counter 0

(0=active on low to high; 1=active on high to low)

3

4

T0E

T0ON

Enables or disables the Timer 0 counting (0=disable; 1=enable)

Defines the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

6

7

T0M0

T0M1

TMR0C (0EH) Register

Bit No.

Label

Function

0~2, 5

¾

Unused bit, read as ²0²

Defines the TMR1 active edge of the Timer/Event Counter 1

(0=active on low to high; 1=active on high to low)

3

4

T1E

T1ON

Enables or disables the Timer 1 counting (0=disable; 1=enable)

Defines the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

6

7

T1M0

T1M1

TMR1C (11H) Register

Bit No.

Label

Function

Defines the prescaler stages

000: f_INT=f_S/2

001: f_INT=f_S/4

010: f_INT=f_S/8

T2PSC0~

T2PSC2

0~2

011: f_INT=f_S/16

100: f_INT=f_S/32

101: f_INT=f_S/64

110: f_INT=f_S/128

111: f_INT=f_S/256

Defines the active edge of the TMR2 pin input signal

(0=active on low to high; 1=active on high to low)

3

T2E

4

5

T2ON

Enables or disables the timer counting (0=disable; 1=enable)

¾

Unused bit, read as ²0²

Defines the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

6

7

T2M0

T2M1

TMR2C (22H) Register

Rev. 1.30

17

January 7, 2009

HT48RU80/HT48CU80

cording to the transient edges. In the case of counter

overflows, the Counter 0/1/2 is reloaded from the

Timer/Event Counter 0/1/2 preload register and issues

the interrupt request just like the other two modes. To

enable the counting operation, the timer ON bit (T0ON:

bit 4 of the TMR0C; T1ON: bit 4 of the TMR1C; T2ON:

bit 4 of the TMR2C) should be set to 1.

able the corresponding interrupt services. In the case of

Timer/Event Counter 0/1/2 OFF condition, writing data

to the Timer/Event Counter 0/1/2 preload register will

also reload that data to the Timer/Event Counter 0/1/2.

But if the Timer/Event Counter 0/1/2 is turned on, data

written to it will only be kept in the Timer/Event Counter

0/1/2 preload register. The Timer/Event Counter 0/1/2

will still operate until overflow occurs (a Timer/Event

Counter 0/1/2 reloading will occur at the same time).

When the Timer/Event Counter 0/1/2 (reading

TMR0/TMR1/TMR2) is read, the clock will be blocked to

avoid errors. As clock blocking may results in a counting

error, this must be taken into consideration by the pro-

grammer.

In the pulse width measurement mode, the T0ON/

T1ON/T2ON will be cleared automatically after the mea-

surement cycle is completed. But in the other two

modes the T0ON/T1ON/T2ON can only be reset by in-

structions. The overflow of the Timer/Event Counter 0/1/

2 is one of the wake-up sources. No matter what the op-

eration mode is, writing a 0 to ET0I/ET1I/ET2I can dis-

D

a

t

a

B

u

s

f

S

Y

S

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4

M

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Timer/Event Counter 0

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Timer/Event Counter 2

Rev. 1.30

18

January 7, 2009

HT48RU80/HT48CU80

Input/Output Ports

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H, 17H, 19H, 1BH, 1DH and 26H.

There are 56 bidirectional input/output lines in the

microcontroller, labeled from PA to PG, which are

mapped to the data memory of [12H], [14H], [16H],

[18H], [1AH], [1CH] and [25H] respectively. All of these

I/O ports can be used for input and output operations.

For input operation, these ports are non-latching, that is,

the inputs must be ready at the T2 rising edge of

instruction ²MOV A,[m]² (m=12H, 14H, 16H, 18H, 1AH,

1CH or 25H). For output operation, all the data is latched

and remains unchanged until the output latch is rewrit-

ten.

After a chip reset, these input/output lines remain at high

levels or floating state (depending on the pull-high op-

tions). Each bit of these input/output latches can be set

or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H, 18H, 1AH, 1CH or 25H) instructions.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each I/O line has its own control register (PAC, PBC,

PCC, PDC, PEC, PFC, PGC) to control the input/output

configuration. With this control register, CMOS output or

Schmitt trigger input with or without pull-high resistor

structures can be reconfigured dynamically under soft-

ware control. To function as an input, the corresponding

latch of the control register must write ²1². The input

source also depends on the control register. If the con-

trol register bit is ²1², the input will read the pad state. If

the control register bit is ²0², the contents of the latches

will move to the internal bus. The latter is possible in the

²read-modify-write² instruction.

Each line of Port A has the capability of waking-up the

device.

There is a pull-high option available for all I/O lines (port

option). Once the pull-high option of an I/O line is se-

lected, the I/O line has a pull-high resistor. Otherwise,

the pull-high resistor is absent. It should be noted that a

non-pull-high I/O line operating in input mode will cause

a floating state.

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PA, PB, PC2~PC7, PD, PE, PF, PG Input/Output Ports

Rev. 1.30

19

January 7, 2009

HT48RU80/HT48CU80

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PC1/RX Input/Output Ports

Low Voltage Reset - LVR

The relationship between V_DDand V_LVRis shown below.

The microcontroller provides a low voltage reset circuit

in order to monitor the supply voltage of the device. If the

supply voltage of the device is within the range

0.9V~V_LVR, such as changing a battery, the LVR will au-

tomatically reset the device internally.

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The LVR includes the following specifications:

3

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·

The low voltage (0.9V~V_LVR) has to remain in its origi-

nal state for longer than 1ms. If the low voltage state

does not exceed 1ms, the LVR will ignore it and will

not perform a reset function.

2

.

2

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0

.

9

V

V_OPRis the voltage range for proper chip opera-

tion at 4MHz system clock.

·

Note:

The LVR uses an ²OR² function with the external RES

signal to perform a chip reset.

Rev. 1.30

20

January 7, 2009

HT48RU80/HT48CU80

V

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Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock

pulses before entering the normal operation.

*2: Since the low voltage has to maintain its original state for longer than 1ms, therefore a 1ms delay enters the

reset mode.

·

UART Bus Serial Interface

UART external pin interfacing

To communicate with an external serial interface, the

internal UART has two external pins known as TX and

RX. The TX pin is the UART transmitter pin, which can

be used as a general purpose I/O pin if the pin is not

configured as a UART transmitter, which occurs when

the TXEN bit in the UCR2 control register is equal to

zero. Similarly, the RX pin is the UART receiver pin,

which can also be used as a general purpose I/O pin,

if the pin is not configured as a receiver, which occurs

if the RXEN bit in the UCR2 register is equal to zero.

Along with the UARTEN bit, the TXEN and RXEN bits,

if set, will automatically setup these I/O pins to their re-

spective TX output and RX input conditions and dis-

able any pull-high resistor option which may exist on

the RX pin.

The HT48RU80/HT48CU80 devices contain an inte-

grated full-duplex asynchronous serial communications

UART interface that enables communication with exter-

nal devices that contain a serial interface. The UART

function has many features and can transmit and re-

ceive data serially by transferring a frame of data with

eight or nine data bits per transmission as well as being

able to detect errors when the data is overwritten or in-

correctly framed. The UART function possesses its own

internal interrupt which can be used to indicate when a

reception occurs or when a transmission terminates.

·

UART features

The integrated UART function contains the following

features:

¨

Full-duplex, asynchronous communication

8 or 9 bits character length

·

UART data transfer scheme

The block diagram shows the overall data transfer

structure arrangement for the UART. The actual data

to be transmitted from the MCU is first transferred to

the TXR register by the application program. The data

will then be transferred to the Transmit Shift Register

from where it will be shifted out, LSB first, onto the TX

pin at a rate controlled by the Baud Rate Generator.

Only the TXR register is mapped onto the MCU Data

Memory, the Transmit Shift Register is not mapped

and is therefore inaccessible to the application pro-

gram.

Even, odd or no parity options

One or two stop bits

Baud rate generator with 8-bit prescaler

Parity, framing, noise and overrun error detection

Support for interrupt on address detect

(last character bit=1)

¨

Separately enabled transmitter and receiver

2-byte Deep Fifo Receive Data Buffer

Transmit and receive interrupts

Interrupts can be initialized by the following

conditions:

Data to be received by the UART is accepted on the

external RX pin, from where it is shifted in, LSB first, to

the Receiver Shift Register at a rate controlled by the

Baud Rate Generator. When the shift register is full,

the data will then be transferred from the shift register

to the internal RXR register, where it is buffered and

can be manipulated by the application program.

-

Transmitter Empty

-

Transmitter Idle

-

Receiver Full

-

Receiver Overrun

-

Address Mode Detect

Rev. 1.30

21

January 7, 2009

HT48RU80/HT48CU80

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UART Data Transfer Scheme

ter with TIDLE set and then writing to the TXR regis-

ter. The flag is not generated when a data

character, or a break is queued and ready to be

sent.

Only the RXR register is mapped onto the MCU Data

Memory, the Receiver Shift Register is not mapped

and is therefore inaccessible to the application pro-

gram.

¨

RXIF

It should be noted that the actual register for data

transmission and reception, although referred to in the

text, and in application programs, as separate TXR

and RXR registers, only exists as a single shared reg-

ister in the Data Memory. This shared register known

as the TXR/RXR register is used for both data trans-

mission and data reception.

The RXIF flag is the receive register status flag.

When this read only flag is ²0² it indicates that the

RXR read data register is empty. When the flag is

²1² it indicates that the RXR read data register con-

tains new data. When the contents of the shift regis-

ter are transferred to the RXR register, an interrupt

is generated if RIE=1 in the UCR2 register. If one or

more errors are detected in the received word, the

appropriate receive-related flags NF, FERR, and/or

PERR are set within the same clock cycle. The

RXIF flag is cleared when the USR register is read

with RXIF set, followed by a read from the RXR reg-

ister, and if the RXR register has no data available.

·

UART status and control registers

There are five control registers associated with the

UART function. The USR, UCR1 and UCR2 registers

control the overall function of the UART, while the

BRG register controls the Baud rate. The actual data

to be transmitted and received on the serial interface

is managed through the TXR/RXR data registers.

¨

RIDLE

The RIDLE flag is the receiver status flag. When

this read only flag is ²0² it indicates that the receiver

is between the initial detection of the start bit and

the completion of the stop bit. When the flag is ²1² it

indicates that the receiver is idle. Between the com-

pletion of the stop bit and the detection of the next

start bit, the RIDLE bit is ²1² indicating that the

UART is idle.

·

USR register

The USR register is the status register for the UART,

which can be read by the program to determine the

present status of the UART. All flags within the USR

register are read only.

Further explanation on each of the flags is given below:

¨

TXIF

OERR

The TXIF flag is the transmit data register empty

flag. When this read only flag is ²0² it indicates that

the character is not transferred to the transmit shift

registers. When the flag is ²1² it indicates that the

transmit shift register has received a character from

the TXR data register. The TXIF flag is cleared by

reading the UART status register (USR) with TXIF

set and then writing to the TXR data register. Note

that when the TXEN bit is set, the TXIF flag bit will

also be set since the transmit buffer is not yet full.

The OERR flag is the overrun error flag, which indi-

cates when the receiver buffer has overflowed.

When this read only flag is ²0² there is no overrun er-

ror. When the flag is ²1² an overrun error occurs

which will inhibit further transfers to the RXR receive

data register. The flag is cleared by a software se-

quence, which is a read to the status register USR

followed by an access to the RXR data register.

FERR

¨

TIDLE

The FERR flag is the framing error flag. When this

read only flag is ²0² it indicates no framing error.

When the flag is ²1² it indicates that a framing error

has been detected for the current character. The

flag can also be cleared by a software sequence

which will involve a read to the USR status register

followed by an access to the RXR data register.

The TIDLE flag is known as the transmission com-

plete flag. When this read only flag is ²0² it indicates

that a transmission is in progress. This flag will be

set to ²1² when the TXIF flag is ²1² and when there

is no transmit data, or break character being trans-

mitted. When TIDLE is ²1² the TX pin becomes idle.

The TIDLE flag is cleared by reading the USR regis-

Rev. 1.30

22

January 7, 2009

HT48RU80/HT48CU80

b

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¨

·

NF

UCR1 register

The NF flag is the noise flag. When this read only

flag is ²0² it indicates a no noise condition. When

the flag is ²1² it indicates that the UART has de-

tected noise on the receiver input. The NF flag is set

during the same cycle as the RXIF flag but will not

be set in the case of an overrun. The NF flag can be

cleared by a software sequence which will involve a

read to the USR status register, followed by an ac-

cess to the RXR data register.

The UCR1 register together with the UCR2 register

are the two UART control registers that are used to set

the various options for the UART function, such as

overall on/off control, parity control, data transfer bit

length etc.

Further explanation on each of the bits is given below:

¨

TX8

This bit is only used if 9-bit data transfers are used,

in which case this bit location will store the 9th bit of

the transmitted data, known as TX8. The BNO bit is

used to determine whether data transfers are in

8-bit or 9-bit format.

¨

PERR

The PERR flag is the parity error flag. When this

read only flag is ²0² it indicates that a parity error

has not been detected. When the flag is ²1² it indi-

cates that the parity of the received word is incor-

rect. This error flag is applicable only if Parity mode

(odd or even) is selected. The flag can also be

cleared by a software sequence which involves a

read to the USR status register, followed by an ac-

cess to the RXR data register.

¨

RX8

This bit is only used if 9-bit data transfers are used,

in which case this bit location will store the 9th bit of

the received data, known as RX8. The BNO bit is

used to determine whether data transfers are in

8-bit or 9-bit format.

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Rev. 1.30

23

January 7, 2009

HT48RU80/HT48CU80

¨

TXBRK

disabled it will empty the buffer so any character re-

maining in the buffer will be discarded. In addition,

the baud rate counter value will be reset. When the

UART is disabled, all error and status flags will be

reset. The TXEN, RXEN, TXBRK, RXIF, OERR,

FERR, PERR, and NF bits will be cleared, while the

TIDLE, TXIF and RIDLE bits will be set. Other con-

trol bits in UCR1, UCR2, and BRG registers will re-

main unaffected. If the UART is active and the

UARTEN bit is cleared, all pending transmissions

and receptions will be terminated and the module

will be reset as defined above. When the UART is

re-enabled it will restart in the same configuration.

The TXBRK bit is the Transmit Break Character bit.

When this bit is ²0² there are no break characters

and the TX pin operates normally. When the bit is

²1² there are transmit break characters and the

transmitter will send logic zeros. When equal to ²1²

after the buffered data has been transmitted, the

transmitter output is held low for a minimum of a

13-bit length and until the TXBRK bit is reset.

¨

STOPS

This bit determines if one or two stop bits are to be

used. When this bit is equal to ²1² two stop bits are

used, if the bit is equal to ²0² then only one stop bit

is used.

·

UCR2 register

The UCR2 register is the second of the two UART

control registers and serves several purposes. One of

its main functions is to control the basic enable/dis-

able operation of the UART Transmitter and Receiver

as well as enabling the various UART interrupt

sources. The register also serves to control the baud

rate speed, receiver wake-up enable and the address

detect enable.

¨

PRT

This is the parity type selection bit. When this bit is

equal to ²1² odd parity will be selected, if the bit is

equal to ²0² then even parity will be selected.

PREN

This is parity enable bit. When this bit is equal to ²1²

the parity function will be enabled, if the bit is equal

to ²0² then the parity function will be disabled.

Further explanation on each of the bits is given below:

¨

TEIE

BNO

This bit enables or disables the transmitter empty

interrupt. If this bit is equal to ²1² when the transmit-

ter empty TXIF flag is set, due to a transmitter

empty condition, the UART interrupt request flag

will be set. If this bit is equal to ²0² the UART inter-

rupt request flag will not be influenced by the condi-

tion of the TXIF flag.

This bit is used to select the data length format,

which can have a choice of either 8-bits or 9-bits. If

this bit is equal to ²1² then a 9-bit data length will be

selected, if the bit is equal to ²0² then an 8-bit data

length will be selected. If 9-bit data length is se-

lected then bits RX8 and TX8 will be used to store

the 9th bit of the received and transmitted data re-

spectively.

¨

TIIE

¨

UARTEN

This bit enables or disables the transmitter idle in-

terrupt. If this bit is equal to ²1² when the transmitter

idle TIDLE flag is set, the UART interrupt request

flag will be set. If this bit is equal to ²0² the UART in-

terrupt request flag will not be influenced by the

condition of the TIDLE flag.

The UARTEN bit is the UART enable bit. When the

bit is ²0² the UART will be disabled and the RX and

TX pins will function as General Purpose I/O pins.

When the bit is ²1² the UART will be enabled and

the TX and RX pins will function as defined by the

TXEN and RXEN control bits. When the UART is

b

7

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Rev. 1.30

24

January 7, 2009

HT48RU80/HT48CU80

¨

RIE

TX pin will be controlled by the UART. Clearing the

TXEN bit during a transmission will cause the trans-

mission to be aborted and will reset the transmitter.

If this occurs, the TX pin can be used as a general

purpose I/O pin.

This bit enables or disables the receiver interrupt. If

this bit is equal to ²1² when the receiver overrun

OERR flag or receive data available RXIF flag is

set, the UART interrupt request flag will be set. If

this bit is equal to ²0² the UART interrupt will not be

influenced by the condition of the OERR or RXIF

flags.

·

Baud rate generator

To setup the speed of the serial data communication,

the UART function contains its own dedicated baud

rate generator. The baud rate is controlled by its own

internal free running 8-bit timer, the period of which is

determined by two factors. The first of these is the

value placed in the BRG register and the second is the

value of the BRGH bit within the UCR2 control regis-

ter. The BRGH bit decides, if the baud rate generator

is to be used in a high speed mode or low speed

mode, which in turn determines the formula that is

used to calculate the baud rate. The value in the BRG

register determines the division factor, N, which is

used in the following baud rate calculation formula.

Note that N is the decimal value placed in the BRG

register and has a range of between 0 and 255.

WAKE

This bit enables or disables the receiver wake-up

function. If this bit is equal to ²1² and if the MCU is in

the Power Down Mode, a low going edge on the RX

input pin will wake-up the device. If this bit is equal

to ²0² and if the MCU is in the Power Down Mode,

any edge transitions on the RX pin will not wake-up

the device.

ADDEN

The ADDEN bit is the address detect mode bit.

When this bit is ²1² the address detect mode is en-

abled. When this occurs, if the 8th bit, which corre-

sponds to RX7 if BNO=0, or the 9th bit, which

corresponds to RX8 if BNO=1, has a value of ²1²

then the received word will be identified as an ad-

dress, rather than data. If the corresponding inter-

rupt is enabled, an interrupt request will be

generated each time the received word has the ad-

dress bit set, which is the 8 or 9 bit depending on the

value of BNO. If the address bit is ²0² an interrupt

will not be generated, and the received data will be

discarded.

UCR2 BRGH Bit

0

1

f_SYS

Baud Rate

[64 (N+ 1)]

[16 (N+ 1)]

By programming the BRGH bit which allows selection

of the related formula and programming the required

value in the BRG register, the required baud rate can

be setup. Note that because the actual baud rate is

determined using a discrete value, N, placed in the

BRG register, there will be an error associated be-

tween the actual and requested value. The following

example shows how the BRG register value N and the

error value can be calculated.

¨

BRGH

The BRGH bit selects the high or low speed mode

of the Baud Rate Generator. This bit, together with

the value placed in the BRG register, controls the

Baud Rate of the UART. If this bit is equal to ²1² the

high speed mode is selected. If the bit is equal to ²0²

the low speed mode is selected.

Calculating the register and error values

For a clock frequency of 8MHz, and with BRGH set to

²0² determine the BRG register value N, the actual

baud rate and the error value for a desired baud rate

of 9600.

¨

RXEN

The RXEN bit is the Receiver Enable Bit. When this

bit is equal to ²0² the receiver will be disabled with

any pending data receptions being aborted. In addi-

tion the buffer will be reset. In this situation the RX

pin can be used as a general purpose I/O pin. If the

RXEN bit is equal to ²1² the receiver will be enabled

and if the UARTEN bit is equal to ²1² the RX pin will

be controlled by the UART. Clearing the RXEN bit

during a transmission will cause the data reception

to be aborted and will reset the receiver. If this oc-

curs, the RX pin can be used as a general purpose

I/O pin.

From the above table the desired baud rate BR

f_SYS

=

[64 (N+ 1)]

f_SYS

Re-arranging this equation gives N =

- 1

(BRx64)

8000000

Giving a value for N =

- 1 = 12.0208

(9600x64)

To obtain the closest value, a decimal value of 12

should be placed into the BRG register. This gives an

¨

TXEN

The TXEN bit is the Transmitter Enable Bit. When

this bit is equal to ²0² the transmitter will be disabled

with any pending transmissions being aborted. In

addition the buffer will be reset. In this situation the

TX pin can be used as a general purpose I/O pin. If

the TXEN bit is equal to ²1² the transmitter will be

enabled and if the UARTEN bit is equal to ²1² the

actual or calculated baud rate value of

8000000

BR =

= 9615

[64(12 + 1)]

9

6

1

5

9

6

0

Therefore the error is equal to

= 0.16%

9

6

0

Rev. 1.30

25

January 7, 2009

HT48RU80/HT48CU80

The following tables show actual values of baud rate and error values for the two values of BRGH.

Baud Rates for BRGH=0

Baud

Rate

K/BPS

f

_SYS=8MHz

f_SYS=7.159MHz

BRG Kbaud Error

f_SYS=4MHz

f_SYS=3.579545MHz

BRG Kbaud Error

0.3

1.2

207

51

25

12

6

0.300

1.202

2.404

4.808

8.929

20.83

¾

0.00

0.16

-6.99

8.51

¾

185

46

22

11

5

0.300

1.19

0.00

-0.83

1.32

-2.9

¾

103

51

25

12

6

¾

92

46

22

11

5

¾

1.202

2.404

4.807

9.615

0.16

1.203

2.38

0.23

-0.83

1.32

-2.9

2.4

2.432

4.661

9.321

18.643

¾

4.8

4.863

9.322

18.64

37.29

55.93

111.86

9.6

19.2

38.4

57.6

115.2

17.857 -6.99

41.667 8.51

2

1

62.5

125

8.51

1

0

62.5

¾

8.51

¾

0

55.93

¾

-2.9

¾

0

¾

Baud Rates and Error Values for BRGH = 0

Baud Rates for BRGH=1

Baud

Rate

K/BPS

f

_SYS=8MHz

f_SYS=7.159MHz

f_SYS=4MHz

BRG Kbaud Error

f_SYS=3.579545MHz

BRG Kbaud Error

0.3

1.2

¾

207

103

51

25

12

8

¾

185

92

46

22

11

7

¾

207

103

51

25

12

6

¾

185

92

46

22

11

5

¾

0.23

-0.83

1.32

-2.9

¾

1.202

2.404

4.808

9.615

0.16

1.203

2.406

4.76

¾

2.4

2.404

4.808

9.615

0.16

2.405

4.811

0.23

4.8

9.6

9.520 -0.832

19.454 1.32

9.727

18.643

37.286

55.930

111.86

¾

19.2

38.4

57.6

115.2

250

19.231 0.16

38.462 0.16

55.556 -3.55

19.231 0.16

35.714 -6.99

37.287

55.93

111.86

¾

-2.9

¾

3

62.5

125

250

8.51

0

3

125

250

8.51

0

3

1

0

¾

Baud Rates and Error Values for BRGH = 1

·

LSB first. Although the UART¢s transmitter and re-

ceiver are functionally independent, they both use

the same data format and baud rate. In all cases

stop bits will be used for data transmission.

Setting up and controlling the UART

¨

Introduction

For data transfer, the UART function utilizes a

non-return-to-zero, more commonly known as

NRZ, format. This is composed of one start bit, eight

or nine data bits, and one or two stop bits. Parity is

supported by the UART hardware, and can be

setup to be even, odd or no parity. For the most

common data format, 8 data bits along with no par-

ity and one stop bit, denoted as 8, N, 1, is used as

the default setting, which is the setting at power-on.

The number of data bits and stop bits, along with the

parity, are setup by programming the corresponding

BNO, PRT, PREN, and STOPS bits in the UCR1

register. The baud rate used to transmit and receive

data is setup using the internal 8-bit baud rate gen-

erator, while the data is transmitted and received

¨

Enabling/disabling the UART

The basic on/off function of the internal UART func-

tion is controlled using the UARTEN bit in the UCR1

register. As the UART transmit and receive pins, TX

and RX respectively, are pin-shared with normal I/O

pins, one of the basic functions of the UARTEN con-

trol bit is to control the UART function of these two

pins. If the UARTEN, TXEN and RXEN bits are set,

then these two I/O pins will be setup as a TX output

pin and an RX input pin respectively, in effect dis-

abling the normal I/O pin function. If no data is being

transmitted on the TX pin then it will default to a

logic high value.

Rev. 1.30

26

January 7, 2009

HT48RU80/HT48CU80

·

Clearing the UARTEN bit will disable the TX and RX

pins and allow these two pins to be used as normal

I/O pins. When the UART function is disabled the

buffer will be reset to an empty condition, at the

same time discarding any remaining residual data.

Disabling the UART will also reset the error and sta-

tus flags with bits TXEN, RXEN, TXBRK, RXIF,

OERR, FERR, PERR and NF being cleared while

bits TIDLE, TXIF and RIDLE will be set. The re-

maining control bits in the UCR1, UCR2 and BRG

registers will remain unaffected. If the UARTEN bit

in the UCR1 register is cleared while the UART is

active, then all pending transmissions and recep-

tions will be immediately suspended and the UART

will be reset to a condition as defined above. If the

UART is then subsequently re-enabled, it will restart

again in the same configuration.

UART transmitter

Data word lengths of either 8 or 9 bits, can be selected

by programming the BNO bit in the UCR1 register.

When BNO bit is set, the word length will be set to 9

bits. In this case the 9th bit, which is the MSB, needs

to be stored in the TX8 bit in the UCR1 register. At the

transmitter core lies the Transmitter Shift Register,

more commonly known as the TSR, whose data is ob-

tained from the transmit data register, which is known

as the TXR register. The data to be transmitted is

loaded into this TXR register by the application pro-

gram. The TSR register is not written to with new data

until the stop bit from the previous transmission has

been sent out. As soon as this stop bit has been trans-

mitted, the TSR can then be loaded with new data

from the TXR register, if it is available. It should be

noted that the TSR register, unlike many other regis-

ters, is not directly mapped into the Data Memory area

and as such is not available to the application program

for direct read/write operations. An actual transmis-

sion of data will normally be enabled when the TXEN

bit is set, but the data will not be transmitted until the

TXR register has been loaded with data and the baud

rate generator has defined a shift clock source. How-

ever, the transmission can also be initiated by first

loading data into the TXR register, after which the

TXEN bit can be set. When a transmission of data be-

gins, the TSR is normally empty, in which case a

transfer to the TXR register will result in an immediate

transfer to the TSR. If during a transmission the TXEN

bit is cleared, the transmission will immediately cease

and the transmitter will be reset. The TX output pin will

then return to having a normal general purpose I/O pin

function.

¨

Data, parity and stop bit selection

The format of the data to be transferred, is com-

posed of various factors such as data bit length,

parity on/off, parity type, address bits and the num-

ber of stop bits. These factors are determined by

the setup of various bits within the UCR1 register.

The BNO bit controls the number of data bits which

can be set to either 8 or 9, the PRT bit controls the

choice of odd or even parity, the PREN bit controls

the parity on/off function and the STOPS bit decides

whether one or two stop bits are to be used. The fol-

lowing table shows various formats for data trans-

mission. The address bit identifies the frame as an

address character. The number of stop bits, which

can be either one or two, is independent of the data

length.

Start

Bit

Data Address Parity

Bits Bits Bits

Stop

Bit

Example of 8-bit Data Formats

¨

Transmitting data

1

8

7

0

1

0

1

When the UART is transmitting data, the data is

shifted on the TX pin from the shift register, with the

least significant bit first. In the transmit mode, the

TXR register forms a buffer between the internal

bus and the transmitter shift register. It should be

noted that if 9-bit data format has been selected,

then the MSB will be taken from the TX8 bit in the

UCR1 register. The steps to initiate a data transfer

can be summarized as follows:

1¹

Example of 9-bit Data Formats

1

9

8

0

1

0

1

1¹

-

Make the correct selection of the BNO, PRT,

Transmitter Receiver Data Format

PREN and STOPS bits to define the required

word length, parity type and number of stop bits.

The following diagram shows the transmit and receive

waveforms for both 8-bit and 9-bit data formats.

-

Setup the BRG register to select the desired baud

rate.

N

e

x

t

P

a

r

i

t

y

B

i

t

S

t

a

r

t

S

t

a

r

t

B

i

t

B

i

t

0

B

i

t

1

B

i

t

2

B

i

t

3

B

i

t

4

B

i

t

5

B

i

t

6

B

i

t

7

B

i

t

S

t

o

p

B

i

t

8

-

B

i

t

D

a

t

a

F

o

r

m

a

t

N

e

x

t

P

a

r

i

t

y

B

i

t

S

t

a

r

t

S

t

a

r

t

B

i

t

B

i

t

0

B

i

t

1

B

i

t

2

B

i

t

3

B

i

t

4

B

i

t

5

B

i

t

6

B

i

t

7

B

i

t

8

B

i

t

S

t

o

p

B

i

t

9

-

B

i

t

D

a

t

a

F

o

r

m

a

t

Rev. 1.30

27

January 7, 2009

HT48RU80/HT48CU80

-

Set the TXEN bit to ensure that the TX pin is used

as a UART transmitter pin and not as an I/O pin.

the Receive Serial Shift Register, commonly known

as the RSR. The data which is received on the RX

external input pin, is sent to the data recovery block.

The data recovery block operating speed is 16 times

that of the baud rate, while the main receive serial

shifter operates at the baud rate. After the RX pin is

sampled for the stop bit, the received data in RSR is

transferred to the receive data register, if the register

is empty. The data which is received on the external

RX input pin is sampled three times by a majority de-

tect circuit to determine the logic level that has been

placed onto the RX pin. It should be noted that the

RSR register, unlike many other registers, is not di-

rectly mapped into the Data Memory area and as

such is not available to the application program for

direct read/write operations.

Access the USR register and write the data that is

to be transmitted into the TXR register. Note that

this step will clear the TXIF bit.

-

This sequence of events can now be repeated to

send additional data.

It should be noted that when TXIF=0, data will be in-

hibited from being written to the TXR register. Clear-

ing the TXIF flag is always achieved using the

following software sequence:

1. A USR register access

2. A TXR register write execution

The read-only TXIF flag is set by the UART hard-

ware and if set indicates that the TXR register is

empty and that other data can now be written into

the TXR register without overwriting the previous

data. If the TEIE bit is set then the TXIF flag will gen-

erate an interrupt.

¨

Receiving data

When the UART receiver is receiving data, the data

is serially shifted in on the external RX input pin,

LSB first. In the read mode, the RXR register forms

a buffer between the internal bus and the receiver

shift register. The RXR register is a two byte deep

FIFO data buffer, where two bytes can be held in the

FIFO while a third byte can continue to be received.

Note that the application program must ensure that

the data is read from RXR before the third byte has

been completely shifted in, otherwise this third byte

will be discarded and an overrun error OERR will be

subsequently indicated. The steps to initiate a data

transfer can be summarized as follows:

During a data transmission, a write instruction to the

TXR register will place the data into the TXR regis-

ter, which will be copied to the shift register at the

end of the present transmission. When there is no

data transmission in progress, a write instruction to

the TXR register will place the data directly into the

shift register, resulting in the commencement of

data transmission, and the TXIF bit being immedi-

ately set. When a frame transmission is complete,

which happens after stop bits are sent or after the

break frame, the TIDLE bit will be set. To clear the

TIDLE bit the following software sequence is used:

1. A USR register access

-

Make the correct selection of BNO, PRT, PREN

and STOPS bits to define the word length, parity

type and number of stop bits.

2. A TXR register write execution

-

Setup the BRG register to select the desired baud

Note that both the TXIF and TIDLE bits are cleared

by the same software sequence.

rate.

-

Set the RXEN bit to ensure that the RX pin is used

¨

Transmit break

as a UART receiver pin and not as an I/O pin.

If the TXBRK bit is set then break characters will be

sent on the next transmission. Break character

transmission consists of a start bit, followed by 13´

N ¢0¢ bits and stop bits, where N=1, 2, etc. If a break

character is to be transmitted then the TXBRK bit

must be first set by the application program, then

cleared to generate the stop bits. Transmitting a

break character will not generate a transmit inter-

rupt. Note that a break condition length is at least 13

bits long. If the TXBRK bit is continually kept at a

logic high level then the transmitter circuitry will

transmit continuous break characters. After the ap-

plication program has cleared the TXBRK bit, the

transmitter will finish transmitting the last break

character and subsequently send out one or two

stop bits. The automatic logic highs at the end of the

last break character will ensure that the start bit of

the next frame is recognized.

At this point the receiver will be enabled which will

begin to look for a start bit.

When a character is received the following se-

quence of events will occur:

-

The RXIF bit in the USR register will be set when

RXR register has data available, at least one


型号：	HT48RU80(48SSOP-A)
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Microcontroller, 8-Bit, MROM, 4MHz, CMOS, PDSO48 LTE 微控制器光电二极管
文件：	总51页 (文件大小：357K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT48RU80(48SSOP-A) [HOLTEK]

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