HT49R50A-1(64LQFP-A)

HT49R50A-1/HT49C50-1/HT49C50L

LCD Type 8-Bit MCU

Technical Document

·

Tools Information

FAQs

Application Note

-

HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs

HA0024E Using the RTC in the HT49 MCU Series

HA0025E Using the Time Base in the HT49 MCU Series

HA0026E Using the I/O Ports on the HT49 MCU Series

HA0027E Using the Timer/Event Counter in the HT49 MCU Series

HA0075E MCU Reset and Oscillator Circuits Application Note

Features

·

Operating voltage:

On-chip crystal, RC and 32768Hz crystal oscillator

f

_SYS=4MHz: 2.2V~5.5V for HT49R50A-1/HT49C50-1

_SYS=8MHz: 3.3V~5.5V for HT49R50A-1/HT49C50-1

_SYS=500kHz: 1.2V~2.2V for HT49C50L

HALT function and wake-up feature reduce power

consumption

·

6-level subroutine nesting

Bit manipulation instruction

15-bit table read instruction

·

8 input lines

12 bidirectional I/O lines

Two external interrupt input

Up to 0.5ms instruction cycle with 8MHz system clock

for HT49R50A-1/HT49C50-1

Two 8-bit programmable timer/event counter with

PFD (programmable frequency divider) function

·

Up to 8ms instruction cycle with 500kHz system clock

for HT49C50L

·

LCD driver with 33´2, 33´3 or 32´4 segments

4K´15 program memory

160´8 data memory RAM

Real Time Clock (RTC)

8-bit prescaler for RTC

Watchdog Timer

·

63 powerful instructions

All instructions in 1 or 2 machine cycles

Low voltage reset/detector function

for HT49R50A-1/HT49C50-1

·

48-pin SSOP, 64-pin LQFP and

100-pin LQFP packages

Buzzer output

General Description

The HT49R50A-1/HT49C50-1/HT49C50L are 8-bit,

high performance, RISC architecture microcontroller

devices specifically designed for a wide range of LCD

applications. The mask version HT49C50-1 and

HT49C50L are fully pin and functionally compatible with

the OTP version HT49R50A-1 device. The HT49C50L

is a low voltage version, with the ability to operate at a

minimum power supply of 1.2V, making it suitable for

single cell battery applications.

The advantages of low power consumption, I/O flexibil-

ity, programmable frequency divider, timer functions,

oscillator options, HALT and wake-up functions and

buzzer driver in addition to a flexible and configurable

LCD interface, enhance the versatility of these devices

to control a wide range of LCD-based application possi-

bilities such as measuring scales, electronic multi-

meters, gas meters, timers, calculators, remote

controllers and many other LCD-based industrial and

home appliance applications.

Rev. 2.40

1

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Block Diagram

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Rev. 2.40

2

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Pin Assignment

P

A

0

1

/

B

Z

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4

3

2

8

7

6

5

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1

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2

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1

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4

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A

8 2 7 7

7 9 7 6

8 8 8 8 3 8 4 8 5 8 8 6 9 7 9 8 9 1 9 9 0 9 1 9 2 9 3 9 4 7 9 5 1 9 6 7 8 8 0 9 0

8 0

7

P

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1

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4

Rev. 2.40

3

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Pin Description

Pin Name

I/O

Options

Description

PA0~PA7 constitute an 8-bit bidirectional input/output port with Schmitt trig-

ger input capability. Each pin on port can be configured as wake-up input by

options. PA0~PA3 can be configured as CMOS output or NMOS input/out-

PA0/BZ

PA1/BZ

PA2

Wake-up

I/O Pull-high or None put with or without pull-high resistor by options. PA4~PA7 are always

CMOS or NMOS pull-high NMOS input/output. Of the eight bits, PA0~PA1 can be set as I/O

pins or buzzer outputs by options. PA3 can be set as an I/O pin or as a PFD

output also by options.

PA3/PFD

PA4~PA7

PB0/INT0

PB1/INT1

PB2/TMR0

PB3/TMR1

PB4~PB7

PB0~PB7 constitute an 8-bit Schmitt trigger input port. Each pin on port are

with pull-high resistor. Of the eight bits, PB0 and PB1 can be set as input

I

pins or as external interrupt control pins (INT0) and (INT1) respectively, by

software application. PB2 and PB3 can be set as input pin or as timer/event

counter input pin TMR0 and TMR1 also by software application.

¾

PC0~PC3 constitute a 4-bit bidirectional input/output port with Schmitt trig-

ger input capability. On the port, such can be configured as CMOS output or

NMOS input/output with or without pull-high resistor by options.

Pull-high or None

CMOS or NMOS

PC0~PC3

V2

I/O

I

Voltage pump for HT49R50A-1/HT49C50-1.

LCD power supply for HT49C50L.

¾

LCD power supply for HT49R50A-1/HT49C50-1.

Voltage pump for HT49C50L.

VLCD

I

¾

V1, C1, C2

I

Voltage pump

COM0~COM2

COM3/SEG32

1/2, 1/3 or 1/4

Duty

SEG32 can be set as a segment or as a common output driver for LCD

panel by options. COM0~COM2 are outputs for LCD panel plate.

O

SEG0~SEG31

LCD driver outputs for LCD panel segments

¾

OSC1 and OSC2 are connected to an RC network or a crystal (by options)

for the internal system clock. In the case of RC operation, OSC2 is the out-

put terminal for 1/4 system clock.

OSC1

OSC2

I

Crystal or RC

O

The system clock may come from the RTC oscillator. If the system clock co-

mes from RTCOSC, these two pins can be floating.

Real time clock oscillators. OSC3 and OSC4 are connected to a 32768Hz

crystal oscillator for timing purposes or to a system clock source (depend-

ing on the options).

OSC3

OSC4

I

RTC or

O

System Clock

No built-in capacitor

RES

VSS

VDD

I

Schmitt trigger reset input, active low.

Negative power supply, ground

Positive power supply

¾

Absolute Maximum Ratings

Supply Voltage..........................V_SS-0.3V to V_SS+6.0V*

Storage Temperature ............................-50°C to 125°C

Operating Temperature...........................-40°C to 85°C

Supply Voltage ........................V_SS-0.3V to V_SS+2.5V**

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

I

_OLTotal ..............................................................150mA

I_OHTotal............................................................-100mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

²*² For HT49R50A-1/HT49C50-1

²**² For HT49C50L

Rev. 2.40

4

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

D.C. Characteristics

V_DD=1.5V for HT49C50L, V_DD=3V & V_DD=5V for HT49R50A-1 and HT49C50-1

Ta=25°C

Test Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

Conditions

For HT49C50L

1.2

2.2

5.5

V

¾

LVR disable, f_SYS=4MHz

V_DD

Operating Voltage

¾

(for HT49R50A-1/HT49C50-1)

f

_SYS=8MHz

3.3

2.2

5.5

V

¾

(for HT49R50A-1/HT49C50-1)

For HT49R50A-1/HT49C50-1,

V_LCD

LCD Power Supply (Note *)

¾

VA£5.5V

No load, f_SYS=455kHz

No load, f_SYS=4MHz

No load, f_SYS=400kHz

No load, f_SYS=4MHz

1.5V

3V

60

1

100

2

¾

mA

Operating Current

(Crystal OSC)

I_DD1

5V

3

5

1.5V

3V

50

1

100

2

Operating Current

(RC OSC)

I_DD2

I_DD3

I_DD4

mA

5V

3

5

Operating Current

No load, f_SYS=8MHz

5V

4

8

mA

¾

(Crystal OSC, RC OSC)

1.5V

2.5

0.3

0.6

0.1

¾

5

0.6

1

¾

mA

Operating Current

(f_SYS=RTC OSC)

3V No load

5V

1.5V

0.5

1

Standby Current

(*f_S=T1)

No load, system HALT,

I_STB1

I_STB2

I_STB3

3V

5V

LCD off at HALT

2

¾

1.5V

3V

1

2

Standby Current

(*f_S=RTC OSC)

No load, system HALT,

LCD On at HALT, C type

2.5

10

0.5

2

5

5V

20

1

1.5V

3V

Standby Current

No load, system HALT

5

(*f_S=WDT RC OSC)

LCD On at HALT, C type

5V

6

10

30

60

25

50

25

50

20

40

3V

17

34

13

26

14

28

10

20

Standby Current

(*f_S=RTC OSC)

No load, system HALT,

I_STB4

I_STB5

I_STB6

LCD on at HALT, R type, 1/2 bias

5V

3V

Standby Current

(*f_S=RTC OSC)

No load, system HALT,

LCD on at HALT, R type, 1/3 bias

5V

3V

Standby Current

No load, system HALT,

(*f_S=WDT RC OSC)

LCD on at HALT, R type, 1/2 bias

5V

3V

Standby Current

No load, system HALT,

I_STB7

(*f_S=WDT RC OSC)

LCD on at HALT, R type, 1/3 bias

5V

Input Low Voltage for I/O

Ports, TMR and INT

V_IL1

0.3V_DD

0

V

¾

Rev. 2.40

5

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

0.8V_DD

0.7V_DD

0

V_DD

V

For HT49C50L

¾

Input High Voltage for I/O

Ports, TMR and INT

V_IH1

¾

For HT49R50A-1/HT49C50-1

V_IL2

V_IH2

0.4V_DD

V_DD

Input Low Voltage (RES)

Input High Voltage (RES)

V

¾

0.9V_DD

0.4

V

¾

1.5V

3V

0.8

12

mA

kW

V

¾

I_OL1

V_OL=0.1V_DD

I/O Port Sink Current

6

5V

10

25

¾

1.5V

3V

-0.3

-2

-0.6

-4

¾

I_OH1

V_OH=0.9V_DD

I/O Port Source Current

¾

5V

-5

-8

¾

3V

210

350

-80

420

700

-160

¾

LCD Common and Segment

Current

I_OL2

V

_OL=0.1V_DD

_OH=0.9V_DD

5V

¾

3V

¾

LCD Common and Segment

Current

I_OH2

5V

-180 -360

¾

1.5V

3V

75

20

150

60

300

100

50

3.6

R_PH

Pull-high Resistance

¾

5V

10

30

V_LVR

V_LVD

Low Voltage Reset Voltage

Low Voltage Detector Voltage

2.7

3.0

3.2

3.3

¾

V

¾

Note:

²*² for the value of VA refer to the LCD driver section.

²*f_S² please refer to WDT clock option

Rev. 2.40

6

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

A.C. Characteristics

V_DD=1.5V for HT49C50L, V_DD=3V & V_DD=5V for HT49R50A-1 and HT49C50-1

Ta=25°C

Test Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

¾

Conditions

1.2V~2.2V (for HT49C50L)

2.2V~5.5V

400

500

4000

8000

500

kHz

¾

System Clock

f_SYS1

¾

(Crystal OSC)

3.3V~5.5V

¾

1.2V~2.2V (for HT49C50L)

2.2V~5.5V

¾

System Clock

(RC OSC)

f_SYS2

4000

8000

¾

3.3V~5.5V

¾

System Clock

f_SYS3

32768

Hz

¾

(32768Hz Crystal OSC)

f_RTCOSC

RTC Frequency

32768

¾

Hz

¾

1.2V~2.2V (for HT49C50L)

2.2V~5.5V

¾

0

¾

500

4000

8000

140

180

130

¾

kHz

f_TIMER

Timer I/P Frequency

0

¾

3.3V~5.5V

0

¾

1.5V

3V

5V

35

45

32

10

1

70

90

65

¾

ms

t_WDTOSC

Watchdog Oscillator Period

¾

ms

For HT49C50L

ms

t_RES

External Reset Low Pulse Width

¾

For HT49R50A-1/HT49C50-1

Wake-up from HALT

¾

ms

t_SST

t_LVR

*t_SYS

System Start-up Timer Period

Low Voltage Width to Reset

1024

1

¾

0.25

10

1

¾

2

ms

For HT49C50L

¾

t_INT

Interrupt Pulse Width

¾

For HT49R50A-1/HT49C50-1

¾

Note: *t_SYS= 1/f_SYS1, 1/f_SYS2or 1/f_SYS3

Rev. 2.40

7

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Functional Description

Execution Flow

After accessing a program memory word to fetch an in-

struction code, the value of the PC is incremented by

one. The PC then points to the memory word containing

the next instruction code.

The system clock is derived from either a crystal or an

RC oscillator or a 32768Hz crystal oscillator. It is inter-

nally divided into four non-overlapping clocks. One in-

struction cycle consists of four system clock cycles.

When executing a jump instruction, conditional skip ex-

ecution, loading a PCL register, a subroutine call, an ini-

tial reset, an internal interrupt, an external interrupt, or

returning from a subroutine, the PC manipulates the

program transfer by loading the address corresponding

to each instruction.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

The pipelining scheme causes each instruction to effec-

tively execute in a cycle. If an instruction changes the

value of the program counter, two cycles are required to

complete the instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get a proper instruction; oth-

erwise proceed with the next instruction.

Program Counter - PC

The program counter (PC) is of 12 bits wide and controls

the sequence in which the instructions stored in the pro-

gram ROM are executed. The contents of the PC can

specify a maximum of 4096 addresses.

The lower byte of the PC (PCL) is a readable and

writeable register (06H). Moving data into the PCL per-

forms a short jump. The destination is within 256 locations.

T

1

T

2

T

3

T

1

T

4

T

2

T

3

T

1

T

4

T

2

T

3

T

4

S

y

s

t

e

m

C

l

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Execution Flow

Program Counter

Mode

*11 *10

*9

0

*8

0

*7

0

*6

0

*5

0

*4

0

1

*3

0

1

0

1

*2

0

1

0

1

0

1

0

*1

0

*0

0

Initial Reset

0

External Interrupt 0

External Interrupt 1

Timer/Event Counter 0 overflow

Timer/Event Counter 1 overflow

Time Base Interrupt

RTC Interrupt

Skip

Program Counter + 2

*8 @7 @6 @5 @4 @3 @2 @1 @0

Loading PCL

*11 *10

*9

Jump, Call Branch

Return From Subroutine

#11 #10 #9

S11 S10 S9

#8

S8

#7

S7

#6

S6

#5

S5

#4

S4

#3

S3

#2

S2

#1

S1

#0

S0

Program Counter

Note: *11~*0: Program counter bits

#11~#0: Instruction code bits

S11~S0: Stack register bits

@7~@0: PCL bits

Rev. 2.40

8

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

0

4

8

H

When a control transfer takes place, an additional

dummy cycle is required.

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Program Memory - ROM

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The program memory (ROM) is used to store the pro-

gram instructions which are to be executed. It also con-

tains data, table, and interrupt entries, and is organized

into 4096 ´ 15 bits which are addressed by the program

counter and table pointer.

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Certain locations in the ROM are reserved for special

usage:

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·

Location 000H

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Location 000H is reserved for program initialization.

After chip reset, the program always begins execution

at this location.

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Location 004H

F

H

Location 004H is reserved for the external interrupt

service program. If the INT0 input pin is activated, and

the interrupt is enabled, and the stack is not full, the

program begins execution at location 004H.

1

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Program Memory

·

Location 008H

·

Location 018H

Location 008H is reserved for the external interrupt

service program also. If the INT1 input pin is activated,

and the interrupt is enabled, and the stack is not full,

the program begins execution at location 008H.

Location 018H is reserved for the real time clock inter-

rupt service program. If a real time clock interrupt oc-

curs, and the interrupt is enabled, and the stack is not

full, the program begins execution at location 018H.

Location 00CH

Table location

Location 00CH is reserved for the Timer/Event Coun-

ter 0 interrupt service program. If a timer interrupt re-

sults from a Timer/Event Counter 0 overflow, and if the

interrupt is enabled and the stack is not full, the pro-

gram begins execution at location 00CH.

Any location in the ROM can be used as a look-up ta-

ble. The instructions ²TABRDC [m]² (the current page,

1 page=256 words) and ²TABRDL [m]² (the last page)

transfer the contents of the lower-order byte to the

specified data memory, and the contents of the

higher-order byte to TBLH (Table Higher-order byte

register) (08H). Only the destination of the lower-order

byte in the table is well-defined; the other bits of the ta-

ble word are all transferred to the lower portion of

TBLH, and the remaining 1 bit is read as ²0². The

TBLH is read only, and the table pointer (TBLP) is a

read/write register (07H), indicating the table location.

Before accessing the table, the location should be

placed in TBLP. All the table related instructions re-

quire 2 cycles to complete the operation. These areas

may function as a normal ROM depending upon the

user¢s requirements.

·

Location 010H

Location 010H is reserved for the Timer/Event Coun-

ter 1 interrupt service program. If a timer interrupt re-

sults from a Timer/Event Counter 1 overflow, and if the

interrupt is enabled and the stack is not full, the pro-

gram begins execution at location 010H.

Location 014H

Location 014H is reserved for the Time Base interrupt

service program. If a Time Base interrupt occurs, and

the interrupt is enabled, and the stack is not full, the

program begins execution at location 014H.

Table Location

Instruction(s)

*11

P11

1

*10

P10

1

*9

P9

1

*8

P8

1

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

@7

@6

@5

@4

@3

@2

@1

@0

Table Location

P11~P8: Current program Counter bits

Note: *11~*0: Table location bits

@7~@0: Table pointer bits

Rev. 2.40

9

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Stack Register - STACK

0

1

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

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0

The stack register is a special part of the memory used

to save the contents of the program counter. The stack

is organized into 6 levels and is neither part of the data

nor part of the program, and is neither readable nor

writeable. Its activated level is indexed by a stack

pointer (SP) and is neither readable nor writeable. At a

commencement of a subroutine call or an interrupt ac-

knowledgment, the contents of the program counter is

pushed onto the stack. At the end of the subroutine or in-

terrupt routine, signaled by a return instruction (RET or

RETI), the contents of the program counter is restored

to its previous value from the stack. After chip reset, the

SP will point to the top of the stack.

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0

C

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag is recorded but the ac-

knowledgment is still inhibited. Once the SP is decre-

mented (by RET or RETI), the interrupt is serviced. This

feature prevents stack overflow, allowing the program-

mer to use the structure easily. Likewise, if the stack is

full, and a ²CALL² is subsequently executed, a stack

overflow occurs and the first entry is lost (only the most

recent six return addresses are stored).

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1

T

M

R

1

C

P

A

P

B

P

C

Data Memory - RAM

:

U

n

u

The data memory (RAM) is designed with 192´8 bits,

and is divided into two functional groups, namely special

function registers and general purpose data memory,

most of which are readable/writeable, although some

are read only.

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a

²

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0

²

0 a

H

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C

1

5

F

H

Of the two types of functional groups, the special func-

tion registers consist of an Indirect addressing register 0

(00H), a Memory pointer register 0 (MP0;01H), an Indi-

rect addressing register 1 (02H), a Memory pointer reg-

ister 1 (MP1;03H), a Bank pointer (BP;04H), an

Accumulator (ACC;05H), a Program counter lower-or-

der byte register (PCL;06H), a Table pointer

(TBLP;07H), a Table higher-order byte register

(TBLH;08H), a Real time clock control register

(RTCC;09H), a Status register (STATUS;0AH), an Inter-

rupt control register 0 (INTC0;0BH), a Timer/Event

Counter 0 (TMR0;0DH), a Timer/Event Counter 0 con-

trol register (TMR0C;0EH), a Timer/Event Counter 1

(TMR1;10H), a Timer/Event Counter 1 control register

(TMR1C;11H), I/O registers (PA;12H, PB;14H,

PC;16H), and Interrupt control register 1 (INTC1;1EH).

On the other hand, the general purpose data memory,

addressed from 60H to FFH, is used for data and control

information under instruction commands.

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0

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RAM Mapping

Indirect Addressing Register

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] accesses the RAM pointed to

by MP0 (01H) and MP1(03H) respectively. Reading lo-

cation 00H or 02H indirectly returns the result 00H.

While, writing it indirectly leads to no operation.

The function of data movement between two indirect ad-

dressing registers is not supported. The memory pointer

registers, MP0 and MP1, are both 8-bit registers used to

access the RAM by combining corresponding indirect

addressing registers. MP0 can only be applied to data

memory, while MP1 can be applied to data memory and

LCD display memory.

The areas in the RAM can directly handle arithmetic,

logic, increment, decrement, and rotate operations. Ex-

cept some dedicated bits, Each pin in the RAM can be

set and reset by ²SET [m].i² and ²CLR [m].i². They are

also indirectly accessible through the Memory pointer

register 0 (MP0;01H) or the Memory pointer register 1

(MP1;03H).

Rev. 2.40

10

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Accumulator - ACC

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack. If the contents of the status

is important, and if the subroutine is likely to corrupt the

status register, the programmer should take precautions

and save it properly.

The accumulator (ACC) is related to the ALU opera-

tions. It is also mapped to location 05H of the RAM and

is capable of operating with immediate data. The data

movement between two data memory locations must

pass through the ACC.

Interrupts

Arithmetic and Logic Unit - ALU

The devices provides two external interrupts, two inter-

nal timer/event counter interrupts, an internal time base

interrupt, and an internal real time clock interrupt. The

interrupt control register 0 (INTC0;0BH) and interrupt

control register 1 (INTC1;1EH) both contain the interrupt

control bits that are used to set the enable/disable status

and interrupt request flags.

This circuit performs 8-bit arithmetic and logic opera-

tions and provides the following functions:

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ etc.)

Once an interrupt subroutine is serviced, other inter-

rupts are all blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may take place during this interval,

but only the interrupt request flag will be recorded. If a

certain interrupt requires servicing within the service

routine, the EMI bit and the corresponding bit of the

INTC0 or of INTC1 may be set in order to allow interrupt

nesting. Once the stack is full, the interrupt request will

not be acknowledged, even if the related interrupt is en-

abled, until the SP is decremented. If immediate service

is desired, the stack should be prevented from becom-

ing full.

The ALU not only saves the results of a data operation but

also changes the status register.

Status Register - STATUS

The status register (0AH) is of 8 bits wide and contains,

a carry flag (C), an auxiliary carry flag (AC), a zero flag

(Z), an overflow flag (OV), a power down flag (PDF), and

a watchdog time-out flag (TO). It also records the status

information and controls the operation sequence.

Except the TO and PDF flags, bits in the status register

can be altered by instructions similar to other registers.

Data written into the status register does not alter the TO

or PDF flags. Operations related to the status register,

however, may yield different results from those in-

tended. The TO and PDF flags can only be changed by

a Watchdog Timer overflow, chip power-up, or clearing

the Watchdog Timer and executing the ²HALT² instruc-

tion. The Z, OV, AC, and C flags reflect the status of the

latest operations.

All these interrupts can support a wake-up function. As

an interrupt is serviced, a control transfer occurs by

pushing the contents of the program counter onto the

stack followed by a branch to a subroutine at the speci-

fied location in the ROM. Only the contents of the pro-

gram counter is pushed onto the stack. If the contents of

the register or of the status register (STATUS) is altered

by the interrupt service program which corrupts the de-

sired control sequence, the contents should be saved in

advance.

Bit No.

Label

Function

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-

tate through carry instruction.

0

C

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

1

2

3

AC

Z

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

OV

PDF is cleared by either a system power-up or executing the ²CLR WDT² instruction. PDF is

set by executing the ²HALT² instruction.

4

PDF

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO

is set by a WDT time-out.

5

TO

6, 7

¾

Unused bit, read as ²0²

Status (0AH) Register

Rev. 2.40

11

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

External interrupts are triggered by a high to low transi-

tion of INT0 or INT1, and the related interrupt request

flag (EIF0;bit 4 of INTC0, EIF1;bit 5 of INTC0) is set as

well. After the interrupt is enabled, the stack is not full,

and the external interrupt is active, a subroutine call to

location 04H or 08H occurs. The interrupt request flag

(EIF0 or EIF1) and EMI bits are all cleared to disable

other interrupts.

INTC1), that is caused by a regular real time clock sig-

nal. After the interrupt is enabled, and the stack is not

full, and the RTF bit is set, a subroutine call to location

18H occurs. The related interrupt request flag (RTF) is

reset and the EMI bit is cleared to disable further inter-

rupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are all held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set both to 1 (if the stack is not

full). To return from the interrupt subroutine, ²RET² or

²RETI² may be invoked. RETI sets the EMI bit and en-

ables an interrupt service, but RET does not.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F;bit 6 of INTC0), which is normally

caused by a timer overflow. After the interrupt is en-

abled, and the stack is not full, and the T0F bit is set, a

subroutine call to location 0CH occurs. The related inter-

rupt request flag (T0F) is reset, and the EMI bit is

cleared to disable further interrupts. The Timer/Event

Counter 1 is operated in the same manner but its related

interrupt request flag is T1F (bit 4 of INTC1) and its sub-

routine call location is 10H.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses are serviced on the

latter of the two T2 pulses if the corresponding interrupts

are enabled. In the case of simultaneous requests, the

priorities in the following table apply. These can be

masked by resetting the EMI bit.

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF;bit 5 of INTC1), that is

caused by a regular time base signal. After the interrupt

is enabled, and the stack is not full, and the TBF bit is

set, a subroutine call to location 14H occurs. The related

interrupt request flag (TBF) is reset and the EMI bit is

cleared to disable further interrupts.

Interrupt Source

External interrupt 0

Priority Vector

1

2

3

4

5

6

04H

08H

0CH

10H

14H

18H

External interrupt 1

Timer/Event Counter 0 overflow

Timer/Event Counter 1 overflow

Time base interrupt

The real time clock interrupt is initialized by setting the

real time clock interrupt request flag (RTF; bit 6 of

Real time clock interrupt

Bit No.

Label

EMI

Function

0

1

2

3

4

5

6

7

Controls the master (global) interrupt (1=enabled; 0=disabled)

Controls the external interrupt 0 (1=enabled; 0=disabled)

Controls the external interrupt 1 (1=enabled; 0=disabled)

EEI0

EEI1

ET0I

EIF0

EIF1

T0F

Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)

External interrupt 0 request flag (1=active; 0=inactive)

External interrupt 1 request flag (1=active; 0=inactive)

Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)

Unused bit, read as ²0²

¾

INTC0 (0BH) Register

Bit No.

Label

ET1I

ETBI

ERTI

¾

Function

Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)

Controls the time base interrupt (1=enabled; 0:disabled)

Controls the real time clock interrupt (1=enabled; 0:disabled)

Unused bit, read as ²0²

0

1

2

3

4

5

6

7

T1F

TBF

RTF

¾

Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)

Time base request flag (1=active; 0=inactive)

Real time clock request flag (1=active; 0=inactive)

Unused bit, read as ²0²

INTC1 (1EH) Register

Rev. 2.40

12

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

V

D

The Timer/Event Counter 0 interrupt request flag (T0F),

external interrupt 1 request flag (EIF1), external inter-

rupt 0 request flag (EIF0), enable Timer/Event Counter

0 interrupt bit (ET0I), enable external interrupt 1 bit

(EEI1), enable external interrupt 0 bit (EEI0), and en-

able master interrupt bit (EMI) make up of the Interrupt

Control register 0 (INTC0) which is located at 0BH in the

RAM. The real time clock interrupt request flag (RTF),

time base interrupt request flag (TBF), Timer/Event

Counter 1 interrupt request flag (T1F), enable real time

clock interrupt bit (ERTI), and enable time base interrupt

bit (ETBI), enable Timer/Event Counter 1 interrupt bit

(ET1I) on the other hand, constitute the Interrupt Control

register 1 (INTC1) which is located at 1EH in the RAM.

EMI, EEI0, EEI1, ET0I, ET1I, ETBI, and ERTI are all

used to control the enable/disable status of interrupts.

These bits prevent the requested interrupt from being

serviced. Once the interrupt request flags (RTF, TBF, T0F,

T1F, EIF1, EIF0) are all set, they remain in the INTC1 or

INTC0 respectively until the interrupts are serviced or

cleared by a software instruction.

O

S

C

1

O

S

C

1

V

D

O

S

C

2

O

S

C

2

f

S

Y

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System Oscillator

O

S

C

3

O

S

C

4

32768Hz Crystal/RTC Oscillator

ature, and the chip itself due to process variations. It is

therefore, not suitable for timing sensitive operations

where accurate oscillator frequency is desired.

It is recommended that a program not use the ²CALL

subroutine² within the interrupt subroutine. It¢s because

interrupts often occur in an unpredictable manner or re-

quire to be serviced immediately in some applications. At

this time, if only one stack is left, and enabling the inter-

rupt is not well controlled, operation of the ²call² in the in-

terrupt subroutine may damage the original control

sequence.

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

the crystal and to get a frequency reference, but two ex-

ternal capacitors in OSC1 and OSC2 are required.

There is another oscillator circuit designed for the real

time clock. In this case, only the 32.768kHz crystal oscil-

lator can be applied. The crystal should be connected

between OSC3 and OSC4, and two external capacitors

along with one external resistor are required for the os-

cillator circuit in order to get a stable frequency.

Oscillator Configuration

These devices provide three oscillator circuits for sys-

tem clocks, i.e., RC oscillator and crystal oscillator, de-

termined by option. No matter what type of oscillator is

selected, the signal is used for the system clock. The

HALT mode stops the system oscillator and ignores ex-

ternal signal to conserve power.

The RTC oscillator circuit can be controlled to oscillate

quickly by setting the ²QOSC² bit (bit 4 of RTCC). It is

recommended to turn on the quick oscillating function

upon power on, and turn it off after 2 seconds.

Of the three oscillators, if the RC oscillator is used, an

external resistor between OSC1 and VSS is required,

and the range of the resistance should be from 24kW to

1MW for HT49R50A-1/HT49C50-1 and from 560kW to

1MW for HT49C50L. The system clock, divided by 4, is

available on OSC2 with pull-high resistor, which can be

used to synchronize external logic. The RC oscillator

provides the most cost effective solution. However, the

frequency of the oscillation may vary with VDD, temper-

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Although

the system enters the power down mode, the system

clock stops, and the WDT oscillator still works with a pe-

riod of approximately 65ms at 5V. The WDT oscillator

can be disabled by option to conserve power.

Symbol

Parameter

Min.

¾

Typ.

32.768

50

Max.

¾

Unit

kHz

kW

f_O

Nominal Frequency

Series Resistance

Load Capacitance

ESR

C_L

65

¾

9

pF

¾

Note: 1. It is strongly recommended to use a crystal with load capacitance 9pF.

2. The oscillator selection can be optimized using a high quality resonator with small ESR value. Refer to

crystal manufacturer for more details: www.microcrystal.com

Crystal Specifications

Rev. 2.40

13

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Watchdog Timer - WDT

WDT OSC or RTC OSC or the instruction clock (i.e., sys-

tem clock divided by 4). The multi-function timer also pro-

vides a selectable frequency signal (ranges from f_S/2²to

f_S/2⁸) for LCD driver circuits, and a selectable frequency

signal (ranges from f_S/2²to f_S/2⁹) for the buzzer output by

option. It is recommended to select a near 4kHz signal to

LCD driver circuits for proper display.

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or an instruction clock

(system clock/4) or a real time clock oscillator (RTC os-

cillator). The timer is designed to prevent a software

malfunction or sequence from jumping to an unknown

location with unpredictable results. The WDT can be

disabled by option. But if the WDT is disabled, all execu-

tions related to the WDT lead to no operation.

Time Base

The time base offers a periodic time-out period to gener-

ate a regular internal interrupt. Its time-out period

ranges from f_S/2¹²to f_S/2¹⁵selected by options. If time

base time-out occurs, the related interrupt request flag

(TBF; bit 5 of INTC1) is set. But if the interrupt is en-

abled, and the stack is not full, a subroutine call to loca-

tion 14H occurs. The time base time-out signal also can

be applied to be a clock source of Timer/Event Counter

1 for getting a longer timer-out period.

The WDT time-out period is as f_S/2¹⁶~f_S/2¹⁵

.

If the WDT clock source chooses the internal WDT oscilla-

tor, the time-out period may vary with temperature, VDD,

and process variations. On the other hand, if the clock

source selects the instruction clock and the ²HALT² in-

struction is executed, WDT may stop counting and lose its

protecting purpose, and the logic can only be restarted by

an external logic.

When the device operates in a noisy environment, using

the on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT can stop the system clock.

f

S

D

i

v

i

d

e

r

P

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c

a

l

The WDT overflow under normal operation initializes a

²chip reset² and sets the status bit ²TO². In the HALT

mode, the overflow initializes a ²warm reset², and only

the program counter and SP are reset to zero. To clear

the contents of the WDT, there are three methods to be

adopted, i.e., external reset (a low level to RES), soft-

ware instruction, and a ²HALT² instruction. There are

two types of software instructions; ²CLR WDT² and the

other set - ²CLR WDT1² and ²CLR WDT2². Of these

two types of instruction, only one type of instruction can

be active at a time depending on the options - ²CLR

WDT² times selection option. If the ²CLR WDT² is se-

lected (i.e., CLR WDT times equal one), any execution

of the ²CLR WDT² instruction clears the WDT. In the

case that ²CLR WDT1² and ²CLR WDT2² are chosen

(i.e., CLR WDT times equal two), these two instructions

have to be executed to clear the WDT; otherwise, the

WDT may reset the chip due to time-out.

O

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2

8

T

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B

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B

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2

i

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e

~

r

f

)

(

1

2

1

5

2

9

(

S

/

f

2

S

/

2

~

u

z

S

z

/

e

2

r

S

/

2

(

~

f

)

Time Base

Real Time Clock - RTC

The real time clock (RTC) is operated in the same man-

ner as the time base that is used to supply a regular in-

ternal interrupt. Its time-out period ranges from f_S/2⁸to

f_S/2¹⁵by software programming . Writing data to RT2,

RT1 and RT0 (bit2, 1, 0 of RTCC;09H) yields various

time-out periods. If the RTC time-out occurs, the related

interrupt request flag (RTF; bit 6 of INTC1) is set. But if

the interrupt is enabled, and the stack is not full, a sub-

routine call to location 18H occurs. The real time clock

f

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Multi-function Timer

1

2

1

5

R

T

2

1

0

8

t

o

1

f

S

/

2

S

/

2

~

These devices provide a multi-function timer for the WDT,

time base and RTC but with different time-out periods. The

multi-function timer consists of a 7-stage divider and an

8-bit prescaler, with the clock source coming from the

M

u

x

.

R

T

C

I

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Real Time Clock

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6

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1

6

1

5

O

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f

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2

~

f

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Watchdog Timer

Rev. 2.40

14

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

time-out signal also can be applied to be a clock source

of Timer/Event Counter 0 for getting a longer time-out

period.

When an interrupt request flag is set before entering the

²HALT² status, the system cannot be awaken using that

interrupt.

If wake-up events occur, it takes 1024 t_SYS(system

clock period) to resume normal operation. In other

words, a dummy period is inserted after the wake-up. If

the wake-up results from an interrupt acknowledgment,

the actual interrupt subroutine execution is delayed by

more than one cycle. However, if the Wake-up results in

the next instruction execution, the execution will be per-

formed immediately after the dummy period is finished.

RT2

0

RT1

0

RT0 RTC Clock Divided Factor

0

1

0

1

0

1

0

1

2^8*

2^9*

0

1

2^10*

2^11*

2¹²

2¹³

2¹⁴

2¹⁵

0

1

0

1

0

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Reset

1

There are three ways in which reset may occur.

Note: ²*² not recommended to be used

Power Down Operation - HALT

·

RES is reset during normal operation

RES is reset during HALT

WDT time-out is reset during normal operation

The HALT mode is initialized by the ²HALT² instruction

and results in the following.

The WDT time-out during HALT differs from other chip

reset conditions, for it can perform a ²warm reset² that

resets only the program counter and SP and leaves the

other circuits at their original state. Some registers re-

main unaffected during any other reset conditions. Most

registers are reset to the ²initial condition² once the re-

set conditions are met. Examining the PDF and TO

flags, the program can distinguish between different

²chip resets².

·

The system oscillator turns off but the WDT oscillator

keeps running (if the WDT oscillator or the real time

clock is selected).

·

The contents of the on-chip RAM and of the registers

remain unchanged.

The WDT is cleared and start recounting (if the WDT

clock source is from the WDT oscillator or the real time

clock oscillator).

·

All I/O ports maintain their original status.

Note:

²*² Make the length of the wiring, which is con-

The PDF flag is set but the TO flag is cleared.

nected to the RES pin as short as possible, to

avoid noise interference.

LCD driver is still running (if the WDT OSC or RTC

OSC is selected).

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES Wake-up HALT

The system quits the HALT mode by an external reset, an

interrupt, an external falling edge signal on port A, or a

WDT overflow. An external reset causes device initializa-

tion, and the WDT overflow performs a ²warm reset². Af-

ter examining the TO and PDF flags, the reason for chip

reset can be determined. The PDF flag is cleared by sys-

tem power-up or by executing the ²CLR WDT² instruc-

tion, and is set by executing the ²HALT² instruction. On

the other hand, the TO flag is set if WDT time-out occurs,

and causes a wake-up that only resets the program

counter and SP, and leaves the others at their original

state.

0

u

0

1

0

u

1

u

1

WDT time-out during normal operation

WDT Wake-up HALT

Note:

²u² means unchanged

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem awakes from the HALT state. Awaking from the

HALT state, the SST delay is added.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each pin

in port A can be independently selected to wake-up the

device by option. Awakening from an I/O port stimulus,

the program resumes execution of the next instruction.

On the other hand, awakening from an interrupt, two se-

quences may occur. If the related interrupt is disabled or

the interrupt is enabled but the stack is full, the program

resumes execution at the next instruction. But if the in-

terrupt is enabled, and the stack is not full, the regular in-

terrupt response takes place.

An extra SST delay is added during the power-up period

and any wakeup from the HALT may enable only the

SST delay.

Rev. 2.40

15

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

V

D

V

D

The functional unit chip reset status is shown below.

0

.

m

0

F

1

Program Counter

Interrupt

000H

1

0

W

0

k

1

0

W

0

k

Disabled

Cleared

R

E

S

R

E

S

Prescaler, Divider

0

m

. F 1

1

0

W

k

WDT, RTC,

Time base

Cleared. After master reset,

WDT starts counting

B

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H

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o

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t

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0

m

. F 1

C

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c

u

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C

i

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c

u

Timer/Event Counter Off

Reset Circuit

Input/output ports

Stack Pointer

Input mode

Points to the top of the stack

Note: Most applications can use the Basic Reset Circuit

as shown, however for applications with extensive noise,

it is recommended to use the Hi-noise Reset Circuit.

H

A

L

T

W

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Reset Timing Chart

P

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Reset Configuration

The states of the registers are summarized below:

Reset WDT Time-out

(Power On) (Normal Operation) (Normal Operation)

RES Reset

WDT Time-out

(HALT)*

Register

(HALT)

xxxx xxxx

0000 1---

xxxx xxxx

0000 1---

000H

TMR0

xxxx xxxx

0000 1---

xxxx xxxx

0000 1---

000H

xxxx xxxx

0000 1---

xxxx xxxx

0000 1---

000H

xxxx xxxx

0000 1---

xxxx xxxx

0000 1---

000H

uuuu uuuu

uuuu u---

uuuu uuuu

uuuu u---

000H

TMR0C

TMR1

TMR1C

Program Counter

MP0

xxxx xxxx

---- ---0

uuuu uuuu

---- ---0

uuuu uuuu

---- ---0

uuuu uuuu

---- ---0

uuuu uuuu

---- ---u

MP1

BP

ACC

xxxx xxxx

-xxx xxxx

--00 xxxx

-000 0000

-000 -000

--00 0111

1111 1111

xxxx xxxx

---- 1111

uuuu uuuu

-uuu uuuu

--1u uuuu

-000 0000

-000 -000

--00 0111

1111 1111

xxxx xxxx

---- 1111

uuuu uuuu

-uuu uuuu

--uu uuuu

-000 0000

-000 -000

--00 0111

1111 1111

xxxx xxxx

---- 1111

uuuu uuuu

-uuu uuuu

--01 uuuu

-000 0000

-000 -000

--00 0111

1111 1111

xxxx xxxx

---- 1111

uuuu uuuu

-uuu uuuu

--11 uuuu

-uuu uuuu

-uuu -uuu

--uu uuuu

uuuu uuuu

---- uuuu

TBLP

TBLH

STATUS

INTC0

INTC1

RTCC

PA

PB

PC

Note:

²*² refers to warm reset

²u² means unchanged

²x² means unknown

Rev. 2.40

16

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Timer/Event Counter

There are two registers related to the Timer/Event

Counter 0, i.e., TMR0 ([0DH]) and TMR0C ([0EH]), and

two registers related to the Timer/Event Counter 1, i.e.,

TMR1 ([10H], and TMR1C ([11H]). There are also two

physical registers are mapped to TMR0 (TMR1) loca-

tion; writing TMR0 (TMR1) places the starting value in

the timer/event counter preload register, while reading it

yields the contents of the timer/event counter. TMR0C

and TMR1C are timer/event counter control registers

used to define some options.

Two timer/event counters are implemented in the de-

vices. Both of them contain an 8-bit programmable

count-up counter.

The timer/event counter 0 clock source may come from

the system clock or system clock/4 or RTC time-out sig-

nal or external source. System clock source or system

clock/4 is selected by option.

The timer/event counter 1 clock source may come from

TMR0 overflow or system clock or time base time-out

signal or system clock/4 or external source, and the

three former clock source is selected by option. Using

external clock input allows the user to count external

events, measure time internals or pulse widths, or gen-

erate an accurate time base. While using the internal

clock allows the user to generate an accurate time base.

The T0M0 and T0M1 (T1M0 and T1M1) bits define the

operation mode. The event count mode is used to count

external events, which means that the clock source is

from an external (TMR0, TMR1) pin. The timer mode

functions as a normal timer with the clock source com-

ing from the internal selected clock source. Finally, the

pulse width measurement mode can be used to count

the high or low level duration of the external signal

(TMR0, TMR1), and the counting is based on the inter-

nal selected clock source.

The two timer/event counters are operated almost in the

same manner, except the clock source and related reg-

isters.

S

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X

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4

D

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0

M

1

T

0

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T

0

M

0

T

M

R

0

P

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0

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M

0

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W

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0

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0

T

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T

0

M

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t

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l

T

0

O

N

P

F

D

0

Timer/Event Counter 0

T

M

R

0

O

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f

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k

M

U

X

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B

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O

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l

a

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S

y

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k

/

4

T

1

M

1

o

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T

1

S

T

1

M

0

T

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P

1

M

0

M

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W

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1

M

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1

M

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T

1

O

N

P

F

D

1

Timer/Event Counter 1

P

F

D

0

1

M

U

1

/

2

P

F

D

X

P

A

3

D

a

t

a

C

T

R

L

P

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S

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p

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n

PFD Source Option

Rev. 2.40

17

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Bit No.

Label

Function

0~2

¾

Unused bit, read as ²0²

Defines the TMR0 active edge of the timer/event counter:

In Event Counter Mode (T0M1,T0M0)=(0,1):

1:count on falling edge;

3

T0E

0:count on rising edge

In Pulse Width measurement mode (T0M1,T0M0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

To enable/disable timer counting

(0=disabled; 1=enabled)

4

5

T0ON

T0S

2 to 1 multiplexer control inputs to select the timer/event counter clock source

(0=RTC outputs; 1= system clock or system clock/4)

To define the operating mode (T0M1, T0M0)

01=Event count mode (External clock)

10=Timer mode (Internal clock)

6

7

T0M0

T0M1

11=Pulse Width measurement mode (External clock)

00=Unused

TMR0C (0EH) Register

Bit No.

Label

Function

0~2

¾

Unused bit, read as ²0²

Defines the TMR1 active edge of the timer/event counter:

In Event Counter Mode (T1M1,T1M0)=(0,1):

1:count on falling edge;

3

T1E

0:count on rising edge

In Pulse Width measurement mode (T1M1,T1M0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

To enable/disable timer counting

(0= disabled; 1= enabled)

4

5

T1ON

T1S

2 to 1 multiplexer control inputs to select the timer/event counter clock source

(0= options clock source; 1= system clock/4)

To define the operating mode (T1M1, T1M0)

01= Event count mode (External clock)

10= Timer mode (Internal clock)

6

7

T1M0

T1M1

11= Pulse Width measurement mode (External clock)

00= Unused

TMR1C (11H) Register

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at FFH. Once an overflow

occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag (T0F;bit 6 of INTC0, T1F;bit 4 of INTC1).

surement can be made until the T0ON/T1ON is set. The

cycle measurement will re-function as long as it receives

further transient pulse. In this operation mode, the

timer/event counter begins counting according not to the

logic level but to the transient edges. In the case of coun-

ter overflows, the counter is reloaded from the

timer/event counter preload register and issues an inter-

rupt request, as in the other two modes, i.e., event and

timer modes.

In the pulse width measurement mode with the val-

ues of the T0ON/T1ON and T0E/T1E bits equal to

one, after the TMR0 (TMR1) has received a transient

from low to high (or high to low if the T0E/T1E bit is

²0²), it will start counting until the TMR0 (TMR1) re-

turns to the original level and resets the

T0ON/T1ON. The measured result remains in the

timer/event counter even if the activated transient

occurs again. In other words, only one cycle mea-

To enable the counting operation, the Timer ON bit

(T0ON: bit 4 of TMR0C; T1ON: bit 4 of TMR1C) should

be set to 1. In the pulse width measurement mode, the

T0ON/T1ON is automatically cleared after the measure-

ment cycle is completed. But in the other two modes, the

T0ON/T1ON can only be reset by instructions. The

Rev. 2.40

18

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

START:

overflow of the Timer/Event Counter 0/1 is one of the

wake-up sources and can also be applied to a PFD (Pro-

grammable Frequency Divider) output at PA3 by option.

Only one PFD (PFD0 or PFD1) can be applied to PA3 by

options. If PA3 is set as PFD output, there are two types of

selections; One is PFD0 as the PFD output, the other is

PFD1 as the PFD output. PFD0, PFD1 are the timer over-

flow signals of the Timer/Event Counter 0, Timer/Event

Counter 1 respectively. No matter what the operation

mode is, writing a 0 to ET0I or ET1I disables the related in-

terrupt service. When the PFD function is selected, exe-

cuting ²CLR [PA].3² instruction to enable PFD output and

executing ²SET [PA].3² instruction to disable PFD output.

mov a, 09h ; Set ET0I & EMI bits to

mov intc0, a ; enable timer 0 and

; global interrupt

mov a, 01h ; Set ET1I bit to enable

mov intc1, a ; timer 1 interrupt

mov a, 80h ; Set operating mode as

mov tmr1c, a ; timer mode and select mask

; option clock source

mov a, 0a0h ; Set operating mode as timer

mov tmr0c, a ; mode and select system

; clock/4

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turn on, data written to the

timer/event counter is kept only in the timer/event coun-

ter preload register. The timer/event counter still contin-

ues its operation until an overflow occurs.

set tmr1c.4 ; Enable then disable timer 1

clr tmr1c.4 ; for the first time

mov a, 00h ; Load a desired value into

mov tmr0, a ; the TMR0/TMR1 register

mov a, 00h

mov tmr1, a

;

When the timer/event counter (reading TMR0/TMR1) is

read, the clock is blocked to avoid errors. As this may re-

sults in a counting error, blocking of the clock should be

taken into account by the programmer.

set tmr0c.4 ; Normal operating

set tmr1c.4

END

;

It is strongly recommended to load a desired value into

the TMR0/TMR1 register first, then turn on the related

timer/event counter for proper operation. Because the

initial value of TMR0/TMR1 is unknown.

Input/Output Ports

There are a 12-bit bidirectional input/output port, an 8-bit

input port in the devices, labeled PA, PB and PC which

are mapped to [12H], [14H] and [16H] of the RAM, re-

spectively. PA0~PA3 can be configured as CMOS (out-

put) or NMOS (input/output) with or without pull-high

resistor by option. PA4~PA7 are always pull-high and

NMOS (input/output). If you choose NMOS (input), Each

pin on the port (PA0~PA7) can be configured as a

wake-up input. PB can only be used for input operation.

The contents of PC4~PC7 are unknown. PC can be con-

figured as CMOS output or NMOS input/output with or

without pull-high resistor by option. All the port for the in-

put operation (PA, PB and PC), these ports are

non-latched, that is, the inputs should be ready at the T2

Due to the timer/event scheme, the programmer should

pay special attention on the instruction to enable then

disable the timer for the first time, whenever there is a

need to use the timer/event function, to avoid

unpredicatable result. After this procedure, the

timer/event function can be operated normally. The ex-

ample given below, using two 8-bit width Timer¢s (timer

0 ;timer 1) cascade into 16-bit width.

V

D

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D

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p

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(

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A

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7

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3

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n

PA, PC Input/Output Ports

Rev. 2.40

19

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

V

D

user wants to use the BZ/BZ or PFD function, the related

PA port should be set as a CMOS output. The buzzer

output signals are controlled by PA0 and PA1 data reg-

isters and defined in the following table.

W

e

a

k

P

u

l

-

u

p

PA1 Data

Register

PA0 Data

Register

D

a

t

a

b

u

s

P

B

0

~

P

PA0/PA1 Pad State

R

e

a

d

I

/

O

0

1

0

1

PA0=BZ, PA1=BZ

PA0=BZ, PA1=0

PA0=0, PA1=0

PB Input Ports

rising edge of the instruction ²MOV A, [m]² (m=12H or

14H). For PA, PC output operation, all data are latched

andremainunchangeduntiltheoutputlatch is rewritten.

X

Note: ²X² stands for undefined

When the PA and PC structures are open drain NMOS

type, it should be noted that, before reading data from

the pads, a ²1² should be written to the related bits to

disable the NMOS device. That is executing first the in-

struction ²SET [m].i² (i=0~7 for PA) to disable related

NMOS device, and then ²MOV A, [m]² to get stable data.

The PFD output signal function is controlled by the PA3

data register and the timer/event counter state. The

PFD output signal frequency is also dependent on the

timer/event counter overflow period. The definitions of

PFD control signal and PFD output frequency are listed

in the following table.

After chip reset, these input lines remain at the high level

or are left floating (by options). Each pin of these output

latches can be set or cleared by the ²MOV [m], A²

(m=12H or 16H) instruction.

LCD Display Memory

The devices provides an area of embedded data mem-

ory for LCD display. This area is located from 40H to

60H of the RAM at Bank 1. Bank pointer (BP; located at

04H of the RAM) is the switch between the RAM and the

LCD display memory. When the BP is set as ²1², any

data written into 40H~60H will effect the LCD display.

When the BP is cleared to ²0², any data written into

40H~60H means to access the general purpose data

memory. The LCD display memory can be read and writ-

ten to only by indirect addressing mode using MP1.

When data is written into the display data area, it is auto-

matically read by the LCD driver which then generates

the corresponding LCD driving signals. To turn the dis-

play on or off, a ²1² or a ²0² is written to the correspond-

ing bit of the display memory, respectively. The figure

illustrates the mapping between the display memory

and LCD pattern for the devices.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or to the accumulator. When a PA or PC line is

used as an I/O line, the related PA or PC line options

should be configured as NMOS with or without pull-high

resistor. Once a PA or PC line is selected as a CMOS

output, the I/O function cannot be used.

The input state of a PA or PC line is read from the related

PA or PC pad. When the PA or PC is configured as

NMOS with or without pull-high resistor, one should be

careful when applying a read-modify-write instruction to

PA or PC. Since the read-modify-write will read the en-

tire port state (pads state) firstly, execute the specified

instruction and then write the result to the port data reg-

ister. When the read operation is executed, a fault pad

state (caused by the load effect or floating state) may be

read. Errors will then occur.

C

O

M

4

0

4

H

1

H

4

2

H

4

3

H

5

E

H

0

1

2

3

0

1

2

3

There are three function pins that share with the PA port:

PA0/BZ, PA1/BZ and PA3/PFD.

S

E

G

M

E

N

T

0

1

2

3

0

3

1

The BZ and BZ are buzzer driving output pair and the

PFD is a programmable frequency divider output. If the

Display Memory

Timer

OFF

ON

Timer Preload Value

PA3 Data Register

PA3 Pad State

PFD Frequency

X

N

0

1

0

1

U

0

X

PFD

0

f_INT/[2´(256-N)]

ON

X

Note:

²X² stands for undefined

²U² stands for unknown

Rev. 2.40

20

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

LCD Driver Output

HT49C50-1: There are two types of selections: 1/2 bias

or 1/3 bias.

The output number of the LCD driver device can be

32´2, 33´3 or 32´4 by option (i.e., 1/2 duty, 1/3 duty or

1/4 duty). The bias type LCD driver can be ²R² type or

²C² type for HT49R50A-1/HT49C50-1 while the bias

type LCD driver can only be ²C² type for HT49C50L. If

the ²R² bias type is selected, no external capacitor is re-

quired. If the ²C² bias type is selected, a capacitor

mounted between C1 and C2 pins is needed. The LCD

driver bias voltage for HT49R50A-1/HT49C50-1 can be

1/2 bias or 1/3 bias by option, while the LCD driver bias

voltage for HT49C50L can only be 1/2 bias. If 1/2 bias is

selected, a capacitor mounted between V2 pin and

ground is required. If 1/3 bias is selected, two capacitors

are needed for V1 and V2 pins.

LCD bias type selection for HT49R50A-1/HT49C50-1:

This option is to determine what kind of bias is selected,

R type or C type.

Low Voltage Reset/Detector Functions

There is a low voltage detector (LVD) and a low voltage

reset circuit (LVR) implemented in the microcontroller.

These two functions can be enabled/disabled by op-

tions. Once the options of LVD is enabled, the user can

use the RTCC.3 to enable/disable (1/0) the LVD circuit

and read the LVD detector status (0/1) from RTCC.5;

otherwise, the LVD function is disabled.

The LVR has the same effect or function with the exter-

nal RES signal which performs chip reset. During HALT

state, LVR is disabled.

LCD bias power supply selection for HT49R50A-1/

D

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L

LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type)

Rev. 2.40

21

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

V

A

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1

LCD Driver Output (1/4 Duty, 1/3 Bias, C Type)

The RTCC register definitions are listed in the table on the next page.

Bit No.

Label

RT0~RT2

LVDC*

Read/Write

R/W

Reset

111B

0

Function

8 to 1 multiplexer control inputs to select the real clock prescaler

output

0~2

3

R/W

LVD enable/disable (1/0)

32768Hz OSC quick start-up oscillating

0/1: quickly/slowly start

4

QOSC

R/W

0

LVD detection output (1/0)

1: low voltage detected

5

LVDO*

R

0

6, 7

¾

Unused bit, read as ²0²

Note: ²*² For HT49R50A-1/HT49C50-1

RTCC (09H) Register

Rev. 2.40

22

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Options

The following shows the options in the devices. All these options should be defined in order to ensure proper system

functioning.

Options

OSC type selection.

This option is to determine whether an RC or Crystal or 32768Hz crystal oscillator is chosen as system clock.

WDT Clock source selection.

RTC and Time Base. There are three types of selection: system clock/4 or RTC OSC or WDT OSC.

WDT enable/disable selection.

WDT can be enabled or disabled by options.

CLR WDT times selection.

This option defines how to clear the WDT by instruction. ²One time² means that the ²CLR WDT² can clear the WDT.

²Two times² means that if both of the ²CLR WDT1² and ²CLR WDT2² have been executed, only then will the WDT be

cleared.

Time Base time-out period selection.

The Time Base time-out period ranges from clock/2¹²to clock/2¹⁵. ²Clock² means the clock source selected by op-

tions.

Buzzer output frequency selection.

There are eight types of frequency signals for buzzer output: Clock/2²~Clock/2⁹. ²Clock² means the clock source se-

lected by options.

Wake-up selection.

This option defines the wake-up capability. External I/O pins (PA only) all have the capability to wake-up the chip

from a HALT by a falling edge.

Pull-high selection.

This option is to decide whether the pull-high resistance is visible or not on the PA0~PA3 and PC. (PB and PA4~PA7

are always pull-high)

PA0~PA3 and PC CMOS or NMOS selection.

The structure of PA0~PA3 and PC each 4 bits can be selected as CMOS or NMOS individually. When the CMOS is

selected, the related pins only can be used for output operations. When the NMOS is selected, the related pins can

be used for input or output operations. (PA4~PA7 are always NMOS)

Clock source selection of Timer/Event Counter 0. There are two types of selection: system clock or system clock/4.

Clock source selection of Timer/Event Counter 1. There are three types of selection: TMR0 overflow, system clock or

Time Base overflow.

I/O pins share with other functions selection.

PA0/BZ, PA1/BZ: PA0 and PA1 can be set as I/O pins or buzzer outputs.

PA3/PFD: PA3 can be set as I/O pins or PFD output.

LCD common selection.

There are three types of selection: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). If the 4 com-

mon is selected, the segment output pin ²SEG32² will be set as a common output.

LCD bias power supply selection.

There are two types of selection: 1/2 bias or 1/3 bias for HT49R50A-1/HT49C50-1.

LCD bias type selection.

This option is to decide what kind of bias is selected, R type or C type for HT49R50A-1/HT49C50-1.

LCD driver clock selection.

There are seven types of frequency signals for the LCD driver circuits: f_S/2²~f_S/2⁸. ²f_S² means the clock source selec-

tion by options.

LCD ON/OFF at HALT selection

LVR selection.

LVR has enable or disable options

LVD selection.

LVD has enable or disable options

PFD selection.

If PA3 is set as PFD output, there are two types of selection; One is PFD0 as the PFD output, the other is PFD1 as the

PFD output. PFD0, PFD1 are the timer overflow signals of the Timer/Event Counter 0, Timer/Event Counter 1 re-

spectively.

Rev. 2.40

23

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Application Circuits

For HT49R50A-1/HT49C50-1 Application Circuit

V

D

C

O

M

0

~

C

O

M

3

L

C

D

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3

1

P

A

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R

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1

2

0

m

. F 1

0

m

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V

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f

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3

2

7

6

8

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Note: 1. Crystal/resonator system oscillators

For crystal oscillators, C1 and C2 are only required for some crystal frequencies to ensure oscillation. For

resonator applications C1 and C2 are normally required for oscillation to occur. For most applications it is

not necessary to add R1. However if the LVR function is disabled, and if it is required to stop the oscillator

when V_DDfalls below its operating range, it is recommended that R1 is added. The values of C1 and C2

should be selected in consultation with the crystal/resonator manufacturer specifications.

2. Reset circuit

The reset circuit resistance and capacitance values should be chosen to ensure that VDD is stable and re-

mains within its operating voltage range before the RES pin reaches a high level. Ensure that the length of

the wiring connected to the RES pin is kept as short as possible, to avoid noise interference.

3. For applications where noise may interfere with the reset circuit and for details on the oscillator external

components, refer to Application Note HA0075E for more information.

Rev. 2.40

24

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

For HT49C50L Application Circuit

C

3

O

M

0

~

C

O

L

M

C

3

D

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C

S

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0

~

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P

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A

3

N

1

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V

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4

7

0

p

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5

6

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0

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k

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m

F

1

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f

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Y

S

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2

C

1

0

.

1

0

W

0

k

2

0

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r

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y

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1

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1

0

m

. F 1

0

.

1

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S

C

2

V

2

V

D

I

N

T

0

1

O

S

C

1

2

3

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2

7

6

8

H

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l

a

t

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I

T

P

A

0

~

P

A

7

S

C

1

a

n

d

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R

0

1

P

B

0

~

P

B

7

n

c

o

n

e

c

t

e

d

P

C

0

~

P

C

3

H

T

4

9

C

5

0

L

O

S

C

i

r

c

u

i

t

Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is

stable and remains within a valid operating voltage range before bringing RES to high.

Rev. 2.40

25

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Instruction Set

Introduction

subtract instruction mnemonics to enable the necessary

arithmetic to be carried out. Care must be taken to en-

sure correct handling of carry and borrow data when re-

sults exceed 255 for addition and less than 0 for

subtraction. The increment and decrement instructions

INC, INCA, DEC and DECA provide a simple means of

increasing or decreasing by a value of one of the values

in the destination specified.

Central to the successful operation of any

microcontroller is its instruction set, which is a set of pro-

gram instruction codes that directs the microcontroller to

perform certain operations. In the case of Holtek

microcontrollers, a comprehensive and flexible set of

over 60 instructions is provided to enable programmers

to implement their application with the minimum of pro-

gramming overheads.

Logical and Rotate Operations

For easier understanding of the various instruction

codes, they have been subdivided into several func-

tional groupings.

The standard logical operations such as AND, OR, XOR

and CPL all have their own instruction within the Holtek

microcontroller instruction set. As with the case of most

instructions involving data manipulation, data must pass

through the Accumulator which may involve additional

programming steps. In all logical data operations, the

zero flag may be set if the result of the operation is zero.

Another form of logical data manipulation comes from

the rotate instructions such as RR, RL, RRC and RLC

which provide a simple means of rotating one bit right or

left. Different rotate instructions exist depending on pro-

gram requirements. Rotate instructions are useful for

serial port programming applications where data can be

rotated from an internal register into the Carry bit from

where it can be examined and the necessary serial bit

set high or low. Another application where rotate data

operations are used is to implement multiplication and

division calculations.

Instruction Timing

Most instructions are implemented within one instruc-

tion cycle. The exceptions to this are branch, call, or ta-

ble read instructions where two instruction cycles are

required. One instruction cycle is equal to 4 system

clock cycles, therefore in the case of an 8MHz system

oscillator, most instructions would be implemented

within 0.5ms and branch or call instructions would be im-

plemented within 1ms. Although instructions which re-

quire one more cycle to implement are generally limited

to the JMP, CALL, RET, RETI and table read instruc-

tions, it is important to realize that any other instructions

which involve manipulation of the Program Counter Low

register or PCL will also take one more cycle to imple-

ment. As instructions which change the contents of the

PCL will imply a direct jump to that new address, one

more cycle will be required. Examples of such instruc-

tions would be ²CLR PCL² or ²MOV PCL, A². For the

case of skip instructions, it must be noted that if the re-

sult of the comparison involves a skip operation then

this will also take one more cycle, if no skip is involved

then only one cycle is required.

Branches and Control Transfer

Program branching takes the form of either jumps to

specified locations using the JMP instruction or to a sub-

routine using the CALL instruction. They differ in the

sense that in the case of a subroutine call, the program

must return to the instruction immediately when the sub-

routine has been carried out. This is done by placing a

return instruction RET in the subroutine which will cause

the program to jump back to the address right after the

CALL instruction. In the case of a JMP instruction, the

program simply jumps to the desired location. There is

no requirement to jump back to the original jumping off

point as in the case of the CALL instruction. One special

and extremely useful set of branch instructions are the

conditional branches. Here a decision is first made re-

garding the condition of a certain data memory or indi-

vidual bits. Depending upon the conditions, the program

will continue with the next instruction or skip over it and

jump to the following instruction. These instructions are

the key to decision making and branching within the pro-

gram perhaps determined by the condition of certain in-

put switches or by the condition of internal data bits.

Moving and Transferring Data

The transfer of data within the microcontroller program

is one of the most frequently used operations. Making

use of three kinds of MOV instructions, data can be

transferred from registers to the Accumulator and

vice-versa as well as being able to move specific imme-

diate data directly into the Accumulator. One of the most

important data transfer applications is to receive data

from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and

data manipulation is a necessary feature of most

microcontroller applications. Within the Holtek

microcontroller instruction set are a range of add and

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Bit Operations

Other Operations

The ability to provide single bit operations on Data Mem-

ory is an extremely flexible feature of all Holtek

microcontrollers. This feature is especially useful for

output port bit programming where individual bits or port

pins can be directly set high or low using either the ²SET

[m].i² or ²CLR [m].i² instructions respectively. The fea-

ture removes the need for programmers to first read the

8-bit output port, manipulate the input data to ensure

that other bits are not changed and then output the port

with the correct new data. This read-modify-write pro-

cess is taken care of automatically when these bit oper-

ation instructions are used.

In addition to the above functional instructions, a range

of other instructions also exist such as the ²HALT² in-

struction for Power-down operations and instructions to

control the operation of the Watchdog Timer for reliable

program operations under extreme electric or electro-

magnetic environments. For their relevant operations,

refer to the functional related sections.

Instruction Set Summary

The following table depicts a summary of the instruction

set categorised according to function and can be con-

sulted as a basic instruction reference using the follow-

ing listed conventions.

Table Read Operations

Table conventions:

Data storage is normally implemented by using regis-

ters. However, when working with large amounts of

fixed data, the volume involved often makes it inconve-

nient to store the fixed data in the Data Memory. To over-

come this problem, Holtek microcontrollers allow an

area of Program Memory to be setup as a table where

data can be directly stored. A set of easy to use instruc-

tions provides the means by which this fixed data can be

referenced and retrieved from the Program Memory.

x: Bits immediate data

m: Data Memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Mnemonic

Arithmetic

Description

Cycles Flag Affected

ADD A,[m]

ADDM A,[m]

ADD A,x

Add Data Memory to ACC

1

1^Note

1

Z, C, AC, OV

C

Add ACC to Data Memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add Data Memory to ACC with Carry

1

1^Note

Add ACC to Data memory with Carry

Subtract immediate data from the ACC

Subtract Data Memory from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

1

1^Note

Subtract Data Memory from ACC with result in Data Memory

Subtract Data Memory from ACC with Carry

Subtract Data Memory from ACC with Carry, result in Data Memory

Decimal adjust ACC for Addition with result in Data Memory

1

1^Note

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

Logical AND Data Memory to ACC

Logical OR Data Memory to ACC

Logical XOR Data Memory to ACC

Logical AND ACC to Data Memory

Logical OR ACC to Data Memory

Logical XOR ACC to Data Memory

Logical AND immediate Data to ACC

Logical OR immediate Data to ACC

Logical XOR immediate Data to ACC

Complement Data Memory

1

Z

1

1^Note

1

OR A,x

1

XOR A,x

1

1^Note

CPL [m]

CPLA [m]

Complement Data Memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment Data Memory with result in ACC

1

Z

Increment Data Memory

1^Note

DECA [m]

DEC [m]

Decrement Data Memory with result in ACC

Decrement Data Memory

1

1^Note

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Mnemonic

Rotate

Description

Cycles Flag Affected

RRA [m]

RR [m]

Rotate Data Memory right with result in ACC

Rotate Data Memory right

1

1^Note

1

1^Note

1

1^Note

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate Data Memory right through Carry with result in ACC

Rotate Data Memory right through Carry

Rotate Data Memory left with result in ACC

Rotate Data Memory left

C

None

C

RLCA [m]

RLC [m]

Rotate Data Memory left through Carry with result in ACC

Rotate Data Memory left through Carry

1

1^Note

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move Data Memory to ACC

Move ACC to Data Memory

Move immediate data to ACC

1

1^Note

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of Data Memory

Set bit of Data Memory

1^Note

None

Branch

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if Data Memory is zero

1^Note

1^note

1^Note

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if Data Memory is zero with data movement to ACC

Skip if bit i of Data Memory is zero

Skip if bit i of Data Memory is not zero

Skip if increment Data Memory is zero

Skip if decrement Data Memory is zero

Skip if increment Data Memory is zero with result in ACC

Skip if decrement Data Memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m]

TABRDL [m]

Read table (current page) to TBLH and Data Memory

Read table (last page) to TBLH and Data Memory

2^Note

None

Miscellaneous

NOP

No operation

1

1^Note

1

None

CLR [m]

Clear Data Memory

SET [m]

Set Data Memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO, PDF

None

Pre-clear Watchdog Timer

Swap nibbles of Data Memory

Swap nibbles of Data Memory with result in ACC

Enter power down mode

1

1^Note

1

None

1

TO, PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by

the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and

²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags

remain unchanged.

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Instruction Definition

ADC A,[m]

Add Data Memory to ACC with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the Accumulator.

Operation

ACC ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADCM A,[m]

Add ACC to Data Memory with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADD A,[m]

Add Data Memory to ACC

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

ADD A,x

Add immediate data to ACC

Description

The contents of the Accumulator and the specified immediate data are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + x

Affected flag(s)

OV, Z, AC, C

ADDM A,[m]

Add ACC to Data Memory

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

AND A,[m]

Logical AND Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

Z

AND A,x

Logical AND immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical AND

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

Z

ANDM A,[m]

Logical AND ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

Z

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CALL addr

Subroutine call

Description

Unconditionally calls a subroutine at the specified address. The Program Counter then in-

crements by 1 to obtain the address of the next instruction which is then pushed onto the

stack. The specified address is then loaded and the program continues execution from this

new address. As this instruction requires an additional operation, it is a two cycle instruc-

tion.

Operation

Stack ¬ Program Counter + 1

Program Counter ¬ addr

Affected flag(s)

None

CLR [m]

Clear Data Memory

Description

Operation

Each bit of the specified Data Memory is cleared to 0.

[m] ¬ 00H

Affected flag(s)

None

CLR [m].i

Clear bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

None

CLR WDT

Description

Operation

Clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared.

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT1

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT2 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT2

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT1 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

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CPL [m]

Complement Data Memory

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa.

Operation

[m] ¬ [m]

Affected flag(s)

Z

CPLA [m]

Complement Data Memory with result in ACC

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa. The complemented result

is stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

Z

DAA [m]

Decimal-Adjust ACC for addition with result in Data Memory

Description

Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-

sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or

if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble

remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of

6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-

ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C

flag may be affected by this instruction which indicates that if the original BCD sum is

greater than 100, it allows multiple precision decimal addition.

Operation

[m] ¬ ACC + 00H or

[m] ¬ ACC + 06H or

[m] ¬ ACC + 60H or

[m] ¬ ACC + 66H

Affected flag(s)

C

DEC [m]

Decrement Data Memory

Description

Operation

Data in the specified Data Memory is decremented by 1.

[m] ¬ [m] - 1

Affected flag(s)

Z

DECA [m]

Decrement Data Memory with result in ACC

Description

Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-

mulator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] - 1

Affected flag(s)

Z

HALT

Enter power down mode

Description

This instruction stops the program execution and turns off the system clock. The contents

of the Data Memory and registers are retained. The WDT and prescaler are cleared. The

power down flag PDF is set and the WDT time-out flag TO is cleared.

Operation

TO ¬ 0

PDF ¬ 1

Affected flag(s)

TO, PDF

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INC [m]

Increment Data Memory

Description

Operation

Data in the specified Data Memory is incremented by 1.

[m] ¬ [m] + 1

Affected flag(s)

Z

INCA [m]

Increment Data Memory with result in ACC

Description

Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-

lator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] + 1

Affected flag(s)

Z

JMP addr

Jump unconditionally

Description

The contents of the Program Counter are replaced with the specified address. Program

execution then continues from this new address. As this requires the insertion of a dummy

instruction while the new address is loaded, it is a two cycle instruction.

Operation

Program Counter ¬ addr

Affected flag(s)

None

MOV A,[m]

Description

Operation

Move Data Memory to ACC

The contents of the specified Data Memory are copied to the Accumulator.

ACC ¬ [m]

Affected flag(s)

None

MOV A,x

Move immediate data to ACC

Description

Operation

The immediate data specified is loaded into the Accumulator.

ACC ¬ x

Affected flag(s)

None

MOV [m],A

Description

Operation

Move ACC to Data Memory

The contents of the Accumulator are copied to the specified Data Memory.

[m] ¬ ACC

Affected flag(s)

None

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

No operation

None

OR A,[m]

Logical OR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-

ation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

Z

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OR A,x

Logical OR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

Z

ORM A,[m]

Logical OR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-

ation. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²OR² [m]

Affected flag(s)

Z

RET

Return from subroutine

Description

The Program Counter is restored from the stack. Program execution continues at the re-

stored address.

Operation

Program Counter ¬ Stack

Affected flag(s)

None

RET A,x

Return from subroutine and load immediate data to ACC

Description

The Program Counter is restored from the stack and the Accumulator loaded with the

specified immediate data. Program execution continues at the restored address.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

None

RETI

Return from interrupt

Description

The Program Counter is restored from the stack and the interrupts are re-enabled by set-

ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending

when the RETI instruction is executed, the pending Interrupt routine will be processed be-

fore returning to the main program.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

None

RL [m]

Rotate Data Memory left

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ [m].7

Affected flag(s)

None

RLA [m]

Rotate Data Memory left with result in ACC

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-

main unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ [m].7

Affected flag(s)

None

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RLC [m]

Rotate Data Memory left through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7

replaces the Carry bit and the original carry flag is rotated into bit 0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RLCA [m]

Rotate Data Memory left through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces

the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in

the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RR [m]

Rotate Data Memory right

Description

The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into

bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ [m].0

Affected flag(s)

None

RRA [m]

Rotate Data Memory right with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-

tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data

Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ [m].0

Affected flag(s)

None

RRC [m]

Rotate Data Memory right through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0

replaces the Carry bit and the original carry flag is rotated into bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

C

RRCA [m]

Rotate Data Memory right through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-

places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is

stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

C

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SBC A,[m]

Subtract Data Memory from ACC with Carry

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result

of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or

zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SBCM A,[m]

Subtract Data Memory from ACC with Carry and result in Data Memory

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-

sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is

positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SDZ [m]

Skip if decrement Data Memory is 0

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0 the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] - 1

Skip if [m] = 0

Affected flag(s)

None

SDZA [m]

Skip if decrement Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0, the program proceeds with the following instruction.

Operation

ACC ¬ [m] - 1

Skip if ACC = 0

Affected flag(s)

None

SET [m]

Set Data Memory

Description

Operation

Each bit of the specified Data Memory is set to 1.

[m] ¬ FFH

Affected flag(s)

None

SET [m].i

Set bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is set to 1.

[m].i ¬ 1

Affected flag(s)

None

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SIZ [m]

Skip if increment Data Memory is 0

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] + 1

Skip if [m] = 0

Affected flag(s)

None

SIZA [m]

Skip if increment Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0 the program proceeds with the following instruction.

Operation

ACC ¬ [m] + 1

Skip if ACC = 0

Affected flag(s)

None

SNZ [m].i

Skip if bit i of Data Memory is not 0

Description

If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is 0 the program proceeds with the following instruction.

Operation

Skip if [m].i ¹ 0

Affected flag(s)

None

SUB A,[m]

Subtract Data Memory from ACC

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUBM A,[m]

Subtract Data Memory from ACC with result in Data Memory

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUB A,x

Subtract immediate data from ACC

Description

The immediate data specified by the code is subtracted from the contents of the Accumu-

lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-

tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will

be set to 1.

Operation

ACC ¬ ACC - x

Affected flag(s)

OV, Z, AC, C

Rev. 2.40

36

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

SWAP [m]

Description

Operation

Swap nibbles of Data Memory

The low-order and high-order nibbles of the specified Data Memory are interchanged.

[m].3~[m].0 « [m].7 ~ [m].4

Affected flag(s)

None

SWAPA [m]

Swap nibbles of Data Memory with result in ACC

Description

The low-order and high-order nibbles of the specified Data Memory are interchanged. The

result is stored in the Accumulator. The contents of the Data Memory remain unchanged.

Operation

ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4

ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0

Affected flag(s)

None

SZ [m]

Skip if Data Memory is 0

Description

If the contents of the specified Data Memory is 0, the following instruction is skipped. As

this requires the insertion of a dummy instruction while the next instruction is fetched, it is a

two cycle instruction. If the result is not 0 the program proceeds with the following instruc-

tion.

Operation

Skip if [m] = 0

None

Affected flag(s)

SZA [m]

Skip if Data Memory is 0 with data movement to ACC

Description

The contents of the specified Data Memory are copied to the Accumulator. If the value is

zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-

tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the

program proceeds with the following instruction.

Operation

ACC ¬ [m]

Skip if [m] = 0

Affected flag(s)

None

SZ [m].i

Skip if bit i of Data Memory is 0

Description

If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is not 0, the program proceeds with the following instruction.

Operation

Skip if [m].i = 0

None

Affected flag(s)

TABRDC [m]

Read table (current page) to TBLH and Data Memory

Description

The low byte of the program code (current page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

TABRDL [m]

Read table (last page) to TBLH and Data Memory

Description

The low byte of the program code (last page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

Rev. 2.40

37

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

XOR A,[m]

Logical XOR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XORM A,[m]

Logical XOR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XOR A,x

Logical XOR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical XOR

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

Z

Rev. 2.40

38

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Package Information

Note that the package information provided here is for consultation purposes only. As this information may be updated at regu-

lar intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for

the latest version of the package information.

48-pin SSOP (300mil) Outline Dimensions

4

8

2

5

4

A

B

1

C

'

G

H

D

a

E

F

Dimensions in inch

Symbol

Min.

0.395

0.291

0.008

0.613

0.085

¾

Nom.

¾

Max.

0.420

0.299

0.012

0.637

0.099

¾

A

B

C

C¢

D

E

F

¾

0.025

0.004

0.025

0.004

0°

0.010

0.035

0.012

8°

¾

G

H

a

Dimensions in mm

Symbol

Min.

10.03

7.39

0.20

15.57

2.16

¾

Nom.

¾

Max.

10.67

7.59

0.30

16.18

2.51

¾

A

B

C

C¢

D

E

F

¾

0.64

0.10

0.64

0.10

0°

0.25

0.89

0.30

8°

¾

G

H

a

Rev. 2.40

39

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

64-pin LQFP (7mm´7mm) Outline Dimensions

C

D

H

G

4

8

3

I

3

2

4

9

F

A

B

E

6

4

1

7

a

K

J

1

6

Dimensions in inch

Symbol

Min.

0.350

0.272

0.350

0.272

¾

Nom.

¾

Max.

0.358

0.280

0.358

0.280

¾

A

B

C

D

E

F

G

H

I

¾

0.016

0.005

0.053

¾

0.009

0.057

0.063

0.006

0.030

0.008

7°

¾

0.002

0.018

0.004

0°

J

K

a

Dimensions in mm

Symbol

Min.

8.90

6.90

8.90

6.90

¾

Nom.

¾

Max.

9.10

7.10

9.10

7.10

¾

A

B

C

D

E

F

G

H

I

¾

0.40

0.13

1.35

¾

0.23

1.45

1.60

0.15

0.75

0.20

7°

¾

0.05

0.45

0.09

0°

J

K

a

Rev. 2.40

40

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

100-pin LQFP (14mm´14mm) Outline Dimensions

C

H

D

G

7

5

1

I

5

0

7

6

F

A

B

E

1

0

2

6

a

K

J

1

2

5

Dimensions in inch

Symbol

Min.

0.626

0.547

0.626

0.547

¾

Nom.

¾

Max.

0.634

0.555

0.634

0.555

¾

A

B

C

D

E

F

G

H

I

¾

0.020

0.008

¾

0.053

¾

0.057

0.063

¾

0.004

¾

J

0.018

0.004

0°

0.030

0.008

7°

K

a

¾

Dimensions in mm

Symbol

Min.

15.90

13.90

15.90

13.90

¾

Nom.

¾

Max.

16.10

14.10

16.10

14.10

¾

A

B

C

D

E

F

G

H

I

¾

0.50

0.20

¾

1.35

¾

1.45

1.60

¾

0.10

¾

J

0.45

0.10

0°

0.75

0.20

7°

K

a

¾

Rev. 2.40

41

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SSOP 48W

Symbol

Description

Dimensions in mm

330.0±1.0

A

B

Reel Outer Diameter

Reel Inner Diameter

Spindle Hole Diameter

Key Slit Width

100.0±0.1

+0.5/-0.2

13.0

C

D

2.0±0.5

+0.3/-0.2

32.2

T1

T2

Space Between Flange

Reel Thickness

38.2±0.2

Rev. 2.40

42

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

B

0

W

C

K

1

D

1

P

K

2

A

0

R

e

l

H

o

l

e

(

C

i

r

c

l

e

)

I

C

p

a

c

k

a

g

e

p

i

n

1

a

n

d

t

h

e

r

e

a

r

e

l

o

c

a

t

e

d

o

n

t

h

e

s

a

m

e

s

i

d

R

e

l

H

o

l

e

(

E

l

i

p

s

e

)

SSOP 48W

Symbol

Description

Dimensions in mm

32.0±0.3

W

P

Carrier Tape Width

Cavity Pitch

16.0±0.1

E

Perforation Position

1.75±0.10

14.2±0.1

F

Cavity to Perforation (Width Direction)

Perforation Diameter

D

2 Min.

+0.25/-0.00

D1

P0

P1

A0

B0

K1

K2

t

Cavity Hole Diameter

1.50

Perforation Pitch

4.0±0.1

2.0±0.1

Cavity to Perforation (Length Direction)

Cavity Length

12.0±0.1

16.2±0.1

2.4±0.1

Cavity Width

Cavity Depth

3.2±0.1

Carrier Tape Thickness

Cover Tape Width

0.35±0.05

25.5±0.1

C

Rev. 2.40

43

July 30, 2012

HT49R50A-1/HT49C50-1/HT49C50L

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057

Tel: 86-755-8616-9908, 86-755-8616-9308

Fax: 86-755-8616-9722

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538, USA

Tel: 1-510-252-9880

Fax: 1-510-252-9885

http://www.holtek.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 2.40

44

July 30, 2012


型号：	HT49R50A-1(64LQFP-A)
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PQFP64 可编程只读存储器微控制器
文件：	总44页 (文件大小：297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT49R50A-1(64LQFP-A) [HOLTEK]

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