HT62L256-28SOP-A [HOLTEK]
CMOS 32Kx8 Low Power SRAM; CMOS 32Kx8低功耗SRAM
| 型号： | HT62L256-28SOP-A |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | CMOS 32Kx8 Low Power SRAM |
| 文件： | 总10页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT62L256
CMOS 32K´8 Low Power SRAM
Preliminary
Features
·
·
Operation voltage: 2.7V~3.3V
Automatic power down when chip is deselected
·
·
Low power consumption:
Three state outputs
-
·
Operating current: 20mA max.
Fully static operation
-
Standby current: 2mA
·
Data retention supply voltage as low as 2.0V
·
High speed access time: 70ns
·
Easy expansion with CS and OE options
·
Input levels are LVTTL-compatible
·
28-pin SOP/TSOP package
General Description
The HT62L256 is a 262,144-bit static random access
memory organized into 32,768 words by 8 bits and oper-
ating from a low power range of 2.7V to 3.3V supply volt-
age. It is fabricated with high performance CMOS
process that provides both high speed and low power
feature with typical standby current of 2mA and maxi-
mum access time of 70ns.
The HT62L256 has an automatic power down feature,
reducing the power consumption significantly when chip
is deselected. The HT62L256 supports the JEDEC
standard 28-pin SOP and TSOP package.
Block Diagram
A
0
X
Y
-
-
D
D
e
e
c
c
A
d
d
r
e
s
s
M
e
m
o
r
y
C
e
l
l
A
r
r
a
y
B
u
f
f
e
r
s
´
( 3 2 K 8 B i t s
A
1
4
C
S
E
S
e
n
s
e
A
m
p
l
i
f
i
e
r
R
e
a
d
/
W
r
i
t
e
W
E
C
o
n
t
r
o
l
L
o
g
i
c
O
O
u
t
p
u
t
B
u
f
f
e
r
s
V
D
D
V
S
S
D
0
D
7
Pin Assignment
A
1
4
V
D
D
2
2
2
2
2
2
2
2
2
1
1
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
1
2
3
4
5
6
7
8
9
1
1
1
1
1
O
E
2
8
1
A
1
0
A
1
1
9
8
3
A
1
2
7
6
5
4
3
2
1
0
0
1
2
W
A
A
A
A
O
A
C
D
D
D
D
D
E
C
S
7
6
5
4
3
A
A
D
A
A
A
A
A
A
A
A
1
8
9
1
3
D
A
1
D
W
E
D
1
0
V
D
D
H
T
6
2
L
2
5
6
D
E
A
A
1
1
4
2
7
6
5
4
3
V
S
S
2
8
T
S
O
P
-
A
1
D
D
D
A
A
A
2
1
0
A
A
A
A
A
S
7
6
5
4
3
0
1
2
3
4
0
1
2
D
D
D
1
4
1
5
V
S
S
H
T
6
2
L
2
5
6
2
8
S
O
P
-
A
Rev. 0.00
1
August 15, 2002
Preliminary
HT62L256
Pin Description
Pin Name
A0~A14
WE
I/O
I
Description
Address input pins
I
Write enable signal pin, active LOW
Output enable signal pin, active LOW
Chip select signal pin, active LOW
Data input and output signal pins
Positive power supply
OE
I
CS
I
D0~D7
VDD
I/O
¾
¾
VSS
Negative power supply, ground
Absolute Maximum Rating
VDD to VSS ........................................... -0.5V to +3.6V
IN, IN/OUT Voltage to VSS ............. -0.5V to VDD+0.5V
Power Consumption, PT .......................................0.7W
Operating Temperature, TOP ......................0°C to 70°C
Storage Temperature (Plastic), Tstg ... -55°C to 125°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25°C, VDD=3.0V±10%, TOP=0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Min.
2.7
Typ.
3.0
0
Max.
3.3
0.4
¾
Unit
V
Operating Voltage
Input Low Voltage
Input High Voltage
Input Leakage Current
¾
¾
¾
VIL
VIH
ILI
V
¾
V
0.7´VDD
¾
VIN=0 to VDD
1
¾
¾
mA
CS=VIH or OE=VIH
OUT=0 to VDD
,
ILO
Output Leakage Current
1
¾
¾
mA
V
VOL
VOH
IDD
VDD=Max, IOL=2mA
Output Low Voltage
Output High Voltage
Operating Current
0.3
¾
V
V
¾
¾
¾
¾
2
VDD=Min, IOH=-1mA
CS=VIH, IOUT=0mA
CS=VIH, IOUT=0mA
V
DD-0.3
¾
20
50
10
mA
mA
mA
ISB1
ISB2
Standby Current
¾
Power Down Supply Current
CS ³ VDD - 0.2V, VIN³0V
¾
Rev. 0.00
2
August 15, 2002
Preliminary
HT62L256
A.C. Characteristics
Ta=25°C, VDD=3.0V±10%
Symbol
Parameter
Min.
Typ.
Max.
Unit
Read cycle
tRC
Read Cycle Time
70
¾
¾
¾
10
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
70
70
35
¾
¾
25
25
¾
tAA
Address Access Time
tACS
tAOE
tCLZ*
Chip Selection Access Time
Output Enable to Valid Outputs
Chip Selection to Output in Low-Z
Output Enabled to Output in Low-Z
Chip Deselected to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
tOLZ
tCHZ
tOHZ
tOH
*
*
¾
¾
10
*
Write cycle
tWC
Write Cycle Time
70
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
20
¾
¾
¾
tCW
Chip Selection to End of Write
Address Setup Time
tAS
tAW
Address Valid to End of Write
Write Pulse Width
60
50
0
tWP
tWR
Write Recovery Time
tWHZ
tDW
Write to Output in High-Z
Data Valid to End of Write
Data Hold from End of Write
Output Active from End of Write
¾
30
0
tDH
tOW
5
Note: 1. A write cycle occurs during the overlap of a low CS and a low WE
2. OE may be both high and low in a write cycle
3. tAS is specified from CS or WE, whichever occurs last
4. tWP is an overlap time of a low CS and a low WE
5. tWR, tDW and tDH are specified from CS or WE, whichever occurs first
6. tWHZ is specified by the time when DATA OUT is floating and not defined by the output level
7. When the I/O pins are in data output mode, they should not be forced with inverse signals
Rev. 0.00
3
August 15, 2002
Preliminary
HT62L256
A.C. Test Conditions
Item
Conditions
Input Pulse Level
0V to 3V
5ns
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load
1.5V
See figures below
+
1
.
5
V
+
1
.
5
V
1
.
8
k
W
1
.
8
k
I
/
O
I
/
O
1
0
0
p
ꢀ
5
p
ꢀ
9
9
0
W
9
9
0
*
I
n
c
l
u
d
i
n
g
s
c
o
p
e
a
n
d
j
i
g
*
I
n
c
l
u
d
i
n
g
s
c
o
p
e
a
n
d
j
i
g
O
u
t
p
u
t
l
o
a
d
O
u
t
p
u
t
l
o
a
d
f
o
r
t
C
L
Z
,
t
O
L
Z
,
t
C
H
Z
,
t
W
H
Z
a
n
d
t
O
W
Functional Description
Operation truth table
CS
OE
X
WE
X
Mode
Standby
D0~D7
High-Z
High-Z
Dout
H
L
L
L
H
H
Output Disable
Read
L
H
X
L
Write
Din
Data retention characteristics
Ta=-40°C to 85°C
Symbol
VDR
Parameter
Conditions
Min.
Max.
Unit
CS ³ VDD-0.2V
VDD for Data Retention
2.0
3.3
V
VIN ³ VDD-0.2V or VIN£0.2V
CS ³ VDD-0.2V
ICCDR
Data Retention Current
2
¾
mA
VIN ³ VDD-0.2V or VIN£0.2V
tCDR
tR
Chip Disable Data Retention Time
Operation Recovery Time
See retention timing
See retention timing
0
ns
ns
¾
¾
tRC
*
Low VDD data retention timing
V
D
D
3
.
0
V
3
.
0
V
V
D
D
t
C
D
R
t
R
C
S
V
I
H
V
I H
C
³
D
D
Rev. 0.00
4
August 15, 2002
Preliminary
HT62L256
Timing Diagrams
Read cycle 1 output enable controlled (1)
t
R C
A
d
d
r
e
s
s
t
A A
O
E
t
A O E
t
O H
t
O L Z
C
S
t
A C S
t
O H Z
t
C H Z
t
C L Z
D
O
U
T
D
o
n
'
t
C
a
r
e
U
n
u
s
e
d
Read cycle 2 address controlled (1, 2, 4)
t
R C
A
d
d
r
e
s
s
t
A A
t
O H
t
O H
D
O
U
T
D
U
o
n
n
u
'
s
t
C
a
r
e
e
d
Read cycle 3 chip select controlled (1, 3, 4)
A
d
d
r
e
s
s
t
A C S
t
C H Z
t
C L Z
D
O
U
T
D
U
o
n
n
u
'
s
t
C
a
r
e
e
d
Note: 1. WE is high for read cycle
2. Device is continuously enabled, CS=VIL
3. Address is valid prior to or coincident with the CS transition low
4. OE=VIL
5. Transition is measured at ±500mV from the steady state
Rev. 0.00
5
August 15, 2002
Preliminary
HT62L256
Write cycle 1 OE clock (1)
t
W
C
A
d
d
r
e
s
s
t
W
R
O
E
t
C W
(
5
)
C
S
t
A W
t
W
P
W
E
t
A S
t
O H Z
(
1
,
4
)
D
O
U
T
t
D
W
t
D H
D
I
N
D
o
n
'
t
C
a
r
e
U
n
u
s
e
d
Write cycle 2 OE=VIL Fixed (1, 6)
t
W
C
A
d
d
r
e
s
s
t
C W
t
W
R
(
5
)
C
S
t
A W
t
W
P
W
E
t
O H
t
A S
t
W
H
Z
t
O W
(
7
)
(
8
)
D
O
U
T
t
D
W
t
D H
D
I
N
D
U
o
n
n
u
'
s
t
C
a
r
e
e
d
Rev. 0.00
6
August 15, 2002
Preliminary
HT62L256
Note:
1. WE must be high during all address transitions
2. A write occurs during the overlap (tWP) of a low CS and a low WE
3. tWR is measured from the earliest high going edge of CS or WE to the end of the write cycle
4. During this period, I/O pins are in the output state, so the input signals of opposite phase to the outputs
should not be applied.
5. If the CS low transition occurs simultaneously or after with the WE low transition, the outputs remain in a
high impedance state
6. OE is continuously low (OE=VIL)
7. DOUT is at the same phase as the write data of this write cycle
8. DOUT is the read data of the next address
9. If CS is low during this period, then the I/O pins are in the output state and the data input signals of the
opposite phase to the outputs should not be applied
10. Transition is measured at ±500mV from the steady state
Rev. 0.00
7
August 15, 2002
Preliminary
HT62L256
Package Information
28-pin SOP (330mil) outline dimensions
2
8
1
5
A
B
1
1
4
C
C
'
G
H
D
a
E
ꢀ
Dimensions in mil
Nom.
Symbol
Min.
453
326
14
700
92
¾
Max.
477
336
20
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
728
104
¾
4
¾
G
H
a
32
4
38
12
0°
10°
Rev. 0.00
8
August 15, 2002
Preliminary
HT62L256
28-pin TSOP (8´13.4) outline dimensions
H
D
1
2
8
q
E
0
.
0
1
0
L
D
e
t
a
i
l
ꢀ
1
4
1
5
D
A
2
A
A
1
S
e
e
D
e
t
a
i
l
ꢀ
L
1
S
b
e
y
S
e
a
t
i
n
g
P
l
a
n
e
Dimensions in mm
Nom.
Symbol
Min.
¾
Max.
1.25
0.18
1.05
¾
A
A1
A2
b
¾
¾
0.08
0.95
¾
¾
0.20
¾
D
11.70
13.20
7.90
¾
11.90
13.60
8.10
¾
HD
E
¾
¾
e
0.55
0.50
0.8
¾
L
¾
¾
L1
q
¾
¾
0°
5°
Rev. 0.00
9
August 15, 2002
Preliminary
HT62L256
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holmate Semiconductor, Inc.
48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 0.00
10
August 15, 2002
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