HT68F002_技术文档

Cost-Effective Flash MCU with EEPROM

HT68F002/HT68F0025/HT68F003

Revision: V1.41 Date: April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Table of Contents

Features............................................................................................................ 5

CPU Features ......................................................................................................................... 5

Peripheral Features................................................................................................................. 5

General Description......................................................................................... 6

Selection Table................................................................................................. 6

Block Diagram.................................................................................................. 7

Pin Assignment................................................................................................ 7

Pin Description ................................................................................................ 8

Absolute Maximum Ratings.......................................................................... 10

D.C. Characteristics........................................................................................11

A.C. Characteristics....................................................................................... 12

LVR&LVD Electrical Characteristics ............................................................ 13

Power on Reset Electrical Characteristics.................................................. 13

System Architecture...................................................................................... 14

Clocking and Pipelining......................................................................................................... 14

Program Counter................................................................................................................... 15

Stack ..................................................................................................................................... 15

Arithmetic and Logic Unit – ALU ........................................................................................... 16

Flash Program Memory................................................................................. 16

Structure................................................................................................................................ 16

Special Vectors ..................................................................................................................... 17

Look-up Table........................................................................................................................ 17

Table Program Example........................................................................................................ 18

In Circuit Programming ......................................................................................................... 19

On-Chip Debug Support – OCDS ......................................................................................... 20

RAM Data Memory......................................................................................... 21

Structure................................................................................................................................ 21

General Purpose Data Memory ............................................................................................ 21

Special Purpose Data Memory ............................................................................................. 21

Special Function Register Description........................................................ 24

Indirect Addressing Registers – IAR0, IAR1 ......................................................................... 24

Memory Pointers – MP0, MP1 .............................................................................................. 24

Bank Pointer – BP................................................................................................................. 25

Accumulator – ACC............................................................................................................... 25

Program Counter Low Register – PCL.................................................................................. 25

Look-up Table Registers – TBLP, TBLH................................................................................ 25

Status Register – STATUS.................................................................................................... 26

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April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

EEPROM Data Memory.................................................................................. 28

EEPROM Data Memory Structure ........................................................................................ 28

EEPROM Registers .............................................................................................................. 28

Reading Data from the EEPROM ........................................................................................ 30

Writing Data to the EEPROM................................................................................................ 30

Write Protection..................................................................................................................... 30

EEPROM Interrupt ................................................................................................................ 30

Programming Considerations................................................................................................ 31

Oscillators ...................................................................................................... 32

Oscillator Overview ............................................................................................................... 32

System Clock Conﬁgurations................................................................................................ 32

Internal RC Oscillator – HIRC ............................................................................................... 32

Internal 32kHz Oscillator – LIRC........................................................................................... 33

Supplementary Oscillator...................................................................................................... 33

Operating Modes and System Clocks ......................................................... 33

System Clocks ...................................................................................................................... 33

System Operation Modes...................................................................................................... 34

Control Register .................................................................................................................... 36

Operating Mode Switching ................................................................................................... 38

Standby Current Considerations........................................................................................... 42

Wake-up................................................................................................................................ 42

Watchdog Timer............................................................................................. 43

Watchdog Timer Clock Source.............................................................................................. 43

Watchdog Timer Control Register......................................................................................... 43

Watchdog Timer Operation ................................................................................................... 44

Reset and Initialisation.................................................................................. 45

Reset Functions .................................................................................................................... 45

Reset Initial Conditions ......................................................................................................... 48

Input/Output Ports......................................................................................... 50

Pull-high Resistors ................................................................................................................ 51

Port A Wake-up ..................................................................................................................... 52

I/O Port Control Registers..................................................................................................... 52

Pin-Shared Functions............................................................................................................ 53

I/O Pin Structures.................................................................................................................. 56

Programming Considerations................................................................................................ 56

Timer Modules – TM ...................................................................................... 57

Introduction ........................................................................................................................... 57

TM Operation ........................................................................................................................ 57

TM Clock Source................................................................................................................... 57

TM Interrupts......................................................................................................................... 58

TM External Pins................................................................................................................... 58

TM Input/Output Pin Control ................................................................................................. 58

Programming Considerations................................................................................................ 59

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April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Standard Type TM – STM .............................................................................. 60

Standard TM Operation......................................................................................................... 60

Standard Type TM Register Description ............................................................................... 61

Standard Type TM Operating Modes.................................................................................... 65

Periodic Type TM – PTM................................................................................ 75

Periodic TM Operation .......................................................................................................... 75

Periodic Type TM Register Description................................................................................. 76

Periodic Type TM Operating Modes...................................................................................... 80

Interrupts........................................................................................................ 89

Interrupt Registers................................................................................................................. 89

Interrupt Operation................................................................................................................ 93

External Interrupt................................................................................................................... 94

Multi-function Interrupt .......................................................................................................... 94

Time Base Interrupts............................................................................................................. 95

EEPROM Interrupt ................................................................................................................ 96

TM Interrupts......................................................................................................................... 96

Interrupt Wake-up Function................................................................................................... 96

Programming Considerations................................................................................................ 97

Low Voltage Detector – LVD ......................................................................... 98

LVD Register......................................................................................................................... 98

LVD Operation....................................................................................................................... 99

Application Circuits..................................................................................... 100

Instruction Set.............................................................................................. 101

Introduction ......................................................................................................................... 101

Instruction Timing................................................................................................................ 101

Moving and Transferring Data............................................................................................. 101

Arithmetic Operations.......................................................................................................... 101

Logical and Rotate Operation ............................................................................................. 102

Branches and Control Transfer ........................................................................................... 102

Bit Operations ..................................................................................................................... 102

Table Read Operations ....................................................................................................... 102

Other Operations................................................................................................................. 102

Instruction Set Summary ............................................................................ 103

Table Conventions............................................................................................................... 103

Instruction Deﬁnition................................................................................... 105

Package Information ....................................................................................114

8-pin SOP (150mil) Outline Dimensions ..............................................................................115

10-pin SOP (150mil) Outline Dimensions ............................................................................116

10-pin MSOP Outline Dimensions .......................................................................................117

16-pin NSOP (150mil) Outline Dimensions..........................................................................118

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Features

CPU Features

•ꢀ OperatingꢀVoltage

ꢀ

♦

f_SYSꢀ=ꢀ8MHz:ꢀ2.2V~5.5V

•ꢀ Upꢀtoꢀ0.5μsꢀinstructionꢀcycleꢀwithꢀ8MHzꢀsystemꢀclockꢀatꢀV_DD=5V

•ꢀ Powerꢀdownꢀandꢀwake-upꢀfunctionsꢀtoꢀreduceꢀpowerꢀconsumption

•ꢀ TwoꢀOscillators

ꢀ

♦

InternalꢀHighꢀꢀSpeedꢀ8MHzꢀRCꢀoscillatorꢀ–ꢀHIRC

InternalꢀLowꢀSpeedꢀ32kHzꢀRCꢀoscillatorꢀ–ꢀLIRC

ꢀ

♦

•ꢀ Fullyꢀintergratedꢀinternalꢀoscillatorsꢀrequireꢀnoꢀexternalꢀcomponents

•ꢀ Multi-modeꢀoperation:ꢀNORMAL,ꢀSLOW,ꢀIDLEꢀandꢀSLEEP

•ꢀ Allꢀinstructionsꢀexecutedꢀinꢀoneꢀorꢀtwoꢀinstructionꢀcycles

•ꢀ Tableꢀreadꢀinstructions

•ꢀ 63ꢀpowerfulꢀinstructions

•ꢀ Upꢀtoꢀ4ꢀlevelꢀsubroutineꢀnesting

•ꢀ Bitꢀmanipulationꢀinstruction

Peripheral Features

•ꢀ FlashꢀProgramꢀMemory:ꢀ1K×14ꢀ~ꢀ2K×14ꢀ

•ꢀ RAMꢀDataꢀMemory:ꢀ64×8

•ꢀ TrueꢀEEPROMꢀMemory:ꢀ32×8

•ꢀ WatchdogꢀTimerꢀfunction

•ꢀ Upꢀtoꢀ14ꢀbidirectionalꢀI/Oꢀlines

•ꢀ Oneꢀpin-sharedꢀexternalꢀinterrupt

•ꢀ MultipleꢀTimerꢀModulesꢀforꢀtimeꢀmeasure,ꢀcompareꢀmatchꢀoutput,ꢀcaptureꢀinput,ꢀ

PWMꢀoutputꢀfunctions

•ꢀ DualꢀTime-Baseꢀfunctionsꢀforꢀgenerationꢀofꢀﬁxedꢀtimeꢀinterruptꢀsignals

•ꢀ Lowꢀvoltageꢀresetꢀfunction

•ꢀ Lowꢀvoltageꢀdetectꢀfunction

•ꢀ Multipleꢀpackageꢀtypes

•ꢀ Flashꢀprogramꢀmemoryꢀcanꢀbeꢀre-programmedꢀupꢀtoꢀ100,000ꢀtimes

•ꢀ Flashꢀprogramꢀmemoryꢀdataꢀretentionꢀ>ꢀ10ꢀyears

•ꢀ TrueꢀEEPROMꢀdataꢀmemoryꢀcanꢀbeꢀre-programmedꢀupꢀtoꢀ1,000,000ꢀtimes

•ꢀ TrueꢀEEPROMꢀdataꢀmemoryꢀdataꢀretentionꢀ>ꢀ10ꢀyears

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April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

General Description

TheꢀdevicesꢀareꢀFlashꢀMemoryꢀtypeꢀ8-bitꢀhighꢀperformanceꢀRISCꢀarchitectureꢀmicrocontrollers.ꢀ

OfferingꢀusersꢀtheꢀconvenienceꢀofꢀFlashꢀMemoryꢀmulti-programmingꢀfeatures,ꢀtheseꢀdevicesꢀalsoꢀ

includeꢀaꢀwideꢀrangeꢀofꢀfunctionsꢀandꢀfeatures.ꢀOtherꢀmemoryꢀincludesꢀanꢀareaꢀofꢀRAMꢀDataꢀ

MemoryꢀasꢀwellꢀasꢀanꢀareaꢀofꢀtrueꢀEEPROMꢀmemoryꢀforꢀstorageꢀofꢀnon-volatileꢀdataꢀsuchꢀasꢀserialꢀ

numbers,ꢀcalibrationꢀdataꢀetc.

AnalogꢀfeaturesꢀincludeꢀmultipleꢀandꢀextremelyꢀflexibleꢀTimerꢀModulesꢀprovideꢀtiming,ꢀpulseꢀ

generation,ꢀcaptureꢀinput,ꢀcompareꢀmatchꢀoutputꢀandꢀPWMꢀgenerationꢀfunctions.ꢀProtectiveꢀfeaturesꢀ

suchꢀasꢀanꢀinternalꢀWatchdogꢀTimerꢀandꢀLowꢀVoltageꢀResetꢀandꢀLowꢀVoltageꢀDetectorꢀcoupledꢀwithꢀ

excellentꢀnoiseꢀimmunityꢀandꢀESDꢀprotectionꢀensureꢀthatꢀreliableꢀoperationꢀisꢀmaintainedꢀinꢀhostileꢀ

electricalꢀenvironments.

AꢀfullꢀchoiceꢀofꢀHIRCꢀandꢀLIRCꢀoscillatorꢀfunctionsꢀareꢀprovidedꢀincludingꢀaꢀfullyꢀintegratedꢀ

systemꢀoscillatorꢀwhichꢀrequiresꢀnoꢀexternalꢀcomponentsꢀforꢀitsꢀimplementation.

TheꢀinclusionꢀofꢀﬂexibleꢀI/Oꢀprogrammingꢀfeatures,ꢀTime-Baseꢀfunctionsꢀalongꢀwithꢀmanyꢀotherꢀ

featuresꢀensureꢀthatꢀtheꢀdevicesꢀwillꢀﬁndꢀexcellentꢀuseꢀinꢀapplicationsꢀsuchꢀasꢀelectronicꢀmetering,ꢀ

environmentalꢀmonitoring,ꢀhandheldꢀinstruments,ꢀhouseholdꢀappliances,ꢀelectronicallyꢀcontrolledꢀ

tools,ꢀmotorꢀdrivingꢀinꢀadditionꢀtoꢀmanyꢀothers.

Selection Table

Mostꢀfeaturesꢀareꢀcommonꢀtoꢀallꢀdevices,ꢀtheꢀmainꢀfeatureꢀdistinguishingꢀthemꢀareꢀProgramꢀMemoryꢀ

andꢀDataꢀmemoryꢀcapacity.ꢀTheꢀfollowingꢀtableꢀsummarisesꢀtheꢀmainꢀfeaturesꢀofꢀeachꢀdevice.

Program

Memory Memory EEPROM

Data

Ext.

Interrupt

Part No.

I/O

8

Timer Module Time Base Stack Package

8SOP

HT68F002

1K×14

64×8

32×8

1

10-bit STM×1

2

4

2

10MSOP

8SOP

10SOP

HT68F0025 2K×14

HT68F003 1K×14

8

10-bit STM×1

10-bit PTM×1

14

16NSOP

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April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Block Diagram

Watchdog

Timer

Low Voltage

Reset

Flash/EEPROM

Programming Circuitry

Reset

Circuit

8-bit

RISC

MCU

Core

EEPROM

Data

Memory

Flash

Program

Memory

Time

Bases

Interrupt

Controller

Internal RC

Oscillators

RAM Data

Memory

Timer

Modules

I/O

Low Voltage

Detect

Pin Assignment

VDD

10

9

VSS

1

2

3

4

5

PA6/STP0I/[STCK0]

PA5/INT/STP0B

VDD

VSS

8

PA0/[STP0]/[STP0I]/ICPDA

PA1/[STP0B]

PA2/[INT]/STP0

PA3/[INT]

1

2

3

4

PA6/STP0I/[STCK0]

PA0/[STP0]/[STP0I]/ICPDA

8

7

6

5

PA5/INT/STP0B

PA1/[STP0B]

7

PA7/[INT]/STCK0/RES/ICPCK

PA4

PA7/[INT]/STCK0/RES/ICPCK

PA2/[INT]/STP0

6

HT68F002

10 MSOP-A

HT68F002

8 SOP-A

VDD

PA6/STP0I/[STCK0]

PA5/INT/STP0B

10

9

1

2

3

4

5

VSS

VDD

PA0/[STP0]/[STP0I]/ICPDA

PA1/[STP0B]

VSS

1

2

3

4

8

7

6

5

PA6/STP0I/[STCK0]

8

PA0/[STP0]/[STP0I]/ICPDA

PA1/[STP0B]

PA5/INT/STP0B

PA7/[INT]/STCK0/RES/ICPCK

PA4

7

PA2/[INT]/STP0

PA3/[INT]

6

PA7/[INT]/STCK0/RES/ICPCK

PA2/[INT]/STP0

HT68F0025

10 SOP-A

HT68F0025

8 SOP-A

VDD

VSS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PB3/[PTP1]

PB2/PTP1B

PB1/[PTCK1]/STP0B

PB0/[PTP1I]

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PA6/STP0I/[STCK0]

PA0/[STP0]/[STP0I]/ICPDA

PA1/[STP0B]

PB4/[PTP1B]

PA5/INT/STP0B

PA7/[INT]/STCK0/RES/ICPCK

PA4

PB5/PTP1

PA2/[INT]/STP0

PA3/[INT]

NC

PA3/INT/STCK0

PA4/[INT]/PTCK1/STP0

PA5/[INT]/PTP1I

PA2/[INT]/[STCK0]/OCDSCK/ICPCK

PA1

NC

PA6/[PTCK1]/STP0I/[STP0]

PA7/[PTCK1]/[STP0B]/RES

VDD

NC

PA0/[STP0I]/OCDSDA/ICPDA

VSS

NC

OCDSDA

OCDSCK

HT68F003/HT68V003

16 NSOP-A

HT68V002/HT68V0025

16 NSOP-A

Note:ꢀBracketedꢀpinꢀnamesꢀindicateꢀnon-defaultꢀpinoutꢀremappingꢀlocations.

Rev. 1.41

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April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Pin Description

Withꢀtheꢀexceptionꢀofꢀtheꢀpowerꢀpinsꢀandꢀsomeꢀrelevantꢀtransformerꢀcontrolꢀpins,ꢀallꢀpinsꢀonꢀtheseꢀ

devicesꢀcanꢀbeꢀreferencedꢀbyꢀtheirꢀPortꢀname,ꢀe.g.ꢀPA0,ꢀPA1ꢀetc,ꢀwhichꢀreferꢀtoꢀtheꢀdigitalꢀI/Oꢀ

functionꢀofꢀtheꢀpins.ꢀHoweverꢀtheseꢀPortꢀpinsꢀareꢀalsoꢀsharedꢀwithꢀotherꢀfunctionꢀsuchꢀasꢀtheꢀAnalogꢀ

toꢀDigitalꢀConverter,ꢀTimerꢀModuleꢀpinsꢀetc.ꢀTheꢀfunctionꢀofꢀeachꢀpinꢀisꢀlistedꢀinꢀtheꢀfollowingꢀtable,ꢀ

howeverꢀtheꢀdetailsꢀbehindꢀhowꢀeachꢀpinꢀisꢀconﬁguredꢀisꢀcontainedꢀinꢀotherꢀsectionsꢀofꢀtheꢀdatasheet.

HT68F002/HT68F0025

Pin Name

Function

OPT

I/T

O/T

Description

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

PA0

ST

CMOS

PA0/[STP0]/

[STP0I]/ICPDA

STP0

STP0I

ICPDA

PASR

—

ST

CMOS TM0 (STM) output

TM0 (STM) input

CMOS ICP Data Line

General purpose I/O. Register enabled pull-up and

PASR

IFS0

—

PAWU

PAPU

PASR

PA1

STP0B

PA2

ST

—

CMOS

wake-up

PA1/[STP0B]

PASR

CMOS TM0 (STM) inverting output

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

ST

CMOS

PA2/[INT]/STP0

PASR

IFS0

INT

ST

—

External interrupt input

STP0

PASR

CMOS TM0 (STM) output

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

PA3

ST

CMOS

PA3/[INT]

PA4

PASR

IFS0

INT

ST

—

External interrupt input

PAWU

PAPU

General purpose I/O. Register enabled pull-up and

wake-up

PA4

CMOS

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

PA5

ST

CMOS

PA5/INT/STP0B

PASR

IFS0

INT

STP0B

PA6

ST

—

External interrupt input

PASR

CMOS TM0 (STM) inverting output

PAWU

PAPU

General purpose I/O. Register enabled pull-up and

wake-up

ST

CMOS

PA6/STP0I/

[STCK0]

STP0I

IFS0

ST

—

TM0 (STM) input

STCK0

TM0 (STM) clock input

PAWU

PAPU

General purpose I/O. Register enabled pull-up and

wake-up

PA7

ST

CMOS

INT

STCK0

RES

IFS0

RSTC

—

ST

—

External interrupt input

TM0 (STM) clock input

External reset input

PA7/[INT]/STCK0/

RES/ICPCK

ST

ICPCK

VDD

ST

CMOS ICP Clock Line

VDD

—

PWR

ST

—

Digital positive power supply

VSS

—

Digital negative power supply

OCDSCK

OCDSDA

OCDSCK

OCDSDA

—

On Chip Debug System Clock Line (OCDS EV only)

—

ST

CMOS On Chip Debug System Data Line (OCDS EV only)

Rev. 1.41

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April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

HT68F003

Pin Name

Function

OPT

I/T

O/T

Description

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

PA0

ST

CMOS

PA0/[STP0I]/

OCDSDA/ICPDA

PASR

IFS0

STP0I

ST

—

TM0 (STM) input

OCDSDA

ICPDA

—

ST

CMOS On Chip Debug System Data Line (OCDS EV only)

CMOS ICP Data Line

PAWU

PAPU

General purpose I/O. Register enabled pull-up and

wake-up

PA1

PA2

INT

ST

CMOS

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

CMOS

PA2/[INT]/

[STCK0]

/OCDSCK/ICPCK

PASR

IFS0

—

External interrupt input

STCK0

OCDSCK

ICPCK

IFS0

—

ST

—

TM0 (STM) clock input

On Chip Debug System Clock Line (OCDS EV only)

—

CMOS ICP Clock Line

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

PA3

ST

CMOS

PA3/INT/STCK0

PASR

IFS0

INT

ST

—

External interrupt input

TM0 (STM) clock input

STCK0

IFS0

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

PA4

INT

ST

CMOS

PASR

IFS0

PA4/[INT]/PTCK1/

STP0

—

External interrupt input

TM1 (PTM) clock input

PASR

IFS0

PTCK1

STP0

PA5

ST

—

PASR

CMOS TM0 (STM) output

PAWU

PAPU

General purpose I/O. Register enabled pull-up and

wake-up

ST

CMOS

PA5/[INT]/PTP1I

INT

IFS0

ST

—

External interrupt input

TM1 (PTM) input

PTP1I

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

PA6

ST

CMOS

PASR

IFS0

PA6/[PTCK1]/

STP0I/[STP0]

PTCK1

—

TM1 (PTM) clock input

TM0 (STM) input

PASR

IFS0

STP0I

STP0

ST

—

PASR

CMOS TM0 (STM) output

PAWU

PAPU

PASR

General purpose I/O. Register enabled pull-up and

wake-up

PA7

ST

CMOS

PA7/[PTCK1]/

[STP0B]/RES

PASR

IFS0

PTCK1

ST

—

TM1 (PTM) clock input

STP0B

RES

PASR

RSTC

ST

CMOS TM0 (STM) inverting output

— External reset input

Rev. 1.41

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April 11, 2017

..................................................................................................-40˚Cꢀtoꢀ85˚Cꢀ

StorageꢀTemperature

OperatingꢀTemperature

I_OLꢀTotalꢀ..................................................................................................................................... 80mAꢀ

_OHꢀTotalꢀ....................................................................................................................................-80mAꢀ

....................................................................................................-50˚Cꢀtoꢀ125˚Cꢀ

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Pin Name

Function

OPT

I/T

O/T

CMOS General purpose I/O. Register enabled pull-up

TM1 (PTM) input

CMOS General purpose I/O. Register enabled pull-up

TM1 (PTM) clock input

Description

PBPU

PBSR

PB0

ST

PB0/[PTP1I]

PBSR

IFS0

PTP1I

PB1

ST

—

PBPU

PBSR

PB1/[PTCK1]/

STP0B

PBSR

IFS0

PTCK1

STP0B

PB2

ST

—

PBSR

CMOS TM0 (STM) inverting output

PBPU

PBSR

CMOS General purpose I/O. Register enabled pull-up

CMOS TM1 (PTM) inverting output

PB2/PTP1B

PB3/[PTP1]

PB4/[PTP1B]

PB5/PTP1

PTP1B

PB3

PBSR

PBPU

PBSR

CMOS General purpose I/O. Register enabled pull-up

CMOS TM1 (PTM) output

PTP1

PB4

PBSR

PBPU

PBSR

ST

—

CMOS General purpose I/O. Register enabled pull-up

CMOS TM1 (PTM) inverting output

PTP1B

PB5

PBSR

PBPU

PBSR

ST

CMOS General purpose I/O. Register enabled pull-up

CMOS TM1 (PTM) output

PTP1

VDD

PBSR

—

VDD

VSS

PWR

—

Digital positive power supply

Digital negative power supply

VSS

—

PWR

Note:ꢀI/T:ꢀInputꢀtype;ꢀ

O/T:ꢀOutputꢀtype

OPT:ꢀOptionalꢀbyꢀregisterꢀoption

PWR:ꢀPower;ꢀ

ST:ꢀSchmittꢀTriggerꢀinput

CMOS:ꢀCMOSꢀoutput

Absolute Maximum Ratings

SupplyꢀVoltageꢀ................................................................................................V_SS−0.3VꢀtoꢀV_SS+6.0Vꢀ

InputꢀVoltageꢀ..................................................................................................V_SS−0.3VꢀtoꢀV_DD+0.3Vꢀ

I

TotalꢀPowerꢀDissipationꢀ......................................................................................................... 500mWꢀ

Note:ꢀTheseꢀareꢀstressꢀratingsꢀonly.ꢀStressesꢀexceedingꢀtheꢀrangeꢀspecifiedꢀunderꢀ"AbsoluteꢀMaximumꢀ

Ratings"ꢀmayꢀcauseꢀsubstantialꢀdamageꢀtoꢀtheseꢀdevices.ꢀFunctionalꢀoperationꢀofꢀtheseꢀdevicesꢀatꢀ

otherꢀconditionsꢀbeyondꢀthoseꢀlistedꢀinꢀtheꢀspeciﬁcationꢀisꢀnotꢀimpliedꢀandꢀprolongedꢀexposureꢀtoꢀ

extremeꢀconditionsꢀmayꢀaffectꢀdevicesꢀreliability.

Rev. 1.41

10

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

D.C. Characteristics

Ta = 25°C

Test Conditions

Conditions

Symbol

V_DD

Parameter

Min. Typ. Max. Unit

V_DD

—

Operating Voltage (HIRC)

f_SYS=8MHz

2.2

—

1.0

2.0

20

5.5

2.0

3.0

30

V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

—

mA

μA

mA

μA

mA

μA

V

Operating Current,

Normal Mode, f_SYS=f_H(HIRC)

No load, f_H=8MHz, WDT enable,

LVR enable

I_DD1

—

Operating Current,

Slow Mode, f_SYS=f_L=LIRC

No load, f_SYS=LIRC, WDT enable,

LVR enable

I_DD2

—

30

60

—

1.0

1.5

0.9

1.3

0.8

1.1

0.7

1.0

0.6

0.9

0.5

0.8

1.3

5.0

0.8

1.0

0.1

0.3

1.3

2.2

—

1.5

2.0

1.3

1.8

1.1

1.6

1.0

1.4

0.9

1.2

0.8

1.1

3.0

10

No load, f_SYS=f_H/2, WDT enable,

LVR enable

—

No load, f_SYS=f_H/4, WDT enable,

LVR enable

—

No load, f_SYS=f_H/8, WDT enable,

LVR enable

—

Operating Current,

Normal Mode, f_H=8MHz (HIRC)

I_DD3

—

No load, f_SYS=f_H/16, WDT enable,

LVR enable

—

No load, f_SYS=f_H/32, WDT enable,

LVR enable

—

No load, f_SYS=f_H/64, WDT enable,

LVR enable

—

IDLE0 Mode Standby Current

(LIRC on)

No load, WDT enable, LVR

disable

I_IDLE0

I_IDLE1

I_SLEEP0

I_SLEEP1

V_IL1

—

1.6

2.0

1.0

2.0

5.0

10

IDLE1 Mode Standby Current

(HIRC)

No load, WDT enable,

f_SYS=8MHz on

—

SLEEP0 Mode Standby Current

(LIRC off)

No load, WDT disable,

LVR disable

—

SLEEP1 Mode Standby Current

(LIRC on)

No load, WDT enable,

LVR disable

—

0

1.5

0.2V_DD

5.0

V_DD

0.4V_DD

V_DD

—

Input Low Voltage for I/O Ports or

Input Pins except RES pin

0

—

V

5V

—

3.5

0.8V_DD

0

—

V

Input High Voltage for I/O Ports or

Input Pins except RES pin

V_IH1

—

V

V_IL2

V_IH2

Input Low Voltage (RES)

Input High Voltage (RES)

—

V

—

0.9V_DD

18

40

-3

—

V

3V V_OL=0.1V_DD

5V V_OL=0.1V_DD

3V V_OH=0.9V_DD

5V V_OH=0.9V_DD

3V

36

mA

kΩ

I_OL

I/O Port Sink Current

80

—

-6

—

I_OH

I/O Port, Source Current

Pull-high Resistance for I/O Ports

-7

-14

60

—

20

10

100

50

R_PH

5V

30

Operating Current, Normal Mode,

f_SYS=f_H(HIRC) (for OCDS EV

testing, connect to an e-Link)

I_OCDS

I_LEAK

3V No load, f_H=8MHz, WDT enable

5V V_IN=V_DDor V_IN=V_SS

—

1.4

—

2.0

±1

mA

Input Leakage Current

μA

Rev. 1.41

11

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

A.C. Characteristics

Ta = 25°C

Test Conditions

Symbol

Parameter

Operating Clock

Min.

Typ. Max. Unit

V_DD

Condition

f_CPU

2.2~5.5V

3V/5V

—

DC

-2%

-5%

-8%

-12%

8

—

8

MHz

Ta = 25°C

Ta = 0°C to 70°C

+2% MHz

+5% MHz

+8% MHz

+12% MHz

3V/5V

8

f_HIRC

System Clock (HIRC)

2.2V~5.5V Ta = 0°C to 70°C

2.2V~5.5V Ta = -40°C to 85°C

8

f_LIRC

t_TIMER

t_RES

System Clock (LIRC)

32

—

2

50

—

4

kHz

μs

xTCKn, xTPnI Input Pulse Width

External Reset Low Pulse Width

Interrupt Pulse Width

—

0.3

10

μs

t_INT

0.3

—

μs

t_EERD

t_EEWR

EEPROM Read Time

t_SYS

ms

EEPROM Write Time

—

4

10

—

System Start-up Timer Period

(Wake-up from HALT, f_SYSoff at

HALT State)

f_SYS= HIRC

f_SYS= LIRC

16

—

t_SST

—

t_SYS

2

—

System Reset Delay Time

(Power On Reset, LVR Reset,

WDT S/W Reset(WDTC))

—

25

50

100

ms

t_RSTD

System Reset Delay Time

(RES Reset, WDT Normal Reset)

8.3

16.7

33.3

Note:ꢀ1.ꢀt_SYS=ꢀ1/f_SYS

2.ꢀToꢀmaintainꢀtheꢀaccuracyꢀofꢀtheꢀinternalꢀHIRCꢀoscillatorꢀfrequency,ꢀaꢀ0.1μFꢀdecouplingꢀcapacitorꢀshouldꢀ

beꢀconnectedꢀbetweenꢀVDDꢀandꢀVSSꢀandꢀlocatedꢀasꢀcloseꢀtoꢀtheꢀdeviceꢀasꢀpossible.

Rev. 1.41

12

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

LVR&LVD Electrical Characteristics

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ. Max. Unit

V_DD

—

V_DD

Operating Voltage

—

1.9

—

2.1

2.0

2.2

2.4

2.7

3.0

3.3

3.6

4.0

320

—

5.5

V

V_LVR

Low Voltage Reset Voltage

Low Voltage Detector Voltage

—

LVR Enable, 2.1V option

ENLVD = 1, V_LVD= 2.0V

ENLVD = 1, V_LVD= 2.2V

ENLVD = 1, V_LVD= 2.4V

ENLVD = 1, V_LVD= 2.7V

ENLVD = 1, V_LVD= 3.0V

ENLVD = 1, V_LVD= 3.3V

ENLVD = 1, V_LVD= 3.6V

ENLVD = 1, V_LVD= 4.0V

—

-5%

+5%

V

V_LVD

—

-5%

+5%

V

t_LVR

Low Voltage Width to Reset

LVDO stable time

—

160

—

640

15

μs

For LVR enable, LVD off→on

For LVR disable, LVD off→on

t_LVDS

—

150

Power on Reset Electrical Characteristics

Ta = 25°C

Typ. Max. Unit

Test Conditions

Symbol

Parameter

Min.

V_DD

Conditions

V_POR

V_DDStart Voltage to Ensure Power-on Reset

V_DDRising Rate to Ensure Power-on Reset

—

100

—

mV

RR_POR

0.035

V/ms

Minimum Time for V_DDStays at V_PORto

Ensure Power-on Reset

t_POR

—

1

—

ms

V

D

t

P

R

O

R

P

R

O

V

P

R

O

T

m

i

Rev. 1.41

13

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

System Architecture

Aꢀkeyꢀfactorꢀinꢀtheꢀhigh-performanceꢀfeaturesꢀofꢀtheꢀHoltekꢀrangeꢀofꢀmicrocontrollersꢀisꢀattributedꢀ

toꢀtheirꢀinternalꢀsystemꢀarchitecture.ꢀTheꢀdeviceꢀtakesꢀadvantageꢀofꢀtheꢀusualꢀfeaturesꢀfoundꢀwithinꢀ

RISCꢀmicrocontrollersꢀprovidingꢀincreasedꢀspeedꢀofꢀoperationꢀandꢀPeriodicꢀperformance.ꢀTheꢀ

pipeliningꢀschemeꢀisꢀimplementedꢀinꢀsuchꢀaꢀwayꢀthatꢀinstructionꢀfetchingꢀandꢀinstructionꢀexecutionꢀ

areꢀoverlapped,ꢀhenceꢀinstructionsꢀareꢀeffectivelyꢀexecutedꢀinꢀoneꢀcycle,ꢀwithꢀtheꢀexceptionꢀofꢀbranchꢀ

orꢀcallꢀinstructions.ꢀAnꢀ8-bitꢀwideꢀALUꢀisꢀusedꢀinꢀpracticallyꢀallꢀinstructionꢀsetꢀoperations,ꢀwhichꢀ

carriesꢀoutꢀarithmeticꢀoperations,ꢀlogicꢀoperations,ꢀrotation,ꢀincrement,ꢀdecrement,ꢀbranchꢀdecisions,ꢀ

etc.ꢀTheꢀinternalꢀdataꢀpathꢀisꢀsimplifiedꢀbyꢀmovingꢀdataꢀthroughꢀtheꢀAccumulatorꢀandꢀtheꢀALU.ꢀ

CertainꢀinternalꢀregistersꢀareꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀdirectlyꢀorꢀindirectlyꢀ

addressed.ꢀTheꢀsimpleꢀaddressingꢀmethodsꢀofꢀtheseꢀregistersꢀalongꢀwithꢀadditionalꢀarchitecturalꢀ

featuresꢀensureꢀthatꢀaꢀminimumꢀofꢀexternalꢀcomponentsꢀisꢀrequiredꢀtoꢀprovideꢀaꢀfunctionalꢀI/Oꢀ

controlꢀsystemꢀwithꢀmaximumꢀreliabilityꢀandꢀﬂexibility.ꢀThisꢀmakesꢀtheseꢀdevicesꢀsuitableꢀforꢀlow-

cost,ꢀhigh-volumeꢀproductionꢀforꢀcontrollerꢀapplications

Clocking and Pipelining

Theꢀmainꢀsystemꢀclock,ꢀderivedꢀfromꢀeitherꢀaꢀHIRCꢀorꢀLIRCꢀoscillatorꢀisꢀsubdividedꢀintoꢀfourꢀ

internallyꢀgeneratedꢀnon-overlappingꢀclocks,ꢀT1~T4.ꢀTheꢀProgramꢀCounterꢀisꢀincrementedꢀatꢀtheꢀ

beginningꢀofꢀtheꢀT1ꢀclockꢀduringꢀwhichꢀtimeꢀaꢀnewꢀinstructionꢀisꢀfetched.ꢀTheꢀremainingꢀT2~T4ꢀ

clocksꢀcarryꢀoutꢀtheꢀdecodingꢀandꢀexecutionꢀfunctions.ꢀInꢀthisꢀway,ꢀoneꢀT1~T4ꢀclockꢀcycleꢀformsꢀ

oneꢀinstructionꢀcycle.ꢀAlthoughꢀtheꢀfetchingꢀandꢀexecutionꢀofꢀinstructionsꢀtakesꢀplaceꢀinꢀconsecutiveꢀ

instructionꢀcycles,ꢀtheꢀpipeliningꢀstructureꢀofꢀtheꢀmicrocontrollerꢀensuresꢀthatꢀinstructionsꢀareꢀ

effectivelyꢀexecutedꢀinꢀoneꢀinstructionꢀcycle.ꢀTheꢀexceptionꢀtoꢀthisꢀareꢀinstructionsꢀwhereꢀtheꢀ

contentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀchanged,ꢀsuchꢀasꢀsubroutineꢀcallsꢀorꢀjumps,ꢀinꢀwhichꢀcaseꢀtheꢀ

instructionꢀwillꢀtakeꢀoneꢀmoreꢀinstructionꢀcycleꢀtoꢀexecute.

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P

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2

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System Clock and Pipelining

Forꢀinstructionsꢀinvolvingꢀbranches,ꢀsuchꢀasꢀjumpꢀorꢀcallꢀinstructions,ꢀtwoꢀmachineꢀcyclesꢀareꢀ

requiredꢀtoꢀcompleteꢀinstructionꢀexecution.ꢀAnꢀextraꢀcycleꢀisꢀrequiredꢀasꢀtheꢀprogramꢀtakesꢀoneꢀ

cycleꢀtoꢀﬁrstꢀobtainꢀtheꢀactualꢀjumpꢀorꢀcallꢀaddressꢀandꢀthenꢀanotherꢀcycleꢀtoꢀactuallyꢀexecuteꢀtheꢀ

branch.ꢀTheꢀrequirementꢀforꢀthisꢀextraꢀcycleꢀshouldꢀbeꢀtakenꢀintoꢀaccountꢀbyꢀprogrammersꢀinꢀtimingꢀ

sensitiveꢀapplications.

Rev. 1.41

14

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

F

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Instruction Fetching

Program Counter

Duringꢀprogramꢀexecution,ꢀtheꢀProgramꢀCounterꢀisꢀusedꢀtoꢀkeepꢀtrackꢀofꢀtheꢀaddressꢀofꢀtheꢀ

nextꢀinstructionꢀtoꢀbeꢀexecuted.ꢀItꢀisꢀautomaticallyꢀincrementedꢀbyꢀoneꢀeachꢀtimeꢀanꢀinstructionꢀ

isꢀexecutedꢀexceptꢀforꢀinstructions,ꢀsuchꢀasꢀ"JMP"ꢀorꢀ"CALL"ꢀthatꢀdemandꢀaꢀjumpꢀtoꢀaꢀnon-

consecutiveꢀProgramꢀMemoryꢀaddress.ꢀOnlyꢀtheꢀlowerꢀ8ꢀbits,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀLowꢀ

Register,ꢀareꢀdirectlyꢀaddressableꢀbyꢀtheꢀapplicationꢀprogram.

Whenꢀexecutingꢀinstructionsꢀrequiringꢀjumpsꢀtoꢀnon-consecutiveꢀaddressesꢀsuchꢀasꢀaꢀjumpꢀinstruction,ꢀ

aꢀsubroutineꢀcall,ꢀinterruptꢀorꢀreset,ꢀetc.,ꢀtheꢀmicrocontrollerꢀmanagesꢀprogramꢀcontrolꢀbyꢀloadingꢀ

theꢀrequiredꢀaddressꢀintoꢀtheꢀProgramꢀCounter.ꢀForꢀconditionalꢀskipꢀinstructions,ꢀonceꢀtheꢀconditionꢀ

hasꢀbeenꢀmet,ꢀtheꢀnextꢀinstruction,ꢀwhichꢀhasꢀalreadyꢀbeenꢀfetchedꢀduringꢀtheꢀpresentꢀinstructionꢀ

execution,ꢀisꢀdiscardedꢀandꢀaꢀdummyꢀcycleꢀtakesꢀitsꢀplaceꢀwhileꢀtheꢀcorrectꢀinstructionꢀisꢀobtained.

Program Counter

Device

Program Counter High byte

PC9~PC8

PCL Register

PCL7~PCL0

HT68F002/HT68F003

HT68F0025

PC10~PC8

TheꢀlowerꢀbyteꢀofꢀtheꢀProgramꢀCounter,ꢀknownꢀasꢀtheꢀProgramꢀCounterꢀLowꢀregisterꢀorꢀPCL,ꢀisꢀ

availableꢀforꢀprogramꢀcontrolꢀandꢀisꢀaꢀreadableꢀandꢀwriteableꢀregister.ꢀByꢀtransferringꢀdataꢀdirectlyꢀ

intoꢀthisꢀregister,ꢀaꢀshortꢀprogramꢀjumpꢀcanꢀbeꢀexecutedꢀdirectly,ꢀhowever,ꢀasꢀonlyꢀthisꢀlowꢀbyteꢀisꢀ

availableꢀforꢀmanipulation,ꢀtheꢀjumpsꢀareꢀlimitedꢀtoꢀtheꢀpresentꢀpageꢀofꢀmemory,ꢀthatꢀisꢀ256ꢀlocations.ꢀ

Whenꢀsuchꢀprogramꢀjumpsꢀareꢀexecutedꢀitꢀshouldꢀalsoꢀbeꢀnotedꢀthatꢀaꢀdummyꢀcycleꢀwillꢀbeꢀinserted.ꢀ

ManipulatingꢀtheꢀPCLꢀregisterꢀmayꢀcauseꢀprogramꢀbranching,ꢀsoꢀanꢀextraꢀcycleꢀisꢀneededꢀtoꢀpre-fetch.

Stack

ThisꢀisꢀaꢀspecialꢀpartꢀofꢀtheꢀmemoryꢀwhichꢀisꢀusedꢀtoꢀsaveꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀ

only.ꢀTheꢀstackꢀisꢀneitherꢀpartꢀofꢀtheꢀdataꢀnorꢀpartꢀofꢀtheꢀprogramꢀspace,ꢀandꢀisꢀneitherꢀreadableꢀnorꢀ

writeable.ꢀTheꢀactivatedꢀlevelꢀisꢀindexedꢀbyꢀtheꢀStackꢀPointer,ꢀandꢀisꢀneitherꢀreadableꢀnorꢀwriteable.ꢀ

Atꢀaꢀsubroutineꢀcallꢀorꢀinterruptꢀacknowledgeꢀsignal,ꢀtheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀpushedꢀ

ontoꢀtheꢀstack.ꢀAtꢀtheꢀendꢀofꢀaꢀsubroutineꢀorꢀanꢀinterruptꢀroutine,ꢀsignaledꢀbyꢀaꢀreturnꢀinstruction,ꢀ

RETꢀorꢀRETI,ꢀtheꢀProgramꢀCounterꢀisꢀrestoredꢀtoꢀitsꢀpreviousꢀvalueꢀfromꢀtheꢀstack.ꢀAfterꢀaꢀdeviceꢀ

reset,ꢀtheꢀStackꢀPointerꢀwillꢀpointꢀtoꢀtheꢀtopꢀofꢀtheꢀstack.

Ifꢀtheꢀstackꢀisꢀfullꢀandꢀanꢀenabledꢀinterruptꢀtakesꢀplace,ꢀtheꢀinterruptꢀrequestꢀﬂagꢀwillꢀbeꢀrecordedꢀ

butꢀtheꢀacknowledgeꢀsignalꢀwillꢀbeꢀinhibited.ꢀWhenꢀtheꢀStackꢀPointerꢀisꢀdecremented,ꢀbyꢀRETꢀorꢀ

RETI,ꢀtheꢀinterruptꢀwillꢀbeꢀserviced.ꢀThisꢀfeatureꢀpreventsꢀstackꢀoverﬂowꢀallowingꢀtheꢀprogrammerꢀ

toꢀuseꢀtheꢀstructureꢀmoreꢀeasily.ꢀHowever,ꢀwhenꢀtheꢀstackꢀisꢀfull,ꢀaꢀCALLꢀsubroutineꢀinstructionꢀcanꢀ

stillꢀbeꢀexecutedꢀwhichꢀwillꢀresultꢀinꢀaꢀstackꢀoverﬂow.ꢀPrecautionsꢀshouldꢀbeꢀtakenꢀtoꢀavoidꢀsuchꢀ

casesꢀwhichꢀmightꢀcauseꢀunpredictableꢀprogramꢀbranching.ꢀIfꢀtheꢀstackꢀisꢀoverﬂow,ꢀtheꢀﬁrstꢀProgramꢀ

Counterꢀsaveꢀinꢀtheꢀstackꢀwillꢀbeꢀlost.

Rev. 1.41

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Program Counter

Top of Stack

Stack Level 1

:

Stack

Pointer

Program Memory

Stack Level N

Bottom of Stack

Device

Stack Levels

N=2

HT68F002/HT68F003

HT68F0025

N=4

Arithmetic and Logic Unit – ALU

Theꢀarithmetic-logicꢀunitꢀorꢀALUꢀisꢀaꢀcriticalꢀareaꢀofꢀtheꢀmicrocontrollerꢀthatꢀcarriesꢀoutꢀarithmeticꢀ

andꢀlogicꢀoperationsꢀofꢀtheꢀinstructionꢀset.ꢀConnectedꢀtoꢀtheꢀmainꢀmicrocontrollerꢀdataꢀbus,ꢀtheꢀALUꢀ

receivesꢀrelatedꢀinstructionꢀcodesꢀandꢀperformsꢀtheꢀrequiredꢀarithmeticꢀorꢀlogicalꢀoperationsꢀafterꢀ

whichꢀtheꢀresultꢀwillꢀbeꢀplacedꢀinꢀtheꢀspeciﬁedꢀregister.ꢀAsꢀtheseꢀALUꢀcalculationꢀorꢀoperationsꢀmayꢀ

resultꢀinꢀcarry,ꢀborrowꢀorꢀotherꢀstatusꢀchanges,ꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀcorrespondinglyꢀupdatedꢀtoꢀ

reﬂectꢀtheseꢀchanges.ꢀTheꢀALUꢀsupportsꢀtheꢀfollowingꢀfunctions:

•ꢀ Arithmeticꢀoperations:ꢀADD,ꢀADDM,ꢀADC,ꢀADCM,ꢀSUB,ꢀSUBM,ꢀSBC,ꢀSBCM,ꢀDAA

•ꢀ Logicꢀoperations:ꢀAND,ꢀOR,ꢀXOR,ꢀANDM,ꢀORM,ꢀXORM,ꢀCPL,ꢀCPLA

•ꢀ Rotation:ꢀRRA,ꢀRR,ꢀRRCA,ꢀRRC,ꢀRLA,ꢀRL,ꢀRLCA,ꢀRLC

•ꢀ IncrementꢀandꢀDecrement:ꢀINCA,ꢀINC,ꢀDECA,ꢀDEC

•ꢀ Branchꢀdecision:ꢀJMP,ꢀSZ,ꢀSZA,ꢀSNZ,ꢀSIZ,ꢀSDZ,ꢀSIZA,ꢀSDZA,ꢀCALL,ꢀRET,ꢀRETI

Flash Program Memory

TheꢀProgramꢀMemoryꢀisꢀtheꢀlocationꢀwhereꢀtheꢀuserꢀcodeꢀorꢀprogramꢀisꢀstored.ꢀForꢀtheseꢀdevicesꢀ

theꢀProgramꢀMemoryꢀareꢀFlashꢀtype,ꢀwhichꢀmeansꢀitꢀcanꢀbeꢀprogrammedꢀandꢀre-programmedꢀaꢀ

largeꢀnumberꢀofꢀtimes,ꢀallowingꢀtheꢀuserꢀtheꢀconvenienceꢀofꢀcodeꢀmodiﬁcationꢀonꢀtheꢀsameꢀdevice.ꢀ

Byꢀusingꢀtheꢀappropriateꢀprogrammingꢀtools,ꢀtheseꢀFlashꢀdevicesꢀofferꢀusersꢀtheꢀflexibilityꢀtoꢀ

convenientlyꢀdebugꢀandꢀdevelopꢀtheirꢀapplicationsꢀwhileꢀalsoꢀofferingꢀaꢀmeansꢀofꢀﬁeldꢀprogrammingꢀ

andꢀupdating.

Structure

TheꢀProgramꢀMemoryꢀhasꢀaꢀcapacityꢀofꢀ1K×14ꢀbits.ꢀTheꢀProgramꢀMemoryꢀisꢀaddressedꢀbyꢀtheꢀ

ProgramꢀCounterꢀandꢀalsoꢀcontainsꢀdata,ꢀtableꢀinformationꢀandꢀinterruptꢀentries.ꢀTableꢀdata,ꢀwhichꢀ

canꢀbeꢀsetupꢀinꢀanyꢀlocationꢀwithinꢀtheꢀProgramꢀMemory,ꢀisꢀaddressedꢀbyꢀaꢀseparateꢀtableꢀpointerꢀ

register.

Device

HT68F002/HT68F003

HT68F0025

Capacity

1K×14

2K×14

Rev. 1.41

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Program Memory Structure

Special Vectors

WithinꢀtheꢀProgramꢀMemory,ꢀcertainꢀlocationsꢀareꢀreservedꢀforꢀtheꢀresetꢀandꢀinterrupts.ꢀTheꢀlocationꢀ

000Hꢀisꢀreservedꢀforꢀuseꢀbyꢀtheseꢀdevicesꢀresetꢀforꢀprogramꢀinitialisation.ꢀAfterꢀaꢀdeviceꢀresetꢀisꢀ

initiated,ꢀtheꢀprogramꢀwillꢀjumpꢀtoꢀthisꢀlocationꢀandꢀbeginꢀexecution.

Look-up Table

AnyꢀlocationꢀwithinꢀtheꢀProgramꢀMemoryꢀcanꢀbeꢀdeﬁnedꢀasꢀaꢀlook-upꢀtableꢀwhereꢀprogrammersꢀcanꢀ

storeꢀﬁxedꢀdata.ꢀToꢀuseꢀtheꢀlook-upꢀtable,ꢀtheꢀtableꢀpointerꢀmustꢀﬁrstꢀbeꢀsetupꢀbyꢀplacingꢀtheꢀaddressꢀ

ofꢀtheꢀlookꢀupꢀdataꢀtoꢀbeꢀretrievedꢀinꢀtheꢀtableꢀpointerꢀregister,ꢀTBLP.ꢀThisꢀregisterꢀdeﬁnesꢀtheꢀtotalꢀ

addressꢀofꢀtheꢀlook-upꢀtable.

Afterꢀsettingꢀupꢀtheꢀtableꢀpointer,ꢀtheꢀtableꢀdataꢀcanꢀbeꢀretrievedꢀfromꢀtheꢀProgramꢀMemoryꢀusingꢀ

theꢀ"TABRDC[m]"ꢀorꢀ"TABRDL[m]"ꢀinstructions,ꢀrespectively.ꢀWhenꢀtheꢀinstructionꢀisꢀexecuted,ꢀ

theꢀlowerꢀorderꢀtableꢀbyteꢀfromꢀtheꢀProgramꢀMemoryꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀuserꢀdefinedꢀ

DataꢀMemoryꢀregisterꢀ[m]ꢀasꢀspecifiedꢀinꢀtheꢀinstruction.ꢀTheꢀhigherꢀorderꢀtableꢀdataꢀbyteꢀfromꢀ

theꢀProgramꢀMemoryꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀTBLHꢀspecialꢀregister.ꢀAnyꢀunusedꢀbitsꢀinꢀthisꢀ

transferredꢀhigherꢀorderꢀbyteꢀwillꢀbeꢀreadꢀasꢀ"0".ꢀ

Theꢀaccompanyingꢀdiagramꢀillustratesꢀtheꢀaddressingꢀdataꢀﬂowꢀofꢀtheꢀlook-upꢀtable.

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Cost-Effective Flash MCU with EEPROM

Table Program Example

Theꢀfollowingꢀexampleꢀshowsꢀhowꢀtheꢀtableꢀpointerꢀandꢀtableꢀdataꢀisꢀdeﬁnedꢀandꢀretrievedꢀfromꢀtheꢀ

microcontroller.ꢀThisꢀexampleꢀusesꢀrawꢀtableꢀdataꢀlocatedꢀinꢀtheꢀProgramꢀMemoryꢀwhichꢀisꢀstoredꢀ

thereꢀusingꢀtheꢀORGꢀstatement.ꢀTheꢀvalueꢀatꢀthisꢀORGꢀstatementꢀisꢀ"300H"ꢀwhichꢀrefersꢀtoꢀtheꢀstartꢀ

addressꢀofꢀtheꢀlastꢀpageꢀwithinꢀtheꢀ1KꢀwordsꢀProgramꢀMemoryꢀofꢀtheꢀdevice.ꢀTheꢀtableꢀpointerꢀisꢀ

setupꢀhereꢀtoꢀhaveꢀanꢀinitialꢀvalueꢀofꢀ"06H".ꢀThisꢀwillꢀensureꢀthatꢀtheꢀﬁrstꢀdataꢀreadꢀfromꢀtheꢀdataꢀ

tableꢀwillꢀbeꢀatꢀtheꢀProgramꢀMemoryꢀaddressꢀ"306H"ꢀorꢀ6ꢀlocationsꢀafterꢀtheꢀstartꢀofꢀtheꢀlastꢀpage.ꢀ

Noteꢀthatꢀtheꢀvalueꢀforꢀtheꢀtableꢀpointerꢀisꢀreferencedꢀtoꢀtheꢀﬁrstꢀaddressꢀofꢀtheꢀpresentꢀpageꢀifꢀtheꢀ

"TABRDC[m]"ꢀinstructionꢀisꢀbeingꢀused.ꢀTheꢀhighꢀbyteꢀofꢀtheꢀtableꢀdataꢀwhichꢀinꢀthisꢀcaseꢀisꢀequalꢀ

toꢀzeroꢀwillꢀbeꢀtransferredꢀtoꢀtheꢀTBLHꢀregisterꢀautomaticallyꢀwhenꢀtheꢀ"TABRDC[m]"ꢀinstructionꢀ

isꢀexecuted.

BecauseꢀtheꢀTBLHꢀregisterꢀisꢀaꢀread-onlyꢀregisterꢀandꢀcannotꢀbeꢀrestored,ꢀcareꢀshouldꢀbeꢀtakenꢀ

toꢀensureꢀitsꢀprotectionꢀifꢀbothꢀtheꢀmainꢀroutineꢀandꢀInterruptꢀServiceꢀRoutineꢀuseꢀtableꢀreadꢀ

instructions.ꢀIfꢀusingꢀtheꢀtableꢀreadꢀinstructions,ꢀtheꢀInterruptꢀServiceꢀRoutinesꢀmayꢀchangeꢀtheꢀ

valueꢀofꢀtheꢀTBLHꢀandꢀsubsequentlyꢀcauseꢀerrorsꢀifꢀusedꢀagainꢀbyꢀtheꢀmainꢀroutine.ꢀAsꢀaꢀruleꢀitꢀisꢀ

recommendedꢀthatꢀsimultaneousꢀuseꢀofꢀtheꢀtableꢀreadꢀinstructionsꢀshouldꢀbeꢀavoided.ꢀHowever,ꢀinꢀ

situationsꢀwhereꢀsimultaneousꢀuseꢀcannotꢀbeꢀavoided,ꢀtheꢀinterruptsꢀshouldꢀbeꢀdisabledꢀpriorꢀtoꢀtheꢀ

executionꢀofꢀanyꢀmainꢀroutineꢀtable-readꢀinstructions.ꢀNoteꢀthatꢀallꢀtableꢀrelatedꢀinstructionsꢀrequireꢀ

twoꢀinstructionꢀcyclesꢀtoꢀcompleteꢀtheirꢀoperation.

Table Read Program Example

tempreg1 db ?

; temporary register #1

tempreg2 db ?

; temporary register #2

:

mov a,06h

mov tblp,a

; initialise low table pointer - note that this address is referenced

; to the last page or present page

:

tabrdl tempreg1

; transfers value in table referenced by table pointer data at program

; memory address "306H" transferred to tempreg1 and TBLH

; reduce value of table pointer by one

dec tblp

tabrdl tempreg2

; transfers value in table referenced by table pointer data at program

; memory address "305H" transferred to tempreg2 and TBLH in this

; example the data "1AH" is transferred to tempreg1 and data "0FH" to

; register tempreg2

:

org 300h

; sets initial address of program memory

dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

:

Rev. 1.41

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Cost-Effective Flash MCU with EEPROM

In Circuit Programming

TheꢀprovisionꢀofꢀFlashꢀtypeꢀProgramꢀMemoryꢀprovidesꢀtheꢀuserꢀwithꢀaꢀmeansꢀofꢀconvenientꢀandꢀeasyꢀ

upgradesꢀandꢀmodiﬁcationsꢀtoꢀtheirꢀprogramsꢀonꢀtheꢀsameꢀdevice.ꢀAsꢀanꢀadditionalꢀconvenience,ꢀ

Holtekꢀhasꢀprovidedꢀaꢀmeansꢀofꢀprogrammingꢀtheꢀmicrocontrollerꢀin-circuitꢀusingꢀaꢀ4-pinꢀinterface.ꢀ

Thisꢀprovidesꢀmanufacturersꢀwithꢀtheꢀpossibilityꢀofꢀmanufacturingꢀtheirꢀcircuitꢀboardsꢀcompleteꢀwithꢀ

aꢀprogrammedꢀorꢀun-programmedꢀmicrocontroller,ꢀandꢀthenꢀprogrammingꢀorꢀupgradingꢀtheꢀprogramꢀ

atꢀaꢀlaterꢀstage.ꢀThisꢀenablesꢀproductꢀmanufacturersꢀtoꢀeasilyꢀkeepꢀtheirꢀmanufacturedꢀproductsꢀ

suppliedꢀwithꢀtheꢀlatestꢀprogramꢀreleasesꢀwithoutꢀremovalꢀandꢀre-insertionꢀofꢀtheꢀdevice.

MCU Programming Pins

Holtek Write Pins

Function

HT68F002/HT68F0025

HT68F003

ICPDA

ICPCK

VDD

PA0

PA7

Programming Serial Data

Programming Serial Clock

Power Supply

PA2

VDD

VSS

Ground

TheꢀProgramꢀMemoryꢀandꢀEEPROMꢀdataꢀmemoryꢀcanꢀbothꢀbeꢀprogrammedꢀseriallyꢀin-circuitꢀusingꢀ

thisꢀ4-wireꢀinterface.ꢀDataꢀisꢀdownloadedꢀandꢀuploadedꢀseriallyꢀonꢀaꢀsingleꢀpinꢀwithꢀanꢀadditionalꢀ

lineꢀforꢀtheꢀclock.ꢀTwoꢀadditionalꢀlinesꢀareꢀrequiredꢀforꢀtheꢀpowerꢀsupplyꢀandꢀground.ꢀTheꢀtechnicalꢀ

detailsꢀregardingꢀtheꢀin-circuitꢀprogrammingꢀofꢀtheꢀdeviceꢀareꢀbeyondꢀtheꢀscopeꢀofꢀthisꢀdocumentꢀ

andꢀwillꢀbeꢀsuppliedꢀinꢀsupplementaryꢀliterature.

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HT68F003

Note:ꢀ*ꢀmayꢀbeꢀresistorꢀorꢀcapacitor.ꢀTheꢀresistanceꢀofꢀ*ꢀmustꢀbeꢀgreaterꢀthanꢀ1kꢀorꢀtheꢀcapacitanceꢀ

ofꢀ*ꢀmustꢀbeꢀlessꢀthanꢀ1nF.

Rev. 1.41

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Cost-Effective Flash MCU with EEPROM

On-Chip Debug Support – OCDS

ThereꢀisꢀanꢀEVꢀchipꢀwhichꢀisꢀusedꢀtoꢀemulateꢀtheꢀHT68F00xꢀdeviceꢀseries.ꢀThisꢀEVꢀchipꢀdeviceꢀ

alsoꢀprovidesꢀanꢀ"On-ChipꢀDebug"ꢀfunctionꢀtoꢀdebugꢀtheꢀdeviceꢀduringꢀtheꢀdevelopmentꢀprocess.ꢀ

TheꢀEVꢀchipꢀandꢀtheꢀactualꢀMCUꢀdevicesꢀareꢀalmostꢀfunctionallyꢀcompatibleꢀexceptꢀforꢀtheꢀ"On-

ChipꢀDebug"ꢀfunction.ꢀUsersꢀcanꢀuseꢀtheꢀEVꢀchipꢀdeviceꢀtoꢀemulateꢀtheꢀrealꢀchipꢀdeviceꢀbehaviorꢀ

byꢀconnectingꢀtheꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀtoꢀtheꢀHoltekꢀHT-IDEꢀdevelopmentꢀtools.ꢀTheꢀ

OCDSDAꢀpinꢀisꢀtheꢀOCDSꢀData/Addressꢀinput/outputꢀpinꢀwhileꢀtheꢀOCDSCKꢀpinꢀisꢀtheꢀOCDSꢀ

clockꢀinputꢀpin.ꢀWhenꢀusersꢀuseꢀtheꢀEVꢀchipꢀforꢀdebugging,ꢀotherꢀfunctionsꢀwhichꢀareꢀsharedꢀwithꢀ

theꢀOCDSDAꢀandꢀOCDSCKꢀpinsꢀinꢀtheꢀactualꢀMCUꢀdeviceꢀwillꢀhaveꢀnoꢀeffectꢀinꢀtheꢀEVꢀchip.ꢀ

However,ꢀtheꢀtwoꢀOCDSꢀpinsꢀwhichꢀareꢀpin-sharedꢀwithꢀtheꢀICPꢀprogrammingꢀpinsꢀareꢀstillꢀusedꢀasꢀ

theꢀFlashꢀMemoryꢀprogrammingꢀpinsꢀforꢀICP.ꢀForꢀaꢀmoreꢀdetailedꢀOCDSꢀdescription,ꢀreferꢀtoꢀtheꢀ

correspondingꢀdocumentꢀnamedꢀ"Holtekꢀe-Linkꢀforꢀ8-bitꢀMCUꢀOCDSꢀUser’sꢀGuide".

Holtek e-Link Pins

OCDSDA

OCDSCK

VDD

EV Chip Pins

OCDSDA

OCDSCK

VDD

Pin Description

On-chip Debug Support Data/Address input/output

On-chip Debug Support Clock input

Power Supply

GND

VSS

Ground

Rev. 1.41

20

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Cost-Effective Flash MCU with EEPROM

RAM Data Memory

TheꢀDataꢀMemoryꢀisꢀaꢀvolatileꢀareaꢀofꢀ8-bitꢀwideꢀRAMꢀinternalꢀmemoryꢀandꢀisꢀtheꢀlocationꢀwhereꢀ

temporaryꢀinformationꢀisꢀstored.

Structure

Dividedꢀintoꢀtwoꢀsections,ꢀtheꢀﬁrstꢀofꢀtheseꢀisꢀanꢀareaꢀofꢀRAM,ꢀknownꢀasꢀtheꢀSpecialꢀFunctionꢀDataꢀ

Memory.ꢀHereꢀareꢀlocatedꢀregistersꢀwhichꢀareꢀnecessaryꢀforꢀcorrectꢀoperationꢀofꢀtheꢀdevice.ꢀManyꢀ

ofꢀtheseꢀregistersꢀcanꢀbeꢀreadꢀfromꢀandꢀwrittenꢀtoꢀdirectlyꢀunderꢀprogramꢀcontrol,ꢀhowever,ꢀsomeꢀ

remainꢀprotectedꢀfromꢀuserꢀmanipulation.ꢀTheꢀsecondꢀareaꢀofꢀDataꢀMemoryꢀisꢀknownꢀasꢀtheꢀGeneralꢀ

PurposeꢀDataꢀMemory,ꢀwhichꢀisꢀreservedꢀforꢀgeneralꢀpurposeꢀuse.ꢀAllꢀlocationsꢀwithinꢀthisꢀareaꢀareꢀ

readꢀandꢀwriteꢀaccessibleꢀunderꢀprogramꢀcontrol.

TheꢀoverallꢀDataꢀMemoryꢀisꢀsubdividedꢀintoꢀtwoꢀbanks.ꢀTheꢀSpecialꢀPurposeꢀDataꢀMemoryꢀregistersꢀ

areꢀaccessibleꢀinꢀallꢀbanks,ꢀwithꢀtheꢀexceptionꢀofꢀtheꢀEECꢀregisterꢀatꢀaddressꢀ40H,ꢀwhichꢀisꢀonlyꢀ

accessibleꢀinꢀBankꢀ1.ꢀSwitchingꢀbetweenꢀtheꢀdifferentꢀDataꢀMemoryꢀbanksꢀisꢀachievedꢀbyꢀsettingꢀtheꢀ

BankꢀPointerꢀtoꢀtheꢀcorrectꢀvalue.ꢀTheꢀstartꢀaddressꢀofꢀtheꢀDataꢀMemoryꢀforꢀallꢀdevicesꢀisꢀtheꢀaddressꢀ

00H.

General Purpose Data Memory

Thereꢀisꢀ64×8ꢀbytesꢀofꢀgeneralꢀpurposeꢀdataꢀmemoryꢀwhichꢀareꢀarrangedꢀinꢀ40H~7FHꢀofꢀBankꢀ0ꢀandꢀ

Bank1.ꢀAllꢀmicrocontrollerꢀprogramsꢀrequireꢀanꢀareaꢀofꢀread/writeꢀmemoryꢀwhereꢀtemporaryꢀdataꢀ

canꢀbeꢀstoredꢀandꢀretrievedꢀforꢀuseꢀlater.ꢀItꢀisꢀthisꢀareaꢀofꢀRAMꢀmemoryꢀthatꢀisꢀknownꢀasꢀGeneralꢀ

PurposeꢀDataꢀMemory.ꢀThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀfullyꢀaccessibleꢀbyꢀtheꢀuserꢀprogramingꢀforꢀ

bothꢀreadingꢀandꢀwritingꢀoperations.ꢀByꢀusingꢀtheꢀbitꢀoperationꢀinstructionsꢀindividualꢀbitsꢀcanꢀbeꢀsetꢀ

orꢀresetꢀunderꢀprogramꢀcontrolꢀgivingꢀtheꢀuserꢀaꢀlargeꢀrangeꢀofꢀﬂexibilityꢀforꢀbitꢀmanipulationꢀinꢀtheꢀ

DataꢀMemory.

Special Purpose Data Memory

ThisꢀareaꢀofꢀDataꢀMemoryꢀisꢀwhereꢀregisters,ꢀnecessaryꢀforꢀtheꢀcorrectꢀoperationꢀofꢀtheꢀ

microcontroller,ꢀareꢀstored.ꢀMostꢀofꢀtheꢀregistersꢀareꢀbothꢀreadableꢀandꢀwriteableꢀbutꢀsomeꢀareꢀ

protectedꢀandꢀareꢀreadableꢀonly,ꢀtheꢀdetailsꢀofꢀwhichꢀareꢀlocatedꢀunderꢀtheꢀrelevantꢀSpecialꢀFunctionꢀ

Registerꢀsection.ꢀNoteꢀthatꢀforꢀlocationsꢀthatꢀareꢀunused,ꢀanyꢀreadꢀinstructionꢀtoꢀtheseꢀaddressesꢀwillꢀ

returnꢀtheꢀvalueꢀ"00H".

Device

Capacity

Bank 0

Bank 1

HT68F002

HT68F0025

HT68F003

64×8

40H~7FH

40H EEC register only

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Bank0 & Bank1

Unused

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

IAR0

MP0

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

Unused

IAR1

Unused

MP1

BP

Unused

ACC

RSTC

PCL

PASR

TBLP

TBLH

Unused

STATUS

SMOD

LVDC

INTEG

INTC0

INTC1

Unused

MFI0

Unused

STM0C0

STM0C1

STM0DL

STM0DH

STM0AL

STM0AH

2EH

~

3FH

Unused

PA

PAC

PAPU

PAWU

IFS0

WDTC

Unused

TBC

SMOD1

Unused

EEA

EED

: Unused, read as “00”

HT68F002/HT68F0025 Special Purpose Data Memory Structure

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Bank0 & Bank1

Unused

RSTC

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

IAR0

MP0

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

IAR1

MP1

BP

ACC

PCL

PASR

TBLP

TBLH

Unused

STATUS

SMOD

LVDC

INTEG

INTC0

INTC1

Unused

MFI0

PBSR

STM0C0

STM0C1

STM0DL

STM0DH

STM0AL

STM0AH

Unused

PB

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

PBC

PBPU

MFI1

PTM1C0

PTM1C1

PTM1DL

PTM1DH

PTM1AL

PTM1AH

PTM1RPL

PTM1RPH

Unused

PA

PAC

PAPU

PAWU

IFS0

38H

39H

3AH

~

WDTC

Unused

TBC

Unused

3FH

SMOD1

Unused

EEA

EED

: Unused, read as “00”

HT68F003 Special Purpose Data Memory Structure

40H

EEC

General

Purpose

Data

Memory

Unused

7FH

HT68F002/HT68F0025/HT68F003 General Purpose Data Memory

Rev. 1.41

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Cost-Effective Flash MCU with EEPROM

Special Function Register Description

MostꢀofꢀtheꢀSpecialꢀFunctionꢀRegisterꢀdetailsꢀwillꢀbeꢀdescribedꢀinꢀtheꢀrelevantꢀfunctionalꢀsection,ꢀ

howeverꢀseveralꢀregistersꢀrequireꢀaꢀseparateꢀdescriptionꢀinꢀthisꢀsection.

Indirect Addressing Registers – IAR0, IAR1

TheꢀIndirectꢀAddressingꢀRegisters,ꢀIAR0ꢀandꢀIAR1,ꢀalthoughꢀhavingꢀtheirꢀlocationsꢀinꢀnormalꢀRAMꢀ

registerꢀspace,ꢀdoꢀnotꢀactuallyꢀphysicallyꢀexistꢀasꢀnormalꢀregisters.ꢀTheꢀmethodꢀofꢀindirectꢀaddressingꢀ

forꢀRAMꢀdataꢀmanipulationꢀusesꢀtheseꢀIndirectꢀAddressingꢀRegistersꢀandꢀMemoryꢀPointers,ꢀinꢀ

contrastꢀtoꢀdirectꢀmemoryꢀaddressing,ꢀwhereꢀtheꢀactualꢀmemoryꢀaddressꢀisꢀspeciﬁed.ꢀActionsꢀonꢀtheꢀ

IAR0ꢀandꢀIAR1ꢀregistersꢀwillꢀresultꢀinꢀnoꢀactualꢀreadꢀorꢀwriteꢀoperationꢀtoꢀtheseꢀregistersꢀbutꢀratherꢀ

toꢀtheꢀmemoryꢀlocationꢀspeciﬁedꢀbyꢀtheirꢀcorrespondingꢀMemoryꢀPointers,ꢀMP0ꢀorꢀMP1.ꢀActingꢀasꢀaꢀ

pair,ꢀIAR0ꢀandꢀMP0ꢀcanꢀtogetherꢀaccessꢀdataꢀfromꢀBankꢀ0ꢀwhileꢀtheꢀIAR1ꢀandꢀMP1ꢀregisterꢀpairꢀcanꢀ

accessꢀdataꢀfromꢀanyꢀbank.ꢀAsꢀtheꢀIndirectꢀAddressingꢀRegistersꢀareꢀnotꢀphysicallyꢀimplemented,ꢀ

readingꢀtheꢀIndirectꢀAddressingꢀRegistersꢀindirectlyꢀwillꢀreturnꢀaꢀresultꢀofꢀ"00H"ꢀandꢀwritingꢀtoꢀtheꢀ

registersꢀindirectlyꢀwillꢀresultꢀinꢀnoꢀoperation.

Memory Pointers – MP0, MP1

TwoꢀMemoryꢀPointers,ꢀknownꢀasꢀMP0ꢀandꢀMP1ꢀareꢀprovided.ꢀTheseꢀMemoryꢀPointersꢀareꢀ

physicallyꢀimplementedꢀinꢀtheꢀDataꢀMemoryꢀandꢀcanꢀbeꢀmanipulatedꢀinꢀtheꢀsameꢀwayꢀasꢀnormalꢀ

registersꢀprovidingꢀaꢀconvenientꢀwayꢀwithꢀwhichꢀtoꢀaddressꢀandꢀtrackꢀdata.ꢀWhenꢀanyꢀoperationꢀtoꢀ

theꢀrelevantꢀIndirectꢀAddressingꢀRegistersꢀisꢀcarriedꢀout,ꢀtheꢀactualꢀaddressꢀthatꢀtheꢀmicrocontrollerꢀ

isꢀdirectedꢀtoꢀisꢀtheꢀaddressꢀspeciﬁedꢀbyꢀtheꢀrelatedꢀMemoryꢀPointer.ꢀMP0,ꢀtogetherꢀwithꢀIndirectꢀ

AddressingꢀRegister,ꢀIAR0,ꢀareꢀusedꢀtoꢀaccessꢀdataꢀfromꢀBankꢀ0,ꢀwhileꢀMP1ꢀandꢀIAR1ꢀareꢀusedꢀtoꢀ

accessꢀdataꢀfromꢀallꢀbanksꢀaccordingꢀtoꢀBPꢀregister.ꢀDirectꢀAddressingꢀcanꢀonlyꢀbeꢀusedꢀwithꢀBankꢀ0,ꢀ

allꢀotherꢀBanksꢀmustꢀbeꢀaddressedꢀindirectlyꢀusingꢀMP1ꢀandꢀIAR1.

TheꢀfollowingꢀexampleꢀshowsꢀhowꢀtoꢀclearꢀaꢀsectionꢀofꢀfourꢀDataꢀMemoryꢀlocationsꢀalreadyꢀdeﬁnedꢀ

asꢀlocationsꢀadres1ꢀtoꢀadres4.

Indirect Addressing Program Example

data .section ´data´

adres1 db ?

adres2 db ?

adres3 db ?

adres4 db ?

block

db ?

code .section at 0 ´code´

org 00h

start:

mov a,04h

; setup size of block

mov block,a

mov a,offset adres1 ; Accumulator loaded with ﬁrst RAM address

mov mp0,a

; setup memory pointer with ﬁrst RAM address

loop:

clr IAR0

inc mp0

; clear the data at address deﬁned by mp0

; increment memory pointer

sdz block

jmp loop

; check if last memory location has been cleared

continue:

Theꢀimportantꢀpointꢀtoꢀnoteꢀhereꢀisꢀthatꢀinꢀtheꢀexampleꢀshownꢀabove,ꢀnoꢀreferenceꢀisꢀmadeꢀtoꢀspeciﬁcꢀ

DataꢀMemoryꢀaddresses.

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Bank Pointer – BP

Forꢀthisꢀseriesꢀofꢀdevices,ꢀtheꢀDataꢀMemoryꢀisꢀdividedꢀintoꢀtwoꢀbanks,ꢀBank0ꢀandꢀBank1.ꢀSelectingꢀ

theꢀrequiredꢀDataꢀMemoryꢀareaꢀisꢀachievedꢀusingꢀtheꢀBankꢀPointer.ꢀBitꢀ0ꢀofꢀtheꢀBankꢀPointerꢀisꢀusedꢀ

toꢀselectꢀDataꢀMemoryꢀBanksꢀ0~1.ꢀ

TheꢀDataꢀMemoryꢀisꢀinitialisedꢀtoꢀBankꢀ0ꢀafterꢀaꢀreset,ꢀexceptꢀforꢀaꢀWDTꢀtime-outꢀresetꢀinꢀtheꢀPowerꢀ

DownꢀMode,ꢀinꢀwhichꢀcase,ꢀtheꢀDataꢀMemoryꢀbankꢀremainsꢀunaffected.ꢀItꢀshouldꢀbeꢀnotedꢀthatꢀtheꢀ

SpecialꢀFunctionꢀDataꢀMemoryꢀisꢀnotꢀaffectedꢀbyꢀtheꢀbankꢀselection,ꢀwhichꢀmeansꢀthatꢀtheꢀSpecialꢀ

FunctionꢀRegistersꢀcanꢀbeꢀaccessedꢀfromꢀwithinꢀanyꢀbank.ꢀDirectlyꢀaddressingꢀtheꢀDataꢀMemoryꢀ

willꢀalwaysꢀresultꢀinꢀBankꢀ0ꢀbeingꢀaccessedꢀirrespectiveꢀofꢀtheꢀvalueꢀofꢀtheꢀBankꢀPointer.ꢀAccessingꢀ

dataꢀfromꢀBank1ꢀmustꢀbeꢀimplementedꢀusingꢀIndirectꢀAddressing.ꢀ

BP Register

Bit

Name

R/W

7

6

5

4

3

2

1

0

DMBP0

R/W

0

—

POR

Bitꢀ7ꢀ~ꢀ1ꢀ

Bitꢀ0

Unimplemented,ꢀreadꢀasꢀ"0"

DMBP0:ꢀSelectꢀDataꢀMemoryꢀBanks

0:ꢀBankꢀ0

1:ꢀBankꢀ1

Accumulator – ACC

TheꢀAccumulatorꢀisꢀcentralꢀtoꢀtheꢀoperationꢀofꢀanyꢀmicrocontrollerꢀandꢀisꢀcloselyꢀrelatedꢀwithꢀ

operationsꢀcarriedꢀoutꢀbyꢀtheꢀALU.ꢀTheꢀAccumulatorꢀisꢀtheꢀplaceꢀwhereꢀallꢀintermediateꢀresultsꢀ

fromꢀtheꢀALUꢀareꢀstored.ꢀWithoutꢀtheꢀAccumulatorꢀitꢀwouldꢀbeꢀnecessaryꢀtoꢀwriteꢀtheꢀresultꢀofꢀ

eachꢀcalculationꢀorꢀlogicalꢀoperationꢀsuchꢀasꢀaddition,ꢀsubtraction,ꢀshift,ꢀetc.,ꢀtoꢀtheꢀDataꢀMemoryꢀ

resultingꢀinꢀhigherꢀprogrammingꢀandꢀtimingꢀoverheads.ꢀDataꢀtransferꢀoperationsꢀusuallyꢀinvolveꢀ

theꢀtemporaryꢀstorageꢀfunctionꢀofꢀtheꢀAccumulator;ꢀforꢀexample,ꢀwhenꢀtransferringꢀdataꢀbetweenꢀ

oneꢀuser-definedꢀregisterꢀandꢀanother,ꢀitꢀisꢀnecessaryꢀtoꢀdoꢀthisꢀbyꢀpassingꢀtheꢀdataꢀthroughꢀtheꢀ

Accumulatorꢀasꢀnoꢀdirectꢀtransferꢀbetweenꢀtwoꢀregistersꢀisꢀpermitted.

Program Counter Low Register – PCL

Toꢀprovideꢀadditionalꢀprogramꢀcontrolꢀfunctions,ꢀtheꢀlowꢀbyteꢀofꢀtheꢀProgramꢀCounterꢀisꢀmadeꢀ

accessibleꢀtoꢀprogrammersꢀbyꢀlocatingꢀitꢀwithinꢀtheꢀSpecialꢀPurposeꢀareaꢀofꢀtheꢀDataꢀMemory.ꢀByꢀ

manipulatingꢀthisꢀregister,ꢀdirectꢀjumpsꢀtoꢀotherꢀprogramꢀlocationsꢀareꢀeasilyꢀimplemented.ꢀLoadingꢀ

aꢀvalueꢀdirectlyꢀintoꢀthisꢀPCLꢀregisterꢀwillꢀcauseꢀaꢀjumpꢀtoꢀtheꢀspeciﬁedꢀProgramꢀMemoryꢀlocation,ꢀ

however,ꢀasꢀtheꢀregisterꢀisꢀonlyꢀ8-bitꢀwide,ꢀonlyꢀjumpsꢀwithinꢀtheꢀcurrentꢀProgramꢀMemoryꢀpageꢀareꢀ

permitted.ꢀWhenꢀsuchꢀoperationsꢀareꢀused,ꢀnoteꢀthatꢀaꢀdummyꢀcycleꢀwillꢀbeꢀinserted.

Look-up Table Registers – TBLP, TBLH

Theseꢀtwoꢀspecialꢀfunctionꢀregistersꢀareꢀusedꢀtoꢀcontrolꢀoperationꢀofꢀtheꢀlook-upꢀtableꢀwhichꢀisꢀ

storedꢀinꢀtheꢀProgramꢀMemory.ꢀTBLPꢀisꢀtheꢀtableꢀpointerꢀandꢀindicateꢀtheꢀlocationꢀwhereꢀtheꢀtableꢀ

dataꢀisꢀlocated.ꢀItsꢀvalueꢀmustꢀbeꢀsetupꢀbeforeꢀanyꢀtableꢀreadꢀcommandsꢀareꢀexecuted.ꢀItsꢀvalueꢀ

canꢀbeꢀchanged,ꢀforꢀexampleꢀusingꢀtheꢀ"INC"ꢀorꢀ"DEC"ꢀinstructions,ꢀallowingꢀforꢀeasyꢀtableꢀdataꢀ

pointingꢀandꢀreading.ꢀTBLHꢀisꢀtheꢀlocationꢀwhereꢀtheꢀhighꢀorderꢀbyteꢀofꢀtheꢀtableꢀdataꢀisꢀstoredꢀ

afterꢀaꢀtableꢀreadꢀdataꢀinstructionꢀhasꢀbeenꢀexecuted.ꢀNoteꢀthatꢀtheꢀlowerꢀorderꢀtableꢀdataꢀbyteꢀisꢀ

transferredꢀtoꢀaꢀuserꢀdeﬁnedꢀlocation.

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Status Register – STATUS

Thisꢀ8-bitꢀregisterꢀcontainsꢀtheꢀzeroꢀﬂagꢀ(Z),ꢀcarryꢀﬂagꢀ(C),ꢀauxiliaryꢀcarryꢀﬂagꢀ(AC),ꢀoverﬂowꢀﬂagꢀ

(OV),ꢀpowerꢀdownꢀﬂagꢀ(PDF),ꢀandꢀwatchdogꢀtime-outꢀﬂagꢀ(TO).ꢀTheseꢀarithmetic/logicalꢀoperationꢀ

andꢀsystemꢀmanagementꢀﬂagsꢀareꢀusedꢀtoꢀrecordꢀtheꢀstatusꢀandꢀoperationꢀofꢀtheꢀmicrocontroller.ꢀ

WithꢀtheꢀexceptionꢀofꢀtheꢀTOꢀandꢀPDFꢀﬂags,ꢀbitsꢀinꢀtheꢀstatusꢀregisterꢀcanꢀbeꢀalteredꢀbyꢀinstructionsꢀ

likeꢀmostꢀotherꢀregisters.ꢀAnyꢀdataꢀwrittenꢀintoꢀtheꢀstatusꢀregisterꢀwillꢀnotꢀchangeꢀtheꢀTOꢀorꢀPDFꢀﬂag.ꢀ

Inꢀaddition,ꢀoperationsꢀrelatedꢀtoꢀtheꢀstatusꢀregisterꢀmayꢀgiveꢀdifferentꢀresultsꢀdueꢀtoꢀtheꢀdifferentꢀ

instructionꢀoperations.ꢀTheꢀTOꢀﬂagꢀcanꢀbeꢀaffectedꢀonlyꢀbyꢀaꢀsystemꢀpower-up,ꢀaꢀWDTꢀtime-outꢀorꢀ

byꢀexecutingꢀtheꢀ"CLRꢀWDT"ꢀorꢀ"HALT"ꢀinstruction.ꢀTheꢀPDFꢀﬂagꢀisꢀaffectedꢀonlyꢀbyꢀexecutingꢀ

theꢀ"HALT"ꢀorꢀ"CLRꢀWDT"ꢀinstructionꢀorꢀduringꢀaꢀsystemꢀpower-up.

TheꢀZ,ꢀOV,ꢀACꢀandꢀCꢀﬂagsꢀgenerallyꢀreﬂectꢀtheꢀstatusꢀofꢀtheꢀlatestꢀoperations.

•ꢀ Cꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀnotꢀtakeꢀ

placeꢀduringꢀaꢀsubtractionꢀoperation;ꢀotherwiseꢀCꢀisꢀcleared.ꢀCꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀ

carryꢀinstruction.

•ꢀ ACꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀfromꢀ

theꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction;ꢀotherwiseꢀACꢀisꢀcleared.ꢀ

•ꢀ Zꢀisꢀsetꢀifꢀtheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero;ꢀotherwiseꢀZꢀisꢀcleared.

•ꢀ OVꢀisꢀsetꢀifꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ

highest-orderꢀbit,ꢀorꢀviceꢀversa;ꢀotherwiseꢀOVꢀisꢀcleared.ꢀ

•ꢀ PDFꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ"CLRꢀWDT"ꢀinstruction.ꢀPDFꢀisꢀsetꢀbyꢀ

executingꢀtheꢀ"HALT"ꢀinstruction.

•ꢀ TOꢀisꢀclearedꢀbyꢀaꢀsystemꢀpower-upꢀorꢀexecutingꢀtheꢀ"CLRꢀWDT"ꢀorꢀ"HALT"ꢀinstruction.ꢀTOꢀisꢀ

setꢀbyꢀaꢀWDTꢀtime-out.

Inꢀaddition,ꢀonꢀenteringꢀanꢀinterruptꢀsequenceꢀorꢀexecutingꢀaꢀsubroutineꢀcall,ꢀtheꢀstatusꢀregisterꢀwillꢀ

notꢀbeꢀpushedꢀontoꢀtheꢀstackꢀautomatically.ꢀIfꢀtheꢀcontentsꢀofꢀtheꢀstatusꢀregistersꢀareꢀimportantꢀandꢀifꢀ

theꢀsubroutineꢀcanꢀcorruptꢀtheꢀstatusꢀregister,ꢀprecautionsꢀmustꢀbeꢀtakenꢀtoꢀcorrectlyꢀsaveꢀit.

Rev. 1.41

26

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

STATUS Register

Bit

Name

R/W

7

6

5

TO

R

4

PDF

R

3

OV

R/W

×

2

Z

1

AC

R/W

×

0

—

C

R/W

×

POR

0

×

"×" unknown

Bitꢀ7~6ꢀ

Bitꢀ5

Unimplemented,ꢀreadꢀasꢀ"0"

TO:ꢀWatchdogꢀTime-Outꢀﬂag

0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ"CLRꢀWDT"ꢀorꢀ"HALT"ꢀinstruction

1:ꢀAꢀwatchdogꢀtime-outꢀoccurred.

Bitꢀ4

Bitꢀ3

PDF:ꢀPowerꢀdownꢀﬂag

0:ꢀAfterꢀpowerꢀupꢀorꢀexecutingꢀtheꢀ"CLRꢀWDT"ꢀinstruction

1:ꢀByꢀexecutingꢀtheꢀ"HALT"ꢀinstruction

OV:ꢀOverﬂowꢀﬂag

0:ꢀnoꢀoverﬂow

1:ꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀintoꢀtheꢀhighest-orderꢀbitꢀbutꢀnotꢀaꢀcarryꢀoutꢀofꢀtheꢀ

highest-orderꢀbitꢀorꢀviceꢀversa.

Bitꢀ2

Bitꢀ1

Z:ꢀZeroꢀﬂag

0:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀnotꢀzero

1:ꢀTheꢀresultꢀofꢀanꢀarithmeticꢀorꢀlogicalꢀoperationꢀisꢀzero

AC:ꢀAuxiliaryꢀﬂag

0:ꢀnoꢀauxiliaryꢀcarry

1:ꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀoutꢀofꢀtheꢀlowꢀnibblesꢀinꢀaddition,ꢀorꢀnoꢀborrowꢀ

fromꢀtheꢀhighꢀnibbleꢀintoꢀtheꢀlowꢀnibbleꢀinꢀsubtraction

Bitꢀ0

C:ꢀCarryꢀﬂag

0:ꢀnoꢀcarry-out

1:ꢀanꢀoperationꢀresultsꢀinꢀaꢀcarryꢀduringꢀanꢀadditionꢀoperationꢀorꢀifꢀaꢀborrowꢀdoesꢀnotꢀ

takeꢀplaceꢀduringꢀaꢀsubtractionꢀoperation

Cꢀisꢀalsoꢀaffectedꢀbyꢀaꢀrotateꢀthroughꢀcarryꢀinstruction.

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Cost-Effective Flash MCU with EEPROM

EEPROM Data Memory

TheseꢀdevicesꢀcontainꢀanꢀareaꢀofꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀEEPROM,ꢀwhichꢀstandsꢀforꢀ

ElectricallyꢀErasableꢀProgrammableꢀReadꢀOnlyꢀMemory,ꢀisꢀbyꢀitsꢀnatureꢀaꢀnon-volatileꢀformꢀofꢀ

memory,ꢀwithꢀdataꢀretentionꢀevenꢀwhenꢀitsꢀpowerꢀsupplyꢀisꢀremoved.ꢀByꢀincorporatingꢀthisꢀkindꢀ

ofꢀdataꢀmemory,ꢀaꢀwholeꢀnewꢀhostꢀofꢀapplicationꢀpossibilitiesꢀareꢀmadeꢀavailableꢀtoꢀtheꢀdesigner.ꢀ

TheꢀavailabilityꢀofꢀEEPROMꢀstorageꢀallowsꢀinformationꢀsuchꢀasꢀproductꢀidentiﬁcationꢀnumbers,ꢀ

calibrationꢀvalues,ꢀspeciﬁcꢀuserꢀdata,ꢀsystemꢀsetupꢀdataꢀorꢀotherꢀproductꢀinformationꢀtoꢀbeꢀstoredꢀ

directlyꢀwithinꢀtheꢀproductꢀmicrocontroller.ꢀTheꢀprocessꢀofꢀreadingꢀandꢀwritingꢀdataꢀtoꢀtheꢀEEPROMꢀ

memoryꢀhasꢀbeenꢀreducedꢀtoꢀaꢀveryꢀtrivialꢀaffair.

EEPROM Data Memory Structure

TheꢀEEPROMꢀDataꢀMemoryꢀcapacityꢀisꢀ32×8ꢀbitsꢀforꢀthisꢀseriesꢀofꢀdevices.ꢀUnlikeꢀtheꢀProgramꢀ

MemoryꢀandꢀRAMꢀDataꢀMemory,ꢀtheꢀEEPROMꢀDataꢀMemoryꢀisꢀnotꢀdirectlyꢀmappedꢀandꢀisꢀ

thereforeꢀnotꢀdirectlyꢀaccessibleꢀinꢀtheꢀsameꢀwayꢀasꢀtheꢀotherꢀtypesꢀofꢀmemory.ꢀReadꢀandꢀWriteꢀ

operationsꢀtoꢀtheꢀEEPROMꢀareꢀcarriedꢀoutꢀinꢀsingleꢀbyteꢀoperationsꢀusingꢀoneꢀaddressꢀregisterꢀandꢀ

oneꢀdataꢀregisterꢀandꢀaꢀsingleꢀcontrolꢀregisterꢀinꢀBankꢀ1.

EEPROM Registers

ThreeꢀregistersꢀcontrolꢀtheꢀoverallꢀoperationꢀofꢀtheꢀinternalꢀEEPROMꢀDataꢀMemory.ꢀTheseꢀareꢀtheꢀ

addressꢀregisters,ꢀEEA,ꢀtheꢀdataꢀregister,ꢀEEDꢀandꢀaꢀsingleꢀcontrolꢀregister,ꢀEEC.ꢀAsꢀbothꢀtheꢀEEAꢀ

andꢀEEDꢀregistersꢀareꢀlocatedꢀinꢀBankꢀ0,ꢀtheyꢀcanꢀbeꢀdirectlyꢀaccessedꢀinꢀtheꢀsameꢀwayꢀasꢀanyꢀotherꢀ

SpecialꢀFunctionꢀRegister.ꢀTheꢀEECꢀregisterꢀhowever,ꢀbeingꢀlocatedꢀinꢀBank1,ꢀcannotꢀbeꢀdirectlyꢀ

addressedꢀdirectlyꢀandꢀcanꢀonlyꢀbeꢀreadꢀfromꢀorꢀwrittenꢀtoꢀindirectlyꢀusingꢀtheꢀMP1ꢀMemoryꢀPointerꢀ

andꢀIndirectꢀAddressingꢀRegister,ꢀIAR1.ꢀBecauseꢀtheꢀEECꢀcontrolꢀregisterꢀisꢀlocatedꢀatꢀaddressꢀ40Hꢀ

inꢀBankꢀ1,ꢀtheꢀMP1ꢀMemoryꢀPointerꢀmustꢀﬁrstꢀbeꢀsetꢀtoꢀtheꢀvalueꢀ40HꢀandꢀtheꢀBankꢀPointerꢀregister,ꢀ

BP,ꢀsetꢀtoꢀtheꢀvalue,ꢀ01H,ꢀbeforeꢀanyꢀoperationsꢀonꢀtheꢀEECꢀregisterꢀareꢀexecuted.

EEPROM Control Registers List

Bit

Register

Name

7

6

5

4

3

D3

2

1

D1

0

EEA

EED

EEC

—

D7

—

D6

—

D5

—

D4

—

D2

WR

D0

RD

D3

D1

WREN

RDEN

EEA Register

Bit

Name

R/W

7

6

5

4

D4

R/W

0

3

D3

R/W

0

2

D2

R/W

0

1

D1

R/W

0

D0

R/W

0

—

POR

Bitꢀ7ꢀ~ꢀ5ꢀ

Bitꢀ4ꢀ~ꢀ0ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

DataꢀEEPROMꢀaddress

DataꢀEEPROMꢀaddressꢀbitꢀ4ꢀ~ꢀbitꢀ0

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Cost-Effective Flash MCU with EEPROM

EED Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

2

D2

R/W

0

1

D1

R/W

0

D0

R/W

0

POR

Bitꢀ7ꢀ~ꢀ0ꢀ

DataꢀEEPROMꢀdata

DataꢀEEPROMꢀdataꢀbitꢀ7ꢀ~ꢀbitꢀ0

EEC Register

Bit

Name

R/W

7

6

5

4

3

WREN

R/W

0

2

WR

R/W

0

1

RDEN

R/W

0

RD

R/W

0

—

POR

Bitꢀ7ꢀ~ꢀ4ꢀ

Bitꢀ3

Unimplemented,ꢀreadꢀasꢀ"0"

WREN:ꢀDataꢀEEPROMꢀWriteꢀEnable

0:ꢀDisable

1:ꢀEnable

ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀEnableꢀBitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀDataꢀ

EEPROMꢀwriteꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀinhibitꢀDataꢀ

EEPROMꢀwriteꢀoperations.

Bitꢀ2

WR:ꢀEEPROMꢀWriteꢀControl

0:ꢀWriteꢀcycleꢀhasꢀﬁnished

1:ꢀActivateꢀaꢀwriteꢀcycle

ThisꢀisꢀtheꢀDataꢀEEPROMꢀWriteꢀControlꢀBitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ

programꢀwillꢀactivateꢀaꢀwriteꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀzeroꢀbyꢀtheꢀ

hardwareꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀﬁnished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ

theꢀWRENꢀhasꢀnotꢀﬁrstꢀbeenꢀsetꢀhigh.

Bitꢀ1

Bitꢀ0

RDEN:ꢀDataꢀEEPROMꢀReadꢀEnable

0:ꢀDisable

1:ꢀEnable

ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀEnableꢀBitꢀwhichꢀmustꢀbeꢀsetꢀhighꢀbeforeꢀDataꢀ

EEPROMꢀreadꢀoperationsꢀareꢀcarriedꢀout.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀinhibitꢀDataꢀ

EEPROMꢀreadꢀoperations.

RD:ꢀEEPROMꢀReadꢀControl

0:ꢀReadꢀcycleꢀhasꢀﬁnished

1:ꢀActivateꢀaꢀreadꢀcycle

ThisꢀisꢀtheꢀDataꢀEEPROMꢀReadꢀControlꢀBitꢀandꢀwhenꢀsetꢀhighꢀbyꢀtheꢀapplicationꢀ

programꢀwillꢀactivateꢀaꢀreadꢀcycle.ꢀThisꢀbitꢀwillꢀbeꢀautomaticallyꢀresetꢀtoꢀzeroꢀbyꢀtheꢀ

hardwareꢀafterꢀtheꢀreadꢀcycleꢀhasꢀﬁnished.ꢀSettingꢀthisꢀbitꢀhighꢀwillꢀhaveꢀnoꢀeffectꢀifꢀ

theꢀRDENꢀhasꢀnotꢀﬁrstꢀbeenꢀsetꢀhigh.

Note:ꢀTheꢀWREN,ꢀWR,ꢀRDENꢀandꢀRDꢀcanꢀnotꢀbeꢀsetꢀtoꢀ"1"ꢀatꢀtheꢀsameꢀtimeꢀinꢀoneꢀinstruction.ꢀTheꢀ

WRꢀandꢀRDꢀcanꢀnotꢀbeꢀsetꢀtoꢀ"1"ꢀatꢀtheꢀsameꢀtime.

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Cost-Effective Flash MCU with EEPROM

Reading Data from the EEPROM

ToꢀreadꢀdataꢀfromꢀtheꢀEEPROM,ꢀtheꢀreadꢀenableꢀbit,ꢀRDEN,ꢀinꢀtheꢀEECꢀregisterꢀmustꢀﬁrstꢀbeꢀsetꢀ

highꢀtoꢀenableꢀtheꢀreadꢀfunction.ꢀTheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀreadꢀmustꢀthenꢀbeꢀplacedꢀ

inꢀtheꢀEEAꢀregister.ꢀIfꢀtheꢀRDꢀbitꢀinꢀtheꢀEECꢀregisterꢀisꢀnowꢀsetꢀhigh,ꢀaꢀreadꢀcycleꢀwillꢀbeꢀinitiated.ꢀ

SettingꢀtheꢀRDꢀbitꢀhighꢀwillꢀnotꢀinitiateꢀaꢀreadꢀoperationꢀifꢀtheꢀRDENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀWhenꢀ

theꢀreadꢀcycleꢀterminates,ꢀtheꢀRDꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀzero,ꢀafterꢀwhichꢀtheꢀdataꢀcanꢀ

beꢀreadꢀfromꢀtheꢀEEDꢀregister.ꢀTheꢀdataꢀwillꢀremainꢀinꢀtheꢀEEDꢀregisterꢀuntilꢀanotherꢀreadꢀorꢀwriteꢀ

operationꢀisꢀexecuted.ꢀTheꢀapplicationꢀprogramꢀcanꢀpollꢀtheꢀRDꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀdataꢀisꢀ

validꢀforꢀreading.

Writing Data to the EEPROM

TheꢀEEPROMꢀaddressꢀofꢀtheꢀdataꢀtoꢀbeꢀwrittenꢀmustꢀﬁrstꢀbeꢀplacedꢀinꢀtheꢀEEAꢀregisterꢀandꢀtheꢀdataꢀ

placedꢀinꢀtheꢀEEDꢀregister.ꢀToꢀwriteꢀdataꢀtoꢀtheꢀEEPROM,ꢀtheꢀwriteꢀenableꢀbit,ꢀWREN,ꢀinꢀtheꢀEECꢀ

registerꢀmustꢀﬁrstꢀbeꢀsetꢀhighꢀtoꢀenableꢀtheꢀwriteꢀfunction.ꢀAfterꢀthis,ꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀ

mustꢀbeꢀimmediatelyꢀsetꢀhighꢀtoꢀinitiateꢀaꢀwriteꢀcycle.ꢀTheseꢀtwoꢀinstructionsꢀmustꢀbeꢀexecutedꢀ

consecutively.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀﬁrstꢀbeꢀclearedꢀbeforeꢀimplementingꢀanyꢀ

writeꢀoperations,ꢀandꢀthenꢀsetꢀagainꢀafterꢀtheꢀwriteꢀcycleꢀhasꢀstarted.ꢀNoteꢀthatꢀsettingꢀtheꢀWRꢀbitꢀ

highꢀwillꢀnotꢀinitiateꢀaꢀwriteꢀcycleꢀifꢀtheꢀWRENꢀbitꢀhasꢀnotꢀbeenꢀset.ꢀAsꢀtheꢀEEPROMꢀwriteꢀcycleꢀisꢀ

controlledꢀusingꢀanꢀinternalꢀtimerꢀwhoseꢀoperationꢀisꢀasynchronousꢀtoꢀmicrocontrollerꢀsystemꢀclock,ꢀ

aꢀcertainꢀtimeꢀwillꢀelapseꢀbeforeꢀtheꢀdataꢀwillꢀhaveꢀbeenꢀwrittenꢀintoꢀtheꢀEEPROM.ꢀDetectingꢀwhenꢀ

theꢀwriteꢀcycleꢀhasꢀﬁnishedꢀcanꢀbeꢀimplementedꢀeitherꢀbyꢀpollingꢀtheꢀWRꢀbitꢀinꢀtheꢀEECꢀregisterꢀorꢀ

byꢀusingꢀtheꢀEEPROMꢀinterrupt.ꢀWhenꢀtheꢀwriteꢀcycleꢀterminates,ꢀtheꢀWRꢀbitꢀwillꢀbeꢀautomaticallyꢀ

clearedꢀtoꢀzeroꢀbyꢀtheꢀmicrocontroller,ꢀinformingꢀtheꢀuserꢀthatꢀtheꢀdataꢀhasꢀbeenꢀwrittenꢀtoꢀtheꢀ

EEPROM.ꢀTheꢀapplicationꢀprogramꢀcanꢀthereforeꢀpollꢀtheꢀWRꢀbitꢀtoꢀdetermineꢀwhenꢀtheꢀwriteꢀcycleꢀ

hasꢀended.

Write Protection

Protectionꢀagainstꢀinadvertentꢀwriteꢀoperationꢀisꢀprovidedꢀinꢀseveralꢀways.ꢀAfterꢀtheꢀdevicesꢀ

areꢀpowered-onꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀregisterꢀwillꢀbeꢀclearedꢀpreventingꢀanyꢀwriteꢀ

operations.ꢀAlsoꢀatꢀpower-onꢀtheꢀBankꢀPointer,ꢀBP,ꢀwillꢀbeꢀresetꢀtoꢀzero,ꢀwhichꢀmeansꢀthatꢀDataꢀ

MemoryꢀBankꢀ0ꢀwillꢀbeꢀselected.ꢀAsꢀtheꢀEEPROMꢀcontrolꢀregisterꢀisꢀlocatedꢀinꢀBankꢀ1,ꢀthisꢀaddsꢀaꢀ

furtherꢀmeasureꢀofꢀprotectionꢀagainstꢀspuriousꢀwriteꢀoperations.ꢀDuringꢀnormalꢀprogramꢀoperation,ꢀ

ensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀinꢀtheꢀcontrolꢀregisterꢀisꢀclearedꢀwillꢀsafeguardꢀagainstꢀincorrectꢀ

writeꢀoperations.

EEPROM Interrupt

TheꢀEEPROMꢀwriteꢀinterruptꢀisꢀgeneratedꢀwhenꢀanꢀEEPROMꢀwriteꢀcycleꢀhasꢀended.ꢀTheꢀEEPROMꢀ

interruptꢀmustꢀfirstꢀbeꢀenabledꢀbyꢀsettingꢀtheꢀDEEꢀbitꢀinꢀtheꢀrelevantꢀinterruptꢀregister.ꢀWhenꢀanꢀ

EEPROMꢀwriteꢀcycleꢀends,ꢀtheꢀDEFꢀrequestꢀﬂagꢀwillꢀbeꢀset.ꢀIfꢀtheꢀglobal,ꢀEEPROMꢀInterruptꢀareꢀ

enabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀEEPROMꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀ

WhenꢀtheꢀEEPROMꢀInterruptꢀisꢀserviced,ꢀtheꢀEEPROMꢀInterruptꢀﬂagꢀDEFꢀwillꢀbeꢀautomaticallyꢀ

cleared.ꢀTheꢀEMIꢀbitꢀwillꢀalsoꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.

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Cost-Effective Flash MCU with EEPROM

Programming Considerations

CareꢀmustꢀbeꢀtakenꢀthatꢀdataꢀisꢀnotꢀinadvertentlyꢀwrittenꢀtoꢀtheꢀEEPROM.ꢀProtectionꢀcanꢀbeꢀPeriodicꢀ

byꢀensuringꢀthatꢀtheꢀWriteꢀEnableꢀbitꢀisꢀnormallyꢀclearedꢀtoꢀzeroꢀwhenꢀnotꢀwriting.ꢀAlsoꢀtheꢀBankꢀ

PointerꢀcouldꢀbeꢀnormallyꢀclearedꢀtoꢀzeroꢀasꢀthisꢀwouldꢀinhibitꢀaccessꢀtoꢀBankꢀ1whereꢀtheꢀEEPROMꢀ

controlꢀregisterꢀexist.ꢀAlthoughꢀcertainlyꢀnotꢀnecessary,ꢀconsiderationꢀmightꢀbeꢀgivenꢀinꢀtheꢀ

applicationꢀprogramꢀtoꢀtheꢀcheckingꢀofꢀtheꢀvalidityꢀofꢀnewꢀwriteꢀdataꢀbyꢀaꢀsimpleꢀreadꢀbackꢀprocess.ꢀ

WhenꢀwritingꢀdataꢀtheꢀWRꢀbitꢀmustꢀbeꢀsetꢀhighꢀimmediatelyꢀafterꢀtheꢀWRENꢀbitꢀhasꢀbeenꢀsetꢀhigh,ꢀ

toꢀensureꢀtheꢀwriteꢀcycleꢀexecutesꢀcorrectly.ꢀTheꢀglobalꢀinterruptꢀbitꢀEMIꢀshouldꢀalsoꢀbeꢀclearedꢀ

beforeꢀaꢀwriteꢀcycleꢀisꢀexecutedꢀandꢀthenꢀre-enabledꢀafterꢀtheꢀwriteꢀcycleꢀstarts.ꢀNoteꢀthatꢀtheꢀdevicesꢀ

shouldꢀnotꢀenterꢀtheꢀIDLEꢀorꢀSLEEPꢀmodeꢀuntilꢀtheꢀEEPROMꢀreadꢀorꢀwriteꢀoperationꢀisꢀtotallyꢀ

complete.ꢀOtherwise,ꢀtheꢀEEPROMꢀreadꢀorꢀwriteꢀoperationꢀwillꢀfail.

Programming Examples

• Reading data from the EEPROM - polling method

MOV A, EEPROM_ADRES

MOV EEA, A

MOV A, 040H

MOV MP1, A

MOV A, 01H

MOV BP, A

; user deﬁned address

; setup memory pointer MP1

; MP1 points to EEC register

; setup Bank Pointer

SET IAR1.1

SET IAR1.0

BACK:

; set RDEN bit, enable read operations

; start Read Cycle - set RD bit

SZ IAR1.0

JMP BACK

CLR IAR1

; check for read cycle end

; disable EEPROM write

CLR BP

MOV A, EED

MOV READ_DATA, A

; move read data to register

• Writing Data to the EEPROM - polling method

MOV A, EEPROM_ADRES

MOV EEA, A

; user deﬁned address

MOV A, EEPROM_DATA

MOV EED, A

; user deﬁned data

MOV A, 040H

MOV MP1, A

MOV A, 01H

; setup memory pointer MP1

; MP1 points to EEC register

; setup Bank Pointer

MOV BP, A

CLR

EMI

SET IAR1.3

SET IAR1.2

; set WREN bit, enable write operations

; start Write Cycle - set WR bit– executed immediately after

; set WREN bit

SET EMI

BACK:

SZ IAR1.2

JMP BACK

CLR IAR1

CLR BP

; check for write cycle end

; disable EEPROM write

Rev. 1.41

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Cost-Effective Flash MCU with EEPROM

Oscillators

Variousꢀoscillatorꢀoptionsꢀofferꢀtheꢀuserꢀaꢀwideꢀrangeꢀofꢀfunctionsꢀaccordingꢀtoꢀtheirꢀvariousꢀ

applicationꢀrequirements.ꢀTheꢀflexibleꢀfeaturesꢀofꢀtheꢀoscillatorꢀfunctionsꢀensureꢀthatꢀtheꢀbestꢀ

optimisationꢀcanꢀbeꢀachievedꢀinꢀtermsꢀofꢀspeedꢀandꢀpowerꢀsaving.ꢀOscillatorꢀselectionsꢀandꢀoperationꢀ

areꢀselectedꢀthroughꢀregisters.

Oscillator Overview

Inꢀadditionꢀtoꢀbeingꢀtheꢀsourceꢀofꢀtheꢀmainꢀsystemꢀclockꢀtheꢀoscillatorsꢀalsoꢀprovideꢀclockꢀsourcesꢀ

forꢀtheꢀWatchdogꢀTimerꢀandꢀTimeꢀBaseꢀInterrupts.ꢀTwoꢀfullyꢀintegratedꢀinternalꢀoscillators,ꢀrequiringꢀ

noꢀexternalꢀcomponents,ꢀareꢀprovidedꢀtoꢀformꢀaꢀwideꢀrangeꢀofꢀbothꢀfastꢀandꢀslowꢀsystemꢀoscillators.ꢀ

Theꢀhigherꢀfrequencyꢀoscillatorꢀprovidesꢀhigherꢀperformanceꢀbutꢀcarryꢀwithꢀitꢀtheꢀdisadvantageꢀofꢀ

higherꢀpowerꢀrequirements,ꢀwhileꢀtheꢀoppositeꢀisꢀofꢀcourseꢀtrueꢀforꢀtheꢀlowerꢀfrequencyꢀoscillator.ꢀ

Withꢀtheꢀcapabilityꢀofꢀdynamicallyꢀswitchingꢀbetweenꢀfastꢀandꢀslowꢀsystemꢀclock,ꢀtheseꢀdevicesꢀ

haveꢀtheꢀﬂexibilityꢀtoꢀoptimizeꢀtheꢀperformance/powerꢀratio,ꢀaꢀfeatureꢀespeciallyꢀimportantꢀinꢀpowerꢀ

sensitiveꢀportableꢀapplications.

Type

Name

HIRC

LIRC

Freq.

8MHz

32kHz

Internal High Speed RC

Internal Low Speed RC

Oscillator Types

System Clock Conﬁgurations

Thereꢀareꢀtwoꢀmethodsꢀofꢀgeneratingꢀtheꢀsystemꢀclock,ꢀaꢀhighꢀspeedꢀoscillatorꢀandꢀaꢀlowꢀspeedꢀ

oscillator.ꢀTheꢀhighꢀspeedꢀoscillatorꢀisꢀtheꢀinternalꢀ8MHzꢀRCꢀoscillator.ꢀTheꢀlowꢀspeedꢀoscillatorꢀisꢀ

theꢀinternalꢀ32kHzꢀRCꢀoscillator.ꢀSelectingꢀwhetherꢀtheꢀlowꢀorꢀhighꢀspeedꢀoscillatorꢀisꢀusedꢀasꢀtheꢀ

systemꢀoscillatorꢀisꢀimplementedꢀusingꢀtheꢀHLCLKꢀbitꢀandꢀCKS2ꢀ~ꢀCKS0ꢀbitsꢀinꢀtheꢀSMODꢀregisterꢀ

andꢀasꢀtheꢀsystemꢀclockꢀcanꢀbeꢀdynamicallyꢀselected.

f_H/2

f_H/4

High Speed Oscillator

f_H/8

f_SYS

f_H

f_H/16

f_H/32

f_H/64

HIRC

Prescaler

HLCLK

CKS2~CKS0 bits

Low Speed Oscillator

LIRC

f_L

System Clock Conﬁgurations

Internal RC Oscillator – HIRC

TheꢀinternalꢀRCꢀoscillatorꢀisꢀaꢀfullyꢀintegratedꢀsystemꢀoscillatorꢀrequiringꢀnoꢀexternalꢀcomponents.ꢀ

TheꢀinternalꢀRCꢀoscillatorꢀhasꢀaꢀfixedꢀfrequencyꢀofꢀ8MHz.ꢀDeviceꢀtrimmingꢀduringꢀtheꢀ

manufacturingꢀprocessꢀandꢀtheꢀinclusionꢀofꢀinternalꢀfrequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀtoꢀ

ensureꢀthatꢀtheꢀinﬂuenceꢀofꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀtemperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀ

oscillationꢀfrequencyꢀareꢀminimised.ꢀAsꢀaꢀresult,ꢀatꢀaꢀpowerꢀsupplyꢀofꢀ5Vꢀandꢀatꢀtemperatureꢀofꢀ25°Cꢀ

degrees,ꢀtheꢀﬁxedꢀoscillationꢀfrequencyꢀofꢀtheꢀHIRCꢀwillꢀhaveꢀaꢀtoleranceꢀwithinꢀ2%.ꢀ

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Cost-Effective Flash MCU with EEPROM

Internal 32kHz Oscillator – LIRC

Theꢀinternalꢀ32kHzꢀSystemꢀOscillatorꢀisꢀtheꢀlowꢀfrequencyꢀoscillator.ꢀItꢀisꢀaꢀfullyꢀintegratedꢀ

RCꢀoscillatorꢀwithꢀaꢀtypicalꢀfrequencyꢀofꢀ32kHzꢀatꢀ5V,ꢀrequiringꢀnoꢀexternalꢀcomponentsꢀforꢀitsꢀ

implementation.ꢀDeviceꢀtrimmingꢀduringꢀtheꢀmanufacturingꢀprocessꢀandꢀtheꢀinclusionꢀofꢀinternalꢀ

frequencyꢀcompensationꢀcircuitsꢀareꢀusedꢀtoꢀensureꢀthatꢀtheꢀinﬂuenceꢀofꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀ

temperatureꢀandꢀprocessꢀvariationsꢀonꢀtheꢀoscillationꢀfrequencyꢀareꢀminimised.ꢀ

Supplementary Oscillator

Theꢀlowꢀspeedꢀoscillator,ꢀinꢀadditionꢀtoꢀprovidingꢀaꢀsystemꢀclockꢀsourceꢀisꢀalsoꢀusedꢀtoꢀprovideꢀ

aꢀclockꢀsourceꢀtoꢀtwoꢀotherꢀdeviceꢀfunctions.ꢀTheseꢀareꢀtheꢀWatchdogꢀTimerꢀandꢀtheꢀTimeꢀBaseꢀ

Interrupts.

Operating Modes and System Clocks

Presentꢀdayꢀapplicationsꢀrequireꢀthatꢀtheirꢀmicrocontrollersꢀhaveꢀhighꢀperformanceꢀbutꢀoftenꢀstillꢀ

demandꢀthatꢀtheyꢀconsumeꢀasꢀlittleꢀpowerꢀasꢀpossible,ꢀconﬂictingꢀrequirementsꢀthatꢀareꢀespeciallyꢀ

trueꢀinꢀbatteryꢀpoweredꢀportableꢀapplications.ꢀTheꢀfastꢀclocksꢀrequiredꢀforꢀhighꢀperformanceꢀwillꢀ

byꢀtheirꢀnatureꢀincreaseꢀcurrentꢀconsumptionꢀandꢀofꢀcourseꢀvice-versa,ꢀlowerꢀspeedꢀclocksꢀreduceꢀ

currentꢀconsumption.ꢀAsꢀHoltekꢀhasꢀprovidedꢀtheseꢀdevicesꢀwithꢀbothꢀhighꢀandꢀlowꢀspeedꢀclockꢀ

sourcesꢀandꢀtheꢀmeansꢀtoꢀswitchꢀbetweenꢀthemꢀdynamically,ꢀtheꢀuserꢀcanꢀoptimiseꢀtheꢀoperationꢀofꢀ

theirꢀmicrocontrollerꢀtoꢀachieveꢀtheꢀbestꢀperformance/powerꢀratio.

System Clocks

TheseꢀdevicesꢀhaveꢀtwoꢀdifferentꢀclockꢀsourcesꢀforꢀbothꢀtheꢀCPUꢀandꢀperipheralꢀfunctionꢀoperation.ꢀ

Byꢀprovidingꢀtheꢀuserꢀwithꢀclockꢀoptionsꢀusingꢀregisterꢀprogramming,ꢀaꢀclockꢀsystemꢀcanꢀbeꢀ

conﬁguredꢀtoꢀobtainꢀmaximumꢀapplicationꢀperformance.

Theꢀmainꢀsystemꢀclock,ꢀcanꢀcomeꢀfromꢀeitherꢀaꢀhighꢀfrequency,ꢀf_H,ꢀorꢀaꢀlowꢀfrequency,ꢀf_L,ꢀandꢀisꢀ

selectedꢀusingꢀtheꢀHLCLKꢀbitꢀandꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregister.ꢀTheꢀhighꢀspeedꢀsystemꢀ

clockꢀcanꢀbeꢀsourcedꢀfromꢀHIRCꢀoscillator.ꢀTheꢀlowꢀspeedꢀsystemꢀclockꢀsourceꢀcanꢀbeꢀsourcedꢀfromꢀ

theꢀinternalꢀclockꢀf_L.ꢀTheꢀotherꢀchoice,ꢀwhichꢀisꢀaꢀdividedꢀversionꢀofꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀ

hasꢀaꢀrangeꢀofꢀf_H/2~f_H/64.

Thereꢀisꢀoneꢀadditionalꢀinternalꢀclockꢀforꢀtheꢀperipheralꢀcircuits,ꢀtheꢀTimeꢀBaseꢀclock,ꢀf_TBC.ꢀf_TBCꢀisꢀ

sourcedꢀfromꢀtheꢀLIRCꢀoscillators.ꢀTheꢀf_TBCꢀclockꢀisꢀusedꢀasꢀaꢀsourceꢀforꢀtheꢀTimeꢀBaseꢀinterruptꢀ

functionsꢀandꢀforꢀtheꢀTMs.

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f_H/2

f_H/4

f_H/8

High Speed Oscillator

HIRC

f_SYS

f_H

f_H/16

f_H/32

f_H/64

Prescaler

HLCLK

CKS2~CKS0 bits

Low Speed Oscillator

LIRC

f_L

f_LIRC

WDT

f_TBC

f_TB

IDLEN

Time Base 0

f_SYS/4

Time Base 1

TBCK

System Clock Conﬁgurations

Note:ꢀWhenꢀtheꢀsystemꢀclockꢀsourceꢀf_SYSꢀisꢀswitchedꢀtoꢀf_Lꢀfromꢀf_H,ꢀtheꢀhighꢀspeedꢀoscillationꢀwillꢀ

stopꢀtoꢀconserveꢀtheꢀpower.ꢀThusꢀthereꢀisꢀnoꢀf_H~f_H/64ꢀforꢀperipheralꢀcircuitꢀtoꢀuse.

System Operation Modes

Thereꢀareꢀsixꢀdifferentꢀmodesꢀofꢀoperationꢀforꢀtheꢀmicrocontroller,ꢀeachꢀoneꢀwithꢀitsꢀownꢀ

specialꢀcharacteristicsꢀandꢀwhichꢀcanꢀbeꢀchosenꢀaccordingꢀtoꢀtheꢀspecificꢀperformanceꢀandꢀ

powerꢀrequirementsꢀofꢀtheꢀapplication.ꢀThereꢀareꢀtwoꢀmodesꢀallowingꢀnormalꢀoperationꢀofꢀtheꢀ

microcontroller,ꢀtheꢀNORMALꢀModeꢀandꢀSLOWꢀMode.ꢀTheꢀremainingꢀfourꢀmodes,ꢀtheꢀSLEEP0,ꢀ

SLEEP1,ꢀIDLE0ꢀandꢀIDLE1ꢀmodesꢀareꢀusedꢀwhenꢀtheꢀmicrocontrollerꢀCPUꢀisꢀswitchedꢀoffꢀtoꢀ

conserveꢀpower.

Description

Operating

Mode

CPU

On

Off

f_SYS

f_H~f_H/64

f_L

f_LIRC

On

Off

On

f_TBC

On

Off

NORMAL mode

SLOW mode

IDLE0 mode

Off

IDLE1 mode

On

SLEEP0 mode

SLEEP1 mode

Off

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Cost-Effective Flash MCU with EEPROM

NORMAL Mode

Asꢀtheꢀnameꢀsuggestsꢀthisꢀisꢀoneꢀofꢀtheꢀmainꢀoperatingꢀmodesꢀwhereꢀtheꢀmicrocontrollerꢀhasꢀallꢀ

ofꢀitsꢀfunctionsꢀoperationalꢀandꢀwhereꢀtheꢀsystemꢀclockꢀisꢀprovidedꢀtheꢀhighꢀspeedꢀoscillator.ꢀThisꢀ

modeꢀoperatesꢀallowingꢀtheꢀmicrocontrollerꢀtoꢀoperateꢀnormallyꢀwithꢀaꢀclockꢀsourceꢀwillꢀcomeꢀfromꢀ

theꢀhighꢀspeedꢀoscillatorꢀHIRC.ꢀTheꢀhighꢀspeedꢀoscillatorꢀwillꢀhoweverꢀﬁrstꢀbeꢀdividedꢀbyꢀaꢀratioꢀ

rangingꢀfromꢀ1ꢀtoꢀ64,ꢀtheꢀactualꢀratioꢀbeingꢀselectedꢀbyꢀtheꢀCKS2~CKS0ꢀandꢀHLCLKꢀbitsꢀinꢀtheꢀ

SMODꢀregister.ꢀAlthoughꢀaꢀhighꢀspeedꢀoscillatorꢀisꢀused,ꢀrunningꢀtheꢀmicrocontrollerꢀatꢀaꢀdividedꢀ

clockꢀratioꢀreducesꢀtheꢀoperatingꢀcurrent.

SLOW Mode

Thisꢀisꢀalsoꢀaꢀmodeꢀwhereꢀtheꢀmicrocontrollerꢀoperatesꢀnormallyꢀalthoughꢀnowꢀwithꢀaꢀslowerꢀ

speedꢀclockꢀsource.ꢀTheꢀclockꢀsourceꢀusedꢀwillꢀbeꢀfromꢀtheꢀlowꢀspeedꢀoscillatorꢀLIRC.ꢀRunningꢀ

theꢀmicrocontrollerꢀinꢀthisꢀmodeꢀallowsꢀitꢀtoꢀrunꢀwithꢀmuchꢀlowerꢀoperatingꢀcurrents.ꢀInꢀtheꢀSLOWꢀ

Mode,ꢀtheꢀf_Hꢀisꢀoff.

SLEEP0 Mode

TheꢀSLEEPꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ

SMODꢀregisterꢀisꢀlow.ꢀInꢀtheꢀSLEEP0ꢀmodeꢀtheꢀCPUꢀwillꢀbeꢀstopped,ꢀandꢀtheꢀf_LIRCꢀclockꢀwillꢀbeꢀ

stoppedꢀtoo,ꢀandꢀtheꢀWatchdogꢀTimerꢀfunctionꢀisꢀdisabled.

SLEEP1 Mode

TheꢀSLEEPꢀModeꢀisꢀenteredꢀwhenꢀanꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ

SMODꢀregisterꢀisꢀlow.ꢀInꢀtheꢀSLEEP1ꢀmodeꢀtheꢀCPUꢀwillꢀbeꢀstopped.ꢀHoweverꢀtheꢀf_LIRCꢀclocksꢀwillꢀ

continueꢀtoꢀoperateꢀifꢀtheꢀWatchdogꢀTimerꢀfunctionꢀisꢀenabled.

IDLE0 Mode

TheꢀIDLE0ꢀModeꢀisꢀenteredꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ

SMODꢀregisterꢀisꢀhighꢀandꢀtheꢀFSYSONꢀbitꢀinꢀtheꢀSMOD1ꢀregisterꢀisꢀlow.ꢀInꢀtheꢀIDLE0ꢀModeꢀtheꢀ

systemꢀoscillatorꢀwillꢀbeꢀinhibitedꢀfromꢀdrivingꢀtheꢀCPUꢀbutꢀsomeꢀperipheralꢀfunctionsꢀwillꢀremainꢀ

operationalꢀsuchꢀasꢀtheꢀWatchdogꢀTimerꢀandꢀTMs.ꢀInꢀtheꢀIDLE0ꢀMode,ꢀtheꢀsystemꢀoscillatorꢀwillꢀbeꢀ

stopped.ꢀ

IDLE1 Mode

TheꢀIDLE1ꢀModeꢀisꢀenteredꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀandꢀwhenꢀtheꢀIDLENꢀbitꢀinꢀtheꢀ

SMODꢀregisterꢀisꢀhighꢀandꢀtheꢀFSYSONꢀbitꢀinꢀtheꢀSMOD1ꢀregisterꢀisꢀhigh.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀ

systemꢀoscillatorꢀwillꢀbeꢀinhibitedꢀfromꢀdrivingꢀtheꢀCPUꢀbutꢀmayꢀcontinueꢀtoꢀprovideꢀaꢀclockꢀsourceꢀ

toꢀkeepꢀsomeꢀperipheralꢀfunctionsꢀoperationalꢀsuchꢀasꢀtheꢀWatchdogꢀTimerꢀandꢀTMs.ꢀInꢀtheꢀIDLE1ꢀ

Mode,ꢀtheꢀsystemꢀoscillatorꢀwillꢀcontinueꢀtoꢀrun,ꢀandꢀthisꢀsystemꢀoscillatorꢀmayꢀbeꢀhighꢀspeedꢀorꢀlowꢀ

speedꢀsystemꢀoscillator.ꢀInꢀtheꢀIDLE1ꢀMode,ꢀtheꢀWatchdogꢀTimerꢀclock,ꢀf_LIRC,ꢀwillꢀbeꢀon.

Rev. 1.41

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Cost-Effective Flash MCU with EEPROM

Control Register

Aꢀsingleꢀregister,ꢀSMOD,ꢀisꢀusedꢀforꢀoverallꢀcontrolꢀofꢀtheꢀinternalꢀclocksꢀwithinꢀtheꢀdevice.

SMOD Register

Bit

7

CKS2

R/W

0

6

CKS1

R/W

0

5

CKS0

R/W

0

4

3

LTO

R

2

HTO

R

1

IDLEN

R/W

1

0

HLCLK

R/W

1

Name

R/W

—

POR

0

Bitꢀ7ꢀ~ꢀ5

CKS2 ~ CKS0:ꢀTheꢀsystemꢀclockꢀselectionꢀwhenꢀHLCLKꢀisꢀ"0"

000:ꢀf_Lꢀ(f_LIRC

)

001:ꢀf_Lꢀ(f_LIRC

010:ꢀf_H/64

011:ꢀf_H/32

100:ꢀf_H/16

101:ꢀf_H/8

)

110:ꢀf_H/4

111:ꢀf_H/2

Theseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀwhichꢀclockꢀisꢀusedꢀasꢀtheꢀsystemꢀclockꢀsource.ꢀInꢀ

additionꢀtoꢀtheꢀsystemꢀclockꢀsource,ꢀwhichꢀcanꢀbeꢀtheꢀLIRC,ꢀaꢀdividedꢀversionꢀofꢀtheꢀ

highꢀspeedꢀsystemꢀoscillatorꢀcanꢀalsoꢀbeꢀchosenꢀasꢀtheꢀsystemꢀclockꢀsource.

Bitꢀ4ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

Bitꢀ3

LTO:ꢀLowꢀspeedꢀsystemꢀoscillatorꢀreadyꢀﬂagꢀ

0:ꢀNotꢀready

1:ꢀReady

Thisꢀisꢀtheꢀlowꢀspeedꢀsystemꢀoscillatorꢀreadyꢀﬂagꢀwhichꢀindicatesꢀwhenꢀtheꢀlowꢀspeedꢀ

systemꢀoscillatorꢀisꢀstableꢀafterꢀpowerꢀonꢀresetꢀorꢀaꢀwake-upꢀhasꢀoccurred.ꢀTheꢀﬂagꢀ

willꢀbeꢀlowꢀwhenꢀinꢀtheꢀSLEEP0ꢀmode,ꢀbutꢀafterꢀaꢀwake-upꢀhasꢀoccurredꢀtheꢀﬂagꢀwillꢀ

changeꢀtoꢀaꢀhighꢀlevelꢀafterꢀ1~2ꢀcyclesꢀifꢀtheꢀLIRCꢀoscillatorꢀisꢀused.

Bitꢀ2

HTO:ꢀHighꢀspeedꢀsystemꢀoscillatorꢀreadyꢀﬂagꢀ

0:ꢀNotꢀready

1:ꢀReady

Thisꢀisꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀreadyꢀﬂagꢀwhichꢀindicatesꢀwhenꢀtheꢀhighꢀspeedꢀ

systemꢀoscillatorꢀisꢀstable.ꢀThisꢀﬂagꢀisꢀclearedꢀtoꢀ"0"ꢀbyꢀhardwareꢀwhenꢀtheꢀdeviceꢀisꢀ

poweredꢀonꢀandꢀthenꢀchangesꢀtoꢀaꢀhighꢀlevelꢀafterꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀisꢀ

stable.ꢀThereforeꢀthisꢀﬂagꢀwillꢀalwaysꢀbeꢀreadꢀasꢀ"1"ꢀbyꢀtheꢀapplicationꢀprogramꢀafterꢀ

deviceꢀpower-on.ꢀ

Bitꢀ1

IDLEN:ꢀIDLEꢀModeꢀControl

0:ꢀDisable

1:ꢀEnable

ThisꢀisꢀtheꢀIDLEꢀModeꢀControlꢀbitꢀandꢀdeterminesꢀwhatꢀhappensꢀwhenꢀtheꢀHALTꢀ

instructionꢀisꢀexecuted.ꢀIfꢀthisꢀbitꢀisꢀhigh,ꢀwhenꢀaꢀHALTꢀinstructionꢀisꢀexecutedꢀtheꢀ

deviceꢀwillꢀenterꢀtheꢀIDLEꢀMode.ꢀInꢀtheꢀIDLE1ꢀModeꢀtheꢀCPUꢀwillꢀstopꢀrunningꢀ

butꢀtheꢀsystemꢀclockꢀwillꢀcontinueꢀtoꢀkeepꢀtheꢀperipheralꢀfunctionsꢀoperational,ꢀifꢀ

FSYSONꢀbitꢀisꢀhigh.ꢀIfꢀFSYSONꢀbitꢀisꢀlow,ꢀtheꢀCPUꢀandꢀtheꢀsystemꢀclockꢀwillꢀallꢀstopꢀ

inꢀIDLE0ꢀmode.ꢀIfꢀtheꢀbitꢀisꢀlowꢀtheꢀdeviceꢀwillꢀenterꢀtheꢀSLEEPꢀModeꢀwhenꢀaꢀHALTꢀ

instructionꢀisꢀexecuted.

Bitꢀ0

HLCLK:ꢀSystemꢀClockꢀSelection

0:ꢀf_H/2ꢀ~ꢀf_H/64ꢀorꢀf_L

1:ꢀf_H

Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀifꢀtheꢀf_Hꢀclockꢀorꢀtheꢀf_H/2ꢀ~ꢀf_H/64ꢀorꢀf_Lꢀclockꢀisꢀusedꢀasꢀtheꢀ

systemꢀclock.ꢀWhenꢀtheꢀbitꢀisꢀhighꢀtheꢀf_Hꢀclockꢀwillꢀbeꢀselectedꢀandꢀifꢀlowꢀtheꢀf_H/2ꢀ~ꢀ

f_H/64ꢀorꢀf_Lꢀclockꢀwillꢀbeꢀselected.ꢀWhenꢀsystemꢀclockꢀswitchesꢀfromꢀtheꢀf_Hꢀclockꢀtoꢀtheꢀ

f_Lꢀclockꢀandꢀtheꢀf_Hꢀclockꢀwillꢀbeꢀautomaticallyꢀswitchedꢀoffꢀtoꢀconserveꢀpower.

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Cost-Effective Flash MCU with EEPROM

SMOD1 Register

Bit

Name

R/W

7

FSYSON

R/W

6

5

4

3

D3

R/W

0

2

LVRF

R/W

x

1

0

WRF

—

R/W

POR

0

"x" unknown

Bitꢀ7ꢀ

FSYSON:ꢀf_SYSꢀControlꢀinꢀIDLEꢀMode

0:ꢀDisable

1:ꢀEnable

Bitꢀ6~4ꢀ

Bitꢀ3

Unimplemented,ꢀreadꢀasꢀ"0"

D3:ꢀReservedꢀbit

Bitꢀ2

LVRF:ꢀLVRꢀfunctionꢀresetꢀﬂag

0:ꢀNotꢀactive

1:ꢀActive

Thisꢀbitꢀcanꢀbeꢀclearꢀtoꢀ"0",ꢀbutꢀcanꢀnotꢀbeꢀsetꢀtoꢀ"1".

Unimplemented,ꢀreadꢀasꢀ"0"

Bitꢀ1ꢀ

Bitꢀ0

WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀﬂag

0:ꢀNotꢀoccur

1:ꢀOccurred

Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀtheꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ

applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀ

program.

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Operating Mode Switching

Theꢀdevicesꢀcanꢀswitchꢀbetweenꢀoperatingꢀmodesꢀdynamicallyꢀallowingꢀtheꢀuserꢀtoꢀselectꢀtheꢀbestꢀ

performance/powerꢀratioꢀforꢀtheꢀpresentꢀtaskꢀinꢀhand.ꢀInꢀthisꢀwayꢀmicrocontrollerꢀoperationsꢀthatꢀ

doꢀnotꢀrequireꢀhighꢀperformanceꢀcanꢀbeꢀexecutedꢀusingꢀslowerꢀclocksꢀthusꢀrequiringꢀlessꢀoperatingꢀ

currentꢀandꢀprolongingꢀbatteryꢀlifeꢀinꢀportableꢀapplications.ꢀ

Inꢀsimpleꢀterms,ꢀModeꢀSwitchingꢀbetweenꢀtheꢀNORMALꢀModeꢀandꢀSLOWꢀModeꢀisꢀexecutedꢀusingꢀtheꢀ

HLCLKꢀbitꢀandꢀCKS2~CKS0ꢀbitsꢀinꢀtheꢀSMODꢀregisterꢀwhileꢀModeꢀSwitchingꢀfromꢀtheꢀNORMAL/

SLOWꢀModesꢀtoꢀtheꢀSLEEP/IDLEꢀModesꢀisꢀexecutedꢀviaꢀtheꢀHALTꢀinstruction.ꢀWhenꢀaꢀHALTꢀ

instructionꢀisꢀexecuted,ꢀwhetherꢀtheꢀdeviceꢀentersꢀtheꢀIDLEꢀModeꢀorꢀtheꢀSLEEPꢀModeꢀisꢀdeterminedꢀbyꢀ

theꢀconditionꢀofꢀtheꢀIDLENꢀbitꢀinꢀtheꢀSMODꢀregisterꢀandꢀFSYSONꢀinꢀtheꢀSMOD1ꢀregister.ꢀ

WhenꢀtheꢀHLCLKꢀbitꢀswitchesꢀtoꢀaꢀlowꢀlevel,ꢀwhichꢀimpliesꢀthatꢀclockꢀsourceꢀisꢀswitchedꢀfromꢀtheꢀ

highꢀspeedꢀclockꢀsource,ꢀf_H,ꢀtoꢀtheꢀclockꢀsource,ꢀf_H/2~f_H/64ꢀorꢀf_L.ꢀIfꢀtheꢀclockꢀisꢀfromꢀtheꢀf_L,ꢀtheꢀhighꢀ

speedꢀclockꢀsourceꢀwillꢀstopꢀrunningꢀtoꢀconserveꢀpower.ꢀWhenꢀthisꢀhappensꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀ

f_H/16ꢀandꢀf_H/64ꢀinternalꢀclockꢀsourcesꢀwillꢀalsoꢀstopꢀrunning,ꢀwhichꢀmayꢀaffectꢀtheꢀoperationꢀofꢀotherꢀ

internalꢀfunctionsꢀsuchꢀasꢀtheꢀTMs.ꢀ

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Rev. 1.41

38

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

NORMAL Mode to SLOW Mode Switching

WhenꢀrunningꢀinꢀtheꢀNORMALꢀMode,ꢀwhichꢀusesꢀtheꢀhighꢀspeedꢀsystemꢀoscillator,ꢀandꢀthereforeꢀ

consumesꢀmoreꢀpower,ꢀtheꢀsystemꢀclockꢀcanꢀswitchꢀtoꢀrunꢀinꢀtheꢀSLOWꢀModeꢀbyꢀsettingꢀtheꢀ

HLCLKꢀbitꢀtoꢀ"0"ꢀandꢀsettingꢀtheꢀCKS2~CKS0ꢀbitsꢀtoꢀ"000"ꢀorꢀ"001"ꢀinꢀtheꢀSMODꢀregister.Thisꢀ

willꢀthenꢀuseꢀtheꢀlowꢀspeedꢀsystemꢀoscillatorꢀwhichꢀwillꢀconsumeꢀlessꢀpower.ꢀUsersꢀmayꢀdecideꢀtoꢀ

doꢀthisꢀforꢀcertainꢀoperationsꢀwhichꢀdoꢀnotꢀrequireꢀhighꢀperformanceꢀandꢀcanꢀsubsequentlyꢀreduceꢀ

powerꢀconsumption.ꢀ

TheꢀSLOWꢀModeꢀisꢀsourcedꢀfromꢀtheꢀLIRCꢀoscillatorꢀandꢀthereforeꢀrequiresꢀthisꢀoscillatorꢀtoꢀbeꢀ

stableꢀbeforeꢀfullꢀmodeꢀswitchingꢀoccurs.ꢀThisꢀisꢀmonitoredꢀusingꢀtheꢀLTOꢀbitꢀinꢀtheꢀSMODꢀregister.

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Rev. 1.41

39

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

SLOW Mode to NORMAL Mode Switching

InꢀSLOWꢀModeꢀtheꢀsystemꢀusesꢀLIRCꢀlowꢀspeedꢀsystemꢀoscillator.ꢀToꢀswitchꢀbackꢀtoꢀtheꢀNORMALꢀ

Mode,ꢀwhereꢀtheꢀhighꢀspeedꢀsystemꢀoscillatorꢀisꢀused,ꢀtheꢀHLCLKꢀbitꢀshouldꢀbeꢀsetꢀtoꢀ"1"ꢀorꢀ

HLCLKꢀbitꢀisꢀ"0",ꢀbutꢀCKS2~CKS0ꢀisꢀsetꢀtoꢀ"010",ꢀ"011",ꢀ"100",ꢀ"101",ꢀ"110"ꢀorꢀ"111".ꢀAsꢀaꢀcertainꢀ

amountꢀofꢀtimeꢀwillꢀbeꢀrequiredꢀforꢀtheꢀhighꢀfrequencyꢀclockꢀtoꢀstabilise,ꢀtheꢀstatusꢀofꢀtheꢀHTOꢀbitꢀisꢀ

checked.ꢀ

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Entering the SLEEP0 Mode

ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdevicesꢀtoꢀenterꢀtheꢀSLEEP0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ"HALT"ꢀ

instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ"0"ꢀandꢀtheꢀ

WDTꢀandꢀLVDꢀbothꢀoff.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀ

followingꢀwillꢀoccur:

•ꢀ Theꢀsystemꢀclock,ꢀWDTꢀclockꢀandꢀTimeꢀBaseꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀ

willꢀstopꢀatꢀtheꢀ"HALT"ꢀinstruction.

•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.

•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀstopped.

•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.

•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀﬂag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀﬂag,ꢀTO,ꢀ

willꢀbeꢀcleared.

Rev. 1.41

40

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Entering the SLEEP1 Mode

ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdevicesꢀtoꢀenterꢀtheꢀSLEEP1ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ"HALT"ꢀ

instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ"0"ꢀandꢀtheꢀ

WDTꢀorꢀLVDꢀon.ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀdescribedꢀabove,ꢀtheꢀ

followingꢀwillꢀoccur:

•ꢀ TheꢀsystemꢀclockꢀandꢀTimeꢀBaseꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀ

theꢀ"HALT"ꢀinstruction,ꢀbutꢀtheꢀWDTꢀorꢀLVDꢀwillꢀremainꢀwithꢀtheꢀclockꢀsourceꢀcomingꢀfromꢀtheꢀ

f_LIRCꢀclock.

•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.

•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀisꢀenabled.

•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.

•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀﬂag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀﬂag,ꢀTO,ꢀ

willꢀbeꢀcleared.

Entering the IDLE0 Mode

ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdeviceꢀtoꢀenterꢀtheꢀIDLE0ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ"HALT"ꢀ

instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ"1"ꢀandꢀtheꢀ

FSYSONꢀbitꢀinꢀSMOD1ꢀregisterꢀequalꢀtoꢀ"0".ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀ

describedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:

•ꢀ Theꢀsystemꢀclockꢀwillꢀbeꢀstoppedꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ"HALT"ꢀinstruc-

tion,ꢀbutꢀtheꢀTimeꢀBaseꢀclockꢀwillꢀbeꢀon.

•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.

•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀisꢀenabled.ꢀ

•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.

•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀﬂag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀﬂag,ꢀTO,ꢀ

willꢀbeꢀcleared.

Entering the IDLE1 Mode

ThereꢀisꢀonlyꢀoneꢀwayꢀforꢀtheꢀdevicesꢀtoꢀenterꢀtheꢀIDLE1ꢀModeꢀandꢀthatꢀisꢀtoꢀexecuteꢀtheꢀ"HALT"ꢀ

instructionꢀinꢀtheꢀapplicationꢀprogramꢀwithꢀtheꢀIDLENꢀbitꢀinꢀSMODꢀregisterꢀequalꢀtoꢀ"1"ꢀandꢀtheꢀ

FSYSONꢀbitꢀinꢀSMOD1ꢀregisterꢀequalꢀtoꢀ"1".ꢀWhenꢀthisꢀinstructionꢀisꢀexecutedꢀunderꢀtheꢀconditionsꢀ

describedꢀabove,ꢀtheꢀfollowingꢀwillꢀoccur:

•ꢀ TheꢀsystemꢀclockꢀandꢀTimeꢀBaseꢀclockꢀwillꢀbeꢀonꢀandꢀtheꢀapplicationꢀprogramꢀwillꢀstopꢀatꢀtheꢀ

"HALT"ꢀinstruction.

•ꢀ TheꢀDataꢀMemoryꢀcontentsꢀandꢀregistersꢀwillꢀmaintainꢀtheirꢀpresentꢀcondition.

•ꢀ TheꢀWDTꢀwillꢀbeꢀclearedꢀandꢀresumeꢀcountingꢀifꢀtheꢀWDTꢀisꢀenabled.ꢀ

•ꢀ TheꢀI/Oꢀportsꢀwillꢀmaintainꢀtheirꢀpresentꢀconditions.

•ꢀ Inꢀtheꢀstatusꢀregister,ꢀtheꢀPowerꢀDownꢀﬂag,ꢀPDF,ꢀwillꢀbeꢀsetꢀandꢀtheꢀWatchdogꢀtime-outꢀﬂag,ꢀTO,ꢀ

willꢀbeꢀcleared.

Rev. 1.41

41

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Standby Current Considerations

AsꢀtheꢀmainꢀreasonꢀforꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀtoꢀkeepꢀtheꢀcurrentꢀconsumptionꢀofꢀ

theꢀdevicesꢀtoꢀasꢀlowꢀaꢀvalueꢀasꢀpossible,ꢀperhapsꢀonlyꢀinꢀtheꢀorderꢀofꢀseveralꢀmicro-ampsꢀexceptꢀ

inꢀtheꢀIDLE1ꢀMode,ꢀthereꢀareꢀotherꢀconsiderationsꢀwhichꢀmustꢀalsoꢀbeꢀtakenꢀintoꢀaccountꢀbyꢀtheꢀ

circuitꢀdesignerꢀifꢀtheꢀpowerꢀconsumptionꢀisꢀtoꢀbeꢀminimised.ꢀSpecialꢀattentionꢀmustꢀbeꢀmadeꢀtoꢀ

theꢀI/Oꢀpinsꢀonꢀtheꢀdevice.ꢀAllꢀhigh-impedanceꢀinputꢀpinsꢀmustꢀbeꢀconnectedꢀtoꢀeitherꢀaꢀﬁxedꢀhighꢀ

orꢀlowꢀlevelꢀasꢀanyꢀfloatingꢀinputꢀpinsꢀcouldꢀcreateꢀinternalꢀoscillationsꢀandꢀresultꢀinꢀincreasedꢀ

currentꢀconsumption.ꢀThisꢀalsoꢀappliesꢀtoꢀdevicesꢀwhichꢀhaveꢀdifferentꢀpackageꢀtypes,ꢀasꢀthereꢀmayꢀ

beꢀunbonbedꢀpins.ꢀTheseꢀmustꢀeitherꢀbeꢀsetupꢀasꢀoutputsꢀorꢀifꢀsetupꢀasꢀinputsꢀmustꢀhaveꢀpull-highꢀ

resistorsꢀconnected.ꢀ

Careꢀmustꢀalsoꢀbeꢀtakenꢀwithꢀtheꢀloads,ꢀwhichꢀareꢀconnectedꢀtoꢀI/Oꢀpins,ꢀwhichꢀareꢀsetupꢀasꢀ

outputs.ꢀTheseꢀshouldꢀbeꢀplacedꢀinꢀaꢀconditionꢀinꢀwhichꢀminimumꢀcurrentꢀisꢀdrawnꢀorꢀconnectedꢀ

onlyꢀtoꢀexternalꢀcircuitsꢀthatꢀdoꢀnotꢀdrawꢀcurrent,ꢀsuchꢀasꢀotherꢀCMOSꢀinputs.ꢀInꢀtheꢀIDLE1ꢀModeꢀ

theꢀsystemꢀoscillatorꢀisꢀon,ꢀifꢀtheꢀsystemꢀoscillatorꢀisꢀfromꢀtheꢀhighꢀspeedꢀsystemꢀoscillator,ꢀtheꢀ

additionalꢀstandbyꢀcurrentꢀwillꢀalsoꢀbeꢀperhapsꢀinꢀtheꢀorderꢀofꢀseveralꢀhundredꢀmicro-amps.

Wake-up

AfterꢀtheꢀsystemꢀentersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀitꢀcanꢀbeꢀwokenꢀupꢀfromꢀoneꢀofꢀvariousꢀsourcesꢀ

listedꢀasꢀfollows:

•ꢀ Anꢀexternalꢀreset

•ꢀ AnꢀexternalꢀfallingꢀedgeꢀonꢀPortꢀA

•ꢀ Aꢀsystemꢀinterrupt

•ꢀ AꢀWDTꢀoverﬂow

Ifꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀanꢀexternalꢀreset,ꢀtheꢀdeviceꢀwillꢀexperienceꢀaꢀfullꢀsystemꢀreset,ꢀ

however,ꢀIfꢀtheseꢀdevicesꢀareꢀwokenꢀupꢀbyꢀaꢀWDTꢀoverflow,ꢀaꢀWatchdogꢀTimerꢀresetꢀwillꢀbeꢀ

initiated.ꢀAlthoughꢀbothꢀofꢀtheseꢀwake-upꢀmethodsꢀwillꢀinitiateꢀaꢀresetꢀoperation,ꢀtheꢀactualꢀsourceꢀ

ofꢀtheꢀwake-upꢀcanꢀbeꢀdeterminedꢀbyꢀexaminingꢀtheꢀTOꢀandꢀPDFꢀﬂags.ꢀTheꢀPDFꢀﬂagꢀisꢀclearedꢀbyꢀaꢀ

systemꢀpower-upꢀorꢀexecutingꢀtheꢀclearꢀWatchdogꢀTimerꢀinstructionsꢀandꢀisꢀsetꢀwhenꢀexecutingꢀtheꢀ

"HALT"ꢀinstruction.ꢀTheꢀTOꢀﬂagꢀisꢀsetꢀifꢀaꢀWDTꢀtime-outꢀoccurs,ꢀandꢀcausesꢀaꢀwake-upꢀthatꢀonlyꢀ

resetsꢀtheꢀProgramꢀCounterꢀandꢀStackꢀPointer,ꢀtheꢀotherꢀﬂagsꢀremainꢀinꢀtheirꢀoriginalꢀstatus.

EachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀusingꢀtheꢀPAWUꢀregisterꢀtoꢀpermitꢀaꢀnegativeꢀtransitionꢀonꢀtheꢀpinꢀ

toꢀwake-upꢀtheꢀsystem.ꢀWhenꢀaꢀPortꢀAꢀpinꢀwake-upꢀoccurs,ꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀ

theꢀinstructionꢀfollowingꢀtheꢀ"HALT"ꢀinstruction.ꢀIfꢀtheꢀsystemꢀisꢀwokenꢀupꢀbyꢀanꢀinterrupt,ꢀthenꢀ

twoꢀpossibleꢀsituationsꢀmayꢀoccur.ꢀTheꢀﬁrstꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀdisabledꢀorꢀtheꢀinterruptꢀ

isꢀenabledꢀbutꢀtheꢀstackꢀisꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀprogramꢀwillꢀresumeꢀexecutionꢀatꢀtheꢀinstructionꢀ

followingꢀtheꢀ"HALT"ꢀinstruction.ꢀInꢀthisꢀsituation,ꢀtheꢀinterruptꢀwhichꢀwoke-upꢀtheꢀdeviceꢀwillꢀnotꢀ

beꢀimmediatelyꢀserviced,ꢀbutꢀwillꢀratherꢀbeꢀservicedꢀlaterꢀwhenꢀtheꢀrelatedꢀinterruptꢀisꢀﬁnallyꢀenabledꢀ

orꢀwhenꢀaꢀstackꢀlevelꢀbecomesꢀfree.ꢀTheꢀotherꢀsituationꢀisꢀwhereꢀtheꢀrelatedꢀinterruptꢀisꢀenabledꢀandꢀ

theꢀstackꢀisꢀnotꢀfull,ꢀinꢀwhichꢀcaseꢀtheꢀregularꢀinterruptꢀresponseꢀtakesꢀplace.ꢀIfꢀanꢀinterruptꢀrequestꢀ

flagꢀisꢀsetꢀhighꢀbeforeꢀenteringꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀtheꢀwake-upꢀfunctionꢀofꢀtheꢀrelatedꢀ

interruptꢀwillꢀbeꢀdisabled.

Rev. 1.41

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April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Watchdog Timer

TheꢀWatchdogꢀTimerꢀisꢀprovidedꢀtoꢀpreventꢀprogramꢀmalfunctionsꢀorꢀsequencesꢀfromꢀjumpingꢀtoꢀ

unknownꢀlocations,ꢀdueꢀtoꢀcertainꢀuncontrollableꢀexternalꢀeventsꢀsuchꢀasꢀelectricalꢀnoise.

Watchdog Timer Clock Source

TheꢀWatchdogꢀTimerꢀclockꢀsourceꢀisꢀprovidedꢀbyꢀtheꢀinternalꢀf_LIRCꢀclockꢀwhichꢀisꢀsuppliedꢀbyꢀtheꢀ

LIRCꢀoscillator.ꢀTheꢀWatchdogꢀTimerꢀsourceꢀclockꢀisꢀthenꢀsubdividedꢀbyꢀaꢀratioꢀofꢀ2⁸ꢀtoꢀ2¹⁵ꢀtoꢀgiveꢀ

longerꢀtimeouts,ꢀtheꢀactualꢀvalueꢀbeingꢀchosenꢀusingꢀtheꢀWS2~WS0ꢀbitsꢀinꢀtheꢀWDTCꢀregister.ꢀTheꢀ

LIRCꢀinternalꢀoscillatorꢀhasꢀanꢀapproximateꢀperiodꢀofꢀ32kHzꢀatꢀaꢀsupplyꢀvoltageꢀofꢀ5V.ꢀHowever,ꢀitꢀ

shouldꢀbeꢀnotedꢀthatꢀthisꢀspeciﬁedꢀinternalꢀclockꢀperiodꢀcanꢀvaryꢀwithꢀV_DD,ꢀtemperatureꢀandꢀprocessꢀ

variations.ꢀTheꢀWDTꢀcanꢀbeꢀenabled/disabledꢀusingꢀtheꢀWDTCꢀregister.

Watchdog Timer Control Register

Aꢀsingleꢀregister,ꢀWDTC,ꢀcontrolsꢀtheꢀrequiredꢀtimeoutꢀperiodꢀasꢀwellꢀasꢀtheꢀenable/disableꢀ

operation.ꢀTheꢀWRFꢀsoftwareꢀresetꢀﬂagꢀwillꢀbeꢀindicatedꢀinꢀtheꢀSMOD1ꢀregister.ꢀTheseꢀregistersꢀ

controlꢀtheꢀoverallꢀoperationꢀofꢀtheꢀWatchdogꢀTimer.

WDTC Register

Bit

Name

R/W

7

6

5

4

3

2

1

0

WE4

R/W

0

WE3

R/W

1

WE2

R/W

0

WE1

R/W

1

WE0

R/W

0

WS2

R/W

0

WS1

R/W

1

WS0

R/W

1

POR

Bitꢀ7~ꢀ3

WE4 ~ WE0:ꢀWDTꢀfunctionꢀsoftwareꢀcontrol

10101:ꢀWDTꢀdisable

01010:ꢀWDTꢀenableꢀ

Otherꢀvalues:ꢀResetꢀMCUꢀ

Whenꢀtheseꢀbitsꢀareꢀchangedꢀtoꢀanyꢀotherꢀvaluesꢀbyꢀtheꢀenvironmentalꢀnoiseꢀtoꢀresetꢀ

theꢀmicrocontroller,ꢀtheꢀresetꢀoperationꢀwillꢀbeꢀactivatedꢀafterꢀ2~3ꢀLIRCꢀclockꢀcyclesꢀ

andꢀtheꢀWRFꢀbitꢀwillꢀbeꢀsetꢀtoꢀ1toꢀindicateꢀtheꢀresetꢀsource.

Bitꢀ2~ꢀ0

WS2 ~ WS0:ꢀWDTꢀTime-outꢀperiodꢀselection

000:ꢀ2⁸/ꢀf_LIRC

001:ꢀ2⁹/f_LIRC

010:ꢀ2¹⁰/f_LIRC

011:ꢀ2¹¹/f_LIRCꢀ(default)

100:ꢀ2¹²/f_LIRC

101:ꢀ2¹³/f_LIRC

110:ꢀ2¹⁴/f_LIRC

111:ꢀ2¹⁵/f_LIRC

TheseꢀthreeꢀbitsꢀdetermineꢀtheꢀdivisionꢀratioꢀofꢀtheꢀWatchdogꢀTimerꢀsoureceꢀclock,ꢀ

whichꢀinꢀturnꢀdeterminesꢀtheꢀtimeoutꢀperiod.

SMOD1 Register

Bit

7

6

5

4

3

D3

R/W

0

2

LVRF

R/W

x

1

0

WRF

Name

R/W

FSYSON

—

R/W

0

R/W

POR

0

"x" unknown

Bitꢀ7ꢀ

FSYSON:ꢀf_SYSꢀControlꢀinꢀIDLEꢀMode

0:ꢀDisable

1:ꢀEnable

Rev. 1.41

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April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Bitꢀ6~4ꢀ

Bitꢀ3

Unimplemented,ꢀreadꢀasꢀ"0"

D3:ꢀReservedꢀbit

Bitꢀ2

LVRF:ꢀLVRꢀfunctionꢀresetꢀﬂag

0:ꢀNotꢀactive

1:ꢀActive

Thisꢀbitꢀcanꢀbeꢀclearꢀtoꢀ"0",ꢀbutꢀcanꢀnotꢀbeꢀsetꢀtoꢀ"1".

Unimplemented,ꢀreadꢀasꢀ"0"

Bitꢀ1ꢀ

Bitꢀ0

WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀﬂag

0:ꢀNotꢀoccur

1:ꢀOccurred

Thisꢀbitꢀisꢀsetꢀtoꢀ1ꢀbyꢀtheꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀandꢀclearedꢀbyꢀtheꢀ

applicationꢀprogram.ꢀNoteꢀthatꢀthisꢀbitꢀcanꢀonlyꢀbeꢀclearedꢀtoꢀ0ꢀbyꢀtheꢀapplicationꢀ

program.

Watchdog Timer Operation

TheꢀWatchdogꢀTimerꢀoperatesꢀbyꢀprovidingꢀaꢀdeviceꢀresetꢀwhenꢀitsꢀtimerꢀoverﬂows.ꢀThisꢀmeansꢀ

thatꢀinꢀtheꢀapplicationꢀprogramꢀandꢀduringꢀnormalꢀoperationꢀtheꢀuserꢀhasꢀtoꢀstrategicallyꢀclearꢀtheꢀ

WatchdogꢀTimerꢀbeforeꢀitꢀoverﬂowsꢀtoꢀpreventꢀtheꢀWatchdogꢀTimerꢀfromꢀexecutingꢀaꢀreset.ꢀThisꢀisꢀ

doneꢀusingꢀtheꢀclearꢀwatchdogꢀinstructions.ꢀIfꢀtheꢀprogramꢀmalfunctionsꢀforꢀwhateverꢀreason,ꢀjumpsꢀ

toꢀanꢀunknownꢀlocation,ꢀorꢀentersꢀanꢀendlessꢀloop,ꢀtheꢀclearꢀWDTꢀinstructionsꢀwillꢀnotꢀbeꢀexecutedꢀ

inꢀtheꢀcorrectꢀmanner,ꢀinꢀwhichꢀcaseꢀtheꢀWatchdogꢀTimerꢀwillꢀoverﬂowꢀandꢀresetꢀtheꢀdevice.ꢀWithꢀ

regardꢀtoꢀtheꢀWatchdogꢀTimerꢀenable/disableꢀfunction,ꢀthereꢀareꢀﬁveꢀbits,ꢀWE4~WE0,ꢀinꢀtheꢀWDTCꢀ

registerꢀtoꢀadditionalꢀenable/disableꢀandꢀresetꢀcontrolꢀofꢀtheꢀWatchdogꢀTimer.ꢀ

WE4 ~ WE0 Bits

10101B

WDT Function

Disable

01010B

Enable

Any other value

Reset MCU

Watchdog Timer Enable/Disable Control

Underꢀnormalꢀprogramꢀoperation,ꢀaꢀWatchdogꢀTimerꢀtime-outꢀwillꢀinitialiseꢀaꢀdeviceꢀresetꢀandꢀsetꢀ

theꢀstatusꢀbitꢀTO.ꢀHowever,ꢀifꢀtheꢀsystemꢀisꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀMode,ꢀwhenꢀaꢀWatchdogꢀTimerꢀ

time-outꢀoccurs,ꢀtheꢀTOꢀbitꢀinꢀtheꢀstatusꢀregisterꢀwillꢀbeꢀsetꢀandꢀonlyꢀtheꢀProgramꢀCounterꢀandꢀStackꢀ

Pointerꢀwillꢀbeꢀreset.ꢀFourꢀmethodsꢀcanꢀbeꢀadoptedꢀtoꢀclearꢀtheꢀcontentsꢀofꢀtheꢀWatchdogꢀTimer.ꢀ

TheꢀﬁrstꢀisꢀaꢀWDTꢀreset,ꢀwhichꢀmeansꢀaꢀvalueꢀotherꢀthanꢀ01010Bꢀandꢀ10101Bꢀisꢀwrittenꢀintoꢀtheꢀ

WE4~WE0ꢀbitꢀlocations,ꢀtheꢀsecondꢀisꢀanꢀexternalꢀhardwareꢀreset,ꢀwhichꢀmeansꢀaꢀlowꢀlevelꢀonꢀtheꢀ

externalꢀresetꢀpin,ꢀtheꢀthirdꢀisꢀusingꢀtheꢀWatchdogꢀTimerꢀsoftwareꢀclearꢀinstructionsꢀandꢀtheꢀfourthꢀ

isꢀviaꢀaꢀHALTꢀinstruction.ꢀThereꢀisꢀonlyꢀoneꢀmethodꢀofꢀusingꢀsoftwareꢀinstructionꢀtoꢀclearꢀtheꢀ

WatchdogꢀTimer.ꢀThatꢀisꢀtoꢀuseꢀtheꢀsingleꢀ"CLRꢀWDT"ꢀinstructionꢀtoꢀclearꢀtheꢀWDT.

Theꢀmaximumꢀtime-outꢀperiodꢀisꢀwhenꢀtheꢀ2¹⁵ꢀdivisionꢀratioꢀisꢀselected.ꢀAsꢀanꢀexample,ꢀwithꢀaꢀ32kHz

ꢀ

LIRCꢀoscillatorꢀasꢀitsꢀsourceꢀclock,ꢀthisꢀwillꢀgiveꢀaꢀmaximumꢀwatchdogꢀperiodꢀofꢀaroundꢀ1ꢀsecondꢀ

forꢀtheꢀ2¹⁵ꢀdivisionꢀratio,ꢀandꢀaꢀminimumꢀtimeoutꢀofꢀ7.8msꢀforꢀtheꢀ2⁸ꢀdivisionꢀration.

Rev. 1.41

44

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

WDTC Register

WE4~WE0 bits

Reset MCU

CLR

RES pin reset

“CLR WDT”Instruction

“HALT”Instruction

f_LIRC

LIRC

11-stage Divider

7-stage Divider

WDT Time-out

(2⁸/f_LIRC~ 2¹⁵/f_LIRC

)

8-to-1 MUX

WS2~WS0

(f_LIRC/2¹~ f_LIRC/2¹¹

)

Watchdog Timer

Reset and Initialisation

Aꢀresetꢀfunctionꢀisꢀaꢀfundamentalꢀpartꢀofꢀanyꢀmicrocontrollerꢀensuringꢀthatꢀtheꢀdevicesꢀcanꢀbeꢀsetꢀ

toꢀsomeꢀpredeterminedꢀconditionꢀirrespectiveꢀofꢀoutsideꢀparameters.ꢀTheꢀmostꢀimportantꢀresetꢀ

conditionꢀisꢀafterꢀpowerꢀisꢀﬁrstꢀappliedꢀtoꢀtheꢀmicrocontroller.ꢀInꢀthisꢀcase,ꢀinternalꢀcircuitryꢀwillꢀ

ensureꢀthatꢀtheꢀmicrocontroller,ꢀafterꢀaꢀshortꢀdelay,ꢀwillꢀbeꢀinꢀaꢀwellꢀdefinedꢀstateꢀandꢀreadyꢀtoꢀ

executeꢀtheꢀﬁrstꢀprogramꢀinstruction.ꢀAfterꢀthisꢀpower-onꢀreset,ꢀcertainꢀimportantꢀinternalꢀregistersꢀ

willꢀbeꢀsetꢀtoꢀdeﬁnedꢀstatesꢀbeforeꢀtheꢀprogramꢀcommences.ꢀOneꢀofꢀtheseꢀregistersꢀisꢀtheꢀProgramꢀ

Counter,ꢀwhichꢀwillꢀbeꢀresetꢀtoꢀzeroꢀforcingꢀtheꢀmicrocontrollerꢀtoꢀbeginꢀprogramꢀexecutionꢀfromꢀtheꢀ

lowestꢀProgramꢀMemoryꢀaddress.ꢀ

Inꢀadditionꢀtoꢀtheꢀpower-onꢀreset,ꢀsituationsꢀmayꢀariseꢀwhereꢀitꢀisꢀnecessaryꢀtoꢀforcefullyꢀapplyꢀ

aꢀresetꢀconditionꢀwhenꢀtheꢀmicrocontrollerꢀisꢀrunning.ꢀOneꢀexampleꢀofꢀthisꢀisꢀwhereꢀafterꢀpowerꢀ

hasꢀbeenꢀappliedꢀandꢀtheꢀmicrocontrollerꢀisꢀalreadyꢀrunning,ꢀtheꢀRESꢀlineꢀisꢀforcefullyꢀpulledꢀlow.ꢀ

Inꢀsuchꢀaꢀcase,ꢀknownꢀasꢀaꢀnormalꢀoperationꢀreset,ꢀsomeꢀofꢀtheꢀmicrocontrollerꢀregistersꢀremainꢀ

unchangedꢀallowingꢀtheꢀmicrocontrollerꢀtoꢀproceedꢀwithꢀnormalꢀoperationꢀafterꢀtheꢀresetꢀlineꢀisꢀ

allowedꢀtoꢀreturnꢀhigh.ꢀ

AnotherꢀtypeꢀofꢀresetꢀisꢀwhenꢀtheꢀWatchdogꢀTimerꢀoverflowsꢀandꢀresetsꢀtheꢀmicrocontroller.ꢀAllꢀ

typesꢀofꢀresetꢀoperationsꢀresultꢀinꢀdifferentꢀregisterꢀconditionsꢀbeingꢀsetup.ꢀAnotherꢀresetꢀexistsꢀinꢀtheꢀ

formꢀofꢀaꢀLowꢀVoltageꢀReset,ꢀLVR,ꢀwhereꢀaꢀfullꢀresetꢀisꢀimplementedꢀinꢀsituationsꢀwhereꢀtheꢀpowerꢀ

supplyꢀvoltageꢀfallsꢀbelowꢀaꢀcertainꢀthreshold.ꢀ

Reset Functions

Thereꢀareꢀseveralꢀwaysꢀinꢀwhichꢀaꢀmicrocontrollerꢀresetꢀcanꢀoccur,ꢀthroughꢀeventsꢀoccurringꢀbothꢀ

internallyꢀandꢀexternally:

Rev. 1.41

45

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Power-on Reset

Theꢀmostꢀfundamentalꢀandꢀunavoidableꢀresetꢀisꢀtheꢀoneꢀthatꢀoccursꢀafterꢀpowerꢀisꢀﬁrstꢀappliedꢀtoꢀ

theꢀmicrocontroller.ꢀAsꢀwellꢀasꢀensuringꢀthatꢀtheꢀProgramꢀMemoryꢀbeginsꢀexecutionꢀfromꢀtheꢀﬁrstꢀ

memoryꢀaddress,ꢀaꢀpower-onꢀresetꢀalsoꢀensuresꢀthatꢀcertainꢀotherꢀregistersꢀareꢀpresetꢀtoꢀknownꢀ

conditions.ꢀAllꢀtheꢀI/Oꢀportꢀandꢀportꢀcontrolꢀregistersꢀwillꢀpowerꢀupꢀinꢀaꢀhighꢀconditionꢀensuringꢀthatꢀ

allꢀpinsꢀwillꢀbeꢀﬁrstꢀsetꢀtoꢀinputs.

V

D

0

.

V

D

9

D

R

S

E

t

R

T

S

D

+

t

S

T

t

n

r

e

n

a

R

e

l

e

s

t

Note:ꢀt_RSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=50ms

Power-On Reset Timing Chart

RES Pin Reset

AlthoughꢀtheꢀmicrocontrollerꢀhasꢀanꢀinternalꢀRCꢀresetꢀfunction,ꢀifꢀtheꢀV_DDꢀpowerꢀsupplyꢀriseꢀtimeꢀ

isꢀnotꢀfastꢀenoughꢀorꢀdoesꢀnotꢀstabiliseꢀquicklyꢀatꢀpower-on,ꢀtheꢀinternalꢀresetꢀfunctionꢀmayꢀbeꢀ

incapableꢀofꢀprovidingꢀproperꢀresetꢀoperation.ꢀForꢀthisꢀreasonꢀitꢀisꢀrecommendedꢀthatꢀanꢀexternalꢀ

RCꢀnetworkꢀisꢀconnectedꢀtoꢀtheꢀRESꢀpin,ꢀwhoseꢀadditionalꢀtimeꢀdelayꢀwillꢀensureꢀthatꢀtheꢀRESꢀpinꢀ

remainsꢀlowꢀforꢀanꢀextendedꢀperiodꢀtoꢀallowꢀtheꢀpowerꢀsupplyꢀtoꢀstabilise.ꢀDuringꢀthisꢀtimeꢀdelay,ꢀ

normalꢀoperationꢀofꢀtheꢀmicrocontrollerꢀwillꢀbeꢀinhibited.ꢀAfterꢀtheꢀRESꢀlineꢀreachesꢀaꢀcertainꢀ

voltageꢀvalue,ꢀtheꢀresetꢀdelayꢀtimeꢀt_RSTDꢀisꢀinvokedꢀtoꢀprovideꢀanꢀextraꢀdelayꢀtimeꢀafterꢀwhichꢀtheꢀ

microcontrollerꢀwillꢀbeginꢀnormalꢀoperation.ꢀTheꢀabbreviationꢀSSTꢀinꢀtheꢀﬁguresꢀstandsꢀforꢀSystemꢀ

Start-upꢀTimer.

ForꢀmostꢀapplicationsꢀaꢀresistorꢀconnectedꢀbetweenꢀV_DDꢀandꢀtheꢀRESꢀpinꢀandꢀaꢀcapacitorꢀconnectedꢀ

betweenꢀVSSꢀandꢀtheꢀRESꢀpinꢀwillꢀprovideꢀaꢀsuitableꢀexternalꢀresetꢀcircuit.ꢀAnyꢀwiringꢀconnectedꢀ

toꢀtheꢀRESꢀpinꢀshouldꢀbeꢀkeptꢀasꢀshortꢀasꢀpossibleꢀtoꢀminimizeꢀanyꢀstrayꢀnoiseꢀinterference.ꢀForꢀ

applicationsꢀthatꢀoperateꢀwithinꢀanꢀenvironmentꢀwhereꢀmoreꢀnoiseꢀisꢀpresentꢀtheꢀEnhancedꢀResetꢀ

Circuitꢀshownꢀisꢀrecommended.

V

D

0

.

m

0

F

*

1

*

V

D

1

4

N

1

*

4

8

1

k

0

W

~

1

0

W

0

k

R

S

E

/

7

P

A

3

0

W

*

0

.

1

F

~

V

S

Note:ꢀ"*"ꢀItꢀisꢀrecommendedꢀthatꢀthisꢀcomponentꢀisꢀaddedꢀforꢀaddedꢀESDꢀprotection

"**"ꢀItꢀisꢀrecommendedꢀthatꢀthisꢀcomponentꢀisꢀaddedꢀinꢀenvironmentsꢀwhereꢀpowerꢀlineꢀ

noiseisꢀsigniﬁcant

External RES Circuit

PullingꢀtheꢀRESꢀPinꢀlowꢀusingꢀexternalꢀhardwareꢀwillꢀalsoꢀexecuteꢀaꢀdeviceꢀreset.ꢀInꢀthisꢀcase,ꢀasꢀinꢀ

theꢀcaseꢀofꢀotherꢀresets,ꢀtheꢀProgramꢀCounterꢀwillꢀresetꢀtoꢀzeroꢀandꢀprogramꢀexecutionꢀinitiatedꢀfromꢀ

thisꢀpoint.

Rev. 1.41

46

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

0

.

V

D

9

D

0

.

V

D

4

D

R

S

E

t

R

T

S

D

+

t

S

T

t

n

r

e

n

a

R

e

l

e

s

t

Note:ꢀt_RSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=16.7ms

RES Reset Timing Chart

• RSTC External Reset Register

Bit

Name

R/W

7

RSTC7

R/W

0

6

RSTC6

R/W

1

5

RSTC5

R/W

0

4

RSTC4

R/W

1

3

2

1

RSTC1

R/W

0

RSTC0

R/W

1

RSTC3

RSTC2

R

0

R

1

POR

Bitꢀ7ꢀ~ꢀ0

RSTC7 ~ RSTC0:ꢀPA7/RESꢀselection

01010101:ꢀconﬁguredꢀasꢀPA7ꢀpinꢀorꢀotherꢀfunction

10101010:ꢀconﬁguredꢀasꢀRESꢀpin

OtherꢀValues:ꢀInhibitꢀtoꢀuse

AllꢀresetꢀwillꢀresetꢀthisꢀregisterꢀasꢀPORꢀvalueꢀexceptꢀWDTꢀtimeꢀoutꢀHardwareꢀwarmꢀreset.

Low Voltage Reset – LVR

Theꢀmicrocontrollerꢀcontainsꢀaꢀlowꢀvoltageꢀresetꢀcircuitꢀinꢀorderꢀtoꢀmonitorꢀtheꢀsupplyꢀvoltageꢀofꢀ

theꢀdeviceꢀandꢀprovideꢀanꢀMCUꢀresetꢀshouldꢀtheꢀvalueꢀfallꢀbelowꢀaꢀcertainꢀpredeﬁnedꢀlevel.ꢀTheꢀ

LVRꢀfunctionꢀisꢀalwaysꢀenabledꢀduringꢀtheꢀnormalꢀandꢀslowꢀmodesꢀwithꢀaꢀspeciﬁcꢀLVRꢀvoltageꢀ

V_LVR.ꢀIfꢀtheꢀsupplyꢀvoltageꢀofꢀtheꢀdeviceꢀdropsꢀtoꢀwithinꢀaꢀrangeꢀofꢀ0.9V~V_LVRꢀsuchꢀasꢀmightꢀoccurꢀ

whenꢀchangingꢀtheꢀbattery,ꢀtheꢀLVRꢀwillꢀautomaticallyꢀresetꢀtheꢀdeviceꢀinternallyꢀandꢀtheꢀLVRFꢀ

bitꢀinꢀtheꢀSMOD1ꢀregisterꢀwillꢀalsoꢀbeꢀsetꢀto1.ꢀForꢀaꢀvalidꢀLVRꢀsignal,ꢀaꢀlowꢀvoltage,ꢀi.e.,ꢀaꢀvoltageꢀ

inꢀtheꢀrangeꢀbetweenꢀ0.9V~ꢀV_LVRꢀmustꢀexistꢀforꢀgreaterꢀthanꢀtheꢀvalueꢀt_LVRꢀspecifiedꢀinꢀtheꢀA.C.ꢀ

characteristics.ꢀIfꢀtheꢀlowꢀvoltageꢀstateꢀdoesꢀnotꢀexceedꢀthisꢀvalue,ꢀtheꢀLVRꢀwillꢀignoreꢀtheꢀlowꢀ

supplyꢀvoltageꢀandꢀwillꢀnotꢀperformꢀaꢀresetꢀfunction.ꢀTheꢀactualꢀV_LVRꢀisꢀ2.1V,ꢀtheꢀLVRꢀwillꢀresetꢀtheꢀ

deviceꢀafterꢀ2~3ꢀLIRCꢀclockꢀcycles.ꢀNoteꢀthatꢀtheꢀLVRꢀfunctionꢀwillꢀbeꢀautomaticallyꢀdisabledꢀwhenꢀ

theꢀdeviceꢀentersꢀtheꢀSLEEP/IDLEꢀmode.

L

R

V

t

R

T

S

D

+

t

S

T

I

n

r

n

t

a

e

R

e

l

e

s

t

Note:t_RSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=50ms

Low Voltage Reset Timing Chart

• SMOD1 Register

Bit

Name

R/W

7

6

5

4

3

D3

R/W

0

2

LVRF

R/W

x

1

0

WRF

FSYSON

—

R/W

0

R/W

POR

0

"x" unknown

Bitꢀ7ꢀ

FSYSON:ꢀf_SYSꢀControlꢀinꢀIDLEꢀMode

Describeꢀelsewhere

Bitꢀ6~4ꢀ

Bitꢀ3

Unimplemented,ꢀreadꢀasꢀ"0"

D3:ꢀReservedꢀbit

Rev. 1.41

47

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Bitꢀ2

LVRF:ꢀLVRꢀfunctionꢀresetꢀﬂag

0:ꢀNotꢀactive

1:ꢀActive

Thisꢀbitꢀcanꢀbeꢀclearꢀtoꢀ"0",ꢀbutꢀcanꢀnotꢀbeꢀsetꢀtoꢀ"1".

Unimplemented,ꢀreadꢀasꢀ"0"

Bitꢀ1ꢀ

Bitꢀ0

WRF:ꢀWDTꢀControlꢀregisterꢀsoftwareꢀresetꢀﬂag

Describeꢀelsewhere

Watchdog Time-out Reset during Normal Operation

TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀnormalꢀoperationꢀisꢀtheꢀsameꢀasꢀanꢀLVRꢀresetꢀexceptꢀthatꢀtheꢀ

Watchdogꢀtime-outꢀﬂagꢀTOꢀwillꢀbeꢀsetꢀtoꢀ"1".

W

T

D

m

T

-

i

e

u

o

t

R

T

S

D

+

t

S

T

I

n

r

n

t

a

e

R

e

l

e

s

t

Note:ꢀt_RSTDꢀisꢀpower-onꢀdelay,ꢀtypicalꢀtime=16.7ms

WDT Time-out Reset during Normal Operation Timing Chart

Watchdog Time-out Reset during SLEEP or IDLE Mode

TheꢀWatchdogꢀtime-outꢀResetꢀduringꢀSLEEPꢀorꢀIDLEꢀModeꢀisꢀaꢀlittleꢀdifferentꢀfromꢀotherꢀkindsꢀ

ofꢀreset.ꢀMostꢀofꢀtheꢀconditionsꢀremainꢀunchangedꢀexceptꢀthatꢀtheꢀProgramꢀCounterꢀandꢀtheꢀStackꢀ

Pointerꢀwillꢀbeꢀclearedꢀtoꢀ"0"ꢀandꢀtheꢀTOꢀﬂagꢀwillꢀbeꢀsetꢀtoꢀ"1".ꢀReferꢀtoꢀtheꢀA.C.ꢀCharacteristicsꢀforꢀ

t_SSTꢀdetails.

W

T

D

m

T

-

i

e

u

o

t

S

T

I

n

r

n

t

a

e

R

e

l

e

s

t

WDT Time-out Reset during SLEEP or IDLE Timing Chart

Reset Initial Conditions

Theꢀdifferentꢀtypesꢀofꢀresetꢀdescribedꢀaffectꢀtheꢀresetꢀﬂagsꢀinꢀdifferentꢀways.ꢀTheseꢀﬂags,ꢀknownꢀ

asꢀPDFꢀandꢀTOꢀareꢀlocatedꢀinꢀtheꢀstatusꢀregisterꢀandꢀareꢀcontrolledꢀbyꢀvariousꢀmicrocontrollerꢀ

operations,ꢀsuchꢀasꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀfunctionꢀorꢀWatchdogꢀTimer.ꢀTheꢀresetꢀflagsꢀareꢀ

shownꢀinꢀtheꢀtable:

TO

0

PDF

RESET Conditions

0

u

1

Power-on reset

u

LVR reset during NORMAL or SLOW Mode operation

WDT time-out reset during NORMAL or SLOW Mode operation

WDT time-out reset during IDLE or SLEEP Mode operation

1

Note:ꢀ"u"ꢀstandsꢀforꢀunchanged

Theꢀfollowingꢀtableꢀindicatesꢀtheꢀwayꢀinꢀwhichꢀtheꢀvariousꢀcomponentsꢀofꢀtheꢀmicrocontrollerꢀareꢀ

affectedꢀafterꢀaꢀpower-onꢀresetꢀoccurs.

Item

Program Counter

Condition After RESET

Reset to zero

Interrupts

All interrupts will be disabled

WDT

Clear after reset, WDT begins counting

Timer Modules will be turned off

Timer Modules

Input/Output Ports

Stack Pointer

I/O ports will be setup as inputs

Stack Pointer will point to the top of the stack

Rev. 1.41

48

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Theꢀdifferentꢀkindsꢀofꢀresetsꢀallꢀaffectꢀtheꢀinternalꢀregistersꢀofꢀtheꢀmicrocontrollerꢀinꢀdifferentꢀways.ꢀ

Toꢀensureꢀreliableꢀcontinuationꢀofꢀnormalꢀprogramꢀexecutionꢀafterꢀaꢀresetꢀoccurs,ꢀitꢀisꢀimportantꢀtoꢀ

knowꢀwhatꢀconditionꢀtheꢀmicrocontrollerꢀisꢀinꢀafterꢀaꢀparticularꢀresetꢀoccurs.ꢀTheꢀfollowingꢀtableꢀ

describesꢀhowꢀeachꢀtypeꢀofꢀresetꢀaffectsꢀeachꢀofꢀtheꢀmicrocontrollerꢀinternalꢀregisters.ꢀNoteꢀthatꢀ

whereꢀmoreꢀthanꢀoneꢀpackageꢀtypeꢀexistsꢀtheꢀtableꢀwillꢀreﬂectꢀtheꢀsituationꢀforꢀtheꢀlargerꢀpackageꢀ

type.

WDT Time-out

(Normal

Operation)

RES Reset

(Normal

Operation)

Reset

(Power On)

RES Reset

(HALT)

WDT Time-out

(HALT)*

Register

Program

Counter

●

000H

MP0

●

1 x x x x x x x

- - - - - - - 0

x x x x x x x x

0000 0000

x x x x x x x x

- - x x x x x x

- - 0 0 x x x x

0 0 0 - 0 0 11

- - 0 0 - 0 0 0

- - - - - - 0 0

- 0 0 0 0 0 0 0

- - 0 0 - - 0 0

0 - 0 0 0 - 0 0

- - 0 0 - - 0 0

1111 1111

0000 0000

- - 0 0 - - 0 0

0 0 0 0 0 - 0 0

0 1 0 1 0 0 11

0 0 11 - 111

0 - - - 0 x - 0

- - - 0 0 0 0 0

0000 0000

0101 0101

- 0 - 0 - 0 - 0

0 0 0 - - - - -

- - 0 0 0 0 0 -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

1 x x x x x x x

- - - - - - - 0

uuuu uuuu

0000 0000

uuuu uuuu

- - u u u u u u

- - 1 u u u u u

0 0 0 - 0 0 11

- - 0 0 - 0 0 0

- - - - - - 0 0

- 0 0 0 0 0 0 0

- - 0 0 - - 0 0

0 - 0 0 0 - 0 0

- - 0 0 - - 0 0

1111 1111

0000 0000

- - 0 0 - - 0 0

0 0 0 0 0 - 0 0

0 1 0 1 0 0 11

0 0 11 - 111

0 - - - 0 x - 0

- - - 0 0 0 0 0

0000 0000

0101 0101

- 0 - 0 - 0 - 0

0 0 0 - - - - -

- - 0 0 0 0 0 -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

1 x x x x x x x

- - - - - - - 0

uuuu uuuu

0000 0000

uuuu uuuu

- - u u u u u u

0 0 0 - 0 0 11

- - 0 0 - 0 0 0

- - - - - - 0 0

- 0 0 0 0 0 0 0

- - 0 0 - - 0 0

0 - 0 0 0 - 0 0

- - 0 0 - - 0 0

1111 1111

0000 0000

- - 0 0 - - 0 0

0 0 0 0 0 - 0 0

0 1 0 1 0 0 11

0 0 11 - 111

0 - - - 0 x - 0

- - - 0 0 0 0 0

0000 0000

0101 0101

- 0 - 0 - 0 - 0

0 0 0 - - - - -

- - 0 0 0 0 0 -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

1 x x x x x x x

- - - - - - - 0

uuuu uuuu

0000 0000

uuuu uuuu

- - u u u u u u

- - 0 1 u u u u

0 0 0 - 0 0 11

- - 0 0 - 0 0 0

- - - - - - 0 0

- 0 0 0 0 0 0 0

- - 0 0 - - 0 0

0 - 0 0 0 - 0 0

- - 0 0 - - 0 0

1111 1111

0000 0000

- - 0 0 - - 0 0

0 0 0 0 0 - 0 0

0 1 0 1 0 0 11

0 0 11 - 111

0 - - - 0 x - 0

- - - 0 0 0 0 0

0000 0000

0101 0101

- 0 - 0 - 0 - 0

0 0 0 - - - - -

- - 0 0 0 0 0 -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

1uuu uuuu

- - - - - - - u

uuuu uuuu

0000 0000

uuuu uuuu

- - u u u u u u

- - 11 u u u u

u u u - u u u u

- - u u - u u u

- - - - - - u u

- u u u u u u u

- - u u - - u u

u - u u u - u u

- - u u - - u u

uuuu uuuu

- - u u - - u u

u u u u u - u u

uuuu uuuu

uuuu –uuu

u - - - u u - u

- - - u u u u u

uuuu uuuu

- u - u - u - u

u u u - - - - -

- - u u u u u -

uuuu uuuu

- - - - - - u u

uuuu uuuu

- - - - - - u u

MP1

BP

ACC

PCL

TBLP

TBLH

STATUS

SMOD

LVDC

INTEG

INTC0

INTC1

●

MFI0

MFI1

PA

●

PAC

PAPU

PAWU

IFS0

●

WDTC

TBC

●

SMOD1

EEA

EED

RSTC

PASR

●

PBSR

STM0C0

STM0C1

STM0DL

STM0DH

STM0AL

STM0AH

●

Rev. 1.41

49

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

WDT Time-out

(Normal

Operation)

RES Reset

(Normal

Operation)

Reset

(Power On)

RES Reset

(HALT)

WDT Time-out

(HALT)*

Register

PB

●

- - 1 1 1 1 1 1

- - 0 0 0 0 0 0

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

- - - - 0 0 0 0

- - 1 1 1 1 1 1

- - 0 0 0 0 0 0

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

- - - - 0 0 0 0

- - 1 1 1 1 1 1

- - 0 0 0 0 0 0

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

- - - - 0 0 0 0

- - 1 1 1 1 1 1

- - 0 0 0 0 0 0

0 0 0 0 0 - - -

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

0000 0000

- - - - - - 0 0

- - - - 0 0 0 0

- - u u u u u u

u u u u u - - -

uuuu uuuu

- - - - - - u u

uuuu uuuu

- - - - - - u u

uuuu uuuu

- - - - - - u u

- - - - u u u u

PBC

PBPU

PTM1C0

PTM1C1

PTM1DL

PTM1DH

PTM1AL

PTM1AH

PTM1RPL

PTM1RPH

EEC

●

Note:ꢀ"*"ꢀstandsꢀforꢀwarmꢀreset

"-"ꢀnotꢀimplemented

"u"ꢀstandsꢀforꢀ"unchanged"

"x"ꢀstandsꢀforꢀ"unknown"

Input/Output Ports

HoltekꢀmicrocontrollersꢀofferꢀconsiderableꢀﬂexibilityꢀonꢀtheirꢀI/Oꢀports.ꢀWithꢀtheꢀinputꢀorꢀoutputꢀ

designationꢀofꢀeveryꢀpinꢀfullyꢀunderꢀuserꢀprogramꢀcontrol,ꢀpull-highꢀselectionsꢀforꢀallꢀportsꢀandꢀ

wake-upꢀselectionsꢀonꢀcertainꢀpins,ꢀtheꢀuserꢀisꢀprovidedꢀwithꢀanꢀI/Oꢀstructureꢀtoꢀmeetꢀtheꢀneedsꢀofꢀaꢀ

wideꢀrangeꢀofꢀapplicationꢀpossibilities.ꢀ

Theꢀdevicesꢀprovideꢀbidirectionalꢀinput/outputꢀlinesꢀlabeledꢀwithꢀportꢀnamesꢀPAꢀandꢀPB.ꢀTheseꢀI/Oꢀ

portsꢀareꢀmappedꢀtoꢀtheꢀRAMꢀDataꢀMemoryꢀwithꢀspeciﬁcꢀaddressesꢀasꢀshownꢀinꢀtheꢀSpecialꢀPurposeꢀ

DataꢀMemoryꢀtable.ꢀAllꢀofꢀtheseꢀI/Oꢀportsꢀcanꢀbeꢀusedꢀforꢀinputꢀandꢀoutputꢀoperations.ꢀForꢀinputꢀ

operation,ꢀtheseꢀportsꢀareꢀnon-latching,ꢀwhichꢀmeansꢀtheꢀinputsꢀmustꢀbeꢀreadyꢀatꢀtheꢀT2ꢀrisingꢀedgeꢀ

ofꢀinstructionꢀ"MOVꢀA,ꢀ[m]",ꢀwhereꢀmꢀdenotesꢀtheꢀportꢀaddress.ꢀForꢀoutputꢀoperation,ꢀallꢀtheꢀdataꢀisꢀ

latchedꢀandꢀremainsꢀunchangedꢀuntilꢀtheꢀoutputꢀlatchꢀisꢀrewritten.

I/O Control Register List

• HT68F002/HT68F0025

Bit

Register

Name

7

6

D6

5

4

D4

3

2

D2

1

0

D0

PA

D7

—

D5

—

D3

—

D1

—

PAC

D6

D4

D2

D0

PAPU

PAWU

PASR

IFS0

D6

D4

D2

D0

D6

D4

D2

D0

PAS6

—

PAS4

PAS2

—

PAS0

—

STCK0PS STP0IPS

—

INTPS1 INTPS0

Rev. 1.41

50

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

• HT68F003

Bit

4

Register

Name

7

D7

—

6

D6

—

5

D5

3

D3

—

2

D2

—

1

D1

—

0

PA

D4

—

D0

—

PAC

D5

PAPU

PAWU

PB

D5

PBC

—

D5

PBPU

PASR

PBSR

IFS0

—

D5

PAS7

—

PAS6

—

PAS5

PBS5

PBS4

PBS3

PBS2

—

PBS1

—

PTCK1PS1 PTCK1PS0 STCK0PS STP0IPS PTP1IPS

INTPS1 INTPS0

Pull-high Resistors

Manyꢀproductꢀapplicationsꢀrequireꢀpull-highꢀresistorsꢀforꢀtheirꢀswitchꢀinputsꢀusuallyꢀrequiringꢀtheꢀ

useꢀofꢀanꢀexternalꢀresistor.ꢀToꢀeliminateꢀtheꢀneedꢀforꢀtheseꢀexternalꢀresistors,ꢀallꢀI/Oꢀpins,ꢀwhenꢀ

conﬁguredꢀasꢀanꢀinputꢀhaveꢀtheꢀcapabilityꢀofꢀbeingꢀconnectedꢀtoꢀanꢀinternalꢀpull-highꢀresistor.ꢀTheseꢀ

pull-highꢀresistorsꢀareꢀselectedꢀusingꢀregisterꢀPAPU~PBPU,ꢀandꢀareꢀimplementedꢀusingꢀweakꢀPMOSꢀ

transistors.

PAPU Register

Bit

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

2

D2

R/W

0

1

D1

R/W

0

D0

R/W

0

Name

R/W

POR

Bitꢀ7ꢀ~ꢀ0ꢀ

I/OꢀPortꢀAꢀbit7~ꢀbitꢀ0ꢀPull-HighꢀControl

0:ꢀDisable

1:ꢀEnable

PBPU Register – HT68F003 only

Bit

Name

R/W

7

6

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

2

D2

R/W

0

1

D1

R/W

0

D0

R/W

0

—

POR

Bitꢀ7~6ꢀ

Bitꢀ5~0ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

I/OꢀPortꢀBꢀbit5~ꢀbitꢀ0ꢀPull-HighꢀControl

0:ꢀDisable

1:ꢀEnable

Rev. 1.41

51

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Port A Wake-up

TheꢀHALTꢀinstructionꢀforcesꢀtheꢀmicrocontrollerꢀintoꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀwhichꢀpreservesꢀ

power,ꢀaꢀfeatureꢀthatꢀisꢀimportantꢀforꢀbatteryꢀandꢀotherꢀlow-powerꢀapplications.ꢀVariousꢀmethodsꢀ

existꢀtoꢀwake-upꢀtheꢀmicrocontroller,ꢀoneꢀofꢀwhichꢀisꢀtoꢀchangeꢀtheꢀlogicꢀconditionꢀonꢀoneꢀofꢀtheꢀPortꢀ

Aꢀpinsꢀfromꢀhighꢀtoꢀlow.ꢀThisꢀfunctionꢀisꢀespeciallyꢀsuitableꢀforꢀapplicationsꢀthatꢀcanꢀbeꢀwokenꢀupꢀ

viaꢀexternalꢀswitches.ꢀEachꢀpinꢀonꢀPortꢀAꢀcanꢀbeꢀselectedꢀindividuallyꢀtoꢀhaveꢀthisꢀwake-upꢀfeatureꢀ

usingꢀtheꢀPAWUꢀregister.

PAWU Register

Bit

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

2

D2

R/W

0

1

D1

R/W

0

D0

R/W

0

Name

R/W

POR

Bitꢀ7ꢀ~ꢀ0ꢀ

I/OꢀPortꢀAꢀbitꢀ7ꢀ~ꢀbitꢀ0ꢀWakeꢀUpꢀControl

0:ꢀDisable

1:ꢀEnable

I/O Port Control Registers

EachꢀI/OꢀportꢀhasꢀitsꢀownꢀcontrolꢀregisterꢀknownꢀasꢀPAC~PBC,ꢀtoꢀcontrolꢀtheꢀinput/outputꢀ

configuration.ꢀWithꢀtheseꢀcontrolꢀregisters,ꢀeachꢀCMOSꢀoutputꢀorꢀinputꢀcanꢀbeꢀreconfiguredꢀ

dynamicallyꢀunderꢀsoftwareꢀcontrol.ꢀEachꢀpinꢀofꢀtheꢀI/Oꢀportsꢀisꢀdirectlyꢀmappedꢀtoꢀaꢀbitꢀinꢀitsꢀ

associatedꢀportꢀcontrolꢀregister.ꢀForꢀtheꢀI/Oꢀpinꢀtoꢀfunctionꢀasꢀanꢀinput,ꢀtheꢀcorrespondingꢀbitꢀofꢀtheꢀ

controlꢀregisterꢀmustꢀbeꢀwrittenꢀasꢀaꢀ"1".ꢀThisꢀwillꢀthenꢀallowꢀtheꢀlogicꢀstateꢀofꢀtheꢀinputꢀpinꢀtoꢀbeꢀ

directlyꢀreadꢀbyꢀinstructions.ꢀWhenꢀtheꢀcorrespondingꢀbitꢀofꢀtheꢀcontrolꢀregisterꢀisꢀwrittenꢀasꢀaꢀ"0",ꢀ

theꢀI/OꢀpinꢀwillꢀbeꢀsetupꢀasꢀaꢀCMOSꢀoutput.ꢀIfꢀtheꢀpinꢀisꢀcurrentlyꢀsetupꢀasꢀanꢀoutput,ꢀinstructionsꢀ

canꢀstillꢀbeꢀusedꢀtoꢀreadꢀtheꢀoutputꢀregister.ꢀHowever,ꢀitꢀshouldꢀbeꢀnotedꢀthatꢀtheꢀprogramꢀwillꢀinꢀfactꢀ

onlyꢀreadꢀtheꢀstatusꢀofꢀtheꢀoutputꢀdataꢀlatchꢀandꢀnotꢀtheꢀactualꢀlogicꢀstatusꢀofꢀtheꢀoutputꢀpin.

PAC Register

Bit

7

D7

R/W

1

6

D6

R/W

1

5

D5

R/W

1

4

D4

R/W

1

3

D3

R/W

1

2

D2

R/W

1

D1

R/W

1

0

D0

R/W

1

Name

R/W

POR

Bitꢀ7ꢀ~ꢀ0ꢀ

I/OꢀPortꢀAꢀbitꢀ7ꢀ~ꢀbitꢀ0ꢀInput/OutputꢀControl

0:ꢀOutput

1:ꢀInput

PBC Register – HT68F003 only

Bit

Name

R/W

7

6

5

D5

R/W

1

4

D4

R/W

1

3

D3

R/W

1

2

D2

R/W

1

D1

R/W

1

0

D0

R/W

1

—

POR

Bitꢀ7ꢀ~ꢀ6ꢀ

Bitꢀ5ꢀ~ꢀ0ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

I/OꢀPortꢀBꢀbitꢀ5ꢀ~ꢀbitꢀ0ꢀInput/OutputꢀControl

0:ꢀOutput

1:ꢀInput

Rev. 1.41

52

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Pin-Shared Functions

Theꢀﬂexibilityꢀofꢀtheꢀmicrocontrollerꢀrangeꢀisꢀgreatlyꢀenhancedꢀbyꢀtheꢀuseꢀofꢀpinsꢀthatꢀhaveꢀmoreꢀ

thanꢀoneꢀfunction.ꢀLimitedꢀnumbersꢀofꢀpinsꢀcanꢀforceꢀseriousꢀdesignꢀconstraintsꢀonꢀdesignersꢀbutꢀ

byꢀsupplyingꢀpinsꢀwithꢀmulti-functions,ꢀmanyꢀofꢀtheseꢀdifficultiesꢀcanꢀbeꢀovercome.ꢀTheꢀwayꢀinꢀ

whichꢀtheꢀpinꢀfunctionꢀofꢀeachꢀpinꢀisꢀselectedꢀisꢀdifferentꢀforꢀeachꢀfunctionꢀandꢀaꢀpriorityꢀorderꢀisꢀ

establishedꢀwhereꢀmoreꢀthanꢀoneꢀpinꢀfunctionꢀisꢀselectedꢀsimultaneously.ꢀAdditionallyꢀthereꢀareꢀ

aꢀPASRꢀandꢀaꢀPBSRꢀregisterꢀtoꢀestablishꢀcertainꢀpinꢀfunctions.ꢀGenerallyꢀspeaking,ꢀtheꢀanalogꢀ

functionꢀhasꢀhigherꢀpriorityꢀthanꢀtheꢀdigitalꢀfunction.ꢀHowever,ꢀifꢀmoreꢀthanꢀtwoꢀanalogꢀfunctionsꢀ

areꢀenabledꢀandꢀtheꢀanalogꢀsignalꢀinputꢀcomesꢀfromꢀtheꢀsameꢀexternalꢀpin,ꢀtheꢀanalogꢀinputꢀwillꢀbeꢀ

internallyꢀconnectedꢀtoꢀallꢀofꢀtheseꢀactiveꢀanalogꢀfunctionalꢀmodules.

Pin-shared Registers

Theꢀlimitedꢀnumberꢀofꢀsuppliedꢀpinsꢀinꢀaꢀpackageꢀcanꢀimposeꢀrestrictionsꢀonꢀtheꢀamountꢀofꢀfunctionsꢀ

aꢀcertainꢀdeviceꢀcanꢀcontain.ꢀHoweverꢀbyꢀallowingꢀtheꢀsameꢀpinsꢀtoꢀshareꢀseveralꢀdifferentꢀfunctionsꢀ

andꢀprovidingꢀaꢀmeansꢀofꢀfunctionꢀselection,ꢀaꢀwideꢀrangeꢀofꢀdifferentꢀfunctionsꢀcanꢀbeꢀincorporatedꢀ

intoꢀevenꢀrelativelyꢀsmallꢀpackageꢀsizes.

• PASR Register – HT68F002/HT68F0025

Bit

Name

R/W

7

6

PAS6

R/W

0

5

4

PAS4

R/W

0

3

2

PAS2

R/W

0

1

0

PAS0

R/W

0

—

POR

Bitꢀ7ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

Bitꢀ6

PAS6:ꢀPin-SharedꢀControlꢀBit

0:ꢀPA5/INT

1:ꢀSTP0B

Bitꢀ5ꢀ

Bitꢀ4

Unimplemented,ꢀreadꢀasꢀ"0"

PAS4:ꢀPin-SharedꢀControlꢀBits

0:ꢀPA2/INT

1:ꢀSTP0

Bitꢀ3ꢀ

Bitꢀ2

Unimplemented,ꢀreadꢀasꢀ"0"

PAS2:ꢀPin-SharedꢀControlꢀBit

0:ꢀPA1

1:ꢀSTP0B

Bitꢀ1ꢀ

Bitꢀ0

Unimplemented,ꢀreadꢀasꢀ"0"

PAS0:ꢀPin-SharedꢀControlꢀBit

0:ꢀPA0/STP0I

1:ꢀSTP0

Rev. 1.41

53

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

• PASR Register – HT68F003

Bit

Name

R/W

7

PAS7

R/W

0

6

PAS6

R/W

0

5

PAS5

R/W

0

4

3

2

1

0

—

POR

Bitꢀ7

PAS7:ꢀPin-SharedꢀControlꢀBit

0:ꢀPA7/PTCK1

1:ꢀSTP0B

Note:ꢀPAS7ꢀisꢀvalidꢀwhenꢀRSTC=55H

Bitꢀ6

Bitꢀ5

PAS6:ꢀPin-SharedꢀControlꢀBit

0:ꢀPA6/PTCK1/STP0I

1:ꢀSTP0

PAS5:ꢀPin-SharedꢀControlꢀBit

0:ꢀPA4/INT/PTCK1

1:ꢀSTP0

Bitꢀ4~0ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

• PBSR Register – HT68F003 only

Bit

Name

R/W

7

6

5

PBS5

R/W

0

4

PBS4

R/W

0

3

PBS3

R/W

0

2

PBS2

R/W

0

1

PBS1

R/W

0

—

POR

Bitꢀ7~6ꢀ

Bitꢀ5

Unimplemented,ꢀreadꢀasꢀ"0"

PBS5: Pin-SharedꢀControlꢀBit

0:ꢀPB5

1:ꢀPTP1

Bitꢀ4

Bitꢀ3

Bitꢀ2

Bitꢀ1

Bitꢀ0ꢀ

PBS4: Pin-SharedꢀControlꢀBit

0:ꢀPB4

1:ꢀPTP1B

PBS3: Pin-SharedꢀControlꢀBit

0:ꢀPB3

1:ꢀPTP1

PBS2: Pin-SharedꢀControlꢀBit

0:ꢀPB2

1:ꢀPTP1B

PBS1: Pin-SharedꢀControlꢀBit

0:ꢀPB1/PTCK1

1:ꢀSTP0B

Unimplemented,ꢀreadꢀasꢀ"0"

Rev. 1.41

54

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

• IFS0 Register – HT68F002/HT68F0025

Bit

Name

R/W

7

6

5

4

3

2

1

INTPS1

R/W

0

INTPS0

R/W

0

—

STCK0PS STP0IPS

—

R/W

0

R/W

0

POR

Bitꢀ7~6ꢀ

Bitꢀ5

Unimplemented,ꢀreadꢀasꢀ"0"ꢀ

STCK0PS:ꢀSTCK0ꢀPinꢀRemappingꢀControl

0:ꢀSTCK0ꢀonꢀPA7ꢀ(default)

1:ꢀSTCK0ꢀonꢀPA6

Bitꢀ4

STP0IPS:ꢀSTP0IꢀPinꢀRemappingꢀControl

0:ꢀSTP0IꢀonꢀPA6ꢀ(default)

1:ꢀSTP0IꢀonꢀPA0

Bitꢀ3~2ꢀ

Bitꢀ1~0

Unimplemented,ꢀreadꢀasꢀ"0"ꢀ

INTPS1, INTPS0:ꢀINTꢀPinꢀRemappingꢀControl

00:ꢀINTꢀonꢀPA5ꢀ(default)

01:ꢀINTꢀonꢀPA2

10:ꢀINTꢀonꢀPA3

11:ꢀINTꢀonꢀPA7

• IFS0 Register – HT68F003

Bit

Name PTCK1PS1 PTCK1PS0 STCK0PS STP0IPS PTP1IPS

7

6

5

4

3

2

1

INTPS1

R/W

0

INTPS0

R/W

0

—

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7~6

PTCK1PS1, PTCK1PS0:ꢀPTCK1ꢀPinꢀRemappingꢀControlꢀ

00:ꢀPTCK1ꢀonꢀPA4ꢀ(default)

01:ꢀPTCK1ꢀonꢀPA6

10:ꢀPTCK1ꢀonꢀPA7

11:ꢀPTCK1ꢀonꢀPB1

Bitꢀ5

Bitꢀ4

Bitꢀ3

STCK0PS:ꢀSTCK0ꢀPinꢀRemappingꢀControlꢀ

0:ꢀSTCK0ꢀonꢀPA3ꢀ(default)

1:ꢀSTCK0ꢀonꢀPA2

STP0IPS: STP0IꢀPinꢀRemappingꢀControl

0:ꢀSTP0IꢀonꢀPA6ꢀ(default)

1:ꢀSTP0IꢀonꢀPA0

PTP1IPS: PTP1IꢀPinꢀRemappingꢀControlꢀ

0:ꢀPTP1IꢀonꢀPA5ꢀ(default)

1:ꢀPTP1IꢀonꢀPB0

Bitꢀ2ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

Bitꢀ1~0

INTPS1, INTPS0:ꢀINTꢀPinꢀRemappingꢀControlꢀ

00:ꢀINTꢀonꢀPA3ꢀ(default)

01:ꢀINTꢀonꢀPA2

10:ꢀINTꢀonꢀPA4

11:ꢀINTꢀonꢀPA5

Rev. 1.41

55

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

I/O Pin Structures

TheꢀaccompanyingꢀdiagramsꢀillustrateꢀtheꢀinternalꢀstructuresꢀofꢀsomeꢀgenericꢀI/Oꢀpinꢀtypes.ꢀAsꢀ

theꢀexactꢀlogicalꢀconstructionꢀofꢀtheꢀI/Oꢀpinꢀwillꢀdifferꢀfromꢀtheseꢀdrawings,ꢀtheyꢀareꢀsuppliedꢀasꢀaꢀ

guideꢀonlyꢀtoꢀassistꢀwithꢀtheꢀfunctionalꢀunderstandingꢀofꢀtheꢀI/Oꢀpins.ꢀTheꢀwideꢀrangeꢀofꢀpin-sharedꢀ

structuresꢀdoesꢀnotꢀpermitꢀallꢀtypesꢀtoꢀbeꢀshown.

V

D

P

l

u

-

l

i

H

h

g

R

S

g

e

s

i

e

t

r

C

n

o

r

t

l

o

B

t

i

l

e

c

e

t

W

a

e

k

D

t

a

u

s

B

D

Q

P

l

u

l

-

p

W

i

r

e

t

C

o

n

r

l

o

t

R

g

e

s

i

e

t

r

C

K

Q

S

C

i

h

p

R

e

s

t

I

/

O

i

n

p

R

a

e

d

C

o

t

n

o

r

l

R

e

i

g

t

s

r

e

D

t

a

B

i

t

D

Q

W

i

r

e

t

D

t

a

e

s

g

R

e

t

i

r

C

K

Q

S

M

U

X

R

e

a

D

d

t

a

e

s

g

R

e

t

i

r

S

y

e

s

t

m

W

a

e

k

-

u

p

P

A

n

y

l

o

W

k

a

-

e

p

u

S

l

e

c

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t

Generic Input/Output Structure

Programming Considerations

Withinꢀtheꢀuserꢀprogram,ꢀoneꢀofꢀtheꢀﬁrstꢀthingsꢀtoꢀconsiderꢀisꢀportꢀinitialisation.ꢀAfterꢀaꢀreset,ꢀallꢀofꢀ

theꢀI/Oꢀdataꢀandꢀportꢀcontrolꢀregistersꢀwillꢀbeꢀsetꢀhigh.ꢀThisꢀmeansꢀthatꢀallꢀI/Oꢀpinsꢀwillꢀdefaultꢀtoꢀ

anꢀinputꢀstate,ꢀtheꢀlevelꢀofꢀwhichꢀdependsꢀonꢀtheꢀotherꢀconnectedꢀcircuitryꢀandꢀwhetherꢀpull-highꢀ

selectionsꢀhaveꢀbeenꢀchosen.ꢀIfꢀtheꢀportꢀcontrolꢀregisterꢀisꢀthenꢀprogrammedꢀtoꢀsetupꢀsomeꢀpinsꢀ

asꢀoutputs,ꢀtheseꢀoutputꢀpinsꢀwillꢀhaveꢀanꢀinitialꢀhighꢀoutputꢀvalueꢀunlessꢀtheꢀassociatedꢀportꢀdataꢀ

registerꢀisꢀﬁrstꢀprogrammed.ꢀSelectingꢀwhichꢀpinsꢀareꢀinputsꢀandꢀwhichꢀareꢀoutputsꢀcanꢀbeꢀachievedꢀ

byte-wideꢀbyꢀloadingꢀtheꢀcorrectꢀvaluesꢀintoꢀtheꢀappropriateꢀportꢀcontrolꢀregisterꢀorꢀbyꢀprogrammingꢀ

individualꢀbitsꢀinꢀtheꢀportꢀcontrolꢀregisterꢀusingꢀtheꢀ"SETꢀ[m].i"ꢀandꢀ"CLRꢀ[m].i"ꢀinstructions.ꢀ

Noteꢀthatꢀwhenꢀusingꢀtheseꢀbitꢀcontrolꢀinstructions,ꢀaꢀread-modify-writeꢀoperationꢀtakesꢀplace.ꢀTheꢀ

microcontrollerꢀmustꢀﬁrstꢀreadꢀinꢀtheꢀdataꢀonꢀtheꢀentireꢀport,ꢀmodifyꢀitꢀtoꢀtheꢀrequiredꢀnewꢀbitꢀvaluesꢀ

andꢀthenꢀrewriteꢀthisꢀdataꢀbackꢀtoꢀtheꢀoutputꢀports.

PortꢀAꢀhasꢀtheꢀadditionalꢀcapabilityꢀofꢀprovidingꢀwake-upꢀfunctions.ꢀWhenꢀtheꢀdeviceꢀisꢀinꢀtheꢀ

SLEEPꢀorꢀIDLEꢀMode,ꢀvariousꢀmethodsꢀareꢀavailableꢀtoꢀwakeꢀtheꢀdeviceꢀup.ꢀOneꢀofꢀtheseꢀisꢀaꢀhighꢀ

toꢀlowꢀtransitionꢀofꢀanyꢀofꢀtheꢀPortꢀAꢀpins.ꢀSingleꢀorꢀmultipleꢀpinsꢀonꢀPortꢀAꢀcanꢀbeꢀsetupꢀtoꢀhaveꢀthisꢀ

function.

Rev. 1.41

56

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Timer Modules – TM

Oneꢀofꢀtheꢀmostꢀfundamentalꢀfunctionsꢀinꢀanyꢀmicrocontrollerꢀdeviceꢀisꢀtheꢀabilityꢀtoꢀcontrolꢀandꢀ

measureꢀtime.ꢀToꢀimplementꢀtimeꢀrelatedꢀfunctionsꢀtheꢀdevicesꢀincludeꢀseveralꢀTimerꢀModules,ꢀ

abbreviatedꢀtoꢀtheꢀnameꢀTM.ꢀTheꢀTMsꢀareꢀmulti-purposeꢀtimingꢀunitsꢀandꢀserveꢀtoꢀprovideꢀ

operationsꢀsuchꢀasꢀTimer/Counter,ꢀInputꢀCapture,ꢀCompareꢀMatchꢀOutputꢀandꢀSingleꢀPulseꢀOutputꢀ

asꢀwellꢀasꢀbeingꢀtheꢀfunctionalꢀunitꢀforꢀtheꢀgenerationꢀofꢀPWMꢀsignals.ꢀEachꢀofꢀtheꢀTMsꢀhasꢀtwoꢀ

individualꢀinterrupts.ꢀTheꢀadditionꢀofꢀinputꢀandꢀoutputꢀpinsꢀforꢀeachꢀTMꢀensuresꢀthatꢀusersꢀareꢀ

providedꢀwithꢀtimingꢀunitsꢀwithꢀaꢀwideꢀandꢀﬂexibleꢀrangeꢀofꢀfeatures.ꢀ

TheꢀcommonꢀfeaturesꢀofꢀtheꢀdifferentꢀTMꢀtypesꢀareꢀdescribedꢀhereꢀwithꢀmoreꢀdetailedꢀinformationꢀ

providedꢀinꢀtheꢀindividualꢀStandardꢀandꢀPeriodicꢀTMꢀsections.

Introduction

TheꢀdevicesꢀcontainꢀoneꢀorꢀtwoꢀTMsꢀdependingꢀuponꢀwhichꢀdeviceꢀisꢀselectedꢀwithꢀeachꢀTMꢀhavingꢀ

aꢀreferenceꢀnameꢀofꢀTM0~TM1.ꢀEachꢀindividualꢀTMꢀcanꢀbeꢀcategorisedꢀasꢀaꢀcertainꢀtype,ꢀnamelyꢀ

StandardꢀTypeꢀTMꢀorꢀPeriodicꢀTypeꢀTM.ꢀAlthoughꢀsimilarꢀinꢀnature,ꢀtheꢀdifferentꢀTMꢀtypesꢀvaryꢀinꢀ

theirꢀfeatureꢀcomplexity.ꢀTheꢀcommonꢀfeaturesꢀtoꢀtheꢀStandardꢀandꢀPeriodicꢀTMsꢀwillꢀbeꢀdescribedꢀ

inꢀthisꢀsectionꢀandꢀtheꢀdetailedꢀoperationꢀwillꢀbeꢀdescribedꢀinꢀcorrespondingꢀsections.ꢀTheꢀmainꢀ

featuresꢀandꢀdifferencesꢀbetweenꢀtheꢀtwoꢀtypesꢀofꢀTMsꢀareꢀsummarisedꢀinꢀtheꢀaccompanyingꢀtable.

Function

Timer/Counter

STM

PTM

√

I/P Capture

√

Compare Match Output

PWM Channels

√

1

Single Pulse Output

PWM Alignment

1

Edge

PWM Adjustment Period & Duty

Duty or Period

TM Function Summary

TM0

Device

TM1

—

HT68F002/HT68F0025

HT68F003

10-bit STM

10-bit PTM

TM Name/Type Reference

TM Operation

TheꢀtwoꢀdifferentꢀtypesꢀofꢀTMsꢀofferꢀaꢀdiverseꢀrangeꢀofꢀfunctions,ꢀfromꢀsimpleꢀtimingꢀoperationsꢀ

toꢀPWMꢀsignalꢀgeneration.ꢀTheꢀkeyꢀtoꢀunderstandingꢀhowꢀtheꢀTMꢀoperatesꢀisꢀtoꢀseeꢀitꢀinꢀtermsꢀofꢀ

aꢀfreeꢀrunningꢀcounterꢀwhoseꢀvalueꢀisꢀthenꢀcomparedꢀwithꢀtheꢀvalueꢀofꢀpre-programmedꢀinternalꢀ

comparators.ꢀWhenꢀtheꢀfreeꢀrunningꢀcounterꢀhasꢀtheꢀsameꢀvalueꢀasꢀtheꢀpre-programmedꢀcomparator,ꢀ

knownꢀasꢀaꢀcompareꢀmatchꢀsituation,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀbeꢀgeneratedꢀwhichꢀcanꢀclearꢀtheꢀ

counterꢀandꢀperhapsꢀalsoꢀchangeꢀtheꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin.ꢀTheꢀinternalꢀTMꢀcounterꢀisꢀ

drivenꢀbyꢀaꢀuserꢀselectableꢀclockꢀsource,ꢀwhichꢀcanꢀbeꢀanꢀinternalꢀclockꢀorꢀanꢀexternalꢀpin.ꢀ

TM Clock Source

TheꢀclockꢀsourceꢀwhichꢀdrivesꢀtheꢀmainꢀcounterꢀinꢀeachꢀTMꢀcanꢀoriginateꢀfromꢀvariousꢀsources.ꢀ

TheꢀselectionꢀofꢀtheꢀrequiredꢀclockꢀsourceꢀisꢀimplementedꢀusingꢀtheꢀxTnCK2~xTnCK0ꢀbitsꢀinꢀtheꢀ

xTMꢀcontrolꢀregisters.ꢀTheꢀclockꢀsourceꢀcanꢀbeꢀaꢀratioꢀofꢀeitherꢀtheꢀsystemꢀclockꢀf_SYSꢀorꢀtheꢀinternalꢀ

highꢀclockꢀf_H,ꢀtheꢀf_LꢀclockꢀsourceꢀorꢀtheꢀexternalꢀxTCKnꢀpin.ꢀTheꢀxTCKnꢀpinꢀclockꢀsourceꢀisꢀusedꢀtoꢀ

allowꢀanꢀexternalꢀsignalꢀtoꢀdriveꢀtheꢀTMꢀasꢀanꢀexternalꢀclockꢀsourceꢀorꢀforꢀeventꢀcounting.

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Cost-Effective Flash MCU with EEPROM

TM Interrupts

TheꢀStandardꢀandꢀPeriodicꢀtypeꢀTMsꢀeachꢀhasꢀtwoꢀinternalꢀinterrupts,ꢀtheꢀinternalꢀcomparatorꢀAꢀ

orꢀcomparatorꢀP,ꢀwhichꢀgenerateꢀaꢀTMꢀinterruptꢀwhenꢀaꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀWhenꢀaꢀ

TMꢀinterruptꢀisꢀgenerated,ꢀitꢀcanꢀbeꢀusedꢀtoꢀclearꢀtheꢀcounterꢀandꢀalsoꢀtoꢀchangeꢀtheꢀstateꢀofꢀtheꢀTMꢀ

outputꢀpin.ꢀꢀ

TM External Pins

EachꢀofꢀtheꢀTMs,ꢀirrespectiveꢀofꢀwhatꢀtype,ꢀhasꢀtwoꢀTMꢀinputꢀpins,ꢀwithꢀtheꢀlabelꢀxTCKnꢀandꢀ

xTPnI.ꢀTheꢀTMꢀinputꢀpinꢀxTCKn,ꢀisꢀessentiallyꢀaꢀclockꢀsourceꢀforꢀtheꢀTMꢀandꢀisꢀselectedꢀusingꢀtheꢀ

xTnCK2~xTnCK0ꢀbitsꢀinꢀtheꢀxTMnC0ꢀregister.ꢀThisꢀexternalꢀTMꢀinputꢀpinꢀallowsꢀanꢀexternalꢀclockꢀ

sourceꢀtoꢀdriveꢀtheꢀinternalꢀTM.ꢀThisꢀexternalꢀTMꢀinputꢀpinꢀisꢀsharedꢀwithꢀotherꢀfunctionsꢀbutꢀwillꢀ

beꢀconnectedꢀtoꢀtheꢀinternalꢀTMꢀifꢀselectedꢀusingꢀtheꢀxTnCK2~xTnCK0ꢀbits.ꢀTheꢀTMꢀinputꢀpinꢀcanꢀ

beꢀchosenꢀtoꢀhaveꢀeitherꢀaꢀrisingꢀorꢀfallingꢀactiveꢀedge.

TheꢀotherꢀTMꢀinputꢀpin,ꢀxTPnI,ꢀisꢀtheꢀcaptureꢀinputꢀwhoseꢀactiveꢀedgeꢀcanꢀbeꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀ

edgeꢀorꢀbothꢀrisingꢀandꢀfallingꢀedgesꢀandꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀxTnIO1ꢀ

andꢀxTnIO0ꢀbitsꢀinꢀtheꢀxTMnC1ꢀregister.

TheꢀTMsꢀeachꢀhaveꢀtwoꢀoutputꢀpinsꢀwithꢀtheꢀlabelꢀxTPnꢀandꢀxTPnB.ꢀWhenꢀtheꢀTMꢀisꢀinꢀtheꢀ

CompareꢀMatchꢀOutputꢀMode,ꢀtheseꢀpinsꢀcanꢀbeꢀcontrolledꢀbyꢀtheꢀTMꢀtoꢀswitchꢀtoꢀaꢀhighꢀorꢀlowꢀ

levelꢀorꢀtoꢀtoggleꢀwhenꢀaꢀcompareꢀmatchꢀsituationꢀoccurs.ꢀTheꢀexternalꢀxTPnꢀoutputꢀpinꢀisꢀalsoꢀtheꢀ

pinꢀwhereꢀtheꢀTMꢀgeneratesꢀtheꢀPWMꢀoutputꢀwaveform.ꢀAsꢀtheꢀTMꢀoutputꢀpinsꢀareꢀpin-sharedꢀwithꢀ

otherꢀfunction,ꢀtheꢀTMꢀoutputꢀfunctionꢀmustꢀﬁrstꢀbeꢀsetupꢀusingꢀregisters.ꢀAꢀsingleꢀbitꢀinꢀoneꢀofꢀtheꢀ

registersꢀdeterminesꢀifꢀitsꢀassociatedꢀpinꢀisꢀtoꢀbeꢀusedꢀasꢀanꢀexternalꢀTMꢀoutputꢀpinꢀorꢀifꢀitꢀisꢀtoꢀhaveꢀ

anotherꢀfunction.ꢀTheꢀnumberꢀofꢀoutputꢀpinsꢀforꢀeachꢀTMꢀtypeꢀisꢀdifferent,ꢀtheꢀdetailsꢀareꢀprovidedꢀ

inꢀtheꢀaccompanyingꢀtable.

Device

STM

PTM

STCK0, STP0I

STP0, STP0B

HT68F002/HT68F0025

—

STCK0, STP0I

STP0, STP0B

PTCK1, PTP1I

PTP1, PTP1B

HT68F003

TM Input/Output Pins

TM Input/Output Pin Control

SelectingꢀtoꢀhaveꢀaꢀTMꢀinput/outputꢀorꢀwhetherꢀtoꢀretainꢀitsꢀotherꢀsharedꢀfunctionꢀisꢀimplementedꢀ

usingꢀoneꢀregister,ꢀwithꢀaꢀsingleꢀbitꢀinꢀeachꢀregisterꢀcorrespondingꢀtoꢀaꢀTMꢀinput/outputꢀpin.ꢀ

ConﬁguringꢀtheꢀselectionꢀbitsꢀcorrectlyꢀwillꢀsetupꢀtheꢀcorrespondingꢀpinꢀasꢀaꢀTMꢀinput/output.ꢀTheꢀ

detailsꢀofꢀtheꢀpin-sharedꢀfunctionꢀselectionꢀareꢀdescribedꢀinꢀtheꢀpin-sharedꢀfunctionꢀsection.

STP0B

STP0

Inverting Output

Output

STM

Capture Input

TCK Input

STP0I

STCK0

STM Function Pin Control Block Diagram

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PTP1B

PTP1

Inverting Output

Output

PTM

Capture Input

PTP1I

PTCK1

TCK Input

PTM Function Pin Control Block Diagram

Programming Considerations

TheꢀTMꢀCounterꢀRegistersꢀandꢀtheꢀCapture/CompareꢀCCRAꢀregister,ꢀandꢀCCRPꢀregisterꢀpairꢀforꢀ

PeriodicꢀTimerꢀModule,ꢀallꢀhaveꢀaꢀlowꢀandꢀhighꢀbyteꢀstructure.ꢀTheꢀhighꢀbytesꢀcanꢀbeꢀdirectlyꢀ

accessed,ꢀbutꢀasꢀtheꢀlowꢀbytesꢀcanꢀonlyꢀbeꢀaccessedꢀviaꢀanꢀinternalꢀ8-bitꢀbuffer,ꢀreadingꢀorꢀwritingꢀ

toꢀtheseꢀregisterꢀpairsꢀmustꢀbeꢀcarriedꢀoutꢀinꢀaꢀspeciﬁcꢀway.ꢀTheꢀimportantꢀpointꢀtoꢀnoteꢀisꢀthatꢀdataꢀ

transferꢀtoꢀandꢀfromꢀtheꢀ8-bitꢀbufferꢀandꢀitsꢀrelatedꢀlowꢀbyteꢀonlyꢀtakesꢀplaceꢀwhenꢀaꢀwriteꢀorꢀreadꢀ

operationꢀtoꢀitsꢀcorrespondingꢀhighꢀbyteꢀisꢀexecuted.ꢀ

AsꢀtheꢀCCRAꢀregisterꢀandꢀCCRPꢀregistersꢀareꢀimplementedꢀinꢀtheꢀwayꢀshownꢀinꢀtheꢀfollowingꢀ

diagramꢀandꢀaccessingꢀtheꢀregisterꢀisꢀcarriedꢀoutꢀCCRPꢀlowꢀbyteꢀregisterꢀusingꢀtheꢀfollowingꢀ

accessꢀprocedures.ꢀAccessingꢀtheꢀCCRAꢀorꢀCCRPꢀlowꢀbyteꢀregisterꢀwithoutꢀfollowingꢀtheseꢀaccessꢀ

proceduresꢀwillꢀresultꢀinꢀunpredictableꢀvalues.

PTM Counter Register (Read only)

STM Counter Register (Read only)

PTM1DL PTM1DH

STM0DL STM0DH

8-bit Buffer

PTM1AL

PTM1AH

STM0AL

STM CCRA Register (Read/Write)

Data Bus

STM0AH

PTM CCRA Register (Read/Write)

PTM1RPL PTM1RPH

PTM CCRP Register (Read/Write)

Data Bus

Theꢀfollowingꢀstepsꢀshowꢀtheꢀreadꢀandꢀwriteꢀprocedures:

•ꢀ WritingꢀDataꢀtoꢀCCRAꢀorꢀPTMꢀCCRP

ꢀ

♦

Stepꢀ1.ꢀWriteꢀdataꢀtoꢀLowꢀByteꢀSTM0ALꢀorꢀPTM1RPL

–ꢀnoteꢀthatꢀhereꢀdataꢀisꢀonlyꢀwrittenꢀtoꢀtheꢀ8-bitꢀbuffer.

ꢀ

♦

Stepꢀ2.ꢀWriteꢀdataꢀtoꢀHighꢀByteꢀSTM0AHꢀorꢀPTM1RPH

–ꢀhereꢀdataꢀisꢀwrittenꢀdirectlyꢀtoꢀtheꢀhighꢀbyteꢀregistersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀ

fromꢀtheꢀ8-bitꢀbufferꢀtoꢀtheꢀLowꢀByteꢀregisters.

•ꢀ ReadingꢀDataꢀfromꢀtheꢀCounterꢀRegistersꢀandꢀCCRAꢀorꢀPTMꢀCCRP

ꢀ

♦

Stepꢀ1.ꢀReadꢀdataꢀfromꢀtheꢀHighꢀByteꢀSTM0DH,ꢀSTM0AHꢀorꢀPTM1RPH

–ꢀhereꢀdataꢀisꢀreadꢀdirectlyꢀfromꢀtheꢀHighꢀByteꢀregistersꢀandꢀsimultaneouslyꢀdataꢀisꢀlatchedꢀ

fromꢀtheꢀLowꢀByteꢀregisterꢀintoꢀtheꢀ8-bitꢀbuffer.

ꢀ

♦

Stepꢀ2.ꢀReadꢀdataꢀfromꢀtheꢀLowꢀByteꢀSTM0DL,ꢀSTM0ALꢀorꢀPTM1RPL

–ꢀthisꢀstepꢀreadsꢀdataꢀfromꢀtheꢀ8-bitꢀbuffer.

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Cost-Effective Flash MCU with EEPROM

Standard Type TM – STM

TheꢀStandardꢀTypeꢀTMꢀcontainsꢀﬁveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/

EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀStandardꢀTMꢀcanꢀ

beꢀcontrolledꢀwithꢀtwoꢀexternalꢀinputꢀpinsꢀandꢀcanꢀdriveꢀtwoꢀexternalꢀoutputꢀpins.

Device

TM Type

TM Name

TM Input Pin

TM Output Pin

HT68F002

HT68F0025

HT68F003

10-bit STM

STM

STCK0, STP0I

STP0, STP0B

C

P

R

C

m

o

p

a

r

a

P

t

a

c

M

o

t

h

r

3

-

t

C

b

m

o

i

p

a

r

a

P

t

o

r

S

M

T

0

P

F

n

I

t

r

e

p

u

r

t

b

7

~

b

9

S

0

T

C

O

f

S

Y

/

S

4

0

1

0

1

0

1

0

1

0

1

0

1

0

f

S

Y

S

f

/

6

1

S

T

P

0

O

t

u

p

t

P

l

o

r

a

t

i

y

f

/

4

6

0

C

u

o

n

t

C

l

e

a

r

C

o

n

r

l

o

t

C

o

n

r

l

o

t

1

0

t

-

C

b

u

o

i

n

-

p

u

t

C

u

o

n

t

e

r

S

T

B

P

0

f

T

C

B

1

C

B

S

0

T

C

R

L

S

0

T

O

P

L

S

0

T

M

1

S

T

M

0

S

0

T

N

O

S

C

T

0

K

1

b

0

~

b

9

S

0

T

O

I

,

1

S

0

T

O

I

0

S

0

T

A

P

U

C

m

o

p

a

r

a

A

M

t

o

a

h

c

r

1

0

t

-

b

i

S

M

T

0

A

F

I

t

n

r

e

r

p

u

t

C

m

o

p

a

r

a

A

t

o

r

S

0

T

O

I

,

1

S

0

T

O

I

0

S

0

T

K

C

~

2

T

S

C

0

K

C

A

R

E

d

g

e

S

T

I

P

0

D

t

e

c

e

o

t

r

Standard Type TM Block Diagram

Standard TM Operation

Atꢀitsꢀcoreꢀisꢀaꢀ10-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀinternalꢀclockꢀsource.ꢀ

Thereꢀareꢀalsoꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀnames,ꢀComparatorꢀAꢀandꢀComparatorꢀP.ꢀTheseꢀ

comparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀwithꢀCCRPꢀandꢀCCRAꢀregisters.ꢀTheꢀCCRPꢀisꢀ3-bitꢀ

wideꢀwhoseꢀvalueꢀisꢀcomparedꢀwithꢀtheꢀhighestꢀ3ꢀbitsꢀinꢀtheꢀcounterꢀwhileꢀtheꢀCCRAꢀisꢀtheꢀ10ꢀbitsꢀ

andꢀthereforeꢀcomparesꢀwithꢀallꢀcounterꢀbits.

Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ10-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ

clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀST0ONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ

automaticallyꢀbyꢀaꢀcounterꢀoverﬂowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ

Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀStandardꢀ

TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ

sourcesꢀandꢀcanꢀalsoꢀcontrolꢀanꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀselectedꢀusingꢀrelevantꢀ

internalꢀregisters.

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Standard Type TM Register Description

OverallꢀoperationꢀofꢀtheꢀStandardꢀTMꢀisꢀcontrolledꢀusingꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀ

pairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ10-bitꢀvalue,ꢀwhileꢀaꢀread/writeꢀregisterꢀpairꢀexistsꢀtoꢀstoreꢀ

theꢀinternalꢀ10-bitꢀCCRAꢀvalue.ꢀTheꢀremainingꢀtwoꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀsetupꢀtheꢀ

differentꢀoperatingꢀandꢀcontrolꢀmodesꢀasꢀwellꢀasꢀthreeꢀCCRPꢀbits.

Bit

Register

Name

7

6

5

4

3

2

1

0

STM0C0 ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1

ST0RP0

STM0C1 ST0M1

ST0M0

D6

ST0IO1 ST0IO0

ST0OC ST0POL ST0DPX ST0CCLR

STM0DL

STM0DH

STM0AL

STM0AH

D7

—

D5

—

D4

—

D3

—

D2

—

D1

D9

D1

D9

D0

D8

D0

D8

—

D7

—

D6

D5

—

D4

—

D3

—

D2

—

10-bit Standard TM Register List

STM0C0 Register

Bit

7

6

5

4

3

2

1

0

Name

R/W

ST0PAU ST0CK2 ST0CK1 ST0CK0 ST0ON ST0RP2 ST0RP1 ST0RP0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

POR

bitꢀ7

ST0PAU:ꢀSTMꢀCounterꢀPauseꢀControl

0:ꢀRun

1:ꢀPause

Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ

normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀSTMꢀwillꢀremainꢀpoweredꢀ

upꢀandꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀ

thisꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀ

changesꢀtoꢀaꢀlowꢀvalueꢀagain.

bitꢀ6~4

ST0CK2~ST0CK0:ꢀSelectꢀSTMꢀCounterꢀclock

000:ꢀf_SYS/4

001:ꢀf_SYS

010:ꢀf_H/16

011:ꢀf_H/64

100:ꢀf_TBC

101:ꢀf_TBC

110:ꢀSTCK0ꢀrisingꢀedgeꢀclock

111:ꢀSTCK0ꢀfallingꢀedgeꢀclock

TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀSTM.ꢀTheꢀexternalꢀpinꢀclockꢀ

sourceꢀcanꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀf_SYSꢀisꢀ

theꢀsystemꢀclock,ꢀwhileꢀf_Hꢀandꢀf_TBCꢀareꢀotherꢀinternalꢀclocks,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀ

beꢀfoundꢀinꢀtheꢀoscillatorꢀsection.

bitꢀ3

ST0ON:ꢀSTMꢀCounterꢀOn/OffꢀControl

0:ꢀOff

1:ꢀOn

Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀSTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀ

theꢀcounterꢀtoꢀrun,ꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀSTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀ

stopꢀtheꢀcounterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀSTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀ

consumption.ꢀWhenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀ

willꢀbeꢀresetꢀtoꢀzero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀ

counterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀuntilꢀtheꢀbitꢀreturnsꢀhighꢀagain.ꢀIfꢀtheꢀSTMꢀisꢀinꢀ

theꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀtheꢀPWMꢀoutputꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀ

ModeꢀthenꢀtheꢀSTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀtoꢀitsꢀinitialꢀcondition,ꢀasꢀspeciﬁedꢀbyꢀtheꢀ

ST0OCꢀbit,ꢀwhenꢀtheꢀST0ONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh.

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bitꢀ2~0

ST0RP2~ ST0RP0:ꢀSTMꢀCCRPꢀ3-bitꢀregister,ꢀcomparedꢀwithꢀtheꢀSTMꢀCounterꢀbitꢀ9~bitꢀ7

ComparatorꢀPꢀMatchꢀPeriod

000:ꢀ1024ꢀSTM0ꢀclocks

001:ꢀ128ꢀSTM0ꢀclocks

010:ꢀ256ꢀSTM0ꢀclocks

011:ꢀ384ꢀSTM0ꢀclocks

100:ꢀ512ꢀSTM0ꢀclocks

101:ꢀ640ꢀSTM0ꢀclocks

110:ꢀ768ꢀSTM0ꢀclocks

111:ꢀ896ꢀSTM0ꢀclocks

TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀsetupꢀtheꢀvalueꢀonꢀtheꢀinternalꢀCCRPꢀ3-bitꢀregister,ꢀwhichꢀ

areꢀthenꢀcomparedꢀwithꢀtheꢀinternalꢀcounter’sꢀhighestꢀthreeꢀbits.ꢀTheꢀresultꢀofꢀthisꢀ

comparisonꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀifꢀtheꢀST0CCLRꢀbitꢀisꢀsetꢀtoꢀ

zero.ꢀSettingꢀtheꢀST0CCLRꢀbitꢀtoꢀzeroꢀensuresꢀthatꢀaꢀcompareꢀmatchꢀwithꢀtheꢀCCRPꢀ

valuesꢀwillꢀresetꢀtheꢀinternalꢀcounter.ꢀAsꢀtheꢀCCRPꢀbitsꢀareꢀonlyꢀcomparedꢀwithꢀtheꢀ

highestꢀthreeꢀcounterꢀbits,ꢀtheꢀcompareꢀvaluesꢀexistꢀinꢀ128ꢀclockꢀcycleꢀmultiples.ꢀ

Clearingꢀallꢀthreeꢀbitsꢀtoꢀzeroꢀisꢀinꢀeffectꢀallowingꢀtheꢀcounterꢀtoꢀoverflowꢀatꢀitsꢀ

maximumꢀvalue.

STM0C1 Register

Bit

7

6

ST0M0

R/W

0

5

ST0IO1

R/W

0

4

ST0IO0

R/W

0

3

2

1

0

Name

R/W

ST0M1

R/W

0

ST0OC ST0POL ST0DPX ST0CCLR

R/W

0

R/W

0

R/W

0

R/W

0

POR

bitꢀ7~6

ST0M1~ ST0M0:ꢀSelectꢀSTM0ꢀOperatingꢀMode

00:ꢀCompareꢀMatchꢀOutputꢀMode

01:ꢀCaptureꢀInputꢀMode

10:ꢀPWMꢀoutputꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode

11:ꢀTimer/CounterꢀMode

TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀSTM.ꢀToꢀensureꢀreliableꢀoperationꢀ

theꢀSTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀST0M1ꢀandꢀ

ST0M0ꢀbits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀSTMꢀoutputꢀpinꢀstateꢀisꢀundeﬁned.

bitꢀ5~4

ST0IO1~ ST0IO0:ꢀSelectꢀSTM0ꢀfunction

CompareꢀMatchꢀOutputꢀMode

00:ꢀNoꢀchange

01:ꢀOutputꢀlow

10:ꢀOutputꢀhigh

11:ꢀToggleꢀoutput

PWMꢀoutputꢀMode/SingleꢀPulseꢀOutputꢀMode

00:ꢀPWMꢀOutputꢀinactiveꢀstate

01:ꢀPWMꢀOutputꢀactiveꢀstate

10:ꢀPWMꢀoutput

11:ꢀSingleꢀpulseꢀoutput

CaptureꢀInputꢀMode

00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀSTP0I

01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀSTP0I

10:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀSTP0I

11:ꢀInputꢀcaptureꢀdisabled

Timer/counterꢀMode:

Unused

TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ

certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ

modeꢀtheꢀTMꢀisꢀrunning.ꢀ

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀST0IO1~ST0IO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀ

outputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀTheꢀ

TMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀstateꢀ

whenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheꢀST0IO1~ST0IO0

bitsꢀareꢀbothꢀzero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀ

theꢀTMꢀoutputꢀpinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀST0OCꢀbit.ꢀNoteꢀthatꢀtheꢀoutputꢀlevelꢀ

requestedꢀbyꢀtheꢀST0IO1~ST0IO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀvalueꢀsetupꢀ

usingꢀtheꢀST0OCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀwhenꢀaꢀ

compareꢀmatchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀitꢀcanꢀbeꢀresetꢀtoꢀitsꢀ

initialꢀlevelꢀbyꢀchangingꢀtheꢀlevelꢀofꢀtheꢀST0ONꢀbitꢀfromꢀlowꢀtoꢀhigh.

InꢀtheꢀPWMꢀMode,ꢀtheꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ

changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ

functionꢀisꢀmodiﬁedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀchangeꢀtheꢀvaluesꢀofꢀ

theꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀUnpredictableꢀ

PWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀareꢀchangedꢀwhenꢀtheꢀTMꢀisꢀ

running.

bitꢀ3

ST0OC:ꢀSTM0ꢀOutputꢀcontrolꢀbit

CompareꢀMatchꢀOutputꢀMode

0:ꢀInitialꢀlow

1:ꢀInitialꢀhigh

PWMꢀoutputꢀMode/SingleꢀPulseꢀOutputꢀMode

0:ꢀActiveꢀlow

1:ꢀActiveꢀhigh

ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀSTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ

whetherꢀSTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀoutputꢀ

Mode/ꢀSingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀSTMꢀisꢀinꢀtheꢀTimer/Counterꢀ

Mode.ꢀInꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀSTMꢀ

outputꢀpinꢀbeforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀoutputꢀModeꢀitꢀdeterminesꢀ

ifꢀtheꢀPWMꢀsignalꢀisꢀactiveꢀhighꢀorꢀactiveꢀlow.ꢀInꢀtheꢀSingleꢀPulseꢀOutputꢀModeꢀitꢀ

determinesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀSTMꢀoutputꢀpinꢀwhenꢀtheꢀST0ONꢀbitꢀchangesꢀfromꢀ

lowꢀtoꢀhigh.

bitꢀ2

ST0POL:ꢀSTM0ꢀOutputꢀpolarityꢀControl

0:ꢀNon-invert

1:ꢀInvert

ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀSTM0ꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀSTMꢀ

outputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀ

STMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.

bitꢀ1

bitꢀ0

ST0DPX:ꢀSTM0ꢀPWMꢀperiod/dutyꢀControl

0:ꢀCCRPꢀ–ꢀperiod;ꢀCCRAꢀ–ꢀduty

1:ꢀCCRPꢀ–ꢀduty;ꢀCCRAꢀ–ꢀperiod

Thisꢀbit,ꢀdeterminesꢀwhichꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀforꢀperiodꢀandꢀ

dutyꢀcontrolꢀofꢀtheꢀPWMꢀwaveform.

ST0CCLR:ꢀSelectꢀSTM0ꢀCounterꢀclearꢀcondition

0:ꢀSTM0ꢀComparatorꢀPꢀmatch

1:ꢀSTM0ꢀComparatorꢀAꢀmatch

Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ

StandardꢀSTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ

whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀST0CCLRꢀbitꢀsetꢀhigh,ꢀ

theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ

Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ

theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverﬂow.ꢀAꢀcounterꢀoverﬂowꢀclearingꢀmethodꢀcanꢀ

onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀST0CCLRꢀbitꢀisꢀnotꢀ

usedꢀinꢀtheꢀPWMꢀoutputꢀmode,ꢀSingleꢀPulseꢀorꢀInputꢀCaptureꢀMode.

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

STM0DL Register

Bit

7

6

D6

R

5

D5

R

4

D4

R

3

D3

R

2

D2

R

1

D1

R

0

D0

R

Name

R/W

D7

R

POR

0

Bitꢀ7ꢀ~ꢀ0ꢀ

STM0ꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7ꢀ~ꢀbitꢀ0

STM0ꢀ10-bitꢀCounterꢀbitꢀ7ꢀ~ꢀbitꢀ0

STM0DH Register

Bit

6

5

4

3

2

1

D9

R

7

0

D8

R

Name

R/W

—

0

POR

bitꢀ7~2ꢀ

bitꢀ1~0ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

STM0ꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ1ꢀ~ꢀbitꢀ0

STM0ꢀ10-bitꢀCounterꢀbitꢀ9ꢀ~ꢀbitꢀ8

STM0AL Register

Bit

7

6

D6

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

2

D2

R/W

0

1

D1

R/W

0

D0

R/W

0

Name

R/W

D7

R/W

0

POR

bitꢀ7~0ꢀ

STM0ꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7ꢀ~ꢀbitꢀ0

STM0ꢀ10-bitꢀCounterꢀbitꢀ7ꢀ~ꢀbitꢀ0

STM0AH Register

Bit

7

6

5

4

3

2

1

D9

R/W

0

D8

R/W

0

Name

R/W

—

POR

bitꢀ7~2ꢀ

bitꢀ1~0ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

STM0ꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ1ꢀ~ꢀbitꢀ0

STM0ꢀ10-bitꢀCounterꢀbitꢀ9ꢀ~ꢀbitꢀ8

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Standard Type TM Operating Modes

TheꢀStandardꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀﬁveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ

PWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ

operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀST0M1ꢀandꢀST0M0ꢀbitsꢀinꢀtheꢀSTM0C1ꢀregister.

Compare Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀST0M1ꢀandꢀST0M0ꢀinꢀtheꢀSTM0C1ꢀregister,ꢀshouldꢀbeꢀsetꢀtoꢀ00ꢀ

respectively.ꢀInꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀ

methods.ꢀTheseꢀareꢀaꢀcounterꢀoverﬂow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀ

fromꢀComparatorꢀP.ꢀWhenꢀtheꢀST0CCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀ

cleared.ꢀOneꢀisꢀwhenꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀareꢀallꢀ

zeroꢀwhichꢀallowsꢀtheꢀcounterꢀtoꢀoverﬂow.ꢀHereꢀbothꢀSTMA0FꢀandꢀSTMP0Fꢀinterruptꢀrequestꢀﬂagsꢀ

forꢀComparatorꢀAꢀandꢀComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.ꢀ

IfꢀtheꢀST0CCLRꢀbitꢀinꢀtheꢀSTM0C1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ

matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀSTMA0Fꢀinterruptꢀrequestꢀflagꢀwillꢀ

beꢀgeneratedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀ

whenꢀST0CCLRꢀisꢀhighꢀnoꢀSTMP0Fꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.ꢀInꢀtheꢀCompareꢀ

MatchꢀOutputꢀMode,ꢀtheꢀCCRAꢀcanꢀnotꢀbeꢀsetꢀtoꢀ"0".ꢀIfꢀtheꢀCCRAꢀbitsꢀareꢀallꢀzero,ꢀtheꢀcounterꢀwillꢀ

overﬂowꢀwhenꢀitsꢀreachesꢀitsꢀmaximumꢀ10-bit,ꢀ3FFꢀHex,ꢀvalue,ꢀhoweverꢀhereꢀtheꢀSTMA0Fꢀinterruptꢀ

requestꢀﬂagꢀwillꢀnotꢀbeꢀgenerated.

Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀSTMꢀoutputꢀpin,ꢀwillꢀchangeꢀ

state.ꢀTheꢀSTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀanꢀSTMA0Fꢀinterruptꢀrequestꢀ

ﬂagꢀisꢀgeneratedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀSTMP0Fꢀinterruptꢀrequestꢀ

ﬂag,ꢀgeneratedꢀfromꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀSTMꢀ

outputꢀpin.ꢀTheꢀwayꢀinꢀwhichꢀtheꢀSTMꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀ

theꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀinꢀtheꢀSTM0C1ꢀregister.ꢀTheꢀSTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀ

theꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀ

compareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀSTMꢀoutputꢀpin,ꢀwhichꢀisꢀ

setupꢀafterꢀtheꢀST0ONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀST0OCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀ

ST0IO1ꢀandꢀST0IO0ꢀbitsꢀareꢀzeroꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.

Rev. 1.41

65

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter

overflow

ST0CCLR

= 0; ST0M[1:0] = 00

Counter Value

CCRP > 0

Counter cleared by CCRP value

CCRP = 0

0x3FF

CCRP

CCRA

Counter

Reset

Resume

Pause

CCRP > 0

Stop

Time

ST0ON

ST0PAU

ST0POL

CCRP Int.

Flag

STMP0F

CCRA Int.

Flag

STMA0F

STM O/P Pin

Output inverts

when ST0POL is high

Output not affected by

STMA0F flag. Remains High

until reset by ST0ON bit

Output Pin set

to Initial Level

Low if ST0OC

Output Toggle

with STMA0F flag

Output Pin

Now ST0IO[1:0] = 10

Active High Output

Reset to initial value

= 0

Select

Output controlled

by other pin-shared function

Here ST0IO[1:0] = 11

Toggle Output Select

Compare Match Output Mode – ST0CCLR = 0

Note:ꢀ1.ꢀWithꢀST0CCLRꢀ=ꢀ0ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter

2.ꢀTheꢀTMꢀoutputꢀpinꢀcontrolledꢀonlyꢀbyꢀtheꢀSTMA0Fꢀﬂag

3.ꢀTheꢀoutputꢀpinꢀresetꢀtoꢀinitialꢀstateꢀbyꢀaꢀST0ONꢀbitꢀrisingꢀedge

Rev. 1.41

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April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

ST0CCLR

= 1; ST0M[1:0] = 00

Counter Value

CCRA > 0

Counter cleared by CCRA value

CCRA = 0

Counter overflow

0x3FF

CCRA

CCRP

Resume

CCRA = 0

Counter Reset

Pause

Stop

Time

ST0ON

ST0PAU

ST0POL

No STMA0F flag

generated on

CCRP Int.

CCRA overflow

Flag

STMA0F

CCRA Int.

Flag

STMP0F

Output does

not change

STMP0F not

generated

STM O/P Pin

Output not affected by

Output inverts

when ST0POL is high

Output Pin set

Output Toggle

STMA0F flag. Remains High

until reset by ST0ON bit

Output Pin

to Initial Level

Low if ST0OC

with STMA0F flag

Now ST0IO[1:0] = 10

Active High Output

Reset to initial value

Output controlled

by other pin-shared function

= 0

Select

Here ST0IO[1:0] = 11

Toggle Output Select

Compare Match Output Mode – ST0CCLR = 1

Note:ꢀ1.ꢀWithꢀST0CCLRꢀ=ꢀ1ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter

2.ꢀTheꢀTMꢀoutputꢀpinꢀcontrolledꢀonlyꢀbyꢀtheꢀSTMA0Fꢀﬂag

3.ꢀTheꢀoutputꢀpinꢀresetꢀtoꢀinitialꢀstateꢀbyꢀaꢀST0ONꢀrisingꢀedge

4.ꢀTheꢀSTMP0FꢀﬂagꢀisꢀnotꢀgeneratedꢀwhenꢀST0CCLRꢀ=ꢀ1

Rev. 1.41

67

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Timer/Counter Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀST0M1ꢀandꢀST0M0ꢀinꢀtheꢀSTM0C1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀ

respectively.ꢀTheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀ

Modeꢀgeneratingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀ

STMꢀoutputꢀpinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀ

MatchꢀOutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀSTMꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀ

thisꢀmode,ꢀtheꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunctionꢀbyꢀsettingꢀpinshreꢀ

functionꢀregister.

PWM Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀST0M1ꢀandꢀST0M0ꢀinꢀtheꢀSTM0C1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectivelyꢀ

andꢀalsoꢀtheꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectively.ꢀTheꢀPWMꢀfunctionꢀwithinꢀ

theꢀSTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀsuchꢀasꢀmotorꢀcontrol,ꢀheatingꢀcontrol,ꢀ

illuminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀﬁxedꢀfrequencyꢀbutꢀofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀ

STMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀgeneratedꢀwithꢀvaryingꢀequivalentꢀDCꢀRMSꢀ

values.

AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ

waveformꢀisꢀextremelyꢀﬂexible.ꢀInꢀtheꢀPWMꢀoutputꢀmode,ꢀtheꢀST0CCLRꢀbitꢀhasꢀnoꢀeffectꢀasꢀtheꢀ

PWMꢀperiod.ꢀBothꢀofꢀtheꢀCCRAꢀandꢀCCRPꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀoneꢀ

registerꢀisꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀwhileꢀ

theꢀotherꢀoneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀWhichꢀregisterꢀisꢀusedꢀtoꢀcontrolꢀeitherꢀfrequencyꢀ

orꢀdutyꢀcycleꢀisꢀdeterminedꢀusingꢀtheꢀST0DPXꢀbitꢀinꢀtheꢀSTM0C1ꢀregister.ꢀTheꢀPWMꢀwaveformꢀ

frequencyꢀandꢀdutyꢀcycleꢀcanꢀthereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.

Anꢀinterruptꢀﬂag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ

occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀST0OCꢀbitꢀinꢀtheꢀSTM0C1ꢀregisterꢀisꢀusedꢀ

toꢀselectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀareꢀ

usedꢀtoꢀenableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀSTMꢀoutputꢀpinꢀtoꢀaꢀﬁxedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀ

ST0POLꢀbitꢀisꢀusedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.

• 10-bit STM, PWM Mode, Edge-aligned Mode, ST0DPX=0

CCRP

Period

Duty

001b

010b

011b

100b

101b

110b

111b

000b

128

256

384

512

640

768

896

1024

CCRA

Ifꢀf_SYSꢀ=ꢀ16MHz,ꢀTMꢀclockꢀsourceꢀisꢀf_SYS/4,ꢀCCRPꢀ=ꢀ100bꢀandꢀCCRAꢀ=128,

TheꢀSTMꢀPWMꢀoutputꢀfrequencyꢀ=ꢀ(f_SYS/4)ꢀ/ꢀ512ꢀ=ꢀf_SYS/2048ꢀ=ꢀ7.8125ꢀkHz,ꢀdutyꢀ=ꢀ128/512ꢀ=ꢀ25%.

IfꢀtheꢀDutyꢀvalueꢀdeﬁnedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ

PWMꢀoutputꢀdutyꢀisꢀ100%.

• 10-bit STM, PWM Mode, Edge-aligned Mode, ST0DPX=1

CCRP

Period

Duty

001b

010b

011b

100b

101b

110b

111b

000b

CCRA

128

256

384

512

640

768

896

1024

TheꢀPWMꢀoutputꢀperiodꢀisꢀdeterminedꢀbyꢀtheꢀCCRAꢀregisterꢀvalueꢀtogetherꢀwithꢀtheꢀSTMꢀclockꢀ

whileꢀtheꢀPWMꢀdutyꢀcycleꢀisꢀdeﬁnedꢀbyꢀtheꢀCCRPꢀregisterꢀvalue.

Rev. 1.41

68

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter

Value

ST0DPX=0;ST0M[1:0]=10

Counter Clearedby CCRP

Counter reset when

ST0ON returns high

CCRP

Counter Stop If

ST0ON bit low

Pause Resume

CCRA

Time

ST0ON

ST0PAU

ST0POL

CCRA Int.

Flag STMA0F

CCRP Int.

Flag STMP0F

STM O/P Pin

(ST0OC=1)

STM O/P Pin

(ST0OC=0)

Output Inverts

When ST0POL = 1

PWM resumes

operation

PWM Duty Cycle

set by CCRA

Output controlled by

Other pin-shared function

PWM Period

set by CCRP

PWM Output Mode – ST0DPX = 0

Note:ꢀ1.ꢀHereꢀST0DPXꢀ=ꢀ0ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRP

2.ꢀAꢀcounterꢀclearꢀsetsꢀPWMꢀPeriod

3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀST0IO[1:0]ꢀ=ꢀ00ꢀorꢀ01

4.ꢀTheꢀST0CCLRꢀbitꢀhasꢀnoꢀinﬂuenceꢀonꢀPWMꢀoperation

Rev. 1.41

69

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter

Value

ST0DPX=1;ST0M[1:0]=10

Counter Cleared by CCRA

Counter reset when

ST0ON returns high

CCRA

Counter Stop If

ST0ON bit low

Pause Resume

CCRP

Time

ST0ON

ST0PAU

ST0POL

CCRP Int.

Flag STMP0F

CCRA Int.

Flag STMA0F

STM O/P Pin

(ST0OC=1)

STM O/P Pin

(ST0OC=0)

Output Inverts

When ST0POL = 1

PWM resumes

operation

PWM Duty Cycle

set by CCRP

Output controlled by

Other pin-shared function

PWM Period

set by CCRA

PWM Output Mode – ST0DPX = 1

Note:ꢀ1.ꢀHereꢀST0DPXꢀ=ꢀ1ꢀ–ꢀCounterꢀclearedꢀbyꢀCCRA

2.ꢀAꢀcounterꢀclearꢀsetsꢀPWMꢀPeriod

3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀevenꢀwhenꢀST0IO[1:0]ꢀ=ꢀ00ꢀorꢀ01

4.ꢀTheꢀST0CCLRꢀbitꢀhasꢀnoꢀinﬂuenceꢀonꢀPWMꢀoperation

Rev. 1.41

70

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Single Pulse Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀST0M1ꢀandꢀST0M0ꢀinꢀtheꢀSTM0C1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀ

respectivelyꢀandꢀalsoꢀtheꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀrespectively.ꢀTheꢀSingleꢀPulseꢀ

OutputꢀMode,ꢀasꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀshotꢀpulseꢀonꢀtheꢀSTMꢀoutputꢀpin.ꢀ

TheꢀtriggerꢀforꢀtheꢀpulseꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀST0ONꢀbit,ꢀwhichꢀ

canꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogram.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀST0ONꢀ

bitꢀcanꢀalsoꢀbeꢀmadeꢀtoꢀautomaticallyꢀchangeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀSTCK0ꢀpin,ꢀ

whichꢀwillꢀinꢀturnꢀinitiateꢀtheꢀSingleꢀPulseꢀoutput.ꢀWhenꢀtheꢀST0ONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀ

theꢀcounterꢀwillꢀstartꢀrunningꢀandꢀtheꢀpulseꢀleadingꢀedgeꢀwillꢀbeꢀgenerated.ꢀTheꢀST0ONꢀbitꢀshouldꢀ

remainꢀhighꢀwhenꢀtheꢀpulseꢀisꢀinꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀwillꢀbeꢀgeneratedꢀ

whenꢀtheꢀST0ONꢀbitꢀisꢀclearedꢀtoꢀzero,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀ

whenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.

Leading Edge

Trailing Edge

S/W Command

SET“ST0ON”

or

S/W Command

CLR“ST0ON”

ST0ON bit

0 → 1

ST0ON bit

1 → 0

or

STCK0 Pin

Transition

CCRA Compare

Match

STP0/STP0B Output Pin

Pulse Width = CCRA Value

Single Pulse Generation

Rev. 1.41

71

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter Value

ST0M [1:0] = 10 ; ST0IO [1:0] = 11

Counter stopped

by CCRA

Counter Reset when

ST0ON returns high

CCRA

CCRP

Counter Stops

by software

Resume

Pause

Time

ST0ON

Auto. set by

STCK0 pin

Software Cleared by

Trigger CCRA match

Software

Trigger

Software

Clear

Software

Trigger

Software

Trigger

STCK0 pin

ST0PAU

STCK0 pin

Trigger

ST0POL

No CCRP Interrupts

generated

CCRP Int. Flag

STMP0F

CCRA Int. Flag

STMA0F

STM O/P Pin

(ST0OC=1)

STM O/P Pin

(ST0OC=0)

Output Inverts

when ST0POL = 1

Pulse Width

set by CCRA

Single Pulse Mode

Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRAꢀmatch

2.ꢀCCRPꢀisꢀnotꢀused

3.ꢀTheꢀpulseꢀisꢀtriggeredꢀbyꢀsettingꢀtheꢀST0ONꢀbitꢀhigh

4.ꢀInꢀtheꢀSingleꢀPulseꢀMode,ꢀST0IOꢀ[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ"11"ꢀandꢀcanꢀnotꢀbeꢀchanged.

Rev. 1.41

72

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀST0ONꢀbitꢀandꢀthusꢀ

generateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedge.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀ

pulseꢀwidth.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀgenerateꢀaꢀSTMꢀinterrupt.ꢀTheꢀcounterꢀ

canꢀonlyꢀbeꢀresetꢀbackꢀtoꢀzeroꢀwhenꢀtheꢀST0ONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhenꢀtheꢀcounterꢀ

restarts.ꢀInꢀtheꢀSingleꢀPulseꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀTheꢀST0CCLRꢀandꢀST0DPXꢀbitsꢀareꢀnotꢀusedꢀ

inꢀthisꢀMode.

Capture Input Mode

ToꢀselectꢀthisꢀmodeꢀbitsꢀST0M1ꢀandꢀST0M0ꢀinꢀtheꢀSTM0C1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ01ꢀrespectively.ꢀ

Thisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀpresentꢀvalueꢀofꢀtheꢀinternalꢀcounterꢀ

andꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀmeasurements.ꢀTheꢀexternalꢀsignalꢀisꢀ

suppliedꢀonꢀtheꢀSTP0I,ꢀwhoseꢀactiveꢀedgeꢀcanꢀbeꢀeitherꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀ

andꢀfallingꢀedges;ꢀtheꢀactiveꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀinꢀ

theꢀSTM0C1ꢀregister.ꢀTheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀST0ONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀ

initiatedꢀusingꢀtheꢀapplicationꢀprogram.ꢀ

WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀSTP0Iꢀtheꢀpresentꢀvalueꢀinꢀtheꢀcounterꢀwillꢀbeꢀ

latchedꢀintoꢀtheꢀCCRAꢀregistersꢀandꢀaꢀSTMꢀinterruptꢀgenerated.ꢀIrrespectiveꢀofꢀwhatꢀeventsꢀoccurꢀonꢀ

theꢀSTP0IꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀuntilꢀtheꢀST0ONꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow.ꢀWhenꢀ

aꢀCCRPꢀcompareꢀmatchꢀoccursꢀtheꢀcounterꢀwillꢀresetꢀbackꢀtoꢀzero;ꢀinꢀthisꢀwayꢀtheꢀCCRPꢀvalueꢀ

canꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀfromꢀ

ComparatorꢀP,ꢀaꢀSTMꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀCountingꢀtheꢀnumberꢀofꢀoverﬂowꢀinterruptꢀ

signalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀmeasuringꢀlongꢀpulseꢀwidths.ꢀTheꢀST0IO1ꢀandꢀ

ST0IO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀtriggerꢀedgeꢀonꢀtheꢀSTP0Iꢀtoꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀbothꢀ

edgeꢀtypes.ꢀIfꢀtheꢀST0IO1ꢀandꢀST0IO0ꢀbitsꢀareꢀbothꢀsetꢀhigh,ꢀthenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀ

placeꢀirrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀSTP0I,ꢀhoweverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀcounterꢀwillꢀ

continueꢀtoꢀrun.

TheꢀST0CCLRꢀandꢀST0DPXꢀbitsꢀareꢀnotꢀusedꢀinꢀthisꢀMode.

Rev. 1.41

73

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter Value

STnM [1:0] = 01

Counter cleared by

CCRP

Counter

Stop

Counter

Reset

CCRP

YY

Resume

Pause

XX

Time

STnON

STnPAU

Active

edge

Active

edge

Active edge

STMn capture

pin STPnI

CCRA Int.

Flag STMnAF

CCRP Int.

Flag STMnPF

CCRA

Value

XX

YY

XX

YY

STnIO [1:0]

Value

01 – Falling edge

10 – Both edges

11 – Disable Capture

00 – Rising edge

Capture Input Mode (n=0)

Note:ꢀ1.ꢀST0M[1:0]ꢀ=ꢀ01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀST0IO[1:0]ꢀbits

2.ꢀAꢀTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀtheꢀcounterꢀvalueꢀtoꢀCCRA

3.ꢀTheꢀST0CCLRꢀandꢀST0DPXꢀbitsꢀareꢀnotꢀused

4.ꢀNoꢀoutputꢀfunctionꢀ–ꢀST0OCꢀandꢀST0POLꢀbitsꢀareꢀnotꢀused

5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀ

zero.

Rev. 1.41

74

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Periodic Type TM – PTM

TheꢀPeriodicꢀTypeꢀTMꢀcontainsꢀﬁveꢀoperatingꢀmodes,ꢀwhichꢀareꢀCompareꢀMatchꢀOutput,ꢀTimer/

EventꢀCounter,ꢀCaptureꢀInput,ꢀSingleꢀPulseꢀOutputꢀandꢀPWMꢀOutputꢀmodes.ꢀTheꢀPeriodicꢀTMꢀcanꢀ

alsoꢀbeꢀcontrolledꢀwithꢀtwoꢀexternalꢀinputꢀpinsꢀandꢀcanꢀdriveꢀtwoꢀexternalꢀoutputꢀpins.

Device

Name

TM Input Pin

TM Output Pin

HT68F003

10-bit PTM

PTCK1, PTP1I

PTP1,PTP1B

Periodic TM Operation

Atꢀitsꢀcoreꢀisꢀaꢀ10-bitꢀcount-upꢀcounterꢀwhichꢀisꢀdrivenꢀbyꢀaꢀuserꢀselectableꢀinternalꢀorꢀexternalꢀclockꢀ

source.ꢀThereꢀareꢀtwoꢀinternalꢀcomparatorsꢀwithꢀtheꢀnames,ꢀComparatorꢀAꢀandꢀComparatorꢀP.ꢀTheseꢀ

comparatorsꢀwillꢀcompareꢀtheꢀvalueꢀinꢀtheꢀcounterꢀwithꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.

Theꢀonlyꢀwayꢀofꢀchangingꢀtheꢀvalueꢀofꢀtheꢀ10-bitꢀcounterꢀusingꢀtheꢀapplicationꢀprogram,ꢀisꢀtoꢀ

clearꢀtheꢀcounterꢀbyꢀchangingꢀtheꢀPT0ONꢀbitꢀfromꢀlowꢀtoꢀhigh.ꢀTheꢀcounterꢀwillꢀalsoꢀbeꢀclearedꢀ

automaticallyꢀbyꢀaꢀcounterꢀoverﬂowꢀorꢀaꢀcompareꢀmatchꢀwithꢀoneꢀofꢀitsꢀassociatedꢀcomparators.ꢀ

Whenꢀtheseꢀconditionsꢀoccur,ꢀaꢀTMꢀinterruptꢀsignalꢀwillꢀalsoꢀusuallyꢀbeꢀgenerated.ꢀTheꢀPeriodicꢀ

TypeꢀTMꢀcanꢀoperateꢀinꢀaꢀnumberꢀofꢀdifferentꢀoperationalꢀmodes,ꢀcanꢀbeꢀdrivenꢀbyꢀdifferentꢀclockꢀ

sourcesꢀincludingꢀanꢀinputꢀpinꢀandꢀcanꢀalsoꢀcontrolꢀtheꢀoutputꢀpin.ꢀAllꢀoperatingꢀsetupꢀconditionsꢀareꢀ

selectedꢀusingꢀrelevantꢀinternalꢀregisters.

C

R

P

C

m

o

a

p

r

a

P

t

M

a

o

c

t

r

h

P

M

T

1

P

F

I

n

r

t

u

e

p

t

1

-

0

i

b

t

C

o

m

r

p

t

a

r

a

o

P

b

~

0

9

b

P

1

T

C

O

f

S

Y

/

S

4

0

1

0

1

0

1

0

1

0

1

0

1

f

S

Y

S

f

H

/

6

1

P

T

P

1

O

t

u

p

t

P

l

a

o

i

r

y

t

f

/

4

6

0

C

o

u

t

r

n

e

C

e

l

r

a

C

o

n

r

l

o

t

C

o

n

r

l

o

t

P

T

B

P

1

-

0

i

b

t

C

o

u

-

n

p

u

C

t

u

o

t

n

r

e

f

T

C

B

1

C

B

P

1

T

C

R

L

P

1

T

O

P

L

P

1

T

M

1

,

P

T

M

1

0

P

1

T

N

O

1

b

~

0

9

b

P

C

T

1

K

P

1

T

O

I

,

1

T

P

I

1

0

O

P

1

T

P

A

U

C

m

o

a

p

r

a

A

t

M

o

t

a

h

r

c

1

-

0

i

b

t

P

M

T

1

A

F

I

n

r

t

u

e

p

t

C

m

o

a

p

r

a

A

t

o

r

P

1

T

K

C

~

2

T

P

C

1

0

K

P

1

T

O

I

,

1

T

P

I

1

0

O

C

R

A

P

T

I

P

1

0

E

d

g

e

D

t

e

c

e

o

t

r

1

P

1

T

K

C

S

Periodic Type TM Block Diagram

Rev. 1.41

75

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Periodic Type TM Register Description

OverallꢀoperationꢀofꢀtheꢀPeriodicꢀTMꢀisꢀcontrolledꢀusingꢀaꢀseriesꢀofꢀregisters.ꢀAꢀreadꢀonlyꢀregisterꢀ

pairꢀexistsꢀtoꢀstoreꢀtheꢀinternalꢀcounterꢀ10-bitꢀvalue,ꢀwhileꢀtwoꢀread/writeꢀregisterꢀpairsꢀexistꢀtoꢀstoreꢀ

theꢀinternalꢀ10-bitꢀCCRAꢀandꢀCCRPꢀvalue.ꢀTheꢀremainingꢀtwoꢀregistersꢀareꢀcontrolꢀregistersꢀwhichꢀ

setupꢀtheꢀdifferentꢀoperatingꢀandꢀcontrolꢀmodes.

Bit

Register

Name

7

6

5

4

3

2

1

0

PTM1C0 PT1PAU PT1CK2 PT1CK1 PT1CK0 PT1ON

—

PTM1C1

PTM1DL

PTM1DH

PTM1AL

PTM1AH

PTM1RPL

PTM1RPH

PT1M1 PT1M0 PT1IO1

PT1IO0 PT1OC PT1POL PT1CKS PT1CCLR

D7

—

D6

—

D5

—

D4

—

D3

—

D2

—

D1

D9

D1

D9

D1

D9

D0

D8

D0

D8

D0

D8

D7

—

D6

—

D5

—

D4

—

D3

—

D2

—

D7

—

D6

—

D5

—

D4

—

D3

—

D2

—

10-bit Periodic TM Register List

PTM1C0 Register

Bit

7

6

5

4

3

2

1

0

Name

R/W

PT1PAU PT1CK2 PT1CK1 PT1CK0 PT1ON

—

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7

PT1PAU:ꢀPTMꢀCounterꢀPauseꢀControl

0:ꢀrun

1:ꢀpause

Theꢀcounterꢀcanꢀbeꢀpausedꢀbyꢀsettingꢀthisꢀbitꢀhigh.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀrestoresꢀ

normalꢀcounterꢀoperation.ꢀWhenꢀinꢀaꢀPauseꢀconditionꢀtheꢀTMꢀwillꢀremainꢀpoweredꢀupꢀ

andꢀcontinueꢀtoꢀconsumeꢀpower.ꢀTheꢀcounterꢀwillꢀretainꢀitsꢀresidualꢀvalueꢀwhenꢀthisꢀbitꢀ

changesꢀfromꢀlowꢀtoꢀhighꢀandꢀresumeꢀcountingꢀfromꢀthisꢀvalueꢀwhenꢀtheꢀbitꢀchangesꢀ

toꢀaꢀlowꢀvalueꢀagain.

Bitꢀ6~4

PT1CK2~PT1CK0:ꢀSelectꢀPTMꢀCounterꢀclock

000:ꢀf_SYS/4

001:ꢀf_SYS

010:ꢀf_H/16

011:ꢀf_H/64

100:ꢀf_TBC

101:ꢀf_TBC

110:ꢀPTCK1ꢀrisingꢀedgeꢀclock

111:ꢀPTCK1ꢀfallingꢀedgeꢀclock

TheseꢀthreeꢀbitsꢀareꢀusedꢀtoꢀselectꢀtheꢀclockꢀsourceꢀforꢀtheꢀTM.ꢀTheꢀexternalꢀpinꢀclockꢀ

sourceꢀcanꢀbeꢀchosenꢀtoꢀbeꢀactiveꢀonꢀtheꢀrisingꢀorꢀfallingꢀedge.ꢀTheꢀclockꢀsourceꢀf_SYSꢀisꢀ

theꢀsystemꢀclock,ꢀwhileꢀf_TBCꢀisꢀanotherꢀinternalꢀclock,ꢀtheꢀdetailsꢀofꢀwhichꢀcanꢀbeꢀfoundꢀ

inꢀtheꢀoscillatorꢀsection.

Rev. 1.41

76

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Bitꢀ3

PT1ON:ꢀPTMꢀCounterꢀOn/OffꢀControl

0:ꢀOff

1:ꢀOn

Thisꢀbitꢀcontrolsꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀTM.ꢀSettingꢀtheꢀbitꢀhighꢀenablesꢀtheꢀ

counterꢀtoꢀrun,ꢀclearingꢀtheꢀbitꢀdisablesꢀtheꢀTM.ꢀClearingꢀthisꢀbitꢀtoꢀzeroꢀwillꢀstopꢀtheꢀ

counterꢀfromꢀcountingꢀandꢀturnꢀoffꢀtheꢀTMꢀwhichꢀwillꢀreduceꢀitsꢀpowerꢀconsumption.ꢀ

Whenꢀtheꢀbitꢀchangesꢀstateꢀfromꢀlowꢀtoꢀhighꢀtheꢀinternalꢀcounterꢀvalueꢀwillꢀbeꢀresetꢀtoꢀ

zero,ꢀhoweverꢀwhenꢀtheꢀbitꢀchangesꢀfromꢀhighꢀtoꢀlow,ꢀtheꢀinternalꢀcounterꢀwillꢀretainꢀ

itsꢀresidualꢀvalueꢀuntilꢀtheꢀbitꢀreturnsꢀhighꢀagain.ꢀ

IfꢀtheꢀTMꢀisꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀthenꢀtheꢀTMꢀoutputꢀpinꢀwillꢀbeꢀresetꢀ

toꢀitsꢀinitialꢀcondition,ꢀasꢀspeciﬁedꢀbyꢀtheꢀTMꢀOutputꢀcontrolꢀbit,ꢀwhenꢀtheꢀbitꢀchangesꢀ

fromꢀlowꢀtoꢀhigh.

Bitꢀ2~0ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

PTM1C1 Register

Bit

7

6

PT1M0

R/W

0

5

4

3

2

1

0

Name

R/W

PT1M1

R/W

0

PT1IO1 PT1IO0

PT1OC PT1POL PT1CKS PT1CCLR

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7~6

PT1M1~ PT1M0:ꢀSelectꢀPTMꢀOperationꢀMode

00:ꢀCompareꢀMatchꢀOutputꢀMode

01:ꢀCaptureꢀInputꢀMode

10:ꢀPWMꢀModeꢀorꢀSingleꢀPulseꢀOutputꢀMode

11:ꢀTimer/CounterꢀMode

TheseꢀbitsꢀsetupꢀtheꢀrequiredꢀoperatingꢀmodeꢀforꢀtheꢀTM.ꢀToꢀensureꢀreliableꢀoperationꢀ

theꢀTMꢀshouldꢀbeꢀswitchedꢀoffꢀbeforeꢀanyꢀchangesꢀareꢀmadeꢀtoꢀtheꢀPT1M1ꢀandꢀ

PT1M0ꢀbits.ꢀInꢀtheꢀTimer/CounterꢀMode,ꢀtheꢀPTMꢀoutputꢀpinꢀstateꢀisꢀundeﬁned.

Bitꢀ5~4

PT1IO1~ PT1IO0:ꢀSelectꢀPTMꢀoutputꢀfunctionꢀ

CompareꢀMatchꢀOutputꢀMode

00:ꢀNoꢀchange

01:ꢀOutputꢀlow

10:ꢀOutputꢀhigh

11:ꢀToggleꢀoutput

PWMꢀMode/SingleꢀPulseꢀOutputꢀMode

00:ꢀPWMꢀOutputꢀinactiveꢀstate

01:ꢀPWMꢀOutputꢀactiveꢀstate

10:ꢀPWMꢀoutput

11:ꢀSingleꢀpulseꢀoutput

CaptureꢀInputꢀMode

00:ꢀInputꢀcaptureꢀatꢀrisingꢀedgeꢀofꢀPTP1IꢀorꢀPTCK1

01:ꢀInputꢀcaptureꢀatꢀfallingꢀedgeꢀofꢀPTP1IꢀorꢀPTCK1

10:ꢀInputꢀcaptureꢀatꢀfalling/risingꢀedgeꢀofꢀPTP1IꢀorꢀPTCK1

11:ꢀInputꢀcaptureꢀdisabled

Timer/counterꢀMode

Unused

TheseꢀtwoꢀbitsꢀareꢀusedꢀtoꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀ

certainꢀconditionꢀisꢀreached.ꢀTheꢀfunctionꢀthatꢀtheseꢀbitsꢀselectꢀdependsꢀuponꢀinꢀwhichꢀ

modeꢀtheꢀTMꢀisꢀrunning.ꢀ

Rev. 1.41

77

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

InꢀtheꢀCompareꢀMatchꢀOutputꢀMode,ꢀtheꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀdetermineꢀhowꢀ

theꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀ

A.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀsetupꢀtoꢀswitchꢀhigh,ꢀswitchꢀlowꢀorꢀtoꢀtoggleꢀitsꢀpresentꢀ

stateꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀWhenꢀtheseꢀbitsꢀareꢀ

bothꢀzero,ꢀthenꢀnoꢀchangeꢀwillꢀtakeꢀplaceꢀonꢀtheꢀoutput.ꢀTheꢀinitialꢀvalueꢀofꢀtheꢀTMꢀ

outputꢀpinꢀshouldꢀbeꢀsetupꢀusingꢀtheꢀPT1OCꢀbit.ꢀNoteꢀthatꢀtheꢀoutputꢀlevelꢀrequestedꢀ

byꢀtheꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀmustꢀbeꢀdifferentꢀfromꢀtheꢀinitialꢀvalueꢀsetupꢀusingꢀ

theꢀPT1OCꢀbitꢀotherwiseꢀnoꢀchangeꢀwillꢀoccurꢀonꢀtheꢀTMꢀoutputꢀpinꢀwhenꢀaꢀcompareꢀ

matchꢀoccurs.ꢀAfterꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstate,ꢀitꢀcanꢀbeꢀresetꢀtoꢀitsꢀinitialꢀlevelꢀ

byꢀchangingꢀtheꢀlevelꢀofꢀtheꢀPT1ONꢀbitꢀfromꢀlowꢀtoꢀhigh.

InꢀtheꢀPWMꢀMode,ꢀtheꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀdetermineꢀhowꢀtheꢀTMꢀoutputꢀpinꢀ

changesꢀstateꢀwhenꢀaꢀcertainꢀcompareꢀmatchꢀconditionꢀoccurs.ꢀTheꢀPWMꢀoutputꢀ

functionꢀisꢀmodiﬁedꢀbyꢀchangingꢀtheseꢀtwoꢀbits.ꢀItꢀisꢀnecessaryꢀtoꢀchangeꢀtheꢀvaluesꢀofꢀ

theꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀonlyꢀafterꢀtheꢀTMꢀhasꢀbeenꢀswitchedꢀoff.ꢀUnpredictableꢀ

PWMꢀoutputsꢀwillꢀoccurꢀifꢀtheꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀareꢀchangedꢀwhenꢀtheꢀTMꢀisꢀ

running.

Bitꢀ3

PT1OC:ꢀPTP1/PTP1BꢀOutputꢀcontrolꢀbit

CompareꢀMatchꢀOutputꢀMode

0:ꢀinitialꢀlow

1:ꢀinitialꢀhigh

PWMꢀMode/ꢀSingleꢀPulseꢀOutputꢀMode

0:ꢀActiveꢀlow

1:ꢀActiveꢀhigh

ThisꢀisꢀtheꢀoutputꢀcontrolꢀbitꢀforꢀtheꢀTMꢀoutputꢀpin.ꢀItsꢀoperationꢀdependsꢀuponꢀ

whetherꢀTMꢀisꢀbeingꢀusedꢀinꢀtheꢀCompareꢀMatchꢀOutputꢀModeꢀorꢀinꢀtheꢀPWMꢀMode/

SingleꢀPulseꢀOutputꢀMode.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀTMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.ꢀInꢀ

theꢀCompareꢀMatchꢀOutputꢀModeꢀitꢀdeterminesꢀtheꢀlogicꢀlevelꢀofꢀtheꢀTMꢀoutputꢀpinꢀ

beforeꢀaꢀcompareꢀmatchꢀoccurs.ꢀInꢀtheꢀPWMꢀModeꢀitꢀdeterminesꢀifꢀtheꢀPWMꢀsignalꢀisꢀ

activeꢀhighꢀorꢀactiveꢀlow.

Bitꢀ2

PT1POL:ꢀPTP1ꢀOutputꢀpolarityꢀControl

0:ꢀnon-invert

1:ꢀinvert

ThisꢀbitꢀcontrolsꢀtheꢀpolarityꢀofꢀtheꢀPTP1ꢀoutputꢀpin.ꢀWhenꢀtheꢀbitꢀisꢀsetꢀhighꢀtheꢀTMꢀ

outputꢀpinꢀwillꢀbeꢀinvertedꢀandꢀnotꢀinvertedꢀwhenꢀtheꢀbitꢀisꢀzero.ꢀItꢀhasꢀnoꢀeffectꢀifꢀtheꢀ

TMꢀisꢀinꢀtheꢀTimer/CounterꢀMode.

Bitꢀ1

Bitꢀ0

PT1CKS:ꢀPTMꢀcaptureꢀtriggerꢀsourceꢀselect

0:ꢀFromꢀPTP1I

1:ꢀFromꢀPTCK1ꢀpinꢀ

PT1CCLR:ꢀSelectꢀPTMꢀCounterꢀclearꢀconditionꢀ

0:ꢀPTMꢀComparatrorꢀPꢀmatchꢀ

1:ꢀPTMꢀComparatrorꢀAꢀmatch

Thisꢀbitꢀisꢀusedꢀtoꢀselectꢀtheꢀmethodꢀwhichꢀclearsꢀtheꢀcounter.ꢀRememberꢀthatꢀtheꢀ

PeriodicꢀTMꢀcontainsꢀtwoꢀcomparators,ꢀComparatorꢀAꢀandꢀComparatorꢀP,ꢀeitherꢀofꢀ

whichꢀcanꢀbeꢀselectedꢀtoꢀclearꢀtheꢀinternalꢀcounter.ꢀWithꢀtheꢀPT1CCLRꢀbitꢀsetꢀhigh,ꢀ

theꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀtheꢀComparatorꢀA.ꢀ

Whenꢀtheꢀbitꢀisꢀlow,ꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀ

theꢀComparatorꢀPꢀorꢀwithꢀaꢀcounterꢀoverﬂow.ꢀAꢀcounterꢀoverﬂowꢀclearingꢀmethodꢀcanꢀ

onlyꢀbeꢀimplementedꢀifꢀtheꢀCCRPꢀbitsꢀareꢀallꢀclearedꢀtoꢀzero.ꢀTheꢀPT1CCLRꢀbitꢀisꢀnotꢀ

usedꢀinꢀtheꢀPWM,ꢀSingleꢀPulseꢀorꢀInputꢀCaptureꢀMode.

Rev. 1.41

78

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

PTM1DL Register

Bit

Name

R/W

7

D7

R

6

D6

R

5

D5

R

4

D4

R

3

D3

R

2

D2

R

1

D1

R

0

D0

R

POR

0

Bitꢀ7~0

PTM1DL:ꢀPTMꢀCounterꢀLowꢀByteꢀRegisterꢀbitꢀ7ꢀ~ꢀbitꢀ0

PTMꢀ10-bitꢀCounterꢀbitꢀ7ꢀ~ꢀbitꢀ0

PTM1DH Register

Bit

7

6

5

4

3

2

1

D9

R

0

D8

R

Name

R/W

—

POR

0

Bitꢀ7~2ꢀ

Bitꢀ1~0

Unimplemented,ꢀreadꢀasꢀ"0"

PTM1DH:ꢀPTMꢀCounterꢀHighꢀByteꢀRegisterꢀbitꢀ1ꢀ~ꢀbitꢀ0

PTMꢀ10-bitꢀCounterꢀbitꢀ9ꢀ~ꢀbitꢀ8

PTM1AL Register

Bit

7

6

D6

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

2

D2

R/W

0

1

D1

R/W

0

D0

R/W

0

Name

R/W

D7

R/W

0

POR

Bitꢀ7~0

PTM1AL:ꢀPTMꢀCCRAꢀLowꢀByteꢀRegisterꢀbitꢀ7ꢀ~ꢀbitꢀ0

PTMꢀ10-bitꢀCCRAꢀbitꢀ7ꢀ~ꢀbitꢀ0

PTM1AH Register

Bit

7

6

5

4

3

2

1

D9

R/W

0

D8

R/W

0

Name

R/W

—

POR

Bitꢀ7~2ꢀ

Bitꢀ1~0

Unimplemented,ꢀreadꢀasꢀ"0"

PTM1AH:ꢀPTMꢀCCRAꢀHighꢀByteꢀRegisterꢀbitꢀ1ꢀ~ꢀbitꢀ0

PTMꢀ10-bitꢀCCRAꢀbitꢀ9ꢀ~ꢀbitꢀ8

PTM1RPL Register

Bit

Name

R/W

7

D7

R/W

0

6

D6

R/W

0

5

D5

R/W

0

4

D4

R/W

0

3

D3

R/W

0

2

D2

R/W

0

1

D1

R/W

0

D0

R/W

0

POR

Bitꢀ7~0

PTM1RPL:ꢀPTMꢀCCRPꢀLowꢀByteꢀRegisterꢀbitꢀ7ꢀ~ꢀbitꢀ0

PTMꢀ10-bitꢀCCRPꢀbitꢀ7ꢀ~ꢀbitꢀ0

Rev. 1.41

79

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

PTM1RPH Register

Bit

Name

R/W

7

6

5

4

3

2

1

D9

R/W

0

D8

R/W

0

—

POR

Bitꢀ7~2ꢀ

Bitꢀ1~0

Unimplemented,ꢀreadꢀasꢀ"0"

PTM1RPH:ꢀPTMꢀCCRPꢀHighꢀByteꢀRegisterꢀbitꢀ1ꢀ~ꢀbitꢀ0

PTMꢀ10-bitꢀCCRPꢀbitꢀ9ꢀ~ꢀbitꢀ8

Periodic Type TM Operating Modes

TheꢀPeriodicꢀTypeꢀTMꢀcanꢀoperateꢀinꢀoneꢀofꢀﬁveꢀoperatingꢀmodes,ꢀCompareꢀMatchꢀOutputꢀMode,ꢀ

PWMꢀOutputꢀMode,ꢀSingleꢀPulseꢀOutputꢀMode,ꢀCaptureꢀInputꢀModeꢀorꢀTimer/CounterꢀMode.ꢀTheꢀ

operatingꢀmodeꢀisꢀselectedꢀusingꢀtheꢀPT1M1ꢀandꢀPT1M0ꢀbitsꢀinꢀtheꢀPTM1C1ꢀregister.

Compare Match Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀPT1M1ꢀandꢀPT1M0ꢀinꢀtheꢀPTM1C1ꢀregister,ꢀshouldꢀbeꢀallꢀclearedꢀtoꢀ

00ꢀrespectively.ꢀInꢀthisꢀmodeꢀonceꢀtheꢀcounterꢀisꢀenabledꢀandꢀrunningꢀitꢀcanꢀbeꢀclearedꢀbyꢀthreeꢀ

methods.ꢀTheseꢀareꢀaꢀcounterꢀoverﬂow,ꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀandꢀaꢀcompareꢀmatchꢀ

fromꢀComparatorꢀP.ꢀWhenꢀtheꢀPT1CCLRꢀbitꢀisꢀlow,ꢀthereꢀareꢀtwoꢀwaysꢀinꢀwhichꢀtheꢀcounterꢀcanꢀbeꢀ

cleared.ꢀOneꢀisꢀwhenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀtheꢀotherꢀisꢀwhenꢀtheꢀCCRPꢀbitsꢀ

areꢀallꢀzeroꢀwhichꢀallowsꢀtheꢀcounterꢀtoꢀoverﬂow.ꢀHereꢀbothꢀtheꢀPTMA1FꢀandꢀPTMP1Fꢀinterruptꢀ

requestꢀﬂagsꢀforꢀComparatorꢀAandꢀComparatorꢀPꢀrespectively,ꢀwillꢀbothꢀbeꢀgenerated.

IfꢀtheꢀPT1CCLRꢀbitꢀinꢀtheꢀPTM1C1ꢀregisterꢀisꢀhighꢀthenꢀtheꢀcounterꢀwillꢀbeꢀclearedꢀwhenꢀaꢀcompareꢀ

matchꢀoccursꢀfromꢀComparatorꢀA.ꢀHowever,ꢀhereꢀonlyꢀtheꢀPTMA1Fꢀinterruptꢀrequestꢀflagꢀwillꢀ

beꢀgeneratedꢀevenꢀifꢀtheꢀvalueꢀofꢀtheꢀCCRPꢀbitsꢀisꢀlessꢀthanꢀthatꢀofꢀtheꢀCCRAꢀregisters.ꢀThereforeꢀ

whenꢀPT1CCLRꢀisꢀhighꢀnoꢀPTMP1Fꢀinterruptꢀrequestꢀflagꢀwillꢀbeꢀgenerated.ꢀInꢀtheꢀCompareꢀ

MatchꢀOutputꢀMode,ꢀtheꢀCCRAꢀcanꢀnotꢀbeꢀsetꢀtoꢀ"0".ꢀIfꢀtheꢀCCRAꢀbitsꢀareꢀallꢀzero,ꢀtheꢀcounterꢀwillꢀ

overﬂowꢀwhenꢀitsꢀreachesꢀitsꢀmaximumꢀ10-bit,ꢀ3FFꢀHex,ꢀvalue,ꢀhoweverꢀhereꢀtheꢀPTMA1Fꢀinterruptꢀ

requestꢀﬂagꢀwillꢀnotꢀbeꢀgenerated.

Asꢀtheꢀnameꢀofꢀtheꢀmodeꢀsuggests,ꢀafterꢀaꢀcomparisonꢀisꢀmade,ꢀtheꢀTMꢀoutputꢀpin,ꢀwillꢀchangeꢀstate.ꢀ

TheꢀTMꢀoutputꢀpinꢀconditionꢀhoweverꢀonlyꢀchangesꢀstateꢀwhenꢀaꢀPTMA1Fꢀinterruptꢀrequestꢀﬂagꢀisꢀ

generatedꢀafterꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀPTMP1Fꢀinterruptꢀrequestꢀﬂag,ꢀ

generatedꢀfromꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀP,ꢀwillꢀhaveꢀnoꢀeffectꢀonꢀtheꢀTMꢀoutputꢀpin.ꢀ

TheꢀwayꢀinꢀwhichꢀtheꢀTMꢀoutputꢀpinꢀchangesꢀstateꢀareꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀtheꢀPT1IO1ꢀ

andꢀPT1IO0ꢀbitsꢀinꢀtheꢀPTM1C1ꢀregister.ꢀTheꢀTMꢀoutputꢀpinꢀcanꢀbeꢀselectedꢀusingꢀtheꢀPT1IO1ꢀ

andꢀPT1IO0ꢀbitsꢀtoꢀgoꢀhigh,ꢀtoꢀgoꢀlowꢀorꢀtoꢀtoggleꢀfromꢀitsꢀpresentꢀconditionꢀwhenꢀaꢀcompareꢀ

matchꢀoccursꢀfromꢀComparatorꢀA.ꢀTheꢀinitialꢀconditionꢀofꢀtheꢀTMꢀoutputꢀpin,ꢀwhichꢀisꢀsetupꢀafterꢀ

theꢀPT1ONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhigh,ꢀisꢀsetupꢀusingꢀtheꢀPT1OCꢀbit.ꢀNoteꢀthatꢀifꢀtheꢀPT1IO1,ꢀ

PT1IO0ꢀbitsꢀareꢀzeroꢀthenꢀnoꢀpinꢀchangeꢀwillꢀtakeꢀplace.

Rev. 1.41

80

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter overflow

Counter Value

CCRP=0

PT1CCLR = 0; PT1M [1:0] = 00

CCRP > 0

Counter cleared by CCRP value

0x3FF

CCRP > 0

Counter

Restart

Resume

CCRP

CCRA

Pause

Stop

Time

PT1ON

PT1PAU

PT1POL

CCRP Int. Flag

PTMP1F

CCRA Int. Flag

PTMA1F

PTM O/P

Output not affected by

PTMA1F flag. Remains High

until reset by PT1ON bit

Output Inverts

when PT1POL is high

Output pin set to

initial Level Low

if PT1OC=0

Output Toggle with

PTMA1F flag

Output Pin

Reset to Initial value

Output controlled by

other pin-shared function

Note PT1IO [1:0] = 10

Active High Output select

Here PT1IO [1:0] = 11

Toggle Output select

Compare Match Output Mode – PT1CCLR = 0

Note:ꢀ1.ꢀWithꢀPT1CCLRꢀ=ꢀ0ꢀ–ꢀaꢀComparatorꢀPꢀmatchꢀwillꢀclearꢀtheꢀcounter

2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀPTMA1Fꢀﬂag

3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀinitialꢀstateꢀbyꢀaꢀPT1ONꢀbitꢀrisingꢀedge

Rev. 1.41

81

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter Value

PT1CCLR = 1; PT1M [1:0] = 00

CCRA = 0

CCRA > 0 Counter cleared by CCRA value

Counter overflow

0x3FF

CCRA

CCRP

CCRA=0

Resume

Pause

Stop

Counter Restart

Time

PT1ON

PT1PAU

PT1POL

No PTMA1F

flag generated

on CCRA

overflow

CCRA Int. Flag

PTMA1F

CCRP Int. Flag

PTMP1F

PTMP1F not

generated

Output does

not change

PTM O/P

Output not affected by

PTMA1F flag. Remains High

until reset by PT1ON bit

Output Inverts

when PT1POL is high

Output Toggle with

PTMA1F flag

Output pin set to

initial Level Low

if PT1OC=0

Output Pin

Reset to Initial value

Output controlled by

other pin-shared function

Note PT1IO [1:0] = 10

Active High Output select

Here PT1IO [1:0] = 11

Toggle Output select

Compare Match Output Mode – PT1CCLR = 1

Note:ꢀ1.ꢀWithꢀPT1CCLRꢀ=ꢀ1ꢀ–ꢀaꢀComparatorꢀAꢀmatchꢀwillꢀclearꢀtheꢀcounter

2.ꢀTheꢀTMꢀoutputꢀpinꢀisꢀcontrolledꢀonlyꢀbyꢀtheꢀPTMA1Fꢀﬂag

3.ꢀTheꢀoutputꢀpinꢀisꢀresetꢀtoꢀinitialꢀstateꢀbyꢀaꢀPT1ONꢀrisingꢀedge

4.ꢀTheꢀPTMP1FꢀﬂagꢀisꢀnotꢀgeneratedꢀwhenꢀPT1CCLRꢀ=ꢀ1

Rev. 1.41

82

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Timer/Counter Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀPT1M1ꢀandꢀPT1M0ꢀinꢀtheꢀPTM1C1ꢀregisterꢀshouldꢀallꢀbeꢀsetꢀtoꢀ11ꢀ

respectively.ꢀTheꢀTimer/CounterꢀModeꢀoperatesꢀinꢀanꢀidenticalꢀwayꢀtoꢀtheꢀCompareꢀMatchꢀOutputꢀ

Modeꢀgeneratingꢀtheꢀsameꢀinterruptꢀflags.ꢀTheꢀexceptionꢀisꢀthatꢀinꢀtheꢀTimer/CounterꢀModeꢀtheꢀ

TMꢀoutputꢀpinꢀisꢀnotꢀused.ꢀThereforeꢀtheꢀaboveꢀdescriptionꢀandꢀTimingꢀDiagramsꢀforꢀtheꢀCompareꢀ

MatchꢀOutputꢀModeꢀcanꢀbeꢀusedꢀtoꢀunderstandꢀitsꢀfunction.ꢀAsꢀtheꢀTMꢀoutputꢀpinꢀisꢀnotꢀusedꢀinꢀthisꢀ

mode,ꢀtheꢀpinꢀcanꢀbeꢀusedꢀasꢀaꢀnormalꢀI/Oꢀpinꢀorꢀotherꢀpin-sharedꢀfunction.

PWM Output Mode

Toꢀselectꢀthisꢀmode,ꢀbitsꢀPT1M1ꢀandꢀPT1M0ꢀinꢀtheꢀPTM1C1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectivelyꢀ

andꢀalsoꢀtheꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectively.ꢀTheꢀPWMꢀfunctionꢀwithinꢀ

theꢀTMꢀisꢀusefulꢀforꢀapplicationsꢀwhichꢀrequireꢀfunctionsꢀsuchꢀasꢀmotorꢀcontrol,ꢀheatingꢀcontrol,ꢀ

illuminationꢀcontrolꢀetc.ꢀByꢀprovidingꢀaꢀsignalꢀofꢀﬁxedꢀfrequencyꢀbutꢀofꢀvaryingꢀdutyꢀcycleꢀonꢀtheꢀ

TMꢀoutputꢀpin,ꢀaꢀsquareꢀwaveꢀACꢀwaveformꢀcanꢀbeꢀgeneratedꢀwithꢀvaryingꢀequivalentꢀDCꢀRMSꢀ

values.ꢀ

AsꢀbothꢀtheꢀperiodꢀandꢀdutyꢀcycleꢀofꢀtheꢀPWMꢀwaveformꢀcanꢀbeꢀcontrolled,ꢀtheꢀchoiceꢀofꢀgeneratedꢀ

waveformꢀisꢀextremelyꢀﬂexible.ꢀInꢀtheꢀPWMꢀoutputꢀmode,ꢀtheꢀPT1CCLRꢀbitꢀhasꢀnoꢀeffectꢀasꢀtheꢀ

PWMꢀperiod.ꢀBothꢀofꢀtheꢀCCRPꢀandꢀCCRAꢀregistersꢀareꢀusedꢀtoꢀgenerateꢀtheꢀPWMꢀwaveform,ꢀoneꢀ

registerꢀisꢀusedꢀtoꢀclearꢀtheꢀinternalꢀcounterꢀandꢀthusꢀcontrolꢀtheꢀPWMꢀwaveformꢀfrequency,ꢀwhileꢀ

theꢀotherꢀoneꢀisꢀusedꢀtoꢀcontrolꢀtheꢀdutyꢀcycle.ꢀTheꢀPWMꢀwaveformꢀfrequencyꢀandꢀdutyꢀcycleꢀcanꢀ

thereforeꢀbeꢀcontrolledꢀbyꢀtheꢀvaluesꢀinꢀtheꢀCCRAꢀandꢀCCRPꢀregisters.

Anꢀinterruptꢀﬂag,ꢀoneꢀforꢀeachꢀofꢀtheꢀCCRAꢀandꢀCCRP,ꢀwillꢀbeꢀgeneratedꢀwhenꢀaꢀcompareꢀmatchꢀ

occursꢀfromꢀeitherꢀComparatorꢀAꢀorꢀComparatorꢀP.ꢀTheꢀPT1OCꢀbitꢀinꢀtheꢀPTM1C1ꢀregisterꢀisꢀusedꢀtoꢀ

selectꢀtheꢀrequiredꢀpolarityꢀofꢀtheꢀPWMꢀwaveformꢀwhileꢀtheꢀtwoꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀareꢀusedꢀ

toꢀenableꢀtheꢀPWMꢀoutputꢀorꢀtoꢀforceꢀtheꢀTMꢀoutputꢀpinꢀtoꢀaꢀﬁxedꢀhighꢀorꢀlowꢀlevel.ꢀTheꢀPT1POLꢀ

bitꢀisꢀusedꢀtoꢀreverseꢀtheꢀpolarityꢀofꢀtheꢀPWMꢀoutputꢀwaveform.

• 10-bit PWM Mode, Edge-aligned Mode

CCRP

Period

Duty

CCRP = 0~1024

CCRP=0 : period= 1024 clocks

CCRP=1~1023: period=1~1023 clocks

CCRA

Ifꢀf_SYSꢀ=ꢀ16MHz,ꢀPTMꢀclockꢀsourceꢀselectꢀf_SYS/4,ꢀCCRPꢀ=ꢀ512ꢀandꢀCCRAꢀ=ꢀ128,

TheꢀPTMꢀPWMꢀoutputꢀfrequencyꢀ=ꢀ(f_SYS/4)ꢀ/ꢀ512ꢀ=ꢀf_SYS/2048ꢀ=ꢀ7.8125kHz,ꢀdutyꢀ=ꢀ128/512ꢀ=ꢀ25%

IfꢀtheꢀDutyꢀvalueꢀdeﬁnedꢀbyꢀtheꢀCCRAꢀregisterꢀisꢀequalꢀtoꢀorꢀgreaterꢀthanꢀtheꢀPeriodꢀvalue,ꢀthenꢀtheꢀ

PWMꢀoutputꢀdutyꢀisꢀ100%.

Rev. 1.41

83

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter Value

PT1DPX = 0; PT1M [1:0] = 10

Counter cleared

by CCRP

Counter Reset when

PT1ON returns high

CCRP

CCRA

Counter Stop if

PT1ON bit low

Pause

Resume

Time

PT1ON

PT1PAU

PT1POL

CCRA Int. Flag

PTMA1F

CCRP Int. Flag

PTMP1F

PTM O/P Pin

(PT1OC=1)

PTM O/P Pin

(PT1OC=0)

PWM Duty Cycle

set by CCRA

PWM resumes

operation

Output controlled by

other pin-shared function

Output Inverts

When PT1POL = 1

PWM Period

set by CCRP

PWM Output Mode

Note:ꢀ1.ꢀHereꢀCounterꢀclearedꢀbyꢀCCRP

2.ꢀAꢀcounterꢀclearꢀsetsꢀtheꢀPWMꢀPeriod

3.ꢀTheꢀinternalꢀPWMꢀfunctionꢀcontinuesꢀrunningꢀevenꢀwhenꢀPT1IO[1:0]ꢀ=ꢀ00ꢀorꢀ01

4.ꢀTheꢀPT1CCLRꢀbitꢀhasꢀnoꢀinﬂuenceꢀonꢀPWMꢀoperation

Rev. 1.41

84

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Single Pulse Output Mode

Toꢀselectꢀthisꢀmode,ꢀtheꢀrequiredꢀbitꢀpairs,ꢀPT1M1ꢀandꢀPT1M0ꢀshouldꢀbeꢀsetꢀtoꢀ10ꢀrespectivelyꢀandꢀ

alsoꢀtheꢀcorrespondingꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀshouldꢀbeꢀsetꢀtoꢀ11ꢀrespectively.ꢀTheꢀSingleꢀPulseꢀ

OutputꢀMode,ꢀasꢀtheꢀnameꢀsuggests,ꢀwillꢀgenerateꢀaꢀsingleꢀshotꢀpulseꢀonꢀtheꢀTMꢀoutputꢀpin.ꢀ

TheꢀtriggerꢀforꢀtheꢀpulseꢀoutputꢀleadingꢀedgeꢀisꢀaꢀlowꢀtoꢀhighꢀtransitionꢀofꢀtheꢀPT1ONꢀbit,ꢀwhichꢀ

canꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogram.ꢀHoweverꢀinꢀtheꢀSingleꢀPulseꢀMode,ꢀtheꢀPT1ONꢀ

bitꢀcanꢀalsoꢀbeꢀmadeꢀtoꢀautomaticallyꢀchangeꢀfromꢀlowꢀtoꢀhighꢀusingꢀtheꢀexternalꢀPTCK1ꢀpin,ꢀ

whichꢀwillꢀinꢀturnꢀinitiateꢀtheꢀSingleꢀPulseꢀoutput.ꢀWhenꢀtheꢀPT1ONꢀbitꢀtransitionsꢀtoꢀaꢀhighꢀlevel,ꢀ

theꢀcounterꢀwillꢀstartꢀrunningꢀandꢀtheꢀpulseꢀleadingꢀedgeꢀwillꢀbeꢀgenerated.ꢀTheꢀPT1ONꢀbitꢀshouldꢀ

remainꢀhighꢀwhenꢀtheꢀpulseꢀisꢀinꢀitsꢀactiveꢀstate.ꢀTheꢀgeneratedꢀpulseꢀtrailingꢀedgeꢀwillꢀbeꢀgeneratedꢀ

whenꢀtheꢀPT1ONꢀbitꢀisꢀclearedꢀtoꢀzero,ꢀwhichꢀcanꢀbeꢀimplementedꢀusingꢀtheꢀapplicationꢀprogramꢀorꢀ

whenꢀaꢀcompareꢀmatchꢀoccursꢀfromꢀComparatorꢀA.

HoweverꢀaꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀautomaticallyꢀclearꢀtheꢀPT1ONꢀbitꢀandꢀthusꢀ

generateꢀtheꢀSingleꢀPulseꢀoutputꢀtrailingꢀedge.ꢀInꢀthisꢀwayꢀtheꢀCCRAꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀ

theꢀpulseꢀwidth.ꢀAꢀcompareꢀmatchꢀfromꢀComparatorꢀAꢀwillꢀalsoꢀgenerateꢀTMꢀinterrupts.ꢀTheꢀcounterꢀ

canꢀonlyꢀbeꢀresetꢀbackꢀtoꢀzeroꢀwhenꢀtheꢀPT1ONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhenꢀtheꢀcounterꢀ

restarts.ꢀInꢀtheꢀSingleꢀPulseꢀModeꢀCCRPꢀisꢀnotꢀused.ꢀTheꢀPT1CCLRꢀbitꢀisꢀalsoꢀnotꢀused.

Leading Edge

Trailing Edge

S/W Command

SET“PT1ON”

or

S/W Command

CLR“PT1ON”

PT1ON bit

0 → 1

PT1ON bit

1 → 0

or

PTCK1 Pin

Transition

CCRA Compare

Match

PTP1/PTP1B Output Pin

Pulse Width = CCRA Value

Single Pulse Generation

Rev. 1.41

85

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter Value

PT1M [1:0] = 10 ; PT1IO [1:0] = 11

Counter stopped

by CCRA

Counter Reset when

PT1ON returns high

CCRA

CCRP

Counter Stops

by software

Resume

Pause

Time

PT1ON

Auto. set by

PTCK1 pin

Software Cleared by

Trigger CCRA match

Software

Trigger

Software

Clear

Software

Trigger

Software

Trigger

PTCK1 pin

PT1PAU

PTCK1 pin

Trigger

PT1POL

No CCRP Interrupts

generated

CCRP Int. Flag

PTMP1F

CCRA Int. Flag

PTMA1F

PTM O/P Pin

(PT1OC=1)

PTM O/P Pin

(PT1OC=0)

Output Inverts

when PT1POL = 1

Pulse Width

set by CCRA

Single Pulse Mode

Note:ꢀ1.ꢀCounterꢀstoppedꢀbyꢀCCRA

2.ꢀCCRPꢀisꢀnotꢀused

3.ꢀTheꢀpulseꢀisꢀtriggeredꢀbyꢀtheꢀPTCK1ꢀpinꢀorꢀbyꢀsettingꢀtheꢀPT1ONꢀbitꢀhigh

4.ꢀAꢀPTCK1ꢀpinꢀactiveꢀedgeꢀwillꢀautomaticallyꢀsetꢀtheꢀPT1ONꢀbitꢀhigh

5.ꢀInꢀtheꢀSingleꢀPulseꢀMode,ꢀPT1IOꢀ[1:0]ꢀmustꢀbeꢀsetꢀtoꢀ"11"ꢀandꢀcanꢀnotꢀbeꢀchanged.

Rev. 1.41

86

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Capture Input Mode

ToꢀselectꢀthisꢀmodeꢀbitsꢀPT1M1ꢀandꢀPT1M0ꢀinꢀtheꢀPTM1C1ꢀregisterꢀshouldꢀbeꢀsetꢀtoꢀ01ꢀrespectively.ꢀ

Thisꢀmodeꢀenablesꢀexternalꢀsignalsꢀtoꢀcaptureꢀandꢀstoreꢀtheꢀpresentꢀvalueꢀofꢀtheꢀinternalꢀcounterꢀ

andꢀcanꢀthereforeꢀbeꢀusedꢀforꢀapplicationsꢀsuchꢀasꢀpulseꢀwidthꢀmeasurements.ꢀTheꢀexternalꢀsignalꢀ

isꢀsuppliedꢀonꢀtheꢀPTP1IꢀorꢀPTCK1ꢀpin,ꢀselectedꢀbyꢀtheꢀPT1CKSꢀbitꢀinꢀtheꢀPTM1C1ꢀregister.ꢀTheꢀ

inputꢀpinꢀactiveꢀedgeꢀcanꢀbeꢀeitherꢀaꢀrisingꢀedge,ꢀaꢀfallingꢀedgeꢀorꢀbothꢀrisingꢀandꢀfallingꢀedges;ꢀtheꢀ

activeꢀedgeꢀtransitionꢀtypeꢀisꢀselectedꢀusingꢀtheꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀinꢀtheꢀPTM1C1ꢀregister.ꢀ

TheꢀcounterꢀisꢀstartedꢀwhenꢀtheꢀPT1ONꢀbitꢀchangesꢀfromꢀlowꢀtoꢀhighꢀwhichꢀisꢀinitiatedꢀusingꢀtheꢀ

applicationꢀprogram.

WhenꢀtheꢀrequiredꢀedgeꢀtransitionꢀappearsꢀonꢀtheꢀPTP1IꢀorꢀPTCK1ꢀpinꢀtheꢀpresentꢀvalueꢀinꢀtheꢀ

counterꢀwillꢀbeꢀlatchedꢀintoꢀtheꢀCCRAꢀregisterꢀandꢀaꢀTMꢀinterruptꢀgenerated.ꢀIrrespectiveꢀofꢀwhatꢀ

eventsꢀoccurꢀonꢀtheꢀPTP1IꢀorꢀPTCK1ꢀpinꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀfreeꢀrunꢀuntilꢀtheꢀPT1ONꢀbitꢀ

changesꢀfromꢀhighꢀtoꢀlow.ꢀWhenꢀaꢀCCRPꢀcompareꢀmatchꢀoccursꢀtheꢀcounterꢀwillꢀresetꢀbackꢀtoꢀzero;ꢀ

inꢀthisꢀwayꢀtheꢀCCRPꢀvalueꢀcanꢀbeꢀusedꢀtoꢀcontrolꢀtheꢀmaximumꢀcounterꢀvalue.ꢀWhenꢀaꢀCCRPꢀ

compareꢀmatchꢀoccursꢀfromꢀComparatorꢀP,ꢀaꢀTMꢀinterruptꢀwillꢀalsoꢀbeꢀgenerated.ꢀCountingꢀtheꢀ

numberꢀofꢀoverﬂowꢀinterruptꢀsignalsꢀfromꢀtheꢀCCRPꢀcanꢀbeꢀaꢀusefulꢀmethodꢀinꢀmeasuringꢀlongꢀpulseꢀ

widths.ꢀTheꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀcanꢀselectꢀtheꢀactiveꢀtriggerꢀedgeꢀonꢀtheꢀPTP1IꢀorꢀPTCK1ꢀpinꢀ

toꢀbeꢀaꢀrisingꢀedge,ꢀfallingꢀedgeꢀorꢀbothꢀedgeꢀtypes.ꢀIfꢀtheꢀPT1IO1ꢀandꢀPT1IO0ꢀbitsꢀareꢀbothꢀsetꢀhigh,ꢀ

thenꢀnoꢀcaptureꢀoperationꢀwillꢀtakeꢀplaceꢀirrespectiveꢀofꢀwhatꢀhappensꢀonꢀtheꢀPTP1IꢀorꢀPTCK1ꢀpin,ꢀ

howeverꢀitꢀmustꢀbeꢀnotedꢀthatꢀtheꢀcounterꢀwillꢀcontinueꢀtoꢀrun.

AsꢀtheꢀPTP1IꢀorꢀPTCK1ꢀpinꢀisꢀpinꢀsharedꢀwithꢀotherꢀfunctions,ꢀcareꢀmustꢀbeꢀtakenꢀifꢀtheꢀPTMꢀisꢀinꢀ

theꢀCaptureꢀInputꢀMode.ꢀThisꢀisꢀbecauseꢀifꢀtheꢀpinꢀisꢀsetupꢀasꢀanꢀoutput,ꢀthenꢀanyꢀtransitionsꢀonꢀthisꢀ

pinꢀmayꢀcauseꢀanꢀinputꢀcaptureꢀoperationꢀtoꢀbeꢀexecuted.ꢀTheꢀPT1CCLR,ꢀPT1OCꢀandꢀPT1POLꢀbitsꢀ

areꢀnotꢀusedꢀinꢀthisꢀMode.

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Counter Value

PTnM[1:0] = 01

Counter cleared by

CCRP

Counter

Stop

Counter

Reset

CCRP

YY

Resume

Pause

XX

Time

PTnON

PTnPAU

Active

edge

Active

edge

Active edge

PTMn Capture Pin

PTPnI or PTCKn

CCRA Int.

Flag PTMnAF

CCRP Int.

Flag PTMnPF

XX

YY

XX

YY

CCRA Value

00 - Rising edge

01 - Falling edge

10 - Both edges

11 - Disable Capture

PTnIO [1:0] Value

Capture Input Mode (n=1)

Note:ꢀ1.ꢀPT1M[1:0]ꢀ=ꢀ01ꢀandꢀactiveꢀedgeꢀsetꢀbyꢀtheꢀPT1IO[1:0]ꢀbits

2.ꢀAꢀTMꢀCaptureꢀinputꢀpinꢀactiveꢀedgeꢀtransfersꢀcounterꢀvalueꢀtoꢀCCRA

3.ꢀTheꢀPT1CCLRꢀbitꢀisꢀnotꢀused

4.ꢀNoꢀoutputꢀfunctionꢀ–ꢀPT1OCꢀandꢀPT1POLꢀbitsꢀareꢀnotꢀused

5.ꢀCCRPꢀdeterminesꢀtheꢀcounterꢀvalueꢀandꢀtheꢀcounterꢀhasꢀaꢀmaximumꢀcountꢀvalueꢀwhenꢀCCRPꢀisꢀequalꢀtoꢀ

zero

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Interrupts

Interruptsꢀareꢀanꢀimportantꢀpartꢀofꢀanyꢀmicrocontrollerꢀsystem.ꢀWhenꢀanꢀexternalꢀeventꢀorꢀanꢀinternalꢀ

functionꢀsuchꢀasꢀaꢀTimerꢀModuleꢀrequiresꢀmicrocontrollerꢀattention,ꢀtheirꢀcorrespondingꢀinterruptꢀ

willꢀenforceꢀaꢀtemporaryꢀsuspensionꢀofꢀtheꢀmainꢀprogramꢀallowingꢀtheꢀmicrocontrollerꢀtoꢀdirectꢀ

attentionꢀtoꢀtheirꢀrespectiveꢀneeds.ꢀTheꢀdevicesꢀcontainꢀanꢀexternalꢀinterruptꢀandꢀinternalꢀinterruptsꢀ

functions.ꢀTheꢀexternalꢀinterruptꢀisꢀgeneratedꢀbyꢀtheꢀactionꢀofꢀtheꢀexternalꢀINTꢀpin,ꢀwhileꢀtheꢀinternalꢀ

interruptsꢀareꢀgeneratedꢀbyꢀvariousꢀinternalꢀfunctionsꢀsuchꢀasꢀtheꢀTMs,ꢀTimeꢀBaseꢀandꢀEEPROM.

Interrupt Registers

Overallꢀinterruptꢀcontrol,ꢀwhichꢀbasicallyꢀmeansꢀtheꢀsettingꢀofꢀrequestꢀflagsꢀwhenꢀcertainꢀ

microcontrollerꢀconditionsꢀoccurꢀandꢀtheꢀsettingꢀofꢀinterruptꢀenableꢀbitsꢀbyꢀtheꢀapplicationꢀprogram,ꢀ

isꢀcontrolledꢀbyꢀaꢀseriesꢀofꢀregisters,ꢀlocatedꢀinꢀtheꢀSpecialꢀPurposeꢀDataꢀMemory,ꢀasꢀshownꢀinꢀtheꢀ

accompanyingꢀtable.ꢀTheꢀnumberꢀofꢀregistersꢀdependsꢀuponꢀtheꢀdeviceꢀchosenꢀbutꢀfallꢀintoꢀthreeꢀ

categories.ꢀTheꢀﬁrstꢀisꢀtheꢀINTC0~INTC1ꢀregistersꢀwhichꢀsetupꢀtheꢀprimaryꢀinterrupts,ꢀtheꢀsecondꢀ

isꢀtheꢀMFI0~MFI1ꢀregistersꢀwhichꢀsetupꢀtheꢀMulti-functionꢀinterrupts.ꢀFinallyꢀthereꢀisꢀanꢀINTEGꢀ

registerꢀtoꢀsetupꢀtheꢀexternalꢀinterruptꢀtriggerꢀedgeꢀtype.ꢀ

Eachꢀregisterꢀcontainsꢀaꢀnumberꢀofꢀenableꢀbitsꢀtoꢀenableꢀorꢀdisableꢀindividualꢀregistersꢀasꢀwellꢀasꢀ

interruptꢀflagsꢀtoꢀindicateꢀtheꢀpresenceꢀofꢀanꢀinterruptꢀrequest.ꢀTheꢀnamingꢀconventionꢀofꢀtheseꢀ

followsꢀaꢀspeciﬁcꢀpattern.ꢀFirstꢀisꢀlistedꢀanꢀabbreviatedꢀinterruptꢀtype,ꢀthenꢀtheꢀ(optional)ꢀnumberꢀofꢀ

thatꢀinterruptꢀfollowedꢀbyꢀeitherꢀanꢀ"E"ꢀforꢀenable/disableꢀbitꢀorꢀ"F"ꢀforꢀrequestꢀﬂag.

Function

Global

Enable Bit

EMI

Request Flag

—

Notes

—

INT Pin

INTE

INTF

—

Multi-function

Time Base

EEPROM

MFnE

MFnF

n=0 or 1

—

TBnE

TBnF

DEE

DEF

STMA0E

STMP0E

PTMA1E

PTMP1E

STMA0F

STMP0F

PTMA1F

PTMP1F

TM

—

Interrupt Register Bit Naming Conventions

Interrupt Register Contents

• HT68F002/HT68F0025

Register

Bit

Name

7

6

—

5

4

3

—

2

—

1

0

INTEG

INTC0

INTC1

MFI0

—

INT0S1 INT0S0

TB1F

—

TB0F

DEF

INTF

MF0F

TB1E

—

TB0E

—

INTE

DEE

EMI

MF0E

—

STMA0F STMP0F

—

STMA0E STMP0E

• HT68F003

Bit

Register

Name

7

—

6

—

5

4

3

—

2

—

1

0

INTEG

INTC0

INTC1

MFI0

—

INT0S1 INT0S0

—

TB1F

—

TB0F

DEF

INTF

MF0F

TB1E

MF1E

—

TB0E

—

INTE

DEE

EMI

MF1F

—

MF0E

—

STMA0F STMP0F

PTMA1F PTMP1F

—

STMA0E STMP0E

PTMA1E PTMP1E

MFI1

—

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

INTEG Register

Bit

Name

R/W

7

6

5

4

3

2

1

INT0S1

R/W

0

INT0S0

R/W

0

—

POR

Bitꢀ7ꢀ~ꢀ2ꢀꢀ

Bitꢀ1ꢀ~ꢀ0

Unimplemented,ꢀreadꢀasꢀ"0"

INT0S1, INT0S0:ꢀDeﬁnesꢀINTꢀinterruptꢀactiveꢀedge

00:ꢀDisableꢀInterrupt

01:ꢀRisingꢀEdgeꢀInterrupt

10:ꢀFallingꢀEdgeꢀInterrupt

11:ꢀDualꢀEdgeꢀInterrupt

INTC0 Register

Bit

Name

R/W

7

6

TB1F

R/W

0

5

TB0F

R/W

0

4

3

TB1E

R/W

0

2

TB0E

R/W

0

1

INTE

R/W

0

—

INTF

R/W

0

EMI

R/W

0

POR

Bitꢀ7ꢀ

Bitꢀ6

Unimplemented,ꢀreadꢀasꢀ"0"

TB1F:ꢀTimeꢀBaseꢀ1ꢀInterruptꢀRequestꢀFlag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ5

Bitꢀ4

Bitꢀ3ꢀ

Bitꢀ2

Bitꢀ1

Bitꢀ0

TB0F:ꢀTimeꢀBaseꢀ0ꢀInterruptꢀRequestꢀFlag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

INTF:ꢀINTꢀInterruptꢀRequestꢀFlag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

TB1E :ꢀTimeꢀBaseꢀ1ꢀInterruptꢀControl

0:ꢀDisable

1:ꢀEnable

TB0E:ꢀTimeꢀBaseꢀ0ꢀInterruptꢀControl

0:ꢀDisable

1:ꢀEnable

INTE:ꢀINTꢀInterruptꢀControl

0:ꢀDisable

1:ꢀEnable

EMI:ꢀGlobalꢀInterruptꢀControl

0:ꢀDisable

1:ꢀEnable

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

INTC1 Register – HT68F002/HT68F0025

Bit

Name

R/W

7

6

5

4

MF0F

R/W

0

3

2

1

0

MF0E

R/W

0

—

DEF

R/W

0

—

DEE

R/W

0

POR

Bitꢀ7~6ꢀ

Bitꢀ5

Unimplemented,ꢀreadꢀasꢀ"0"

DEF:ꢀDataꢀEEPROMꢀInterruptꢀRequestꢀFlag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ4

MF0F:ꢀMulti-functionꢀ0ꢀInterruptꢀRequestꢀFlag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ3~2ꢀ

Bitꢀ1

Unimplemented,ꢀreadꢀasꢀ"0"

DEE:ꢀDataꢀEEPROMꢀInterruptꢀControl

0:ꢀDisable

1:ꢀEnable

Bitꢀ0

MF0E:ꢀMulti-functionꢀ0ꢀInterruptꢀControl

0:ꢀDisable

1:ꢀEnable

INTC1 Register – HT68F003

Bit

Name

R/W

7

MF1F

R/W

0

6

5

4

MF0F

R/W

0

3

MF1E

R/W

0

2

1

0

MF0E

R/W

0

—

DEF

R/W

0

—

DEE

R/W

0

POR

Bitꢀ7

MF1F:ꢀMulti-functionꢀ1ꢀInterruptꢀRequestꢀFlag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ6ꢀ

Bitꢀ5

Unimplemented,ꢀreadꢀasꢀ"0"

DEF:ꢀDataꢀEEPROMꢀInterruptꢀRequestꢀFlag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ4

MF0F:ꢀMulti-functionꢀ0ꢀInterruptꢀRequestꢀFlag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ3ꢀ

MF1E:ꢀMulti-functionꢀ1ꢀInterruptꢀControl

0:ꢀDisable

1:ꢀEnable

Bitꢀ2ꢀ

Bitꢀ1

Unimplemented,ꢀreadꢀasꢀ"0"

DEE:ꢀDataꢀEEPROMꢀInterruptꢀControl

0:ꢀDisable

1:ꢀEnable

Bitꢀ0

MF0E:ꢀMulti-functionꢀ0ꢀInterruptꢀControl

0:ꢀDisable

1:ꢀEnable

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

MFI0 Register

Bit

Name

R/W

7

6

5

4

3

2

1

0

—

STMA0F STMP0F

—

STMA0E STMP0E

R/W

0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7ꢀ~ꢀ6ꢀ

Bitꢀ5

Unimplemented,ꢀreadꢀasꢀ"0"

STMA0F:ꢀSTMꢀComparatorꢀAꢀmatchꢀinterruptꢀrequestꢀﬂag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ4

STMP0F:ꢀSTMꢀComparatorꢀPꢀmatchꢀinterruptꢀrequestꢀﬂag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ3ꢀ~ꢀ2ꢀ

Bitꢀ1

Unimplemented,ꢀreadꢀasꢀ"0"

STMA0E:ꢀSTMꢀComparatorꢀAꢀmatchꢀinterruptꢀcontrol

0:ꢀDisable

1:ꢀEnable

Bitꢀ0

STMP0E:ꢀSTMꢀComparatorꢀPꢀmatchꢀinterruptꢀcontrol

0:ꢀDisable

1:ꢀEnable

MFI1 Register – HT68F003 only

Bit

Name

R/W

7

6

5

4

3

2

1

0

—

PTMA1F PTMP1F

—

PTMA1E PTMP1E

R/W

0

R/W

0

R/W

0

R/W

0

POR

Bitꢀ7ꢀ~ꢀ6ꢀ

Bitꢀ5

Unimplemented,ꢀreadꢀasꢀ"0"

PTMA1F:ꢀPTMꢀComparatorꢀAꢀmatchꢀinterruptꢀrequestꢀﬂag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ4

PTMP1F:ꢀPTMꢀComparatorꢀPꢀmatchꢀinterruptꢀrequestꢀﬂag

0:ꢀNoꢀrequest

1:ꢀInterruptꢀrequest

Bitꢀ3ꢀ~ꢀ2ꢀꢀ

Bitꢀ1

Unimplemented,ꢀreadꢀasꢀ"0"

PTMA1E:ꢀPTMꢀComparatorꢀAꢀmatchꢀinterruptꢀcontrol

0:ꢀDisable

1:ꢀEnable

Bitꢀ0

PTMP1E:ꢀPTMꢀComparatorꢀPꢀmatchꢀinterruptꢀcontrol

0:ꢀDisable

1:ꢀEnable

Rev. 1.41

92

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Interrupt Operation

Whenꢀtheꢀconditionsꢀforꢀanꢀinterruptꢀeventꢀoccur,ꢀsuchꢀasꢀaꢀTMꢀComparatorꢀPꢀorꢀComparatorꢀAꢀ

matchꢀetc,ꢀtheꢀrelevantꢀinterruptꢀrequestꢀﬂagꢀwillꢀbeꢀset.ꢀWhetherꢀtheꢀrequestꢀﬂagꢀactuallyꢀgeneratesꢀ

aꢀprogramꢀjumpꢀtoꢀtheꢀrelevantꢀinterruptꢀvectorꢀisꢀdeterminedꢀbyꢀtheꢀconditionꢀofꢀtheꢀinterruptꢀenableꢀ

bit.ꢀIfꢀtheꢀenableꢀbitꢀisꢀsetꢀhighꢀthenꢀtheꢀprogramꢀwillꢀjumpꢀtoꢀitsꢀrelevantꢀvector;ꢀifꢀtheꢀenableꢀbitꢀisꢀ

zeroꢀthenꢀalthoughꢀtheꢀinterruptꢀrequestꢀﬂagꢀisꢀsetꢀanꢀactualꢀinterruptꢀwillꢀnotꢀbeꢀgeneratedꢀandꢀtheꢀ

programꢀwillꢀnotꢀjumpꢀtoꢀtheꢀrelevantꢀinterruptꢀvector.ꢀTheꢀglobalꢀinterruptꢀenableꢀbit,ꢀifꢀclearedꢀtoꢀ

zero,ꢀwillꢀdisableꢀallꢀinterrupts.

Whenꢀanꢀinterruptꢀisꢀgenerated,ꢀtheꢀProgramꢀCounter,ꢀwhichꢀstoresꢀtheꢀaddressꢀofꢀtheꢀnextꢀinstructionꢀ

toꢀbeꢀexecuted,ꢀwillꢀbeꢀtransferredꢀontoꢀtheꢀstack.ꢀTheꢀProgramꢀCounterꢀwillꢀthenꢀbeꢀloadedꢀwithꢀaꢀ

newꢀaddressꢀwhichꢀwillꢀbeꢀtheꢀvalueꢀofꢀtheꢀcorrespondingꢀinterruptꢀvector.ꢀTheꢀmicrocontrollerꢀwillꢀ

thenꢀfetchꢀitsꢀnextꢀinstructionꢀfromꢀthisꢀinterruptꢀvector.ꢀTheꢀinstructionꢀatꢀthisꢀvectorꢀwillꢀusuallyꢀ

beꢀaꢀ"JMP"ꢀwhichꢀwillꢀjumpꢀtoꢀanotherꢀsectionꢀofꢀprogramꢀwhichꢀisꢀknownꢀasꢀtheꢀinterruptꢀserviceꢀ

routine.ꢀHereꢀisꢀlocatedꢀtheꢀcodeꢀtoꢀcontrolꢀtheꢀappropriateꢀinterrupt.ꢀTheꢀinterruptꢀserviceꢀroutineꢀ

mustꢀbeꢀterminatedꢀwithꢀaꢀ"RETI",ꢀwhichꢀretrievesꢀtheꢀoriginalꢀProgramꢀCounterꢀaddressꢀfromꢀ

theꢀstackꢀandꢀallowsꢀtheꢀmicrocontrollerꢀtoꢀcontinueꢀwithꢀnormalꢀexecutionꢀatꢀtheꢀpointꢀwhereꢀtheꢀ

interruptꢀoccurred.ꢀ

Theꢀvariousꢀinterruptꢀenableꢀbits,ꢀtogetherꢀwithꢀtheirꢀassociatedꢀrequestꢀflags,ꢀareꢀshownꢀinꢀtheꢀ

accompanyingꢀdiagramsꢀwithꢀtheirꢀorderꢀofꢀpriority.ꢀSomeꢀinterruptꢀsourcesꢀhaveꢀtheirꢀownꢀ

individualꢀvectorꢀwhileꢀothersꢀshareꢀtheꢀsameꢀmulti-functionꢀinterruptꢀvector.ꢀOnceꢀanꢀinterruptꢀ

subroutineꢀisꢀserviced,ꢀallꢀtheꢀotherꢀinterruptsꢀwillꢀbeꢀblocked,ꢀasꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀ

EMIꢀbitꢀwillꢀbeꢀclearedꢀautomatically.ꢀThisꢀwillꢀpreventꢀanyꢀfurtherꢀinterruptꢀnestingꢀfromꢀoccurring.ꢀ

However,ꢀifꢀotherꢀinterruptꢀrequestsꢀoccurꢀduringꢀthisꢀinterval,ꢀalthoughꢀtheꢀinterruptꢀwillꢀnotꢀbeꢀ

immediatelyꢀserviced,ꢀtheꢀrequestꢀﬂagꢀwillꢀstillꢀbeꢀrecorded.

Ifꢀanꢀinterruptꢀrequiresꢀimmediateꢀservicingꢀwhileꢀtheꢀprogramꢀisꢀalreadyꢀinꢀanotherꢀinterruptꢀserviceꢀ

routine,ꢀtheꢀEMIꢀbitꢀshouldꢀbeꢀsetꢀafterꢀenteringꢀtheꢀroutine,ꢀtoꢀallowꢀinterruptꢀnesting.ꢀIfꢀtheꢀstackꢀ

isꢀfull,ꢀtheꢀinterruptꢀrequestꢀwillꢀnotꢀbeꢀacknowledged,ꢀevenꢀifꢀtheꢀrelatedꢀinterruptꢀisꢀenabled,ꢀuntilꢀ

theꢀStackꢀPointerꢀisꢀdecremented.ꢀIfꢀimmediateꢀserviceꢀisꢀdesired,ꢀtheꢀstackꢀmustꢀbeꢀpreventedꢀfromꢀ

becomingꢀfull.ꢀInꢀcaseꢀofꢀsimultaneousꢀrequests,ꢀtheꢀaccompanyingꢀdiagramꢀshowsꢀtheꢀpriorityꢀthatꢀ

isꢀapplied.ꢀAllꢀofꢀtheꢀinterruptꢀrequestꢀﬂagsꢀwhenꢀsetꢀwillꢀwake-upꢀtheꢀdeviceꢀifꢀitꢀisꢀinꢀSLEEPꢀorꢀ

IDLEꢀMode,ꢀhoweverꢀtoꢀpreventꢀaꢀwake-upꢀfromꢀoccurringꢀtheꢀcorrespondingꢀﬂagꢀshouldꢀbeꢀsetꢀ

beforeꢀtheꢀdeviceꢀisꢀinꢀSLEEPꢀorꢀIDLEꢀMode.

EMI auto disabled in ISR

Legend

xxF Request Flag, no auto reset in ISR

Interrupt

Name

Request

Flags

Enable

Bits

Master

Enable

Vector Priority

xxF Request Flag, auto reset in ISR

xxE Enable Bits

High

04H

INT Pin

INT0F

INT0E

TB0E

TB1E

MF0E

DEE

EMI

Time Base 0 TB0F

Time Base 1 TB1F

08H

0CH

10H

14H

Interrupt

Name

Request

Flags

Enable

Bits

STM P

STM A

STMP0F

STMA0F

STMP0E

STMA0E

M. Funct. 0

EEPROM

MF0F

DEF

PTM P

PTM A

PTMP1F

PTMA1F

PTMP1E

PTMA1E

M. Funct. 1

MF1F

MF1E

1CH

Low

Interrupts contained within

Multi-Function Interrupts

HT68F003 only

Interrupt Structure

Rev. 1.41

93

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

External Interrupt

TheꢀexternalꢀinterruptꢀisꢀcontrolledꢀbyꢀsignalꢀtransitionsꢀonꢀtheꢀpinꢀINT.ꢀAnꢀexternalꢀinterruptꢀ

requestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀexternalꢀinterruptꢀrequestꢀﬂag,ꢀINTF,ꢀisꢀset,ꢀwhichꢀwillꢀoccurꢀwhenꢀ

aꢀtransition,ꢀwhoseꢀtypeꢀisꢀchosenꢀbyꢀtheꢀedgeꢀselectꢀbits,ꢀappearsꢀonꢀtheꢀexternalꢀinterruptꢀpin.ꢀToꢀ

allowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀtheꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀ

theꢀexternalꢀinterruptꢀenableꢀbit,ꢀINTE,ꢀmustꢀﬁrstꢀbeꢀset.ꢀAdditionallyꢀtheꢀcorrectꢀinterruptꢀedgeꢀtypeꢀ

mustꢀbeꢀselectedꢀusingꢀtheꢀINTEGꢀregisterꢀtoꢀenableꢀtheꢀexternalꢀinterruptꢀfunctionꢀandꢀtoꢀchooseꢀ

theꢀtriggerꢀedgeꢀtype.ꢀAsꢀtheꢀexternalꢀinterruptꢀpinꢀisꢀpin-sharedꢀwithꢀanꢀI/Oꢀpin,ꢀitꢀcanꢀonlyꢀbeꢀ

conﬁguredꢀasꢀexternalꢀinterruptꢀpinꢀifꢀitsꢀexternalꢀinterruptꢀenableꢀbitꢀinꢀtheꢀcorrespondingꢀinterruptꢀ

registerꢀhasꢀbeenꢀset.ꢀTheꢀpinꢀmustꢀalsoꢀbeꢀsetupꢀasꢀanꢀinputꢀbyꢀsettingꢀtheꢀcorrespondingꢀbitꢀinꢀtheꢀ

portꢀcontrolꢀregister.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀtheꢀcorrectꢀtransitionꢀ

typeꢀappearsꢀonꢀtheꢀexternalꢀinterruptꢀpin,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀexternalꢀinterruptꢀvector,ꢀwillꢀtakeꢀ

place.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀexternalꢀinterruptꢀrequestꢀﬂag,ꢀINTF,ꢀwillꢀbeꢀautomaticallyꢀ

resetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.ꢀNoteꢀthatꢀtheꢀpull-highꢀ

resistorꢀselectionꢀonꢀtheꢀexternalꢀinterruptꢀpinꢀwillꢀremainꢀvalidꢀevenꢀifꢀtheꢀpinꢀisꢀusedꢀasꢀanꢀexternalꢀ

interruptꢀinput.ꢀ

TheꢀINTEGꢀregisterꢀisꢀusedꢀtoꢀselectꢀtheꢀtypeꢀofꢀactiveꢀedgeꢀthatꢀwillꢀtriggerꢀtheꢀexternalꢀinterrupt.ꢀ

Aꢀchoiceꢀofꢀeitherꢀrisingꢀorꢀfallingꢀorꢀbothꢀedgeꢀtypesꢀcanꢀbeꢀchosenꢀtoꢀtriggerꢀanꢀexternalꢀinterrupt.ꢀ

NoteꢀthatꢀtheꢀINTEGꢀregisterꢀcanꢀalsoꢀbeꢀusedꢀtoꢀdisableꢀtheꢀexternalꢀinterruptꢀfunction.

Multi-function Interrupt

WithinꢀtheseꢀdevicesꢀthereꢀareꢀupꢀtoꢀtwoꢀMulti-functionꢀinterrupts.ꢀUnlikeꢀtheꢀotherꢀindependentꢀ

interrupts,ꢀtheseꢀinterruptsꢀhaveꢀnoꢀindependentꢀsource,ꢀbutꢀratherꢀareꢀformedꢀfromꢀotherꢀexistingꢀ

interruptꢀsources,ꢀnamelyꢀtheꢀTMꢀInterrupts.ꢀ

AꢀMulti-functionꢀinterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀanyꢀofꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀ

ﬂags,ꢀMF0F~MF1Fꢀareꢀset.ꢀTheꢀMulti-functionꢀinterruptꢀﬂagsꢀwillꢀbeꢀsetꢀwhenꢀanyꢀofꢀtheirꢀincludedꢀ

functionsꢀgenerateꢀanꢀinterruptꢀrequestꢀﬂag.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀ

vectorꢀaddress,ꢀwhenꢀtheꢀMulti-functionꢀinterruptꢀisꢀenabledꢀandꢀtheꢀstackꢀisꢀnotꢀfull,ꢀandꢀeitherꢀoneꢀ

ofꢀtheꢀinterruptsꢀcontainedꢀwithinꢀeachꢀofꢀMulti-functionꢀinterruptꢀoccurs,ꢀaꢀsubroutineꢀcallꢀtoꢀoneꢀofꢀ

theꢀMulti-functionꢀinterruptꢀvectorsꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀrelatedꢀMulti-

Functionꢀrequestꢀﬂag,ꢀwillꢀbeꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀ

disableꢀotherꢀinterrupts.

However,ꢀitꢀmustꢀbeꢀnotedꢀthat,ꢀalthoughꢀtheꢀMulti-functionꢀInterruptꢀﬂagsꢀwillꢀbeꢀautomaticallyꢀ

resetꢀwhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀrequestꢀﬂagsꢀfromꢀtheꢀoriginalꢀsourceꢀofꢀtheꢀMulti-functionꢀ

interrupts,ꢀnamelyꢀtheꢀTMꢀInterrupts,ꢀwillꢀnotꢀbeꢀautomaticallyꢀresetꢀandꢀmustꢀbeꢀmanuallyꢀresetꢀbyꢀ

theꢀapplicationꢀprogram.

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Time Base Interrupts

TheꢀfunctionꢀofꢀtheꢀTimeꢀBaseꢀInterruptsꢀisꢀtoꢀprovideꢀregularꢀtimeꢀsignalꢀinꢀtheꢀformꢀofꢀanꢀinternalꢀ

interrupt.ꢀTheyꢀareꢀcontrolledꢀbyꢀtheꢀoverﬂowꢀsignalsꢀfromꢀtheirꢀrespectiveꢀtimerꢀfunctions.ꢀWhenꢀ

theseꢀhappensꢀtheirꢀrespectiveꢀinterruptꢀrequestꢀflags,ꢀTB0FꢀorꢀTB1Fꢀwillꢀbeꢀset.ꢀToꢀallowꢀtheꢀ

programꢀtoꢀbranchꢀtoꢀtheirꢀrespectiveꢀinterruptꢀvectorꢀaddresses,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMIꢀ

andꢀTimeꢀBaseꢀenableꢀbits,ꢀTB0EꢀorꢀTB1E,ꢀmustꢀﬁrstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀ

isꢀnotꢀfullꢀandꢀtheꢀTimeꢀBaseꢀoverﬂows,ꢀaꢀsubroutineꢀcallꢀtoꢀtheirꢀrespectiveꢀvectorꢀlocationsꢀwillꢀ

takeꢀplace.ꢀWhenꢀtheꢀinterruptꢀisꢀserviced,ꢀtheꢀrespectiveꢀinterruptꢀrequestꢀﬂag,ꢀTB0FꢀorꢀTB1F,ꢀwillꢀ

beꢀautomaticallyꢀresetꢀandꢀtheꢀEMIꢀbitꢀwillꢀbeꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts.

TheꢀpurposeꢀofꢀtheꢀTimeꢀBaseꢀInterruptꢀisꢀtoꢀprovideꢀanꢀinterruptꢀsignalꢀatꢀﬁxedꢀtimeꢀperiods.ꢀTheirꢀ

clockꢀsourcesꢀoriginateꢀfromꢀtheꢀinternalꢀclockꢀsourceꢀf_TB.ꢀThisꢀf_TBꢀinputꢀclockꢀpassesꢀthroughꢀaꢀ

divider,ꢀtheꢀdivisionꢀratioꢀofꢀwhichꢀisꢀselectedꢀbyꢀprogrammingꢀtheꢀappropriateꢀbitsꢀinꢀtheꢀTBCꢀ

registerꢀtoꢀobtainꢀlongerꢀinterruptꢀperiodsꢀwhoseꢀvalueꢀranges.ꢀTheꢀclockꢀsourceꢀthatꢀgeneratesꢀf_TB,ꢀ

whichꢀinꢀturnꢀcontrolsꢀtheꢀTimeꢀBaseꢀinterruptꢀperiod,ꢀcanꢀoriginateꢀfromꢀseveralꢀdifferentꢀsources,ꢀ

asꢀshownꢀinꢀtheꢀSystemꢀOperatingꢀModeꢀsection.

TBC Register

Bit

Name

R/W

7

TBON

R/W

0

6

TBCK

R/W

0

5

TB11

R/W

1

4

TB10

R/W

1

3

2

TB02

R/W

1

TB01

R/W

1

0

TB00

R/W

1

—

POR

Bitꢀ7

TBON:ꢀTB0ꢀandꢀTB1ꢀControlꢀbit

0:ꢀDisable

1:ꢀEnable

Bitꢀ6

TBCK:ꢀSelectꢀf_TBꢀClock

0:ꢀf_TBC

1:ꢀf_SYS/4

Bitꢀ5ꢀ~ꢀ4

TB11 ~ TB10:ꢀSelectꢀTimeꢀBaseꢀ1ꢀTime-outꢀPeriod

00:ꢀ4096/f_TB

01:ꢀ8192/f_TB

10:ꢀ16384/f_TB

11:ꢀ32768/f_TB

Bitꢀ3ꢀ

Bitꢀ2ꢀ~ꢀ0

Unimplemented,ꢀreadꢀasꢀ"0"

TB02 ~ TB00:ꢀSelectꢀTimeꢀBaseꢀ0ꢀTime-outꢀPeriod

000:ꢀ256/f_TB

001:ꢀ512/f_TB

010:ꢀ1024/f_TB

011:ꢀ2048/f_TB

100:ꢀ4096/f_TB

101:ꢀ8192/f_TB

110:ꢀ16384/f_TB

111:ꢀ32768/f_TB

T

0

B

~

2

B

T

0

f

S

Y

/

4

8

5

1

T

m

i

e

B

a

e

s

0

I

n

r

u

t

r

e

p

¸

2

~

2

M

U

X

f

T

B

f

T

C

B

L

R

I

C

1

2

1

5

T

m

i

e

B

a

e

s

1

I

n

r

u

t

r

e

p

¸

2

~

2

T

C

B

K

B

i

t

T

1

B

~

1

B

T

0

1

Time Base Interrupt

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EEPROM Interrupt

AnꢀEEPROMꢀInterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀtheꢀEEPROMꢀInterruptꢀrequestꢀﬂag,ꢀDEF,ꢀisꢀset,ꢀ

whichꢀoccursꢀwhenꢀanꢀEEPROMꢀWriteꢀcycleꢀends.ꢀToꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀ

interruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀbit,ꢀEMI,ꢀandꢀEEPROMꢀInterruptꢀenableꢀbit,ꢀ

DEE,ꢀmustꢀﬁrstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀanꢀEEPROMꢀWriteꢀ

cycleꢀends,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrespectiveꢀEEPROMꢀInterruptꢀvector,ꢀwillꢀtakeꢀplace.ꢀWhenꢀtheꢀ

EEPROMꢀInterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀinterrupts,ꢀ

andꢀtheꢀEEPROMꢀinterruptꢀrequestꢀﬂag,ꢀDEF,ꢀwillꢀalsoꢀbeꢀautomaticallyꢀcleared.

TM Interrupts

TheꢀTMsꢀeachꢀhasꢀtwoꢀinterrupts.ꢀAllꢀofꢀtheꢀTMꢀinterruptsꢀareꢀcontainedꢀwithinꢀtheꢀMulti-functionꢀ

Interrupts.ꢀForꢀeachꢀofꢀtheꢀTMsꢀthereꢀareꢀtwoꢀinterruptꢀrequestꢀflagsꢀxTMPnFꢀandꢀxTMAnFꢀandꢀ

twoꢀenableꢀbitsꢀxTMPnEꢀandꢀxTMAnE.ꢀAꢀTMꢀinterruptꢀrequestꢀwillꢀtakeꢀplaceꢀwhenꢀanyꢀofꢀtheꢀ

TMꢀrequestꢀﬂagsꢀareꢀset,ꢀaꢀsituationꢀwhichꢀoccursꢀwhenꢀaꢀTMꢀcomparatorꢀPꢀorꢀcomparatorꢀAꢀmatchꢀ

situationꢀhappens.ꢀ

Toꢀallowꢀtheꢀprogramꢀtoꢀbranchꢀtoꢀitsꢀrespectiveꢀinterruptꢀvectorꢀaddress,ꢀtheꢀglobalꢀinterruptꢀenableꢀ

bit,ꢀEMI,ꢀandꢀtheꢀrespectiveꢀTMꢀInterruptꢀenableꢀbit,ꢀandꢀassociatedꢀMulti-functionꢀinterruptꢀenableꢀ

bit,ꢀMFnF,ꢀmustꢀﬁrstꢀbeꢀset.ꢀWhenꢀtheꢀinterruptꢀisꢀenabled,ꢀtheꢀstackꢀisꢀnotꢀfullꢀandꢀaꢀTMꢀcomparatorꢀ

matchꢀsituationꢀoccurs,ꢀaꢀsubroutineꢀcallꢀtoꢀtheꢀrelevantꢀTMꢀInterruptꢀvectorꢀlocations,ꢀwillꢀtakeꢀ

place.ꢀWhenꢀtheꢀTMꢀinterruptꢀisꢀserviced,ꢀtheꢀEMIꢀbitꢀwillꢀbeꢀautomaticallyꢀclearedꢀtoꢀdisableꢀotherꢀ

interrupts,ꢀhoweverꢀonlyꢀtheꢀrelatedꢀMFnFꢀﬂagꢀwillꢀbeꢀautomaticallyꢀcleared.ꢀAsꢀtheꢀTMꢀinterruptꢀ

requestꢀﬂagsꢀwillꢀnotꢀbeꢀautomaticallyꢀcleared,ꢀtheyꢀhaveꢀtoꢀbeꢀclearedꢀbyꢀtheꢀapplicationꢀprogram.

Interrupt Wake-up Function

Eachꢀofꢀtheꢀinterruptꢀfunctionsꢀhasꢀtheꢀcapabilityꢀofꢀwakingꢀupꢀtheꢀmicrocontrollerꢀwhenꢀinꢀtheꢀ

SLEEPꢀorꢀIDLEꢀMode.ꢀAꢀwake-upꢀisꢀgeneratedꢀwhenꢀanꢀinterruptꢀrequestꢀﬂagꢀchangesꢀfromꢀlowꢀtoꢀ

highꢀandꢀisꢀindependentꢀofꢀwhetherꢀtheꢀinterruptꢀisꢀenabledꢀorꢀnot.ꢀTherefore,ꢀevenꢀthoughꢀtheꢀdeviceꢀ

isꢀinꢀtheꢀSLEEPꢀorꢀIDLEꢀModeꢀandꢀitsꢀsystemꢀoscillatorꢀstopped,ꢀsituationsꢀsuchꢀasꢀexternalꢀedgeꢀ

transitionsꢀonꢀtheꢀexternalꢀinterruptꢀpin,ꢀaꢀlowꢀpowerꢀsupplyꢀvoltageꢀorꢀcomparatorꢀinputꢀchangeꢀmayꢀ

causeꢀtheirꢀrespectiveꢀinterruptꢀﬂagꢀtoꢀbeꢀsetꢀhighꢀandꢀconsequentlyꢀgenerateꢀanꢀinterrupt.ꢀCareꢀmustꢀ

thereforeꢀbeꢀtakenꢀifꢀspuriousꢀwake-upꢀsituationsꢀareꢀtoꢀbeꢀavoided.ꢀIfꢀanꢀinterruptꢀwake-upꢀfunctionꢀ

isꢀtoꢀbeꢀdisabledꢀthenꢀtheꢀcorrespondingꢀinterruptꢀrequestꢀﬂagꢀshouldꢀbeꢀsetꢀhighꢀbeforeꢀtheꢀdeviceꢀ

entersꢀtheꢀSLEEPꢀorꢀIDLEꢀMode.ꢀTheꢀinterruptꢀenableꢀbitsꢀhaveꢀnoꢀeffectꢀonꢀtheꢀinterruptꢀwake-upꢀ

function.

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Cost-Effective Flash MCU with EEPROM

Programming Considerations

Byꢀdisablingꢀtheꢀrelevantꢀinterruptꢀenableꢀbits,ꢀaꢀrequestedꢀinterruptꢀcanꢀbeꢀpreventedꢀfromꢀbeingꢀ

serviced,ꢀhowever,ꢀonceꢀanꢀinterruptꢀrequestꢀflagꢀisꢀset,ꢀitꢀwillꢀremainꢀinꢀthisꢀconditionꢀinꢀtheꢀ

interruptꢀregisterꢀuntilꢀtheꢀcorrespondingꢀinterruptꢀisꢀservicedꢀorꢀuntilꢀtheꢀrequestꢀﬂagꢀisꢀclearedꢀbyꢀ

theꢀapplicationꢀprogram.ꢀ

WhereꢀaꢀcertainꢀinterruptꢀisꢀcontainedꢀwithinꢀaꢀMulti-functionꢀinterrupt,ꢀthenꢀwhenꢀtheꢀinterruptꢀ

serviceꢀroutineꢀisꢀexecuted,ꢀasꢀonlyꢀtheꢀMulti-functionꢀinterruptꢀrequestꢀﬂags,ꢀMF0F~MF1F,ꢀwillꢀ

beꢀautomaticallyꢀcleared,ꢀtheꢀindividualꢀrequestꢀflagꢀforꢀtheꢀfunctionꢀneedsꢀtoꢀbeꢀclearedꢀbyꢀtheꢀ

applicationꢀprogram.

Itꢀisꢀrecommendedꢀthatꢀprogramsꢀdoꢀnotꢀuseꢀtheꢀ"CALL"ꢀinstructionꢀwithinꢀtheꢀinterruptꢀserviceꢀ

subroutine.ꢀInterruptsꢀoftenꢀoccurꢀinꢀanꢀunpredictableꢀmannerꢀorꢀneedꢀtoꢀbeꢀservicedꢀimmediately.ꢀ

Ifꢀonlyꢀoneꢀstackꢀisꢀleftꢀandꢀtheꢀinterruptꢀisꢀnotꢀwellꢀcontrolled,ꢀtheꢀoriginalꢀcontrolꢀsequenceꢀwillꢀbeꢀ

damagedꢀonceꢀaꢀCALLꢀsubroutineꢀisꢀexecutedꢀinꢀtheꢀinterruptꢀsubroutine.ꢀ

EveryꢀinterruptꢀhasꢀtheꢀcapabilityꢀofꢀwakingꢀupꢀtheꢀmicrocontrollerꢀwhenꢀitꢀisꢀinꢀSLEEPꢀorꢀIDLEꢀ

Mode,ꢀtheꢀwakeꢀupꢀbeingꢀgeneratedꢀwhenꢀtheꢀinterruptꢀrequestꢀﬂagꢀchangesꢀfromꢀlowꢀtoꢀhigh.ꢀIfꢀitꢀisꢀ

requiredꢀtoꢀpreventꢀaꢀcertainꢀinterruptꢀfromꢀwakingꢀupꢀtheꢀmicrocontrollerꢀthenꢀitsꢀrespectiveꢀrequestꢀ

ﬂagꢀshouldꢀbeꢀﬁrstꢀsetꢀhighꢀbeforeꢀenterꢀSLEEPꢀorꢀIDLEꢀMode.ꢀ

AsꢀonlyꢀtheꢀProgramꢀCounterꢀisꢀpushedꢀontoꢀtheꢀstack,ꢀthenꢀwhenꢀtheꢀinterruptꢀisꢀserviced,ꢀifꢀtheꢀ

contentsꢀofꢀtheꢀaccumulator,ꢀstatusꢀregisterꢀorꢀotherꢀregistersꢀareꢀalteredꢀbyꢀtheꢀinterruptꢀserviceꢀ

program,ꢀtheirꢀcontentsꢀshouldꢀbeꢀsavedꢀtoꢀtheꢀmemoryꢀatꢀtheꢀbeginningꢀofꢀtheꢀinterruptꢀserviceꢀ

routine.

Toꢀreturnꢀfromꢀanꢀinterruptꢀsubroutine,ꢀeitherꢀaꢀRETꢀorꢀRETIꢀinstructionꢀmayꢀbeꢀexecuted.ꢀTheꢀRETIꢀ

instructionꢀinꢀadditionꢀtoꢀexecutingꢀaꢀreturnꢀtoꢀtheꢀmainꢀprogramꢀalsoꢀautomaticallyꢀsetsꢀtheꢀEMIꢀ

bitꢀhighꢀtoꢀallowꢀfurtherꢀinterrupts.ꢀTheꢀRETꢀinstructionꢀhoweverꢀonlyꢀexecutesꢀaꢀreturnꢀtoꢀtheꢀmainꢀ

programꢀleavingꢀtheꢀEMIꢀbitꢀinꢀitsꢀpresentꢀzeroꢀstateꢀandꢀthereforeꢀdisablingꢀtheꢀexecutionꢀofꢀfurtherꢀ

interrupts.

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Cost-Effective Flash MCU with EEPROM

Low Voltage Detector – LVD

EachꢀdeviceꢀhasꢀaꢀLowꢀVoltageꢀDetectorꢀfunction,ꢀalsoꢀknownꢀasꢀLVD.ꢀThisꢀenablesꢀtheꢀdeviceꢀtoꢀ

monitorꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀV_DD,ꢀandꢀprovidesꢀaꢀwarningꢀsignalꢀshouldꢀitꢀfallꢀbelowꢀaꢀcertainꢀ

level.ꢀThisꢀfunctionꢀmayꢀbeꢀespeciallyꢀusefulꢀinꢀbatteryꢀapplicationsꢀwhereꢀtheꢀsupplyꢀvoltageꢀwillꢀ

graduallyꢀreduceꢀasꢀtheꢀbatteryꢀages,ꢀasꢀitꢀallowsꢀanꢀearlyꢀwarningꢀbatteryꢀlowꢀsignalꢀtoꢀbeꢀgenerated.ꢀ

LVD Register

TheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀisꢀcontrolledꢀusingꢀaꢀsingleꢀregisterꢀwithꢀtheꢀnameꢀLVDC.ꢀThreeꢀ

bitsꢀinꢀthisꢀregister,ꢀVLVD2~VLVD0,ꢀareꢀusedꢀtoꢀselectꢀoneꢀofꢀeightꢀﬁxedꢀvoltagesꢀbelowꢀwhichꢀaꢀ

lowꢀvoltageꢀconditionꢀwillꢀbeꢀdetemined.ꢀAꢀlowꢀvoltageꢀconditionꢀisꢀindicatedꢀwhenꢀtheꢀLVDOꢀbitꢀisꢀ

set.ꢀIfꢀtheꢀLVDOꢀbitꢀisꢀlow,ꢀthisꢀindicatesꢀthatꢀtheꢀV_DDꢀvoltageꢀisꢀaboveꢀtheꢀpresetꢀlowꢀvoltageꢀvalue.ꢀ

TheꢀENLVDꢀbitꢀisꢀusedꢀtoꢀcontrolꢀtheꢀoverallꢀon/offꢀfunctionꢀofꢀtheꢀlowꢀvoltageꢀdetector.ꢀSettingꢀtheꢀ

bitꢀhighꢀwillꢀenableꢀtheꢀlowꢀvoltageꢀdetector.ꢀClearingꢀtheꢀbitꢀtoꢀzeroꢀwillꢀswitchꢀoffꢀtheꢀinternalꢀlowꢀ

voltageꢀdetectorꢀcircuits.ꢀAsꢀtheꢀlowꢀvoltageꢀdetectorꢀwillꢀconsumeꢀaꢀcertainꢀamountꢀofꢀpower,ꢀitꢀmayꢀ

beꢀdesirableꢀtoꢀswitchꢀoffꢀtheꢀcircuitꢀwhenꢀnotꢀinꢀuse,ꢀanꢀimportantꢀconsiderationꢀinꢀpowerꢀsensitiveꢀ

batteryꢀpoweredꢀapplications.

LVDC Register

Bit

7

6

5

LVDO

R

4

ENLVD

R/W

0

3

2

VLVD2

R/W

0

1

VLVD1

R/W

0

VLVD0

R/W

0

Name

R/W

—

POR

0

Bitꢀ7ꢀ~ꢀ6ꢀ

Bitꢀ5

Unimplemented,ꢀreadꢀasꢀ"0"

LVDO:ꢀLVDꢀdetectionꢀoutput.

0:ꢀNoꢀactive.

1:ꢀLowꢀvoltageꢀdetected

Bitꢀ4

ENLVD:ꢀLowꢀVoltageꢀDetectorꢀControl

0:ꢀDisable

1:ꢀEnable

Bitꢀ3ꢀ

Unimplemented,ꢀreadꢀasꢀ"0"

Bitꢀ2~0

VLVD2 ~ VLVD0:ꢀSelectꢀLVDꢀVoltage

000:ꢀ2.0V

001:ꢀ2.2V

010:ꢀ2.4V

011:ꢀ2.7V

100:ꢀ3.0V

101:ꢀ3.3V

110:ꢀ3.6V

111:ꢀ4.0V

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Cost-Effective Flash MCU with EEPROM

LVD Operation

TheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀoperatesꢀbyꢀcomparingꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀV_DD,ꢀwithꢀaꢀ

pre-speciﬁedꢀvoltageꢀlevelꢀstoredꢀinꢀtheꢀLVDCꢀregister.ꢀThisꢀhasꢀaꢀrangeꢀofꢀbetweenꢀ2.0Vꢀandꢀ4.0V.ꢀ

Whenꢀtheꢀpowerꢀsupplyꢀvoltage,ꢀV_DD,ꢀfallsꢀbelowꢀthisꢀpre-determinedꢀvalue,ꢀtheꢀLVDOꢀbitꢀwillꢀbeꢀ

setꢀhighꢀindicatingꢀaꢀlowꢀpowerꢀsupplyꢀvoltageꢀcondition.ꢀTheꢀLowꢀVoltageꢀDetectorꢀfunctionꢀisꢀ

suppliedꢀbyꢀaꢀreferenceꢀvoltageꢀwhichꢀwillꢀbeꢀautomaticallyꢀenabled.ꢀWhenꢀtheꢀdeviceꢀisꢀinꢀSLEEPꢀ

modeꢀtheꢀlowꢀvoltageꢀdetectorꢀwillꢀbeꢀautomaticallyꢀdisabled.ꢀAfterꢀenablingꢀtheꢀLowꢀVoltageꢀ

Detector,ꢀaꢀtimeꢀdelayꢀt_LVDSꢀshouldꢀbeꢀallowedꢀforꢀtheꢀcircuitryꢀtoꢀstabiliseꢀbeforeꢀreadingꢀtheꢀLVDOꢀ

bit.ꢀNoteꢀalsoꢀthatꢀasꢀtheꢀV_DDꢀvoltageꢀmayꢀriseꢀandꢀfallꢀratherꢀslowly,ꢀatꢀtheꢀvoltageꢀnearsꢀthatꢀofꢀ

V_LVD,ꢀthereꢀmayꢀbeꢀmultipleꢀbitꢀLVDOꢀtransitions.ꢀ

VDD

V_LVD

ENLVD

LVDO

t_LVDS

LVD Operation

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Cost-Effective Flash MCU with EEPROM

Application Circuits

V

D

0

.

m

0

F

*

1

*

V

D

1

4

N

1

*

4

8

R

s

e

t

e

1

k

0

W

~

C

r

i

u

c

t

i

1

0

W

0

k

0

1

.

F

R

S

E

P

A

~

0

A

P

7

3

0

W

*

0

.

1

F

~

V

S

Note:ꢀ"*"ꢀRecommendedꢀcomponentꢀforꢀaddedꢀESDꢀprotection.

"**"ꢀRecommendedꢀcomponentꢀinꢀenvironmentsꢀwhereꢀpowerꢀlineꢀnoiseꢀisꢀsigniﬁcant.

HT68F002/HT68F0025

V

D

0

.

m

0

F

*

1

*

V

D

1

4

N

1

*

4

8

R

C

s

e

t

e

1

k

0

W

~

r

i

u

c

t

i

1

0

W

0

k

0

1

.

F

R

S

E

P

A

~

0

A

P

7

3

0

W

*

0

.

1

F

~

P

B

~

0

B

P

5

V

S

Note:ꢀ"*"ꢀRecommendedꢀcomponentꢀforꢀaddedꢀESDꢀprotection.

"**"ꢀRecommendedꢀcomponentꢀinꢀenvironmentsꢀwhereꢀpowerꢀlineꢀnoiseꢀisꢀsigniﬁcant.

HT68F003

Rev. 1.41

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Cost-Effective Flash MCU with EEPROM

Instruction Set

Introduction

Centralꢀtoꢀtheꢀsuccessfulꢀoperationꢀofꢀanyꢀmicrocontrollerꢀisꢀitsꢀinstructionꢀset,ꢀwhichꢀisꢀaꢀsetꢀofꢀ

programꢀinstructionꢀcodesꢀthatꢀdirectsꢀtheꢀmicrocontrollerꢀtoꢀperformꢀcertainꢀoperations.ꢀInꢀtheꢀcaseꢀ

ofꢀHoltekꢀmicrocontroller,ꢀaꢀcomprehensiveꢀandꢀﬂexibleꢀsetꢀofꢀoverꢀ60ꢀinstructionsꢀisꢀprovidedꢀtoꢀ

enableꢀprogrammersꢀtoꢀimplementꢀtheirꢀapplicationꢀwithꢀtheꢀminimumꢀofꢀprogrammingꢀoverheads.ꢀ

Forꢀeasierꢀunderstandingꢀofꢀtheꢀvariousꢀinstructionꢀcodes,ꢀtheyꢀhaveꢀbeenꢀsubdividedꢀintoꢀseveralꢀ

functionalꢀgroupings.

Instruction Timing

Mostꢀinstructionsꢀareꢀimplementedꢀwithinꢀoneꢀinstructionꢀcycle.ꢀTheꢀexceptionsꢀtoꢀthisꢀareꢀbranch,ꢀ

call,ꢀorꢀtableꢀreadꢀinstructionsꢀwhereꢀtwoꢀinstructionꢀcyclesꢀareꢀrequired.ꢀOneꢀinstructionꢀcycleꢀisꢀ

equalꢀtoꢀ4ꢀsystemꢀclockꢀcycles,ꢀthereforeꢀinꢀtheꢀcaseꢀofꢀanꢀ8MHzꢀsystemꢀoscillator,ꢀmostꢀinstructionsꢀ

wouldꢀbeꢀimplementedꢀwithinꢀ0.5μsꢀandꢀbranchꢀorꢀcallꢀinstructionsꢀwouldꢀbeꢀimplementedꢀwithinꢀ

1μs.ꢀAlthoughꢀinstructionsꢀwhichꢀrequireꢀoneꢀmoreꢀcycleꢀtoꢀimplementꢀareꢀgenerallyꢀlimitedꢀtoꢀ

theꢀJMP,ꢀCALL,ꢀRET,ꢀRETIꢀandꢀtableꢀreadꢀinstructions,ꢀitꢀisꢀimportantꢀtoꢀrealizeꢀthatꢀanyꢀotherꢀ

instructionsꢀwhichꢀinvolveꢀmanipulationꢀofꢀtheꢀProgramꢀCounterꢀLowꢀregisterꢀorꢀPCLꢀwillꢀalsoꢀtakeꢀ

oneꢀmoreꢀcycleꢀtoꢀimplement.ꢀAsꢀinstructionsꢀwhichꢀchangeꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀwillꢀimplyꢀaꢀ

directꢀjumpꢀtoꢀthatꢀnewꢀaddress,ꢀoneꢀmoreꢀcycleꢀwillꢀbeꢀrequired.ꢀExamplesꢀofꢀsuchꢀinstructionsꢀ

wouldꢀbeꢀ"CLRꢀPCL"ꢀorꢀ"MOVꢀPCL,ꢀA".ꢀForꢀtheꢀcaseꢀofꢀskipꢀinstructions,ꢀitꢀmustꢀbeꢀnotedꢀthatꢀifꢀ

theꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀoperationꢀthenꢀthisꢀwillꢀalsoꢀtakeꢀoneꢀmoreꢀcycle,ꢀifꢀnoꢀ

skipꢀisꢀinvolvedꢀthenꢀonlyꢀoneꢀcycleꢀisꢀrequired.

Moving and Transferring Data

Theꢀtransferꢀofꢀdataꢀwithinꢀtheꢀmicrocontrollerꢀprogramꢀisꢀoneꢀofꢀtheꢀmostꢀfrequentlyꢀusedꢀ

operations.ꢀMakingꢀuseꢀofꢀthreeꢀkindsꢀofꢀMOVꢀinstructions,ꢀdataꢀcanꢀbeꢀtransferredꢀfromꢀregistersꢀtoꢀ

theꢀAccumulatorꢀandꢀvice-versaꢀasꢀwellꢀasꢀbeingꢀableꢀtoꢀmoveꢀspeciﬁcꢀimmediateꢀdataꢀdirectlyꢀintoꢀ

theꢀAccumulator.ꢀOneꢀofꢀtheꢀmostꢀimportantꢀdataꢀtransferꢀapplicationsꢀisꢀtoꢀreceiveꢀdataꢀfromꢀtheꢀ

inputꢀportsꢀandꢀtransferꢀdataꢀtoꢀtheꢀoutputꢀports.

Arithmetic Operations

Theꢀabilityꢀtoꢀperformꢀcertainꢀarithmeticꢀoperationsꢀandꢀdataꢀmanipulationꢀisꢀaꢀnecessaryꢀfeatureꢀofꢀ

mostꢀmicrocontrollerꢀapplications.ꢀWithinꢀtheꢀHoltekꢀmicrocontrollerꢀinstructionꢀsetꢀareꢀaꢀrangeꢀofꢀ

addꢀandꢀsubtractꢀinstructionꢀmnemonicsꢀtoꢀenableꢀtheꢀnecessaryꢀarithmeticꢀtoꢀbeꢀcarriedꢀout.ꢀCareꢀ

mustꢀbeꢀtakenꢀtoꢀensureꢀcorrectꢀhandlingꢀofꢀcarryꢀandꢀborrowꢀdataꢀwhenꢀresultsꢀexceedꢀ255ꢀforꢀ

additionꢀandꢀlessꢀthanꢀ0ꢀforꢀsubtraction.ꢀTheꢀincrementꢀandꢀdecrementꢀinstructionsꢀINC,ꢀINCA,ꢀDECꢀ

andꢀDECAꢀprovideꢀaꢀsimpleꢀmeansꢀofꢀincreasingꢀorꢀdecreasingꢀbyꢀaꢀvalueꢀofꢀoneꢀofꢀtheꢀvaluesꢀinꢀtheꢀ

destinationꢀspeciﬁed.

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Cost-Effective Flash MCU with EEPROM

Logical and Rotate Operation

TheꢀstandardꢀlogicalꢀoperationsꢀsuchꢀasꢀAND,ꢀOR,ꢀXORꢀandꢀCPLꢀallꢀhaveꢀtheirꢀownꢀinstructionꢀ

withinꢀtheꢀHoltekꢀmicrocontrollerꢀinstructionꢀset.ꢀAsꢀwithꢀtheꢀcaseꢀofꢀmostꢀinstructionsꢀinvolvingꢀ

dataꢀmanipulation,ꢀdataꢀmustꢀpassꢀthroughꢀtheꢀAccumulatorꢀwhichꢀmayꢀinvolveꢀadditionalꢀ

programmingꢀsteps.ꢀInꢀallꢀlogicalꢀdataꢀoperations,ꢀtheꢀzeroꢀflagꢀmayꢀbeꢀsetꢀifꢀtheꢀresultꢀofꢀtheꢀ

operationꢀisꢀzero.ꢀAnotherꢀformꢀofꢀlogicalꢀdataꢀmanipulationꢀcomesꢀfromꢀtheꢀrotateꢀinstructionsꢀsuchꢀ

asꢀRR,ꢀRL,ꢀRRCꢀandꢀRLCꢀwhichꢀprovideꢀaꢀsimpleꢀmeansꢀofꢀrotatingꢀoneꢀbitꢀrightꢀorꢀleft.ꢀDifferentꢀ

rotateꢀinstructionsꢀexistꢀdependingꢀonꢀprogramꢀrequirements.ꢀRotateꢀinstructionsꢀareꢀusefulꢀforꢀserialꢀ

portꢀprogrammingꢀapplicationsꢀwhereꢀdataꢀcanꢀbeꢀrotatedꢀfromꢀanꢀinternalꢀregisterꢀintoꢀtheꢀCarryꢀ

bitꢀfromꢀwhereꢀitꢀcanꢀbeꢀexaminedꢀandꢀtheꢀnecessaryꢀserialꢀbitꢀsetꢀhighꢀorꢀlow.ꢀAnotherꢀapplicationꢀ

whichꢀrotateꢀdataꢀoperationsꢀareꢀusedꢀisꢀtoꢀimplementꢀmultiplicationꢀandꢀdivisionꢀcalculations.

Branches and Control Transfer

ProgramꢀbranchingꢀtakesꢀtheꢀformꢀofꢀeitherꢀjumpsꢀtoꢀspeciﬁedꢀlocationsꢀusingꢀtheꢀJMPꢀinstructionꢀ

orꢀtoꢀaꢀsubroutineꢀusingꢀtheꢀCALLꢀinstruction.ꢀTheyꢀdifferꢀinꢀtheꢀsenseꢀthatꢀinꢀtheꢀcaseꢀofꢀaꢀ

subroutineꢀcall,ꢀtheꢀprogramꢀmustꢀreturnꢀtoꢀtheꢀinstructionꢀimmediatelyꢀwhenꢀtheꢀsubroutineꢀhasꢀ

beenꢀcarriedꢀout.ꢀThisꢀisꢀdoneꢀbyꢀplacingꢀaꢀreturnꢀinstructionꢀ"RET"ꢀinꢀtheꢀsubroutineꢀwhichꢀwillꢀ

causeꢀtheꢀprogramꢀtoꢀjumpꢀbackꢀtoꢀtheꢀaddressꢀrightꢀafterꢀtheꢀCALLꢀinstruction.ꢀInꢀtheꢀcaseꢀofꢀaꢀJMPꢀ

instruction,ꢀtheꢀprogramꢀsimplyꢀjumpsꢀtoꢀtheꢀdesiredꢀlocation.ꢀThereꢀisꢀnoꢀrequirementꢀtoꢀjumpꢀbackꢀ

toꢀtheꢀoriginalꢀjumpingꢀoffꢀpointꢀasꢀinꢀtheꢀcaseꢀofꢀtheꢀCALLꢀinstruction.ꢀOneꢀspecialꢀandꢀextremelyꢀ

usefulꢀsetꢀofꢀbranchꢀinstructionsꢀareꢀtheꢀconditionalꢀbranches.ꢀHereꢀaꢀdecisionꢀisꢀﬁrstꢀmadeꢀregardingꢀ

theꢀconditionꢀofꢀaꢀcertainꢀdataꢀmemoryꢀorꢀindividualꢀbits.ꢀDependingꢀuponꢀtheꢀconditions,ꢀtheꢀ

programꢀwillꢀcontinueꢀwithꢀtheꢀnextꢀinstructionꢀorꢀskipꢀoverꢀitꢀandꢀjumpꢀtoꢀtheꢀfollowingꢀinstruction.ꢀ

Theseꢀinstructionsꢀareꢀtheꢀkeyꢀtoꢀdecisionꢀmakingꢀandꢀbranchingꢀwithinꢀtheꢀprogramꢀperhapsꢀ

determinedꢀbyꢀtheꢀconditionꢀofꢀcertainꢀinputꢀswitchesꢀorꢀbyꢀtheꢀconditionꢀofꢀinternalꢀdataꢀbits.

Bit Operations

TheꢀabilityꢀtoꢀprovideꢀsingleꢀbitꢀoperationsꢀonꢀDataꢀMemoryꢀisꢀanꢀextremelyꢀﬂexibleꢀfeatureꢀofꢀallꢀ

Holtekꢀmicrocontrollers.ꢀThisꢀfeatureꢀisꢀespeciallyꢀusefulꢀforꢀoutputꢀportꢀbitꢀprogrammingꢀwhereꢀ

individualꢀbitsꢀorꢀportꢀpinsꢀcanꢀbeꢀdirectlyꢀsetꢀhighꢀorꢀlowꢀusingꢀeitherꢀtheꢀ"SETꢀ[m].i"ꢀorꢀ"CLRꢀ[m].

i"ꢀinstructionsꢀrespectively.ꢀTheꢀfeatureꢀremovesꢀtheꢀneedꢀforꢀprogrammersꢀtoꢀﬁrstꢀreadꢀtheꢀ8-bitꢀ

outputꢀport,ꢀmanipulateꢀtheꢀinputꢀdataꢀtoꢀensureꢀthatꢀotherꢀbitsꢀareꢀnotꢀchangedꢀandꢀthenꢀoutputꢀtheꢀ

portꢀwithꢀtheꢀcorrectꢀnewꢀdata.ꢀThisꢀread-modify-writeꢀprocessꢀisꢀtakenꢀcareꢀofꢀautomaticallyꢀwhenꢀ

theseꢀbitꢀoperationꢀinstructionsꢀareꢀused.

Table Read Operations

Dataꢀstorageꢀisꢀnormallyꢀimplementedꢀbyꢀusingꢀregisters.ꢀHowever,ꢀwhenꢀworkingꢀwithꢀlargeꢀ

amountsꢀofꢀﬁxedꢀdata,ꢀtheꢀvolumeꢀinvolvedꢀoftenꢀmakesꢀitꢀinconvenientꢀtoꢀstoreꢀtheꢀﬁxedꢀdataꢀinꢀ

theꢀDataꢀMemory.ꢀToꢀovercomeꢀthisꢀproblem,ꢀHoltekꢀmicrocontrollersꢀallowꢀanꢀareaꢀofꢀProgramꢀ

Memoryꢀtoꢀbeꢀsetꢀasꢀaꢀtableꢀwhereꢀdataꢀcanꢀbeꢀdirectlyꢀstored.ꢀAꢀsetꢀofꢀeasyꢀtoꢀuseꢀinstructionsꢀ

providesꢀtheꢀmeansꢀbyꢀwhichꢀthisꢀfixedꢀdataꢀcanꢀbeꢀreferencedꢀandꢀretrievedꢀfromꢀtheꢀProgramꢀ

Memory.

Other Operations

Inꢀadditionꢀtoꢀtheꢀaboveꢀfunctionalꢀinstructions,ꢀaꢀrangeꢀofꢀotherꢀinstructionsꢀalsoꢀexistꢀsuchꢀasꢀ

theꢀ"HALT"ꢀinstructionꢀforꢀPower-downꢀoperationsꢀandꢀinstructionsꢀtoꢀcontrolꢀtheꢀoperationꢀofꢀ

theꢀWatchdogꢀTimerꢀforꢀreliableꢀprogramꢀoperationsꢀunderꢀextremeꢀelectricꢀorꢀelectromagneticꢀ

environments.ꢀForꢀtheirꢀrelevantꢀoperations,ꢀreferꢀtoꢀtheꢀfunctionalꢀrelatedꢀsections.

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Cost-Effective Flash MCU with EEPROM

Instruction Set Summary

Theꢀfollowingꢀtableꢀdepictsꢀaꢀsummaryꢀofꢀtheꢀinstructionꢀsetꢀcategorisedꢀaccordingꢀtoꢀfunctionꢀandꢀ

canꢀbeꢀconsultedꢀasꢀaꢀbasicꢀinstructionꢀreferenceꢀusingꢀtheꢀfollowingꢀlistedꢀconventions.

Table Conventions

x:ꢀBitsꢀimmediateꢀdataꢀ

m:ꢀDataꢀMemoryꢀaddressꢀ

A:ꢀAccumulatorꢀ

i:ꢀ0~7ꢀnumberꢀofꢀbitsꢀ

addr:ꢀProgramꢀmemoryꢀaddress

Mnemonic

Arithmetic

Description

Cycles Flag Affected

ADD A,[m]

ADDM A,[m]

ADD A,x

Add Data Memory to ACC

Add ACC to Data Memory

Add immediate data to ACC

1

1^Note

1

Z, C, AC, OV

C

ADC A,[m]

ADCM A,[m]

SUB A,x

Add Data Memory to ACC with Carry

1

1^Note

Add ACC to Data memory with Carry

Subtract immediate data from the ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

Subtract Data Memory from ACC

1

1^Note

Subtract Data Memory from ACC with result in Data Memory

Subtract Data Memory from ACC with Carry

Subtract Data Memory from ACC with Carry, result in Data Memory

Decimal adjust ACC for Addition with result in Data Memory

1

1^Note

Logic Operation

AND A,[m]

OR A,[m]

Logical AND Data Memory to ACC

Logical OR Data Memory to ACC

Logical XOR Data Memory to ACC

Logical AND ACC to Data Memory

Logical OR ACC to Data Memory

Logical XOR ACC to Data Memory

Logical AND immediate Data to ACC

Logical OR immediate Data to ACC

Logical XOR immediate Data to ACC

Complement Data Memory

1

Z

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

1

1^Note

1

OR A,x

1

XOR A,x

1

1^Note

CPL [m]

CPLA [m]

Complement Data Memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

DECA [m]

DEC [m]

Rotate

Increment Data Memory with result in ACC

1

Z

Increment Data Memory

1^Note

Decrement Data Memory with result in ACC

Decrement Data Memory

1

1^Note

RRA [m]

RR [m]

Rotate Data Memory right with result in ACC

Rotate Data Memory right

1

1^Note

1

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate Data Memory right through Carry with result in ACC

Rotate Data Memory right through Carry

Rotate Data Memory left with result in ACC

Rotate Data Memory left

1^Note

C

1

None

C

1^Note

1

RLCA [m]

RLC [m]

Rotate Data Memory left through Carry with result in ACC

Rotate Data Memory left through Carry

1^Note

C

Rev. 1.41

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Cost-Effective Flash MCU with EEPROM

Mnemonic

Data Move

Description

Cycles Flag Affected

MOV A,[m]

MOV [m],A

MOV A,x

Bit Operation

CLR [m].i

SET [m].i

Branch

Move Data Memory to ACC

Move ACC to Data Memory

Move immediate data to ACC

1

1^Note

1

None

Clear bit of Data Memory

Set bit of Data Memory

1^Note

None

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if Data Memory is zero

1^Note

2

SZA [m]

Skip if Data Memory is zero with data movement to ACC

Skip if bit i of Data Memory is zero

Skip if bit i of Data Memory is not zero

Skip if increment Data Memory is zero

Skip if decrement Data Memory is zero

Skip if increment Data Memory is zero with result in ACC

Skip if decrement Data Memory is zero with result in ACC

Subroutine call

SZ [m].i

SNZ [m].i

SIZ [m]

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

Return from subroutine and load immediate data to ACC

Return from interrupt

2

RETI

2

Table Read

TABRD [m]

TABRDC [m]

TABRDL [m]

Miscellaneous

NOP

Read table (speciﬁc page) to TBLH and Data Memory

Read table (current page) to TBLH and Data Memory

Read table (last page) to TBLH and Data Memory

2^Note

None

No operation

1

1^Note

1

None

CLR [m]

Clear Data Memory

SET [m]

Set Data Memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO, PDF

None

Pre-clear Watchdog Timer

Swap nibbles of Data Memory

Swap nibbles of Data Memory with result in ACC

Enter power down mode

1

1^Note

1

None

1

TO, PDF

Note:ꢀ1.ꢀForꢀskipꢀinstructions,ꢀifꢀtheꢀresultꢀofꢀtheꢀcomparisonꢀinvolvesꢀaꢀskipꢀthenꢀtwoꢀcyclesꢀareꢀrequired,ꢀifꢀnoꢀ

skipꢀtakesꢀplaceꢀonlyꢀoneꢀcycleꢀisꢀrequired.

2.ꢀAnyꢀinstructionꢀwhichꢀchangesꢀtheꢀcontentsꢀofꢀtheꢀPCLꢀwillꢀalsoꢀrequireꢀ2ꢀcyclesꢀforꢀexecution.

3.ꢀForꢀtheꢀ"CLRꢀWDT1"ꢀandꢀ"CLRꢀWDT2"ꢀinstructionsꢀtheꢀTOꢀandꢀPDFꢀflagsꢀmayꢀbeꢀaffectedꢀbyꢀtheꢀ

executionꢀstatus.ꢀTheꢀTOꢀandꢀPDFꢀflagsꢀareꢀclearedꢀafterꢀbothꢀ"CLRꢀWDT1"ꢀandꢀ"CLRꢀWDT2"ꢀ

instructionsꢀareꢀconsecutivelyꢀexecuted.ꢀOtherwiseꢀtheꢀTOꢀandꢀPDFꢀﬂagsꢀremainꢀunchanged.

Rev. 1.41

104

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Instruction Deﬁnition

ꢀ

AddꢀDataꢀMemoryꢀtoꢀACCꢀwithꢀCarry

ADC A,[m]

Descriptionꢀ

ꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀﬂagꢀareꢀadded.ꢀ

TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.

Operationꢀ

ACCꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

ꢀ

AddꢀACCꢀtoꢀDataꢀMemoryꢀwithꢀCarry

ADCM A,[m]

Descriptionꢀ

ꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemory,ꢀAccumulatorꢀandꢀtheꢀcarryꢀﬂagꢀareꢀadded.ꢀꢀ

TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspeciﬁedꢀDataꢀMemory.

Operationꢀ

[m]ꢀ←ꢀACCꢀ+ꢀ[m]ꢀ+ꢀC

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

ꢀ

AddꢀDataꢀMemoryꢀtoꢀACC

ADD A,[m]

Descriptionꢀ

ꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀ

TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.

Operationꢀ

ACCꢀ←ꢀACCꢀ+ꢀ[m]

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

AddꢀimmediateꢀdataꢀtoꢀACC

ADD A,x

Descriptionꢀ

ꢀ

TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀandꢀtheꢀspeciﬁedꢀimmediateꢀdataꢀareꢀadded.ꢀꢀ

TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.

Operationꢀ

ACCꢀ←ꢀACCꢀ+ꢀx

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

ꢀ

AddꢀACCꢀtoꢀDataꢀMemory

ADDM A,[m]

Descriptionꢀ

ꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀareꢀadded.ꢀꢀ

TheꢀresultꢀisꢀstoredꢀinꢀtheꢀspeciﬁedꢀDataꢀMemory.

Operationꢀ

[m]ꢀ←ꢀACCꢀ+ꢀ[m]

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

ꢀ

LogicalꢀANDꢀDataꢀMemoryꢀtoꢀACC

AND A,[m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀꢀ

operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.

Operationꢀ

ACCꢀ←ꢀACCꢀ″AND″ꢀ[m]

Z

Affectedꢀﬂag(s)ꢀ

LogicalꢀANDꢀimmediateꢀdataꢀtoꢀACC

AND A,x

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspeciﬁedꢀimmediateꢀdataꢀperformꢀaꢀbitꢀwiseꢀlogicalꢀANDꢀꢀ

operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.

Operationꢀ

ACCꢀ←ꢀACCꢀ″AND″ꢀx

Z

Affectedꢀﬂag(s)ꢀ

ꢀ

LogicalꢀANDꢀACCꢀtoꢀDataꢀMemory

ANDM A,[m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀANDꢀ

operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.

Operationꢀ

[m]ꢀ←ꢀACCꢀ″AND″ꢀ[m]

Z

Affectedꢀﬂag(s)ꢀ

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

ꢀ

Subroutineꢀcall

CALL addr

Descriptionꢀ

Unconditionallyꢀcallsꢀaꢀsubroutineꢀatꢀtheꢀspeciﬁedꢀaddress.ꢀTheꢀProgramꢀCounterꢀthenꢀ

incrementsꢀbyꢀ1ꢀtoꢀobtainꢀtheꢀaddressꢀofꢀtheꢀnextꢀinstructionꢀwhichꢀisꢀthenꢀpushedꢀontoꢀtheꢀ

stack.ꢀTheꢀspeciﬁedꢀaddressꢀisꢀthenꢀloadedꢀandꢀtheꢀprogramꢀcontinuesꢀexecutionꢀfromꢀthisꢀ

newꢀaddress.ꢀAsꢀthisꢀinstructionꢀrequiresꢀanꢀadditionalꢀoperation,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.

ꢀ

Operationꢀ

ꢀ

Stackꢀ←ꢀProgramꢀCounterꢀ+ꢀ1ꢀ

ProgramꢀCounterꢀ←ꢀaddr

Affectedꢀﬂag(s)ꢀ

None

ꢀ

ClearꢀDataꢀMemory

CLR [m]

Descriptionꢀ

Operationꢀ

EachꢀbitꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.

[m]ꢀ←ꢀ00H

None

Affectedꢀﬂag(s)ꢀ

ClearꢀbitꢀofꢀDataꢀMemory

CLR [m].i

Descriptionꢀ

Operationꢀ

BitꢀiꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀclearedꢀtoꢀ0.

[m].iꢀ←ꢀ0

None

Affectedꢀﬂag(s)ꢀ

ꢀ

ClearꢀWatchdogꢀTimer

CLR WDT

Descriptionꢀ

TheꢀTO,ꢀPDFꢀﬂagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀ

Operationꢀ

ꢀ

WDTꢀclearedꢀ

TOꢀ←ꢀ0ꢀ

PDFꢀ←ꢀ0

Affectedꢀﬂag(s)ꢀ

TO,ꢀPDF

ꢀ

Pre-clearꢀWatchdogꢀTimer

CLR WDT1

Descriptionꢀ

TheꢀTO,ꢀPDFꢀﬂagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀNoteꢀthatꢀthisꢀinstructionꢀworksꢀinꢀ

conjunctionꢀwithꢀCLRꢀWDT2ꢀandꢀmustꢀbeꢀexecutedꢀalternatelyꢀwithꢀCLRꢀWDT2ꢀtoꢀhaveꢀ

effect.ꢀRepetitivelyꢀexecutingꢀthisꢀinstructionꢀwithoutꢀalternatelyꢀexecutingꢀCLRꢀWDT2ꢀwillꢀ

haveꢀnoꢀeffect.

ꢀ

Operationꢀ

ꢀ

WDTꢀclearedꢀ

TOꢀ←ꢀ0ꢀ

PDFꢀ←ꢀ0ꢀ

Affectedꢀﬂag(s)ꢀ

TO,ꢀPDF

ꢀ

Pre-clearꢀWatchdogꢀTimer

CLR WDT2

Descriptionꢀ

ꢀ

ꢀꢀ

ꢀ

TheꢀTO,ꢀPDFꢀﬂagsꢀandꢀtheꢀWDTꢀareꢀallꢀcleared.ꢀNoteꢀthatꢀthisꢀinstructionꢀworksꢀinꢀconjunctionꢀ

withꢀCLRꢀWDT1ꢀandꢀmustꢀbeꢀexecutedꢀalternatelyꢀwithꢀCLRꢀWDT1ꢀtoꢀhaveꢀeffect.ꢀ

RepetitivelyꢀexecutingꢀthisꢀinstructionꢀwithoutꢀalternatelyꢀexecutingꢀCLRꢀWDT1ꢀwillꢀhaveꢀnoꢀ

effect.

Operationꢀ

ꢀ

WDTꢀclearedꢀ

TOꢀ←ꢀ0ꢀ

PDFꢀ←ꢀ0

Affectedꢀﬂag(s)ꢀ

TO,ꢀPDF

ComplementꢀDataꢀMemory

CPL [m]

Descriptionꢀ

ꢀ

EachꢀbitꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ

previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.

Operationꢀ

[m]ꢀ←ꢀ[m]

Z

Affectedꢀﬂag(s)ꢀ

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

ꢀ

ComplementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC

CPLA [m]

Descriptionꢀ

ꢀ

EachꢀbitꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀlogicallyꢀcomplementedꢀ(1′sꢀcomplement).ꢀBitsꢀwhichꢀ

previouslyꢀcontainedꢀaꢀ1ꢀareꢀchangedꢀtoꢀ0ꢀandꢀviceꢀversa.ꢀTheꢀcomplementedꢀresultꢀisꢀstoredꢀinꢀ

theꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.

Operationꢀ

ACCꢀ←ꢀ[m]

Z

Affectedꢀﬂag(s)ꢀ

Decimal-AdjustꢀACCꢀforꢀadditionꢀwithꢀresultꢀinꢀDataꢀMemory

DAA [m]

Descriptionꢀ

ConvertꢀtheꢀcontentsꢀofꢀtheꢀAccumulatorꢀvalueꢀtoꢀaꢀBCDꢀ(BinaryꢀCodedꢀDecimal)ꢀvalueꢀ

resultingꢀfromꢀtheꢀpreviousꢀadditionꢀofꢀtwoꢀBCDꢀvariables.ꢀIfꢀtheꢀlowꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀ

orꢀifꢀACꢀﬂagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀwillꢀbeꢀaddedꢀtoꢀtheꢀlowꢀnibble.ꢀOtherwiseꢀtheꢀlowꢀnibbleꢀ

remainsꢀunchanged.ꢀIfꢀtheꢀhighꢀnibbleꢀisꢀgreaterꢀthanꢀ9ꢀorꢀifꢀtheꢀCꢀﬂagꢀisꢀset,ꢀthenꢀaꢀvalueꢀofꢀ6ꢀ

willꢀbeꢀaddedꢀtoꢀtheꢀhighꢀnibble.ꢀEssentially,ꢀtheꢀdecimalꢀconversionꢀisꢀperformedꢀbyꢀaddingꢀ

00H,ꢀ06H,ꢀ60Hꢀorꢀ66HꢀdependingꢀonꢀtheꢀAccumulatorꢀandꢀﬂagꢀconditions.ꢀOnlyꢀtheꢀCꢀﬂagꢀ

mayꢀbeꢀaffectedꢀbyꢀthisꢀinstructionꢀwhichꢀindicatesꢀthatꢀifꢀtheꢀoriginalꢀBCDꢀsumꢀisꢀgreaterꢀthanꢀ

100,ꢀitꢀallowsꢀmultipleꢀprecisionꢀdecimalꢀaddition.

ꢀ

Operationꢀ

[m]ꢀ←ꢀACCꢀ+ꢀ00Hꢀorꢀ

[m]ꢀ←ꢀACCꢀ+ꢀ06Hꢀorꢀꢀ

[m]ꢀ←ꢀACCꢀ+ꢀ60Hꢀorꢀ

[m]ꢀ←ꢀACCꢀ+ꢀ66H

ꢀ

Affectedꢀﬂag(s)ꢀ

C

ꢀ

DecrementꢀDataꢀMemory

DEC [m]

Descriptionꢀ

Operationꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.

[m]ꢀ←ꢀ[m]ꢀ−ꢀ1

Z

Affectedꢀﬂag(s)ꢀ

DECAꢀ[m]ꢀ

DecrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀdecrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀ

Accumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.

Operationꢀ

ACCꢀ←ꢀ[m]ꢀ−ꢀ1

Z

Affectedꢀﬂag(s)ꢀ

ꢀ

Enterꢀpowerꢀdownꢀmode

HALT

Descriptionꢀ

ꢀ

Thisꢀinstructionꢀstopsꢀtheꢀprogramꢀexecutionꢀandꢀturnsꢀoffꢀtheꢀsystemꢀclock.ꢀTheꢀcontentsꢀofꢀꢀ

theꢀDataꢀMemoryꢀandꢀregistersꢀareꢀretained.ꢀTheꢀWDTꢀandꢀprescalerꢀareꢀcleared.ꢀTheꢀpowerꢀ

downꢀﬂagꢀPDFꢀisꢀsetꢀandꢀtheꢀWDTꢀtime-outꢀﬂagꢀTOꢀisꢀcleared.

Operationꢀ

ꢀ

TOꢀ←ꢀ0ꢀ

PDFꢀ←ꢀ1

Affectedꢀﬂag(s)ꢀ

TO,ꢀPDF

ꢀ

IncrementꢀDataꢀMemoryꢀ

INC [m]

Descriptionꢀ

Operationꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.

[m]ꢀ←ꢀ[m]ꢀ+ꢀ1

Z

Affectedꢀﬂag(s)ꢀ

IncrementꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC

INCA [m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀincrementedꢀbyꢀ1.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀ

TheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.

Operationꢀ

ACCꢀ←ꢀ[m]ꢀ+ꢀ1

Z

Affectedꢀﬂag(s)ꢀ

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Jumpꢀunconditionally

JMP addr

Descriptionꢀ

ꢀ

TheꢀcontentsꢀofꢀtheꢀProgramꢀCounterꢀareꢀreplacedꢀwithꢀtheꢀspeciﬁedꢀaddress.ꢀProgramꢀ

executionꢀthenꢀcontinuesꢀfromꢀthisꢀnewꢀaddress.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ

instructionꢀwhileꢀtheꢀnewꢀaddressꢀisꢀloaded,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.

Operationꢀ

ProgramꢀCounterꢀ←ꢀaddr

None

Affectedꢀﬂag(s)ꢀ

ꢀ

MoveꢀDataꢀMemoryꢀtoꢀACC

MOV A,[m]

Descriptionꢀ

Operationꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.

ACCꢀ←ꢀ[m]

None

Affectedꢀﬂag(s)ꢀ

MoveꢀimmediateꢀdataꢀtoꢀACC

MOV A,x

Descriptionꢀ

Operationꢀ

TheꢀimmediateꢀdataꢀspeciﬁedꢀisꢀloadedꢀintoꢀtheꢀAccumulator.

ACCꢀ←ꢀx

None

Affectedꢀﬂag(s)ꢀ

ꢀ

MoveꢀACCꢀtoꢀDataꢀMemoryꢀ

MOV [m],A

Descriptionꢀ

Operationꢀ

TheꢀcontentsꢀofꢀtheꢀAccumulatorꢀareꢀcopiedꢀtoꢀtheꢀspeciﬁedꢀDataꢀMemory.

[m]ꢀ←ꢀACC

None

Affectedꢀﬂag(s)ꢀ

ꢀ

Noꢀoperation

NOP

Descriptionꢀ

Operationꢀ

Noꢀoperationꢀisꢀperformed.ꢀExecutionꢀcontinuesꢀwithꢀtheꢀnextꢀinstruction.

Noꢀoperation

None

Affectedꢀﬂag(s)ꢀ

LogicalꢀORꢀDataꢀMemoryꢀtoꢀACC

OR A,[m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀ

logicalꢀORꢀoperation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.

Operationꢀ

ACCꢀ←ꢀACCꢀ″OR″ꢀ[m]

Z

Affectedꢀﬂag(s)ꢀ

ꢀ

LogicalꢀORꢀimmediateꢀdataꢀtoꢀACC

OR A,x

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspeciﬁedꢀimmediateꢀdataꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ

operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.

Operationꢀ

ACCꢀ←ꢀACCꢀ″OR″ꢀx

Z

Affectedꢀﬂag(s)ꢀ

ꢀ

LogicalꢀORꢀACCꢀtoꢀDataꢀMemory

ORM A,[m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀORꢀꢀ

operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.

Operationꢀ

[m]ꢀ←ꢀACCꢀ″OR″ꢀ[m]

Z

Affectedꢀﬂag(s)ꢀ

ꢀ

Returnꢀfromꢀsubroutine

RET

Descriptionꢀ

ꢀ

TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstack.ꢀProgramꢀexecutionꢀcontinuesꢀatꢀtheꢀrestoredꢀ

address.

Operationꢀ

ProgramꢀCounterꢀ←ꢀStack

None

Affectedꢀﬂag(s)ꢀ

Rev. 1.41

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HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

ꢀ

ReturnꢀfromꢀsubroutineꢀandꢀloadꢀimmediateꢀdataꢀtoꢀACC

RET A,x

Descriptionꢀ

ꢀ

TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstackꢀandꢀtheꢀAccumulatorꢀloadedꢀwithꢀtheꢀspeciﬁedꢀ

immediateꢀdata.ꢀProgramꢀexecutionꢀcontinuesꢀatꢀtheꢀrestoredꢀaddress.

Operationꢀ

ꢀ

ProgramꢀCounterꢀ←ꢀStackꢀ

ACCꢀ←ꢀx

Affectedꢀﬂag(s)ꢀ

None

ꢀ

Returnꢀfromꢀinterrupt

RETI

Descriptionꢀ

TheꢀProgramꢀCounterꢀisꢀrestoredꢀfromꢀtheꢀstackꢀandꢀtheꢀinterruptsꢀareꢀre-enabledꢀbyꢀsettingꢀtheꢀ

EMIꢀbit.ꢀEMIꢀisꢀtheꢀmasterꢀinterruptꢀglobalꢀenableꢀbit.ꢀIfꢀanꢀinterruptꢀwasꢀpendingꢀwhenꢀtheꢀꢀ

RETIꢀinstructionꢀisꢀexecuted,ꢀtheꢀpendingꢀInterruptꢀroutineꢀwillꢀbeꢀprocessedꢀbeforeꢀreturningꢀꢀ

toꢀtheꢀmainꢀprogram.

ꢀ

Operationꢀ

ꢀ

ProgramꢀCounterꢀ←ꢀStackꢀ

EMIꢀ←ꢀ1

Affectedꢀﬂag(s)ꢀ

None

ꢀ

RotateꢀDataꢀMemoryꢀleft

RL [m]

Descriptionꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.

Operationꢀ

ꢀ

[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ

[m].0ꢀ←ꢀ[m].7

Affectedꢀﬂag(s)ꢀ

None

RotateꢀDataꢀMemoryꢀleftꢀwithꢀresultꢀinꢀACC

RLA [m]

Descriptionꢀ

ꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ7ꢀrotatedꢀintoꢀbitꢀ0.ꢀ

TheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀ

unchanged.

Operationꢀ

ꢀ

ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ

ACC.0ꢀ←ꢀ[m].7

Affectedꢀﬂag(s)ꢀ

None

RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarry

RLC [m]

Descriptionꢀ

ꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀﬂagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀ

replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀﬂagꢀisꢀrotatedꢀintoꢀbitꢀ0.

Operationꢀ

ꢀ

[m].(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ

[m].0ꢀ←ꢀCꢀ

Cꢀ←ꢀ[m].7

Affectedꢀﬂag(s)ꢀ

C

ꢀ

RotateꢀDataꢀMemoryꢀleftꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC

RLCA [m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀﬂagꢀareꢀrotatedꢀleftꢀbyꢀ1ꢀbit.ꢀBitꢀ7ꢀreplacesꢀtheꢀ

Carryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀﬂagꢀisꢀrotatedꢀintoꢀtheꢀbitꢀ0.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀ

AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.

Operationꢀ

ꢀ

ACC.(i+1)ꢀ←ꢀ[m].i;ꢀ(i=0~6)ꢀ

ACC.0ꢀ←ꢀCꢀ

Cꢀ←ꢀ[m].7

Affectedꢀﬂag(s)ꢀ

C

RotateꢀDataꢀMemoryꢀright

RR [m]

Descriptionꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀrotatedꢀintoꢀbitꢀ7.

Operationꢀ

ꢀ

[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ

[m].7ꢀ←ꢀ[m].0

Affectedꢀﬂag(s)ꢀ

None

Rev. 1.41

109

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

RotateꢀDataꢀMemoryꢀrightꢀwithꢀresultꢀinꢀACC

RRA [m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀﬂagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbitꢀwithꢀbitꢀ0ꢀ

rotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀ

DataꢀMemoryꢀremainꢀunchanged.

Operationꢀ

ꢀ

ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ

ACC.7ꢀ←ꢀ[m].0

Affectedꢀﬂag(s)ꢀ

None

RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarry

RRC [m]

Descriptionꢀ

ꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀﬂagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀ

replacesꢀtheꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀﬂagꢀisꢀrotatedꢀintoꢀbitꢀ7.

Operationꢀ

ꢀ

[m].iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ

[m].7ꢀ←ꢀCꢀ

Cꢀ←ꢀ[m].0

Affectedꢀﬂag(s)ꢀ

C

ꢀ

RotateꢀDataꢀMemoryꢀrightꢀthroughꢀCarryꢀwithꢀresultꢀinꢀACC

RRCA [m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀcarryꢀﬂagꢀareꢀrotatedꢀrightꢀbyꢀ1ꢀbit.ꢀBitꢀ0ꢀreplacesꢀꢀ

theꢀCarryꢀbitꢀandꢀtheꢀoriginalꢀcarryꢀﬂagꢀisꢀrotatedꢀintoꢀbitꢀ7.ꢀTheꢀrotatedꢀresultꢀisꢀstoredꢀinꢀtheꢀꢀ

AccumulatorꢀandꢀtheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.

Operationꢀ

ꢀ

ACC.iꢀ←ꢀ[m].(i+1);ꢀ(i=0~6)ꢀ

ACC.7ꢀ←ꢀCꢀ

Cꢀ←ꢀ[m].0

Affectedꢀﬂag(s)ꢀ

C

ꢀ

SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarry

SBC A,[m]

Descriptionꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀﬂagꢀareꢀ

subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀꢀ

resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀﬂagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀ

positiveꢀorꢀzero,ꢀtheꢀCꢀﬂagꢀwillꢀbeꢀsetꢀtoꢀ1.

ꢀ

Operationꢀ

ACCꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀꢀC

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

ꢀ

SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀCarryꢀandꢀresultꢀinꢀDataꢀMemory

SBCM A,[m]

Descriptionꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀcomplementꢀofꢀtheꢀcarryꢀﬂagꢀareꢀꢀ

subtractedꢀfromꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀꢀ

resultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀﬂagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀꢀ

positiveꢀorꢀzero,ꢀtheꢀCꢀﬂagꢀwillꢀbeꢀsetꢀtoꢀ1.

ꢀ

Operationꢀ

[m]ꢀ←ꢀACCꢀ−ꢀ[m]ꢀ−ꢀC

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀ0

SDZ [m]

Descriptionꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀﬁrstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀꢀ

followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ

theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀꢀ

proceedsꢀwithꢀtheꢀfollowingꢀinstruction.

ꢀ

Operationꢀ

ꢀ

[m]ꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ

Skipꢀifꢀ[m]=0

Affectedꢀﬂag(s)ꢀ

None

Rev. 1.41

110

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

ꢀ

SkipꢀifꢀdecrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC

SDZA [m]

Descriptionꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀﬁrstꢀdecrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ

followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspeciﬁedꢀꢀ

DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ

instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀ

theꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.

ꢀ

Operationꢀ

ꢀ

ACCꢀ←ꢀ[m]ꢀ−ꢀ1ꢀ

SkipꢀifꢀACC=0

Affectedꢀﬂag(s)ꢀ

None

ꢀ

SetꢀDataꢀMemory

SET [m]

Descriptionꢀ

Operationꢀ

EachꢀbitꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.

[m]ꢀ←ꢀFFH

None

Affectedꢀﬂag(s)ꢀ

SetꢀbitꢀofꢀDataꢀMemory

SET [m].i

Descriptionꢀ

Operationꢀ

BitꢀiꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀsetꢀtoꢀ1.

[m].iꢀ←ꢀ1

None

Affectedꢀﬂag(s)ꢀ

SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀ0

SIZ [m]

Descriptionꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀﬁrstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀ

followingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀꢀ

theꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀ

proceedsꢀwithꢀtheꢀfollowingꢀinstruction.

ꢀ

Operationꢀ

ꢀ

[m]ꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ

Skipꢀifꢀ[m]=0ꢀ

Affectedꢀﬂag(s)ꢀ

None

SkipꢀifꢀincrementꢀDataꢀMemoryꢀisꢀzeroꢀwithꢀresultꢀinꢀACC

SIZA [m]

Descriptionꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀﬁrstꢀincrementedꢀbyꢀ1.ꢀIfꢀtheꢀresultꢀisꢀ0,ꢀtheꢀꢀ

followingꢀinstructionꢀisꢀskipped.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulatorꢀbutꢀtheꢀspeciﬁedꢀ

DataꢀMemoryꢀcontentsꢀremainꢀunchanged.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀ

instructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ

0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.

ꢀ

Operationꢀ

ꢀ

ACCꢀ←ꢀ[m]ꢀ+ꢀ1ꢀ

SkipꢀifꢀACC=0

Affectedꢀﬂag(s)ꢀ

None

SkipꢀifꢀbitꢀiꢀofꢀDataꢀMemoryꢀisꢀnotꢀ0

SNZ [m].i

Descriptionꢀ

ꢀ

IfꢀbitꢀiꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀnotꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀ

requiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀꢀ

cycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.

Operationꢀ

Skipꢀifꢀ[m].iꢀ≠ꢀ0

None

Affectedꢀﬂag(s)ꢀ

ꢀ

SubtractꢀDataꢀMemoryꢀfromꢀACC

SUB A,[m]

Descriptionꢀ

ꢀ

TheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ

storedꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀﬂagꢀwillꢀbeꢀꢀ

clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀﬂagꢀwillꢀbeꢀsetꢀtoꢀ1.

Operationꢀ

ACCꢀ←ꢀACCꢀ−ꢀ[m]

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

Rev. 1.41

111

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

ꢀ

SubtractꢀDataꢀMemoryꢀfromꢀACCꢀwithꢀresultꢀinꢀDataꢀMemory

SUBM A,[m]

Descriptionꢀ

ꢀ

TheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀTheꢀresultꢀisꢀꢀ

storedꢀinꢀtheꢀDataꢀMemory.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀﬂagꢀwillꢀbeꢀꢀ

clearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀﬂagꢀwillꢀbeꢀsetꢀtoꢀ1.

Operationꢀ

[m]ꢀ←ꢀACCꢀ−ꢀ[m]

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

SubtractꢀimmediateꢀdataꢀfromꢀACC

SUB A,x

Descriptionꢀ

ꢀ

TheꢀimmediateꢀdataꢀspeciﬁedꢀbyꢀtheꢀcodeꢀisꢀsubtractedꢀfromꢀtheꢀcontentsꢀofꢀtheꢀAccumulator.ꢀꢀ

TheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀNoteꢀthatꢀifꢀtheꢀresultꢀofꢀsubtractionꢀisꢀnegative,ꢀtheꢀCꢀꢀ

ﬂagꢀwillꢀbeꢀclearedꢀtoꢀ0,ꢀotherwiseꢀifꢀtheꢀresultꢀisꢀpositiveꢀorꢀzero,ꢀtheꢀCꢀﬂagꢀwillꢀbeꢀsetꢀtoꢀ1.

Operationꢀ

ACCꢀ←ꢀACCꢀ−ꢀx

OV,ꢀZ,ꢀAC,ꢀC

Affectedꢀﬂag(s)ꢀ

SwapꢀnibblesꢀofꢀDataꢀMemory

SWAP [m]

Descriptionꢀ

Operationꢀ

Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀinterchanged.

[m].3~[m].0ꢀ↔ꢀ[m].7~[m].4

None

Affectedꢀﬂag(s)ꢀ

ꢀ

SwapꢀnibblesꢀofꢀDataꢀMemoryꢀwithꢀresultꢀinꢀACC

SWAPA [m]

Descriptionꢀ

ꢀ

Theꢀlow-orderꢀandꢀhigh-orderꢀnibblesꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀinterchanged.ꢀTheꢀꢀ

resultꢀisꢀstoredꢀinꢀtheꢀAccumulator.ꢀTheꢀcontentsꢀofꢀtheꢀDataꢀMemoryꢀremainꢀunchanged.

Operationꢀ

ꢀ

ACC.3~ACC.0ꢀ←ꢀ[m].7~[m].4ꢀ

ACC.7~ACC.4ꢀ←ꢀ[m].3~[m].0

Affectedꢀﬂag(s)ꢀ

None

SkipꢀifꢀDataꢀMemoryꢀisꢀ0

SZ [m]

Descriptionꢀ

ꢀ

IfꢀtheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀꢀ

requiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀꢀ

cycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.

Operationꢀ

Skipꢀifꢀ[m]=0

None

Affectedꢀﬂag(s)ꢀ

SkipꢀifꢀDataꢀMemoryꢀisꢀ0ꢀwithꢀdataꢀmovementꢀtoꢀACC

SZA [m]

Descriptionꢀ

TheꢀcontentsꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀareꢀcopiedꢀtoꢀtheꢀAccumulator.ꢀIfꢀtheꢀvalueꢀisꢀzero,ꢀꢀ

theꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀtheꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀꢀ

whileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀinstruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0ꢀtheꢀꢀ

programꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.

ꢀ

Operationꢀ

ꢀ

ACCꢀ←ꢀ[m]ꢀ

Skipꢀifꢀ[m]=0

Affectedꢀﬂag(s)ꢀ

None

SkipꢀifꢀbitꢀiꢀofꢀDataꢀMemoryꢀisꢀ0

SZ [m].i

Descriptionꢀ

ꢀ

IfꢀbitꢀiꢀofꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀisꢀ0,ꢀtheꢀfollowingꢀinstructionꢀisꢀskipped.ꢀAsꢀthisꢀrequiresꢀ

theꢀinsertionꢀofꢀaꢀdummyꢀinstructionꢀwhileꢀtheꢀnextꢀinstructionꢀisꢀfetched,ꢀitꢀisꢀaꢀtwoꢀcycleꢀ

instruction.ꢀIfꢀtheꢀresultꢀisꢀnotꢀ0,ꢀtheꢀprogramꢀproceedsꢀwithꢀtheꢀfollowingꢀinstruction.

Operationꢀ

Skipꢀifꢀ[m].i=0

None

Affectedꢀﬂag(s)ꢀ

Rev. 1.41

112

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

ꢀ

Readꢀtableꢀ(speciﬁcꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory

TABRD [m]

Descriptionꢀ

ꢀ

Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(speciﬁcꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀpairꢀꢀ

(TBHPꢀandꢀTBLP)ꢀisꢀmovedꢀtoꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.

Operationꢀ

ꢀ

[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ

TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)

Affectedꢀﬂag(s)ꢀ

None

ꢀ

Readꢀtableꢀ(currentꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory

TABRDC [m]

Descriptionꢀ

ꢀ

Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(currentꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀꢀ

movedꢀtoꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.

Operationꢀ

ꢀ

[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ

TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)

Affectedꢀﬂag(s)ꢀ

None

Readꢀtableꢀ(lastꢀpage)ꢀtoꢀTBLHꢀandꢀDataꢀMemory

TABRDL [m]

Descriptionꢀ

ꢀ

Theꢀlowꢀbyteꢀofꢀtheꢀprogramꢀcodeꢀ(lastꢀpage)ꢀaddressedꢀbyꢀtheꢀtableꢀpointerꢀ(TBLP)ꢀisꢀmovedꢀꢀ

toꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀhighꢀbyteꢀmovedꢀtoꢀTBLH.

Operationꢀ

ꢀ

[m]ꢀ←ꢀprogramꢀcodeꢀ(lowꢀbyte)ꢀ

TBLHꢀ←ꢀprogramꢀcodeꢀ(highꢀbyte)

Affectedꢀﬂag(s)ꢀ

None

ꢀ

LogicalꢀXORꢀDataꢀMemoryꢀtoꢀACC

XOR A,[m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ

operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.

Operationꢀ

ACCꢀ←ꢀACCꢀ″XOR″ꢀ[m]

Z

Affectedꢀﬂag(s)ꢀ

ꢀ

LogicalꢀXORꢀACCꢀtoꢀDataꢀMemory

XORM A,[m]

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀspeciﬁedꢀDataꢀMemoryꢀandꢀtheꢀAccumulatorꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ

operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀDataꢀMemory.

Operationꢀ

[m]ꢀ←ꢀACCꢀ″XOR″ꢀ[m]

Z

Affectedꢀﬂag(s)ꢀ

LogicalꢀXORꢀimmediateꢀdataꢀtoꢀACC

XOR A,x

Descriptionꢀ

ꢀ

DataꢀinꢀtheꢀAccumulatorꢀandꢀtheꢀspeciﬁedꢀimmediateꢀdataꢀperformꢀaꢀbitwiseꢀlogicalꢀXORꢀꢀ

operation.ꢀTheꢀresultꢀisꢀstoredꢀinꢀtheꢀAccumulator.

Operationꢀ

ACCꢀ←ꢀACCꢀ″XOR″ꢀx

Z

Affectedꢀﬂag(s)ꢀ

Rev. 1.41

113

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

Package Information

Noteꢀthatꢀtheꢀpackageꢀinformationꢀprovidedꢀhereꢀisꢀforꢀconsultationꢀpurposesꢀonly.ꢀAsꢀthisꢀ

informationꢀmayꢀbeꢀupdatedꢀatꢀregularꢀintervalsꢀusersꢀareꢀremindedꢀtoꢀconsultꢀtheꢀHoltekꢀwebsiteꢀforꢀ

theꢀlatestꢀversionꢀofꢀtheꢀPackage/CartonꢀInformation.

Additionalꢀsupplementaryꢀinformationꢀwithꢀregardꢀtoꢀpackagingꢀisꢀlistedꢀbelow.ꢀClickꢀonꢀtheꢀrelevantꢀ

sectionꢀtoꢀbeꢀtransferredꢀtoꢀtheꢀrelevantꢀwebsiteꢀpage.

•ꢀ FurtherꢀPackageꢀInformationꢀ(includeꢀOutlineꢀDimensions,ꢀProductꢀTapeꢀandꢀReelꢀSpeciﬁcations)

•ꢀ PackingꢀMeterialsꢀInformation

•ꢀ Cartonꢀinformation

Rev. 1.41

114

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

8-pin SOP (150mil) Outline Dimensions

&

#

)

*

ꢁ

"

+

ꢀ

/

0

=

-

.

Dimensions in inch

Symbol

Min.

—

Nom.

Max.

—

A

B

C

C’

D

E

F

0.236 BSC

—

0.154 BSC

—

0.012

—

0.020

—

0.193 BSC

—

0.069

—

0.050 BSC

0.004

0.016

0.004

0°

—

0.010

0.050

0.010

8°

G

H

α

Dimensions in mm

Symbol

Min.

—

Nom.

6.00 BSC

3.90 BSC

—

Max.

—

A

B

C

C’

D

E

F

—

0.31

—

0.51

—

4.90 BSC

—

1.75

—

1.27 BSC

—

0.10

0.40

0.10

0°

0.25

1.27

0.25

8°

G

H

α

—

Rev. 1.41

115

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

10-pin SOP (150mil) Outline Dimensions

ꢁ

ꢂ

$

)

*

ꢁ

#

+

ꢀ

/

0

,

=

-

.

Dimensions in inch

Symbol

Min.

—

Nom.

Max.

—

A

B

C

C’

D

E

F

0.236 BSC

—

0.154 BSC

—

0.012

—

0.018

—

0.193 BSC

—

0.069

—

0.039 BSC

0.004

0.016

0.004

0°

—

0.010

0.050

0.010

8°

G

H

α

Dimensions in mm

Symbol

Min.

—

Nom.

6.00 BSC

3.90 BSC

—

Max.

—

A

B

C

C’

D

E

F

—

0.30

—

0.45

—

4.90 BSC

—

1.75

—

1.00 BSC

—

0.10

0.40

0.10

0°

0.25

1.27

0.25

8°

G

H

α

—

Rev. 1.41

116

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

10-pin MSOP Outline Dimensions

1

0

6

E

1

5

E

D

L

A

2

C

G

e

B

A

1

L

1

R

0

.

1

0

4

C

O

N

R

E

)

S

Dimensions in inch

Symbol

Min.

Nom.

—

Max.

0.043

0.006

0.037

0.013

0.009

—

A

A1

A2

B

—

0.000

0.030

0.007

0.003

—

0.033

—

C

—

D

0.118 BSC

0.193 BSC

0.118 BSC

0.020 BSC

0.024

E

—

E1

e

—

L

0.016

—

0.031

—

L1

y

0.037 BSC

0.004

—

θ

0°

—

8°

Dimensions in mm

Symbol

Min.

—

Nom.

—

Max.

1.10

0.15

0.95

0.33

0.23

—

A

A1

A2

B

0.00

0.75

0.17

0.08

—

0.85

—

C

—

D

3.00 BSC

4.90 BSC

3.00 BSC

0.50 BSC

0.60

E

—

E1

e

—

L

0.40

—

0.80

—

L1

y

0.95 BSC

0.1

—

θ

0°

—

8°

Rev. 1.41

117

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

16-pin NSOP (150mil) Outline Dimensions

ꢀ

$

'

)

*

ꢀ

&

+

ꢁ

/

0

,

=

.

-

Dimensions in inch

Symbol

Min.

—

Nom.

Max.

—

A

B

C

C’

D

E

F

0.236 BSC

—

0.154 BSC

—

0.012

—

0.020

—

0.390 BSC

—

0.069

—

0.050 BSC

0.004

0.016

0.004

0°

—

0.010

0.050

0.010

8°

G

H

α

Dimensions in mm

Symbol

Min.

—

Nom.

6.00 BSC

3.90 BSC

—

Max.

—

A

B

C

C’

D

E

F

—

0.31

—

0.51

—

9.90 BSC

—

1.75

—

1.27 BSC

—

0.10

0.40

0.10

0°

0.25

1.27

0.25

8°

G

H

α

—

Rev. 1.41

118

April 11, 2017

HT68F002/HT68F0025/HT68F003

Cost-Effective Flash MCU with EEPROM

The information appearing in this Data Sheet is believed to be accurate at the time

of publication. However, Holtek assumes no responsibility arising from the use of

the speciﬁcations described. The applications mentioned herein are used solely

for the purpose of illustration and Holtek makes no warranty or representation that

such applications will be suitable without further modification, nor recommends

the use of its products for application that may present a risk to human life due to

malfunction or otherwise. Holtek's products are not authorized for use as critical

components in life support devices or systems. Holtek reserves the right to alter

its products without prior notiﬁcation. For the most up-to-date information, please

visit our web site at http://www.holtek.com.tw/en/home.

Rev. 1.41

119

April 11, 2017


型号：	HT68F002
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Cost-Effective Flash MCU with EEPROM 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件：	总119页 (文件大小：6619K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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