HT82K68A(28SOP) [HOLTEK]
Microprocessor Circuit, CMOS, PDSO28,;
| 型号： | HT82K68A(28SOP) |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | Microprocessor Circuit, CMOS, PDSO28, 光电二极管 |
| 文件： | 总39页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT82K68A
Multimedia Keyboard Encoder 8-Bit Mask MCU
Technical Document
·
·
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Tools Information
FAQs
Application Note
Features
·
·
·
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·
Operating voltage: 2.2V~5.5V
32/34 bidirectional I/O lines
2.4V LVR by option (default disable)
HALT function and wake-up feature reduce power
consumption
One 8-bit programmable timer counter with overflow
interrupts
·
·
·
·
·
·
Six-level subroutine nesting
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·
·
·
Crystal or RC oscillator
Watchdog Timer
Bit manipulation instructions
16-bit table read instructions
63 powerful instructions
3K´16 program ROM
All instructions in 1 or 2 machine cycles
20/28-pin SOP, 48-pin SSOP package
160´8 data RAM
One external interrupt pin (shared with PC2)
General Description
The HT82K68A is an 8-bit high performance peripheral
interface IC, designed for multiple I/O products and mul-
timedia applications. It supports interface to a low speed
PC with multimedia keyboard or wireless keyboard in
Windows 95, Windows 98 or Windows 2000
environment. A HALT feature is included to reduce
power consumption.
Rev. 1.70
1
December 26, 2005
HT82K68A
Block Diagram
P
C
2
S
T
A
A
C
K
0
S
T
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K
1
I
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S
S
S
T
T
T
T
A
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C
C
C
C
K
K
K
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2
3
4
5
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~
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7
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A
Rev. 1.70
2
December 26, 2005
HT82K68A
Pin Assignment
P
P
P
P
P
P
P
P
P
P
B
B
A
A
A
A
B
B
B
B
5
4
3
2
1
0
3
2
1
0
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
P
P
P
P
P
P
N
N
N
N
O
O
V
R
P
P
P
P
P
P
P
P
P
P
B
B
A
A
A
A
6
7
4
5
6
7
C
C
C
C
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
N
C
S
C
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
P
B
B
A
A
A
A
6
7
4
5
6
7
P
B
5
1
2
3
4
5
6
7
8
9
1
1
1
1
1
N
C
S
C
1
P
P
B
4
P
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7
D
D
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P
P
A
3
P
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6
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T
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P
A
2
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3
1
2
3
4
5
6
7
8
9
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2
1
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
2
1
P
A
4
P
P
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5
4
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D
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4
(
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)
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P
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2
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3
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1
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7
6
5
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7
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2
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7
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2
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6
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2
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5
4
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2
3
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8
2
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6
8
A
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T
8
2
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6
8
A
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T
8
2
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6
8
A
2
8
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4
8
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A
2
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Pin Description
Mask
Option
Pin Name I/O
Description
Wake-up
Pull-high
or None
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input
by mask option. Software* instructions determine the CMOS output or Schmitt trig-
ger input with or without 12K pull-high resistor.
PA0~PA7 I/O
PB0~PB7 I/O
Pull-high
or None
Bidirectional 8-bit input/output port. Software* instructions determine the output or
Schmitt trigger input with or without pull-high resistor.
Wake-up
Pull-high
or None
This pin is an I/O port. NMOS open drain output with pull-high resistor and can be
used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up in-
put by mask option.
PC0
PC1
I/O
I/O
Wake-up
Pull-high
or None
This pin is an I/O port. NMOS open drain output with pull-high resistor and can be
used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up in-
put by mask option.
Bidirectional 2-bit input/output port. Each bit can be configured as a wake-up input
by mask option. Software* instructions determine the CMOS output or Schmitt trig-
ger input with or without pull-high resistor.
Wake-up
Pull-high
or None
PC2~PC3 I/O
PC2 also as external interrupt input pin. PE0 determine whether rising edge or fall-
ing edge of PC2 to trigger the INT circuit.
Pull-high
or None
Bidirectional 4-bit input/output port. Software* instructions determine the CMOS
output or Schmitt trigger input with or without pull-high resistor.
PC4~PC7 I/O
PD0~PD7 I/O
Pull-high
or None
Bidirectional 8-bit input/output port. Software* instructions determine the CMOS
output or Schmitt Trigger input with or without pull-high resistor.
Rev. 1.70
3
December 26, 2005
HT82K68A
Mask
Option
Pin Name I/O
Description
Bidirectional input/output port. Software* instruction determine the CMOS output or
Schmitt trigger input with or without pull-high resistor.
Pull-high
or None
PE0~PE1 I/O
If PE0 output 1, rising edge of PC2 trigger INT circuit.
PE0 output 0, falling edge of PC2 trigger INT circuit.
This pin is a CMOS output structure. The pad can function as LED (SCR) drivers for
the keyboard. IOL=18mA at VOL=3.4V
PE2
PE3
PE4
O
O
O
This pin is a CMOS output structure. The pad can function as LED (NUM) drivers
for the keyboard. IOL=18mA at VOL=3.4V
This pin is a CMOS output structure. The pad can function as LED (CAP) drivers for
the keyboard. IOL=18mA at VOL=3.4V
VDD
VSS
Positive power supply
¾
¾
¾
¾
Negative power supply, ground
Chip reset input. Active low. Built-in power-on reset circuit to reset the entire chip.
Chip can also be externally reset via RESET pin
RESET
I
¾
OSC1, OSC2 are connected to an RC network or a crystal for the internal system
clock. In the case of RC operation, OSC2 is the output terminal for the 1/4 system
clock; A 110kW resistor is connected to OSC1 to generate a 2 MHZ frequency.
OSC1
OSC2
I
Crystal or RC
O
Note:
*: Software means the HT-IDE (Holtek Integrated Development Environment) can be configured by mask op-
tion.
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+6.0V
Input Voltage .............................VSS-0.3V to VDD+0.3V
Storage Temperature ...........................-50°C to 125°C
Operating Temperature ..........................-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Operating Voltage
Min. Typ. Max. Unit
VDD
¾
VDD
IDD1
2.2
¾
¾
¾
¾
¾
¾
¾
¾
0
5.5
1.5
5
V
¾
¾
0.7
2
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
3V
5V
No load, fSYS= 6MHz
Operating Current (Crystal OSC)
Operating Current (RC OSC)
mA
0.5
2
1
IDD2
ISTB1
ISTB2
VIL1
No load, fSYS= 6MHz
mA
mA
mA
V
5
8
¾
¾
¾
¾
¾
¾
¾
¾
Standby Current (WDT enabled)
Standby Current (WDT Disabled)
Input Low Voltage for I/O Ports (Schmitt)
Input High Voltage for I/O Ports (Schmitt)
No load, system HALT
15
3
No load, system HALT
6
0.9
1.5
3
¾
¾
0
2.1
3.5
VIH1
V
5
Rev. 1.70
4
December 26, 2005
HT82K68A
Test Conditions
Conditions
Symbol
VLVR
Parameter
Low Voltage Reset
Min. Typ. Max. Unit
VDD
¾
2.4
¾
¾
¾
¾
¾
¾
¾
¾
V
V
¾
¾
¾
0
¾
1.2
2.3
3
3V
5V
3V
5V
3V
5V
3V
5V
VIL2
Input Low Voltage for I/O Ports (CMOS)
Input High Voltage for I/O Ports (CMOS)
Input Low Voltage (RESET)
0
1.7
2.7
0
VIH2
VIL3
VIH3
V
V
V
¾
¾
¾
5
0.7
1.3
3
0
2.4
4.0
Input High Voltage (RESET)
5
I/O Port Sink Current
IOL
V
V
OL= 0.5V
OH= 4.5V
5V
16
25
mA
mA
¾
¾
(PA, PB, PC, PD, PE0~PE1)
I/O Port Source Current
IOH1
5V
5V
-8
-16
(PA, PB, PC2~PC7, PD, PE0~PE1)
IOH2
ILED
tPOR
VOH= 4.5V
I/O Port Source Current (PE2~PE4)
LED Sink Current (SCR, NUM, CAP)
Power-on Reset Time
mA
mA
ms
-2.5
10
30
30
15
4
-4
18
60
60
30
9
¾
24
90
90
45
15
8
5V VOL=3.4V
5V
3V
5V
3V
5V
3V
5V
R=100kW, C=0.1mF
Internal Pull-high Resistance
(PA, PB, PC, PD, PE)
RPH
¾
kW
kW
kW
RPH1
Internal Pull-high Resistance (DATA, CLK)
Internal Pull-high Resistance (RESET)
Frequency Variation
¾
¾
2
4.7
60
31
¾
¾
30
15
¾
¾
90
46
±1
±20
RPH2
Crystal
RC
%
%
5V
Df/f
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
System Clock (Crystal OSC)
System Clock (RC OSC)
Watchdog Oscillator
Min. Typ. Max. Unit
VDD
3V
5V
3V
5V
3V
5V
3V
5V
6
6
¾
¾
¾
¾
fSYS1
MHz
MHz
ms
¾
4.8
4.8
45
35
12
9
6
7.2
7.2
180
130
45
fSYS2
OSC resistor 40kW
¾
6
90
76
23
19
tWDTOSC
tWDT1
Watchdog Time-out Period (RC)
Without WDT prescaler
ms
35
Watchdog Time-out Period
(System Clock)
tWDT2
tRES
tSST
tINT
tSYS
Without WDT prescaler
1024
¾
¾
¾
¾
¾
¾
1
¾
¾
¾
¾
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
¾
ms
Power-up or wake-up
from HALT
tSYS
1024
¾
¾
1
¾
ms
Note: tSYS= 1/fSYS
Rev. 1.70
5
December 26, 2005
HT82K68A
Functional Description
Execution Flow
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The HT82K68A system clock is derived from either a
crystal or an RC oscillator. The system clock is internally
divided into four non-overlapping clocks. One instruc-
tion cycle consists of four system clock cycles.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The 12-bit program counter (PC) controls the sequence
in which the instructions stored in the program ROM are
executed and its contents specify a maximum of 4096
addresses.
Once a control transfer takes place, an additional
dummy cycle is required.
Program Memory - ROM
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized with
3072´16 bits, addressed by the program counter and ta-
ble pointer.
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
S
y
s
t
e
m
C
l
o
c
k
O
S
C
2
(
R
C
o
n
l
y
)
(
N
M
O
S
o
p
e
n
d
r
a
i
n
o
u
t
p
u
t
)
P
C
P
C
+
1
P
C
+
2
P
C
F
e
t
c
h
I
N
S
T
(
P
C
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
-
1
)
F
e
t
c
h
I
N
S
T
(
P
C
+
1
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
)
F
e
t
c
h
I
N
S
T
(
P
C
+
2
)
E
x
e
c
u
t
e
I
N
S
T
(
P
C
+
1
)
Execution Flow
Program Counter
Mode
*11
0
*10
0
*9
0
*8
0
*7
0
*6
0
*5
0
*4
0
*3
0
*2
0
*1
0
*0
0
Initial Reset
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer Counter Overflow
Skip
0
0
0
0
0
0
0
0
1
0
0
0
Program Counter+2
Loading PCL
@7
#7
@6
#6
@5
#5
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
*11
*10
*9
*8
#8
S8
Jump, Call Branch
Return from Subroutine
#11
#10
#9
S9
S11 S10
S7
S6
S5
S4
S3
S2
S1
S0
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
S11~S0: Stack register bits
@7~@0: PCL bits
Rev. 1.70
6
December 26, 2005
HT82K68A
0
0
0
0
0
8
H
H
The TBLH is read only and cannot be restored. If the
main routine and the ISR (Interrupt Service Routine)
both employ the table read instruction, the contents of
the TBLH in the main routine are likely to be changed
by the table read instruction used in the ISR. Errors
can occur. In other words, using the table read instruc-
tion in the main routine and the ISR simultaneously
should be avoided. However, if the table read instruc-
tion has to be applied in both the main routine and the
ISR, the interrupt is supposed to be disabled prior to
the table read instruction. It will not be enabled until
the TBLH has been backed up. The table pointer
(TBLP) is a read/write register (07H), which indicates the
table location. Before accessing the table, the location
must be placed in TBLP. All table related instructions
need 2 cycles to complete the operation. These areas
may function as normal program memory depending
upon the requirements.
D
e
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i
c
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e
P
r
o
g
r
a
m
n
0
0
H
L
o
o
k
-
u
p
t
a
b
l
e
(
2
5
6
w
o
r
d
s
)
R
O
M
n
F
F
H
L
o
o
k
-
u
p
t
a
b
l
e
(
2
5
6
w
o
r
d
s
)
B
F
F
H
1
6
b
i
t
s
N
o
t
e
:
n
r
a
n
g
e
s
f
r
o
m
0
t
o
B
Program Memory
Certain locations in the program memory are reserved
for special usage:
·
Location 000
Stack Register - STACK
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H.
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organized into six levels and is neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledg-
ment, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
·
Location 004H
Location 004H is reserved for external interrupt ser-
vice program. If the PC2 (external input pin) is acti-
vated, the interrupt is enabled, and the stack is not full,
the program begins execution at location 004H. The
pin PE0 determine whether the rising or falling edge of
the PC2 to activate external interrupt service program.
·
·
Location 008H
This area is reserved for the timer counter interrupt
service program. If timer interrupt results from a timer
counter overflow, and if the interrupt is enabled and
the stack is not full, the program begins execution at
location 008H.
Data Memory - RAM
The data memory is designed with 184´8 bits. It is di-
vided into two functional groups: special function regis-
ters and general purpose data memory (160´8). Most of
them are read/write, but some are read only.
Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the cur-
rent page, one page=256 words) and TABRDL [m]
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, the remaining 1 bit is read as 0. The
Table Higher-order byte register (TBLH) is read only.
The special function registers include the Indirect Ad-
dressing register 0 (00H), the Memory Pointer register 0
(MP0;01H), the Indirect Addressing register 1 (02H), the
Memory Pointer register 1 (MP1;03H), the Accumulator
(ACC;05H), the Program Counter Lower-byte register
(PCL;06H), the Table Pointer (TBLP;07H), the Table
Higher-order byte register (TBLH;08H), the Watchdog
Timer option Setting register (WDTS;09H), the Status reg-
ister (STATUS;0AH), the Interrupt Control register
Table Location
Instruction(s)
*11
P11
1
*10
P10
0
*9
P9
1
*8
P8
1
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
TABRDL [m]
@7
@7
@6
@6
@5
@5
@4
@4
@3
@3
@2
@2
@1
@1
@0
@0
Note: *11~*0: Table location bits
@7~@0: Table location bits
P11~P8: Current program counter bits
Rev. 1.70
7
December 26, 2005
HT82K68A
I
n
d
i
r
e
c
t
A
d
d
r
e
M
s
s
i
n
g
R
e
g
i
s
t
e
r
0
Indirect Addressing Register
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
P
0
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] can access the data memory
pointed to by MP0 (01H) and MP1 (03H) respectively.
Reading location 00H or 02H indirectly will return the re-
sult 00H. Writing indirectly results in no operation.
I
n
d
i
r
e
c
t
A
d
d
r
e
s
s
i
n
g
R
e
g
i
s
t
e
r
1
M
P
1
A
C
C
P
C
L
T
B
L
P
T
B
L
H
The function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are 8-bit registers which can
be used to access the data memory by combining corre-
sponding indirect addressing registers.
W
D
T
S
S
T
A
T
U
S
0
0
A
B
H
H
I
N
T
C
0
0
C
D
H
H
T
M
R
S
p
e
c
i
a
l
P
u
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p
o
s
e
T
M
R
C
0
E
H
D
A
T
A
M
E
M
O
R
Y
Accumulator
0
F
H
The accumulator is closely related to the ALU opera-
tions. It is also mapped to location 05H of the data mem-
ory and is capable of carrying out immediate data
operations. The data movement between two data
memory locations must pass through the accumulator.
1
1
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
P
P
A
B
P
P
A
B
C
C
P
C
Arithmetic and Logic Unit - ALU
P
C
C
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
P
D
P
D
C
·
·
·
·
·
P
E
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
1
1
A
B
H
H
P
E
C
:
U
n
u
s
e
d
.
1
1
C
D
H
H
R
²
²
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
1
E
H
1
F
H
2
6
0
H
H
The ALU not only saves the results of a data operation but
also changes the status register.
0
G
e
n
e
r
a
l
P
u
M
r
p
o
s
e
Status Register - Status
D
A
T
A
M
E
O
R
Y
The 8-bit status register (0AH) contains the zero flag (Z),
carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF) and watch dog time-out
flag (TO). The status register not only records the status
information but also controls the operation sequence.
(
1
6
0
B
y
t
e
s
)
F
F
H
RAM Mapping
(INTC;0BH), the timer counter register (TMR;0DH), the
timer counter control register (TMRC;0EH), the I/O regis-
ters (PA;12H, PB;14H, PC;16H, PD;18H, PE;1AH) and
the I/O control registers (PAC;13H, PBC;15H, PCC;17H,
PDC;19H, PEC;1BH). The remaining space before the
60H is reserved for future expanded usage and reading
these locations will get the result 00H. The general pur-
pose data memory, addressed from 60H to FFH, is used
for data and control information under instruction com-
mand.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flags. It should be noted
that operations related to the status register may give
different results from those intended. The TO and PDF
flags can only be changed by system power up, Watch-
dog Timer overflow, executing the HALT instruction and
clearing the Watchdog Timer.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
All data memory areas can handle arithmetic, logic, in-
crement, decrement and rotate operations directly. Ex-
cept for some dedicated bits, each bit in the data
memory can be set and reset by the ²SET [m].i² and
²CLR [m].i² instructions, respectively. They are also indi-
rectly accessible through Memory pointer registers
(MP0;01H, MP1;03H).
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be auto-
matically pushed onto the stack. If the contents of status
are important and if the subroutine can corrupt the sta-
tus register, precaution must be taken to save it properly.
Rev. 1.70
8
December 26, 2005
HT82K68A
Bit No.
Label
Function
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
0
C
AC is set if an operation results in a carry out of the low nibbles in addition or if no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
1
2
3
AC
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
OV
PDF is cleared when either a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing a ²HALT² instruction.
4
PDF
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
5
TO
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Interrupt
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
The HT82K68A provides an internal timer counter inter-
rupt and an external interrupt shared with PC2. The in-
terrupt control register (INTC;0BH) contains the
interrupt control bits to set not only the enable/disable
status but also the interrupt request flags.
program which corrupt the desired control sequence,
the contents should be saved in advance.
The internal timer counter interrupt is initialized by set-
ting the timer counter interrupt request flag (T0F; bit 5 of
INTC), which is normally caused by a timer counter
overflow. When the interrupt is enabled, and the stack is
not full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
Once an interrupt subroutine is serviced, all other inter-
rupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the inter-
rupt request will not be acknowledged, even if the re-
lated interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be pre-
vented from becoming full.
The external interrupt is shared with PC2. The external
interrupt is activated, the related interrupt request flag
(EIF; bit4 of INTC) is then set. When the interrupt is en-
abled, the stack is not full, and the external interrupt is
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will also be
cleared to disable other interrupts.
All these kinds of interrupt have the wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack followed by
a branch to a subroutine at the specified location in the
program memory. Only the program counter is pushed
The external interrupt (PC2) can be triggered by a high
to low transition, or a low to high transition of the PC2,
which is dependent on the output level of the PE0. When
PE0 is output high, the external interrupt is triggered by
Bit No.
Label
EMI
EEI
Function
0
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
Control the external interrupt
2
ET0I
¾
Controls the timer counter interrupt (1= enabled; 0= disabled)
Unused bit, read as ²0²
3, 6~7
4
5
EIF
External interrupt flag
T0F
Internal timer counter request flag (1= active; 0= inactive)
INTC (0BH) Register
Rev. 1.70
9
December 26, 2005
HT82K68A
a low to high transition of the PC2. When PE0 is output
low, the external interrupt is triggered by a high to low
transition of PC2.
nal provides the system clock. The HALT mode stops
the system oscillator and resists the external signal to
conserve power.
VDD
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI instruc-
tion is executed or the EMI bit and the related interrupt
control bit are set to 1 (if the stack is not full). To return
from the interrupt subroutine, a RET or RETI instruction
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET will not.
OSC1
OSC1
fSYS/4
(NMOS Open
Drain Output)
OSC2
OSC2
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Crystal Oscillator
RC Oscillator
System Oscillator
If an RC oscillator is used, an external resistor between
OSC1 and VDD is needed and the resistance must
range from 51kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchro-
nize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of the
oscillation may vary with VDD, temperature and the chip
itself due to process variations. It is, therefore, not suit-
able for timing sensitive operations where accurate os-
cillator frequency is desired.
No.
a
Interrupt Source
External interrupt 1
Timer counter overflow
Vector
04H
b
08H
The timer counter interrupt request flag (T0F), external
interrupt request (EIF) enable timer counter bit (ET0I),
enable external interrupt bit (EEI) and enable master in-
terrupt bit (EMI) constitute an interrupt control register
(INTC) which is located at 0BH in the data memory. EMI,
ET0I and EEI, are used to control the enabling/disabling
of interrupts. These bits prevent the requested interrupt
from being serviced. Once the interrupt request flags
(T0F) are set, they will remain in the INTC register until
the interrupts are serviced or cleared by a software in-
struction.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift needed for oscillator, no other external components
are needed. Instead of a crystal, the resonator can also
be connected between OSC1 and OSC2 to get a fre-
quency reference, but two external capacitors in OSC1
and OSC2 are required.
It is suggested that a program does not use the ²CALL
subroutine² within the interrupt subroutine. Because in-
terrupts often occur in an unpredictable manner or need
to be serviced immediately in some applications, if only
one stack is left and enabling the interrupt is not well
controlled, once the ²CALL subroutine² operates in the in-
terrupt subroutine it will damage the original control se-
quence.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works for a
period of approximately 78ms. The WDT oscillator can
be disabled by mask option to conserve power.
Watchdog Timer - WDT
Oscillator Configuration
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), decided by mask options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
There are two oscillator circuits in HT82K68A. Both are
designed for system clocks; the RC oscillator and the
Crystal oscillator, which are determined by mask op-
tions. No matter what oscillator type is selected, the sig-
S
y
s
t
e
m
c
l
o
c
k
/
4
W
D
T
P
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c
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r
M
a
s
k
8
-
b
i
t
C
o
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r
7
-
b
i
t
C
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t
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r
O
p
t
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n
S
e
l
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c
t
W
D
T
O
S
C
8
-
t
o
-
1
M
U
X
W
S
0
~
W
S
2
W
D
T
T
i
m
e
-
o
u
t
Watchdog Timer
Rev. 1.70
10
December 26, 2005
HT82K68A
Power Down Operation - HALT
dictable results. The Watchdog Timer can be disabled
by mask option. If the Watchdog Timer is disabled, all
the executions related to the WDT results in no opera-
tion.
The HALT mode is initialized by the HALT instruction
and results in the following...
·
·
·
The system oscillator will turn off but the WDT oscilla-
tor keeps running (if the WDT oscillator is selected).
Once the internal WDT oscillator (RC oscillator normally
with a period of 78ms) is selected, it is first divided by 256
(8-stages) to get the nominal time-out period of approxi-
mately 20 ms. This time-out period may vary with tem-
perature, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS)
can give different time-out periods. If WS2, WS1, WS0
are all equal to 1, the division ratio is up to 1:128, and the
maximum time-out period is 2.6 seconds.
The contents of the on chip RAM and registers remain
unchanged.
WDT and WDT prescaler will be cleared and recount
again (if the WDT clock has come from the WDT oscil-
lator).
·
·
All I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, interrupt, and external falling edge signal
on port A and port C [0:3] or a WDT overflow. An exter-
nal reset causes a device initialization and the WDT
overflow performs a ²warm reset². Examining the TO
and PDF flags, the reason for chip reset can be deter-
mined. The PDF flag is cleared when system power-up
or executing the CLR WDT instruction and is set when
the HALT instruction is executed. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and SP, the others keep
their original status.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the WDT logic can be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, which can be used to indicate some speci-
fied status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
On the other hand, awakening from an external interrupt
(PC2), two sequences may happen. If the interrupt is
disabled or the interrupt is enabled but the stack is full,
the program will resume execution at the next instruc-
tion. But if the interrupt is enabled and the stack is not
full, the regular interrupt response takes place.
WS2
WS1
WS0
Division Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:1
1:2
1:4
1:8
The port A or port C [0:3] wake-up can be considered as
a continuation of normal execution. Each bit in port A
can be independently selected to wake up the device by
mask option. Awakening from an I/O port stimulus, the
program will resume execution of the next instruction.
1:16
1:32
1:64
1:128
Once a wake-up event occurs, and the system clock co-
mes from a crystal, it takes 1024 tSYS (system clock pe-
riod) to resume normal operation. In other words, the
HT82K68Awill insert a dummy period after the wake-up.
If the system clock comes from an RC oscillator, it con-
tinues operating immediately. If the wake-up results in
next instruction execution, this will execute immediately
after the dummy period is completed.
WDTS (09H) Register
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit TO. An overflow in the
HALT mode, initializes a ²warm reset² only when the pro-
gram counter and SP are reset to zero. To clear the con-
tents of the WDT (including the WDT prescaler ), three
methods are adopted; external reset (a low level to RE-
SET), software instruction(s), or a ²HALT² instruction.
There are two types of software instructions; ²CLR
WDT² and ²CLR WDT1/CLR WDT2². Of these two
types of instruction, only one can be active depending
on the mask option - ²CLR WDT times selection option².
If the ²CLR WDT² is selected (ie. CLR WDT times equal
one), any execution of the ²CLR WDT² instruction will
clear the WDT. In case ²CLR WDT1² and ²CLR WDT2²
are chosen (ie. CLRWDT times equal two), these two in-
structions must be executed to clear the WDT; otherwise,
the WDT may reset the chip because of the time-out.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
·
·
·
RESET reset during normal operation
RESET reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm reset
that just resets the program counter and SP, leaving the
Rev. 1.70
11
December 26, 2005
HT82K68A
other circuits to remain in their original state. Some reg-
isters remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem powers up or when it awakes from the HALT state.
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RESET pin, the SST delay is disabled.
Any wake-up from HALT will enable the SST delay.
TO PDF
RESET Conditions
RESET reset during power-up
RESET reset during normal operation
RESET wake-up HALT
0
u
0
1
1
0
u
1
u
1
The functional unit chip reset status is shown below.
Program Counter
Prescaler
000H
Clear
WDT time-out during normal operation
WDT wake-up HALT
Clear. After master reset,
WDT begins counting
WDT
Note: ²u² means ²unchanged²
Timer Counter
Input/Output Ports
Stack Pointer
Off
V
D
D
Input mode
t
S S T
R
E
S
E
T
Points to the top of the stack
S
S
T
T
i
m
e
-
o
u
t
Timer Counter
C
h
i
p
R
e
s
e
t
A timer counter (TMR) is implemented in the
HT82K68A. The timer counter contains an 8-bit pro-
grammable count-up counter and the clock may come
from the system clock divided by 4.
Reset Timing Chart
V
D
D
Using the internal instruction clock, there is only one ref-
erence time-base.
R
E
S
E
T
There are two registers related to the timer counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the start-
ing value be placed in the timer counter preload register
and reading TMR gets the contents of the timer counter.
The TMRC is a timer counter control register, which de-
fines some options.
Reset Circuit
In the timer mode, once the timer counter starts count-
ing, it will count from the current contents in the timer
counter to FFH. Once overflow occurs, the counter is re-
loaded from the timer counter preload register and gen-
erates the interrupt request flag (TF; bit 5 of INTC) at the
same time.
H
A
L
T
W
a
r
m
R
e
s
e
t
W
D
T
W
D
T
T
i
m
e
-
o
u
t
R
e
s
e
t
R
E
S
E
T
C
o
l
d
S
S
T
R
e
s
e
t
1
0
-
s
t
a
g
e
O
S
C
1
R
i
p
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C
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n
t
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r
P
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-
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n
D
e
t
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c
t
i
o
n
Reset Configuration
Bits
Label
¾
Function
0~3, 5
4
Unused bit, read as "0"
TON
To enable/disable timer counting (0= disabled; 1= enabled)
10= Timer mode (internal clock)
TM0
TM1
6
7
TMRC (0EH) Register
Rev. 1.70
12
December 26, 2005
HT82K68A
D
R
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l
a
B
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C
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4
T
M
1
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T
M
0
T
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W
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O
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f
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T
O
N
Timer Counter
To enable the counting operation, the timer ON bit
(TON; bit 4 of TMRC) should be set to 1. In the case of
timer counter OFF condition, writing data to the timer
counter preload register will also reload that data to the
timer counter. But if the timer counter is turned on,
data written to it will only be kept in the timer counter
preload register. The timer counter will still operate until
overflow occurs. When the timer counter (reading TMR) is
read, the clock will be blocked to avoid errors. As clock
blocking may results in a counting error, this must be taken
into consideration by the programmer.
The state of the registers is summarized in the following table:
Reset
(Power On)
WDT Time-out RESET Reset
(Normal Operation) (Normal Operation)
RESET Reset
(HALT)
WDT Time-out
(HALT)
Register
TMR
xxxx xxxx
00-0 1---
uuuu uuuu
00-0 1---
uuuu uuuu
00-0 1---
uuuu uuuu
00-0 1---
uuuu uuuu
uu-u u---
TMRC
Program
Counter
000H
000H
000H
000H
000H*
MP0
MP1
ACC
TBLP
TBLH
STATUS
INTC
WDTS
PA
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
--00 xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--1u uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---1 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--uu uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---1 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--01 uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---1 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--11 uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
-000 0000
0000 0111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---1 1111
PAC
PB
PBC
PC
PCC
PD
PDC
PE
PEC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
Note:
²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Rev. 1.70
13
December 26, 2005
HT82K68A
Input/Output Ports
After a chip reset, these input/output lines stay at high
levels or floating (mask option). Each bit of these in-
put/output latches can be set or cleared by the ²SET
[m].i² or ²CLR [m].i² (m=12H, 14H, 16H, 18H or 1AH) in-
struction.
There are 32 bidirectional input/output lines in the
HT82K68A, labeled from PA to PE, which are mapped to
the data memory of [12H], [14H], [16H], [18H] and [1AH]
respectively. All these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction MOV A,[m] (m=12H, 14H, 16H,
18H or 1AH). For output operation, all data is latched and
remains unchanged until the output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, the ²SET [m].i², ²CLR
[m].i², ²CPL [m]² and ²CPLA [m]² instructions read the
entire port states into the CPU, execute the defined op-
erations (bit-operation), and then write the results back
to the latches or the accumulator.
Each I/O line has its own control register (PAC, PBC, PCC,
PDC, PEC) to control the input/output configuration. With
this control register, CMOS output or Schmitt trigger input
with or without pull-high resistor (mask option) structures
can be reconfigured dynamically (i.e., on-the-fly) under
software control. To function as an input, the correspond-
ing latch of the control register must write ²1². The
pull-high resistance will exhibit automatically if the
pull-high option is selected. The input source(s) also de-
pend(s) on the control register. If the control register bit is
²1², input will read the pad state. If the control register bit is
²0², the contents of the latches will move to the internal
bus. The latter is possible in ²read-modify-write² instruc-
tion. For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H, 15H,
17H, 19H and 1BH.
Each line of port A and port C [0:3] has the capability to
wake-up the device.
PC2 is shared with the external interrupt pin, PE2~PE4
is defined as CMOS output pins only. PE0 can deter-
mine whether the high to low transition, or the low to
high transition of PC2 to activate the external subrou-
tine, when PE0 output high, the low to high transition of
PC2 to trigger the external subroutine, when PE0 output
low, the high to low transition of PC2 to trigger the exter-
nal subroutine.
PE2~PE4 is configured as CMOS output only and is
used to drive the LED. PC0, PC1 is configured as
NMOS open drain output with 4.6kW pull-high resistor
such that it can easy to use as DATA or CLOCK line of
PS2 keyboard application.
D
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Input/Output Ports
Rev. 1.70
14
December 26, 2005
HT82K68A
The relationship between VDD and VLVR is shown below.
Low Voltage Reset - LVR
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR such as changing a battery, the LVR will au-
tomatically reset the device internally.
V
D
D
V
O P R
5
.
5
V
5
.
5
V
V
L
V
R
The LVR includes the following specifications:
2
.
4
V
·
The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
2
.
2
V
0
.
9
V
·
The LVR uses the ²OR² function with the external
RES signal to perform chip reset.
VOPR is the voltage range for proper chip opera-
tion at 4MHz system clock.
Note:
V
D
D
5
.
5
V
L
V
R
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*
1
*
2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the
reset mode.
Rev. 1.70
15
December 26, 2005
HT82K68A
Mask Option
The following shows five kinds of mask option in the HT82K68A. All the mask options must be defined to ensure proper
system function.
No.
Mask Option
OSC type selection. This option is to decide if an RC or Crystal oscillator is chosen as system clock. If the
Crystal oscillator is selected, the XST (Crystal Start-up Timer) default is activated, otherwise the XST is dis-
abled.
1
WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable
the WDT.
2
3
4
CLRWDT times selection. This option defines the way to clear the WDT by instruction. ²One time² means
that the ²CLR WDT² instruction can clear the WDT. ²Two times² means only if both of the ²CLR WDT1² and
²CLR WDT2² instructions have been executed, only then will the WDT be cleared.
Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA and PC [0:3] only)
all have the capability to wake-up the chip from a HALT.
Pull-high selection. This option is to decide whether the pull-high resistance is visible or not in the input mode
of the I/O ports. Each bit of an I/O port can be independently selected.
5
6
7
LVR enable/disable. User can configure whether enable or disable the circuit by configuration option.
Input type selection. The input type can select inverter or Schmitt by mask option (for OTP version, only
Schmitt input type can used)
Application Circuits
R
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1
2
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4
5
6
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Rev. 1.70
16
December 26, 2005
HT82K68A
Instruction Set Summary
Mnemonic
Instruction
Cycle
Flag
Affected
Description
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
Add data memory to ACC
1
1(1)
1
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
Add ACC to data memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add data memory to ACC with carry
1
1(1)
Add ACC to data memory with carry
Subtract immediate data from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Subtract data memory from ACC
1
1(1)
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1(1)
Logic Operation
AND A,[m]
OR A,[m]
AND data memory to ACC
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
OR data memory to ACC
XOR A,[m]
ANDM A,[m]
ORM A,[m]
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
1
1(1)
1(1)
1(1)
1
XORM A,[m] Exclusive-OR ACC to data memory
AND A,x
OR A,x
AND immediate data to ACC
OR immediate data to ACC
1
XOR A,x
CPL [m]
CPLA [m]
Exclusive-OR immediate data to ACC
Complement data memory
1
1(1)
Complement data memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment data memory with result in ACC
1
Z
Z
Z
Z
Increment data memory
1(1)
DECA [m]
DEC [m]
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
Rotate
RRA [m]
RR [m]
Rotate data memory right with result in ACC
Rotate data memory right
1
1(1)
1
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
1(1)
C
1
None
None
C
1(1)
1
RLCA [m]
RLC [m]
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1(1)
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Rev. 1.70
17
December 26, 2005
HT82K68A
Instruction
Cycle
Flag
Affected
Mnemonic
Branch
Description
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if data memory is zero
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
Miscellaneous
NOP
No operation
1
1(1)
1(1)
1
None
None
CLR [m]
Clear data memory
SET [m]
Set data memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1
1(1)
1
None
1
TO,PDF
Note: x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2): If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(1) and (2)
(3)
:
(4): The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
Rev. 1.70
18
December 26, 2005
HT82K68A
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
Rev. 1.70
19
December 26, 2005
HT82K68A
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
Operation
The contents of the specified data memory are cleared to 0.
[m] ¬ 00H
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.70
20
December 26, 2005
HT82K68A
CLR [m].i
Clear bit of data memory
Description
Operation
The bit i of the specified data memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
0
PDF
0
OV
Z
AC
C
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
0*
PDF
0*
OV
Z
AC
C
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
0*
PDF
0*
OV
Z
AC
C
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.70
21
December 26, 2005
HT82K68A
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Operation
Data in the specified data memory is decremented by 1.
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.70
22
December 26, 2005
HT82K68A
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
0
PDF
1
OV
Z
AC
C
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Operation
Data in the specified data memory is incremented by 1
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Description
Operation
Move data memory to the accumulator
The contents of the specified data memory are copied to the accumulator.
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.70
23
December 26, 2005
HT82K68A
MOV A,x
Move immediate data to the accumulator
Description
Operation
The 8-bit data specified by the code is loaded into the accumulator.
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
Program Counter ¬ Program Counter+1
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.70
24
December 26, 2005
HT82K68A
RET
Return from subroutine
Description
Operation
Affected flag(s)
The program counter is restored from the stack. This is a 2-cycle instruction.
Program Counter ¬ Stack
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
Operation
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.70
25
December 26, 2005
HT82K68A
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
Operation
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
Rev. 1.70
26
December 26, 2005
HT82K68A
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.70
27
December 26, 2005
HT82K68A
SET [m]
Set data memory
Description
Operation
Each bit of the specified data memory is set to 1.
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Operation
Bit i of the specified data memory is set to 1.
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.70
28
December 26, 2005
HT82K68A
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.70
29
December 26, 2005
HT82K68A
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Rev. 1.70
30
December 26, 2005
HT82K68A
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 1.70
31
December 26, 2005
HT82K68A
Package Information
20-pin SOP (300mil) Outline Dimensions
2
0
1
1
A
B
1
1
0
C
C
'
G
H
D
a
E
F
Dimensions in mil
Nom.
Symbol
Min.
394
290
14
490
92
¾
Max.
419
300
20
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
510
104
¾
4
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.70
32
December 26, 2005
HT82K68A
28-pin SOP (300mil) Outline Dimensions
2
8
1
5
A
B
1
1
4
C
C
'
G
H
D
a
E
F
Dimensions in mil
Nom.
Symbol
Min.
394
290
14
697
92
¾
Max.
419
300
20
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
713
104
¾
4
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.70
33
December 26, 2005
HT82K68A
48-pin SSOP (300mil) Outline Dimensions
4
8
2
2
5
4
A
B
1
C
C
'
G
H
D
a
E
F
Dimensions in mil
Nom.
Symbol
Min.
395
291
8
Max.
420
299
12
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
25
¾
¾
¾
¾
613
85
¾
637
99
¾
4
10
G
H
a
25
4
35
12
0°
8°
Rev. 1.70
34
December 26, 2005
HT82K68A
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SOP 20W
Symbol
Description
Dimensions in mm
A
B
Reel Outer Diameter
Reel Inner Diameter
330±1.0
62±1.5
13.0+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2.0±0.5
24.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
SOP 28W (300mil)
Symbol
Description
Reel Outer Diameter
Reel Inner Diameter
Dimensions in mm
330±1.0
A
B
62±1.5
13.0+0.5
-0.2
C
D
Spindle Hole Diameter
Key Slit Width
2.0±0.5
24.8+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
30.2±0.2
Rev. 1.70
35
December 26, 2005
HT82K68A
SSOP 48W
Symbol
Description
Reel Outer Diameter
Dimensions in mm
A
B
330±1.0
100±0.1
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
13.0+0.5
-0.2
C
D
2.0±0.5
32.2+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
38.2±0.2
Rev. 1.70
36
December 26, 2005
HT82K68A
Carrier Tape Dimensions
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
SOP 20W
Symbol
Description
Dimensions in mm
24.0+0.3
-0.1
W
Carrier Tape Width
P
E
Cavity Pitch
12.0±0.1
1.75±0.1
11.5±0.1
1.5+0.1
1.5+0.25
4.0±0.1
2.0±0.1
10.8±0.1
13.3±0.1
3.2±0.1
0.3±0.05
21.3
Perforation Position
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
SOP 28W (300mil)
Symbol
Description
Carrier Tape Width
Cavity Pitch
Dimensions in mm
24.0±0.3
12.0±0.1
1.75±0.1
11.5±0.1
1.5+0.1
W
P
E
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
F
D
D1
P0
P1
A0
B0
K0
t
1.5+0.25
4.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
10.85±0.1
18.34±0.1
2.97±0.1
0.35±0.01
21.3
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
Rev. 1.70
37
December 26, 2005
HT82K68A
P
0
P
1
t
D
E
F
B
0
W
C
K
1
D
1
P
K
2
A
0
SSOP 48W
Symbol
Description
Dimensions in mm
32.0±0.3
16.0±0.1
1.75±0.1
14.2±0.1
2.0 Min.
W
P
Carrier Tape Width
Cavity Pitch
E
Perforation Position
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
D1
P0
P1
A0
B0
K1
K2
t
1.5+0.25
4.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
12.0±0.1
16.20±0.1
2.4±0.1
Cavity Width
Cavity Depth
Cavity Depth
3.2±0.1
Carrier Tape Thickness
Cover Tape Width
0.35±0.05
25.5
C
Rev. 1.70
38
December 26, 2005
HT82K68A
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.70
39
December 26, 2005
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