HT82K74EE [HOLTEK]
27MHz Keyboard/ Mouse TX 8-Bit MCU; 27MHz的键盘/鼠标TX 8位MCU
| 型号： | HT82K74EE |
| 厂家： | 
HOLTEK SEMICONDUCTOR INC |
| 描述： | 27MHz Keyboard/ Mouse TX 8-Bit MCU |
| 文件： | 总56页 (文件大小：329K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT82K74E/HT82K74EE
27MHz Keyboard/ Mouse TX 8-Bit MCU
Technical Document
·
Application Note
-
HA0075E MCU Reset and Oscillator Circuits Application Note
Features
·
·
·
Operating voltage:
SYS= 27MHz: 3.0V~3.3V for crystal mode
128´8 bits data EEPROM for HT82K74EE
f
One external crystal (27MHz) to supply
microcontroller system clock
·
·
·
·
·
Program Memory: 2K´15 bits
Data Memory: 96´8 bits
·
·
63 powerful instructions
All instructions executed in one or two machine
cycles
36 bidirectional I/O lines, with pull-high options
Watchdog Timer function
·
·
Low voltage reset function
Single 16-bit internal timer with overflow interrupt
and timer input
Crystal oscillator which built-in capacitor value can
configure by firmwave OSCC register
·
Power down and wake-up functions to reduce
power consumption
·
·
Two bit to define microcontroller system clock
(fSYS/1, fSYS/4, fSYS/8, fSYS/16)
·
·
·
·
4-level subroutine nesting
Bit manipulation instruction
Table read instructions
HT82K74E:
28-pin SSOP, 32-pin QFN and
48-pin SSOP/LQFP packages
Built-in DC/DC to provide stable (2.8V, 3.0V, 3.3V
use configuration option) DC_DC 3.0V with error
±0.1V
·
HT82K74EE:
28-pin SSOP and 48-pin SSOP/LQFP packages
·
2.2V/2.0V with ± 0.1V tolerance or 1.8V Low battery
detector with internal bit set, it detects the BAT-in
input voltage
General Description
The device is an 8-bit high performance, RISC architec-
ture microcontroller devices specifically designed for
multiple I/O control product applications.
There are two dice in the HT82K74EE package: one is
the HT82K74E MCU, the other is a 128´8 bits EEPROM
used for data memory purpose. The two dice are
wire-bonded to form HT82K74EE
The advantages of low power consumption, I/O flexibil-
ity, timer functions, Power Down and wake-up functions,
Watchdog timer, motor driving, industrial control, con-
sumer products, subsystem controllers, etc.
Block Diagram
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Rev. 1.00
1
December 15, 2009
HT82K74E/HT82K74EE
Pin Assignment
P
P
P
P
P
P
B
A
A
A
A
A
0
7
6
5
4
3
P
P
P
P
P
P
P
L
V
B
V
R
V
O
O
V
P
P
V
R
P
P
P
P
1
B
B
B
B
B
B
B
P
P
P
P
P
P
B
A
A
A
A
A
0
7
6
5
4
3
P
P
P
P
P
P
P
L
V
B
V
R
V
O
O
V
P
P
V
R
P
P
P
P
B
1
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
2
2
2
2
2
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
1
2
3
4
5
6
7
8
9
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
3
4
5
6
7
B
B
B
B
B
B
2
3
4
5
6
7
P
A
2
/
T
M
R
P
A
2
/
T
M
R
P
P
A
A
1
0
X
P
P
A
A
1
0
X
S
A
D
S
T
L
X
S
A
D
S
T
L
V
S
S
_
I
N
V
S
S
_
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
1
2
3
4
5
6
7
8
9
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
1
1
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
P
P
P
P
P
A
A
A
A
A
7
6
5
4
3
P
P
P
P
L
V
B
V
R
V
O
O
V
R
B
B
B
B
0
1
2
3
P
P
P
P
P
P
P
P
P
P
P
P
C
C
C
C
C
C
C
C
D
D
D
D
7
6
5
4
3
2
1
0
7
6
5
4
D
P
P
P
P
P
P
P
P
P
P
P
P
C
C
C
C
C
C
C
C
D
D
D
D
7
6
5
4
3
2
1
0
7
6
5
4
D
F
_
S
O
U
T
F
_
S
O
S
S
S
S
C
C
1
2
S
S
C
C
1
2
X
P
A
2
/
T
M
R
S
A
D
S
T
L
X
D
E
E
S
D
D
E
E
S
D
P
P
A
A
1
0
1
0
_
I
N
0
1
S
0
1
S
/
/
D
P
P
C
C
F
_
S
O
U
T
0
1
2
3
4
S
E
S
E
S
P
P
D
D
3
2
/
/
Z
Z
B
A
S
S
C
C
1
2
E
E
D
D
2
3
E
E
D
D
2
3
P
P
D
D
1
0
/
/
V
V
B
A
D
D
S
P
P
D
D
3
2
/
/
Z
Z
B
A
0
1
/
/
V
V
A
B
P
P
D
D
3
2
/
/
Z
Z
B
A
0
1
/
/
E
B
H
T
8
2
K
7
4
E
/
H
T
8
2
K
7
4
E
H
E
T
8
2
K
7
4
E
H
T
8
2
K
7
4
E
E
2
8
S
S
O
P
-
A
4
8
S
S
O
P
-
A
4
8
S
S
O
P
-
A
4
8
4
7
4
6
4
5
4
4
4
3
4
1
2
3
4
5
6
7
8
9
1
1
1
3
3
3
3
3
3
3
2
2
2
2
2
6
5
4
3
2
1
0
9
8
7
6
5
P
L
V
B
V
R
V
O
O
V
P
P
B
7
P
A
2
/
T
M
R
P
A
1
0
X
P
A
S
A
D
S
T
L
X
2
2
2
2
5
2
6
3
3
7
3
8
9
0
1
2
V
S
S
_
I
P
A
1
0
5
4
3
2
1
0
V
B
V
R
V
O
O
V
S
A
D
S
T
L
X
1
2
3
4
5
6
7
8
2
2
2
2
2
1
1
1
4
3
2
1
0
9
8
7
P
P
P
P
P
P
P
P
C
C
C
C
C
C
C
C
7
6
5
4
3
2
1
0
D
P
A
_
I
N
P
P
P
P
P
P
C
C
C
C
C
C
F
_
S
O
U
D
H
T
8
2
K
7
4
E
F
E
_
S
O
U
T
4
8
L
Q
F
P
-
A
S
H
T
8
2
K
7
4
S
3
2
Q
F
N
-
A
S
C
1
S
C
1
S
C
2
S
C
2
0
1
2
D
E
E
D
D
D
0
1
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
3
1
4
1
5
1
6
1
7
1
8
1
4
8
4
7
4
6
4
5
4
4
4
3
4
2
4
1
4
0
3
9
3
8
3
7
1
2
3
4
5
6
7
8
9
1
1
1
3
3
3
3
3
3
3
2
2
2
2
2
6
5
4
3
2
1
0
9
8
7
6
5
P
L
V
B
V
R
V
O
O
V
P
P
B
7
P
A
2
/
T
M
R
P
A
1
0
X
P
A
S
A
D
S
T
L
X
V
S
S
_
I
N
P
P
P
P
P
P
P
P
C
C
C
C
C
C
C
C
7
6
5
4
3
2
1
0
D
F
_
S
O
U
T
H
T
8
2
K
7
4
E
E
4
8
L
Q
F
P
-
A
S
S
C
1
S
C
2
0
1
2
D
E
E
D
0
1
/
/
S
D
A
S
C
L
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
Rev. 1.00
2
December 15, 2009
HT82K74E/HT82K74EE
Pin Description
Pin Name I/O
Options
Description
Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up
input (both falling and rising edge) by a configuration option. Software instruc-
tions determine if the pin is a CMOS output or Schmitt Trigger input. Configura-
tion options determine if the pins have pull-high resistors. PA2 is shared with
the external timer input pin TMR.
PA0~PA1
Pull-high
Wake-up
PA2/TMR
PA3~PA7
I/O
I/O
I/O
Bidirectional 8-bit input/output port. Each nibble, PB0~PB3 and PB4~PB7,
pins can be configured as wake-up inputs (both falling and rising edge) by con-
figuration options. Software instructions determine if the pin is a CMOS output
or Schmitt Trigger input. Configuration options determine if the pins have
pull-high resistors.
Pull-high
Wake-up
PB0~PB7
PC0~PC7
Bidirectional 8-bit input/output port. Each nibble, PC0~PC3 and PC4~PC7,
pins can be configured as wake-up inputs (both falling and rising edge) by con-
figuration options. Software instructions determine if the pin is a CMOS output
or Schmitt Trigger input. Configuration options determine if the pins have
pull-high resistors.
Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each nibble, PD0~PD3 and PD4~PD7,
pins can be configured as wake-up inputs (both falling and rising edge) by con-
figuration options. Software instructions determine if the pin is a CMOS output
or Schmitt Trigger input. Configuration options determine if the pins have
pull-high resistors. PD0 and PD1 are shared with the VA and VB pins. PD2 and
PD3 are shared with the ZA and ZB pins.
PD0/VA
PD1/VB
PD2/ZA
PD3/ZB
PD4~PD7
Pull-high
Wake-up
I/O
I/O
Bidirectional 4-bit input/output port. PE0~PE3 pin can be configured as
wake-up inputs (both falling and rising edge) by a configuration option. Soft-
ware instructions determine if the pin is a CMOS output or Schmitt Trigger in-
put. Configuration options determine if the pins have pull-high resistors. For
HT82K74EE PE0 and PE1 are shared with the SDA and SCL lines respec-
tively and not bonded to external pins.
Pull-high
Wake-up
PE0~PE3
OSC1
OSC2
I
OSC1, OSC2 are connected to an external 27MHz crystal/ resonator for the in-
ternal system clock.
¾
O
VSS
Negative power supply, ground
Schmitt trigger reset input. Active low
Positive power supply
Battery input
¾
¾
¾
¾
¾
¾
¾
RES
I
¾
I
VDD
BAT_IN
LX
I
DC/DC LX switch
VSSLX
I
DC/DC ground
Full Power/
Half Power
RF_OUT
O
RF power amplifier output pin
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
I
OL Total ..............................................................150mA
I
OH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
3
December 15, 2009
HT82K74E/HT82K74EE
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
VDD
VOUT
IDD
Operating Voltage
Others
2.0
2.8
¾
3.3
3.3
6
V
V
¾
¾
3
fSYS=27MHz
DC-DC Operating Voltage
¾
No load, fSYS= 27MHz
Operating Current (Crystal OSC) 3V
mA
No load, system HALT
ISTB
VIL1
VIH1
Standby Current
20
¾
¾
¾
¾
0
¾
¾
¾
mA
V
WDT disable, LVR disable
Input Low Voltage for I/O
(Schmitt Trigger)
0.3VDD
VDD
¾
¾
Input High Voltage for I/O
(Schmitt Trigger)
0.7VDD
V
VIL2
VIH2
VLVR
IOL1
IOH1
0.3VDD
VDD
4.0
Input Low Voltage (RES)
Input High Voltage (RES)
Low Voltage Reset
0
0.9VDD
3.5
V
V
¾
¾
¾
¾
¾
¾
¾
3.8
¾
V
¾
V
OL=0.1VDD
OH=0.9VDD
Other I/O Pins Sink Current
Other I/O Pins Source Current
3V
3V
4
mA
mA
¾
V
-2.5
-4.5
¾
Other Pins Internal Pull-high
Resistance
RPH1
3V
10
2
30
50
¾
kW
BAT-in
Input Voltage
2.8
3.3
V
¾
¾
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
fSYS
tRCSYS
tWDT
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
Conditions
System Clock
27
71
MHz
¾
¾
¾
¾
¾
¾
Watchdog OSC Period
3V
ms
Watchdog Time-out Period with
6-stage Prescaler
3V WDTS=1
4.57
ms
¾
¾
tSST
tSYS
ms
ms
ms
System Start-up Timer Period
Crystal Setup
1024
10
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
tOSTSETUP
tLVR
Low Voltage Width to Reset
External Reset Low Pulse Width
0.25
10
1.00
¾
2.00
¾
tRES
Note: tSYS=1/fSYS
Rev. 1.00
4
December 15, 2009
HT82K74E/HT82K74EE
RF Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ. Max. Unit
VDD
Conditions
dBm
dBm
PWRAMP option selected Half
PWRAMP option selected Full
¾
¾
-3
¾
¾
Maximum Output Power
PRF
¾
(Load impedance is 50W)
0
20dB Bandwidth for Modulated
Carrier (3Kbps)
PBW
PRF1
PRF2
6
kHz
dBm
dBm
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
1st Adjacent Channel Transmit
Power 50kHz
¾
¾
-30
-40
2nd Adjacent Channel Transmit
Power 100kHz
DC_AC Power-on Reset AC/DC Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
2.0V~
3.3V
IPOR
Operating Current
0.7
¾
¾
¾
0.05
0.9
2
¾
¾
¾
¾
¾
mA
V/ms
V
VDD Rise Rate to Ensure Power-on
Reset
Without 0.1mF between
RSR_POR
VPOR_MAX
¾
¾
VDD and VSS
Maximum VDD Start Voltage to
Ensure Power-on Reset
Without 0.1mF between
1.5
¾
VDD and VSS
Without 0.1mF between
ms
ms
VDD and VSS
tPOR
Power-on Reset Low Pulse Width
¾
With 0.1mF between
10
¾
V
DD and VSS
Rev. 1.00
5
December 15, 2009
HT82K74E/HT82K74EE
EEPROM A.C. Characteristics
Ta=25°C
Standard Mode*
Unit
Symbol
Parameter
Clock Frequency
Remark
Min.
Max.
100
¾
fSK
kHz
ns
¾
¾
¾
¾
¾
¾
tHIGH
tLOW
tr**
Clock High Time
4000
4700
¾
Clock Low Time
ns
¾
SDA and SCL Rise Time
SDA and SCL Fall Time
1000
300
ns
tf**
ns
¾
After this period the first clock
pulse is generated
tHD:STA
START Condition Hold Time
START Condition Setup Time
4000
4000
ns
ns
¾
¾
Only relevant for repeated
START condition
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tAA
Data Input Hold Time
0
ns
ns
ns
ns
¾
¾
¾
¾
¾
¾
Data Input Setup Time
STOP Condition Setup Time
Output Valid from Clock
200
4000
¾
¾
3500
Time in which the bus must be free be-
fore a new transmission can start
tBUF
Bus Free Time
4700
ns
¾
Input Filter Time Constant
(SDA and SCL Pins)
tSP
Noise suppression time
100
5
ns
¾
¾
tWR
Write Cycle Time
ms
¾
Note: These parameters are periodically sampled but not 100% tested
²*² The standard mode means VDD=2.2V to 3.3V
²**² For related timing, refer to timing diagrams in the EEPROM Data Memory section
Rev. 1.00
6
December 15, 2009
HT82K74E/HT82K74EE
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the inter-
nal system architecture. The devices take advantage of
the usual features found within RISC microcontrollers
providing increased speed of operation and enhanced
performance. The pipelining scheme is implemented in
such a way that instruction fetching and instruction exe-
cution are overlapped, hence instructions are effectively
executed in one cycle, with the exception of branch or
call instructions. An 8-bit wide ALU is used in practically
all operations of the instruction set. It carries out arith-
metic operations, logic operations, rotation, increment,
decrement, branch decisions, etc. The internal data
path is simplified by moving data through the Accumula-
tor and the ALU. Certain internal registers are imple-
mented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea-
tures ensure that a minimum of external components is
required to provide a functional I/O control system with
maximum reliability and flexibility.
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive in-
struction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. It must be
noted that only the lower 8 bits, known as the Program
Counter Low Register, are directly addressable by user.
Clocking and Pipelining
The main system clock, derived from either a Crys-
tal/Resonator or RC oscillator is subdivided into four in-
ternally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
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Instruction Fetching
Rev. 1.00
7
December 15, 2009
HT82K74E/HT82K74EE
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For condi-
tional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is dis-
carded and a dummy cycle takes its place while the cor-
rect instruction is obtained.
After a device reset, the Stack Pointer will point to the
top of the stack.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the ac-
knowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine in-
struction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writeable regis-
ter. By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be in-
serted.
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The lower byte of the Program Counter is fully accessi-
ble under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
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Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic op-
erations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related in-
struction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or oper-
ations may result in carry, borrow or other status
changes, the status register will be correspondingly up-
dated to reflect these changes. The ALU supports the
following functions:
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 4 levels and is neither part of the data nor part
of the program space, and is neither readable nor
writeable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writeable. At a
subroutine call or interrupt acknowledge signal, the con-
tents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, sig-
naled by a return instruction, RET or RETI, the Program
Counter is restored to its previous value from the stack.
·
Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
Program Counter Bits
Mode
b10
0
b9
0
b8
0
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
Initial Reset
Timer/Event Counter Overflow
Skip
0
0
0
0
0
0
0
1
0
0
0
Program Counter + 2
Loading PCL
PC10 PC9 PC8
@7
#7
@6
#6
@5
#5
@4
#4
@3
#3
@2
#2
@1
#1
@0
#0
Jump, Call Branch
Return from Subroutine
#10
S10
#9
S9
#8
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: PC10~PC8: Current Program Counter bits
@7~@0: PCL bits
#10~#0: Instruction code address bits
S10~S0: Stack register bits
Rev. 1.00
8
December 15, 2009
HT82K74E/HT82K74EE
·
·
·
·
Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
Location 008H
This vector is used by the timer/event counter. If a
counter overflow occurs, the program will jump to this
location and begin execution if the timer interrupt is
enabled and the stack is not full.
Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
·
·
Increment and Decrement INCA, INC, DECA, DEC
Table location
Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Any location in the program memory can be used as
look-up tables. There are three methods to read the
ROM data by two table read instructions: ²TABRDC²
and ²TABRDL², transfer the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H).
Program Memory
The Program Memory is the location where the user
code or program is stored. The device is supplied with
One-Time Programmable, OTP, memory where users
can program their application code into the device. By
using the appropriate programming tools, OTP devices
offer users the flexibility to freely develop their applica-
tions which may be useful during debug or for products
requiring frequent upgrades or program changes. OTP
devices are also applicable for use in applications that
require low or medium volume production runs.
¨
The three methods are shown as follows: The in-
structions ²TABRDC [m]² (the current page, one
page=256words), where the table locations is de-
fined by TBLP (07H) in the current page. And the
TBHP function selected via a configuration option is
disabled (default).
¨
The instruction ²TABRDC [m]², where the table lo-
cation is defined by registers TBLP (07H) and
TBHP (01FH). And the TBHP function selected via
a configuration option is enabled.
Structure
¨
The Program Memory has a capacity of 2K´15 bits. The
Program Memory is addressed by the Program Counter
and also contains data, table information and interrupt
entries. Table data, which can be setup in any location
within the Program Memory, is addressed by separate
table pointer registers.
The instructions ²TABRDL [m]², where the table lo-
cations is defined by Registers TBLP (07H) in the
last page (700H~7FFH).
Only the destination of the lower-order byte in the ta-
ble is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the re-
maining 1-bit words are read as 0. The Table
Higher-order byte register (TBLH) is read only. The ta-
ble pointer (TBLP, TBHP) is a read/write register (07H,
1FH), which indicates the table location. Before ac-
cessing the table, the location must be placed in the
TBLP and TBHP (If the TBHP function selected via a
configuration option is disabled, the value in TBHP
has no effect). The TBLH is read only and cannot be
restored. If the main routine and the ISR (Interrupt
Service Routine) both employ the table read instruc-
tion, the contents of the TBLH in the
0
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main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main rou-
tine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt
should be disabled prior to the table read instruction. It
will not be enabled until the TBLH has been backed
up. All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending on the require-
ments.
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Program Memory Structure
Special Vectors
Once TBHP is enabled, the instruction ²TABRDC [m]²
reads the ROM data as defined by TBLP and TBHP
value. Otherwise, the TBHP function selected via a
configuration option is disabled, the instruction
²TABRDC [m]² reads the ROM data as defined by
TBLP and the current program counter bits.
Within the Program Memory, certain locations are re-
served for special usage such as reset and interrupts.
·
Location 000H
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated,
the program will jump to this location and begin execu-
tion.
Rev. 1.00
9
December 15, 2009
HT82K74E/HT82K74EE
Table Location Bits
Instruction
b10
TABRDC[m] PC10
TABRDL[m]
b9
PC9
1
b8
PC8
1
b7
@7
@7
b6
@6
@6
b5
@5
@5
b4
@4
@4
b3
@3
@3
b2
@2
@2
b1
@1
@1
b0
@0
@0
1
Table Location
Note: PC10~PC8: Current program counter bits when TBHP is disabled
TBHP register bit2~bit0 when TBHP is enabled
@7~@0: Table Pointer TBLP bits
Table Program Example
ble will be at the Program Memory address ²706H² or 6
locations after the start of the last page. Note that the
value for the table pointer is referenced to the first ad-
dress of the present page if the ²TABRDC [m]² instruc-
tion is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]² in-
struction is executed.
The following example shows how the table pointer and
table data is defined and retrieved from the
microcontroller. This example uses raw table data lo-
cated in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²700H² which refers to the start address of the last page
within the 2K Program Memory of device. The table
pointer is setup here to have an initial value of ²06H².
This will ensure that the first data read from the data ta-
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Table Read - TBLP/TBHP
Table Read - TBLP only
Rev. 1.00
10
December 15, 2009
HT82K74E/HT82K74EE
tempreg1
tempreg2
db
db
:
?
?
; temporary register #1
; temporary register #2
:
mov
mov
a,06h
; initialise table pointer - note that this address
; is referenced
tblp,a
; to the last page or present page
:
:
tabrdl
tempreg1
; transfers value in table referenced by table pointer
; to tempregl
; data at prog. memory address ²706H² transferred to
; tempreg1 and TBLH
dec
tblp
; reduce value of table pointer by one
tabrdl
tempreg2
; transfers value in table referenced by table pointer
; to tempreg2
; data at prog.memory address ²705H² transferred to
; tempreg2 and TBLH
; in this example the data ²1AH² is transferred to
; tempreg1 and data ²0FH² to register tempreg2
; the value ²00H² will be transferred to the high byte
; register TBLH
:
:
org
dc
700h
; sets initial address of last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection
if both the main routine and Interrupt Service Routine use the table read instructions. If using the table read instructions,
the Interrupt Service Routines may change the value of TBLH and subsequently cause errors if used again by the main
routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However,
in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete
their operation.
Rev. 1.00
11
December 15, 2009
HT82K74E/HT82K74EE
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary in-
formation is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to di-
rectly under program control, however, some remain
protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All
locations within this area are read and write accessible
under program control.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writeable but some are protected and are readable only,
the details of which are located under the relevant Spe-
cial Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H².
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
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H
H
H
H
H
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I
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Structure
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at con-
secutive locations. All are implemented in RAM and are
8-bit wide. The start address of the Data Memory for all
devices is the address ²00H². Registers which are com-
mon to all microcontrollers, such as ACC, PCL, etc.,
have the same Data Memory address.
A
C
C
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B
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Data Memory Structure
P
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1
C
H
W
S
R
Note: Most of the Data Memory bits can be directly
manipulated using the ²SET [m].i² and ²CLR
[m].i² with the exception of a few dedicated bits.
The Data Memory can also be accessed
through the memory pointer register, MP.
1
D
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1
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B
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P
1
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2
2
0
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General Purpose Data Memory
r
e
a
d
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(
9
6
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s
)
9
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H
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user pro-
gram for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions, individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
Special Purpose Data Memory Structure
Rev. 1.00
12
December 15, 2009
HT82K74E/HT82K74EE
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control. The
location of these registers within the Data Memory be-
gins at the address 00H. Any unused Data Memory lo-
cations between these special function registers and the
point where the General Purpose Memory begins is re-
served and attempting to read data from these locations
will return a value of 00H.
stead of the usual direct memory addressing method
where the actual memory address is defined. Any ac-
tions on the IAR register will result in corresponding
read/write operations to the memory location specified
by the Memory Pointer MP. Reading the IAR register in-
directly will return a result of ²00H² and writing to the
register indirectly will result in no operation.
Memory Pointer - MP
One Memory Pointer, known as MP, is physically imple-
mented in the Data Memory. The Memory Pointer can
be written to and manipulated in the same way as nor-
mal registers providing an easy way of addressing and
tracking data. When using any operation on the indirect
addressing register IAR, it is actually the address speci-
fied by the Memory Pointer that the microcontroller will
be directed to.
Indirect Addressing Registers - IAR
The IAR register, located at Data Memory address
²00H², is not physically implemented. This special regis-
ter allows what is known as indirect addressing, which
permits data manipulation using a Memory Pointer in-
data .section ¢data¢
adres1
adres2
adres3
adres4
block
db ?
db ?
db ?
db ?
db ?
code .section at 0 ¢code¢
org 00h
start:
mov a,04h
mov block,a
mov a,offset adres1; Accumulator loaded with first RAM address
; setup size of block
mov mp,a
; setup memory pointer with first RAM address
loop:
clr IAR
inc mp
sdz block
jmp loop
; clear the data at address defined by MP
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific Data Memory ad-
dresses.
Rev. 1.00
13
December 15, 2009
HT82K74E/HT82K74EE
Accumulator - ACC
Otherwise, the TBHP function selected via a configura-
tion option is disabled, the instruction ²TABRDC [m]²
reads the ROM data as defined by TBLP and the current
program counter bits.
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system manage-
ment flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera-
tions related to the status register may give different re-
sults due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² in-
struction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to pro-
grammers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily imple-
mented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory lo-
cation, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are per-
mitted. When such operations are used, note that a
dummy cycle will be inserted.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
·
C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place dur-
ing a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
Look-up Table Registers - TBLP, TBLH, TBHP
·
AC is set if an operation results in a carry out of the
These three special function registers are used to con-
trol operation of the look-up table which is stored in the
Program Memory. TBLP is the table pointer and indi-
cates the location where the table data is located. Its
value must be setup before any table read commands
are executed. Its value can be changed, for example us-
ing the ²INC² or ²DEC² instructions, allowing for easy ta-
ble data pointing and reading. TBLH is the location
where the high order byte of the table data is stored after
a table read data instruction has been executed. Note
that the lower order table data byte is transferred to a
user defined location. Once TBHP is enabled, the in-
struction ²TABRDC [m]² reads the ROM data as defined
by TBLP and TBHP value.
low nibbles in addition, or no borrow from the high nib-
ble into the low nibble in subtraction; otherwise AC is
cleared.
·
Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
·
OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
·
PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
·
TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
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Status Register
Rev. 1.00
14
December 15, 2009
HT82K74E/HT82K74EE
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt rou-
tine can change the status register, precautions must be
taken to correctly save it.
there is an associated control register labeled PAC,
PBC, PCC, PDC, PEC also mapped to specific ad-
dresses with the Data Memory. The control register
specifies which pins of that port are set as inputs and
which are set as outputs. To setup a pin as an input, the
corresponding bit of the control register must be set
high, for an output it must be set low. During program , it
is important to first setup the control registers to specify
which pins are outputs and which are inputs before
reading data from or writing data to the I/O ports. One
flexible feature of these registers is the ability to directly
program single bits using the ²SET [m].i² and ²CLR
[m].i² instructions. The ability to change I/O pins from
output to input and vice versa by manipulating specific
bits of the I/O control registers during normal program
operation is a useful feature of these devices.
Interrupt Control Registers - INTC
The microcontroller provides an internal timer/event
counter overflow interrupt. By setting various bits within
this register using standard bit manipulation instruc-
tions, the enable/disable function of each interrupt can
be independently controlled. Amaster interrupt bit within
this register, the EMI bit, acts like a global enable/dis-
able and is used to set all of the interrupt enable bits on
or off. This bit is cleared when an interrupt routine is en-
tered to disable further interrupt and is set by executing
the ²RETI² instruction.
EEPROM Data Memory
An area of EEPROM, which stands for Electrically Eras-
able Programmable Read Only Memory, is contained
within the device. This type of memory is non-volatile
with data retention even after power is removed. This
type of memory is useful for storing information such as
product identification numbers, calibration values, user
data, system setup data etc.
Timer/Event Counter Registers -
TMRH, TMRL, TMRC
All devices possess a single internal 16-bit count-up
timer. An associated register pair known as
TMRL/TMRH is the location where the timer 16-bit value
is located. This register can also be preloaded with fixed
data to allow different time intervals to be setup. An as-
sociated control register, known as TMRC, contains the
setup information for this timer, which determines in
what mode the timer is to be used as well as containing
the timer on/off control function.
EEPROM Memory Structure
The EEPROM has a capacity is 128 organised into a
structure of 8-bit words. The EEPROM is an IIC type de-
vice and therefore operates using a two wire serial bus.
Watchdog Timer Register - WDTS
Accessing the EEPROM Data Memory
The Watchdog function in the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows.To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ra-
tios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate divi-
sion ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set divi-
sion ratios between 1 and 128.
The two IIC lines are the Serial Clock line, SCL, and the
Serial Data line SDA. The SDA pin is shared with I/O pin
PE0, while the SCL pin is connected to internal I/O PE1.
Normal I/O control software instructions for PE0 and
PE1 are used to control read and write operations on the
EEPROM.
·
Serial data - SDA
The SDA line is the bidirectional EEPROM serial data
line which is shared with pin PE0.
If it is transfer data must be output mode, and it re-
ceive data should be set input mode and select pull
high resistor by option.
·
Serial data - SCL
The SCL line is the EEPROM serial clock input line
which is shared with internal I/O PE1. The SCL input
clocks data into the EEROM on its positive edge and
clocks data out of the EEPROM on its negative edge.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC, PD and PE.
These labeled I/O registers are mapped to specific ad-
dresses within the Data Memory as shown in the Data
Memory table, which are used to transfer the appropri-
ate output or input data on that port. With each I/O port
·
Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted
as a START or STOP condition.
Rev. 1.00
15
December 15, 2009
HT82K74E/HT82K74EE
·
·
Start condition
Write Operations
A high-to-low transition of SDA with SCL high will be
interpreted as a start condition which must precede
any other command - refer to the Start and Stop Defi-
nition Timing diagram.
·
Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledg-
ment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing de-
vice, must terminate the write sequence with a stop
condition. At this time the EEPROM enters an inter-
nally-timed write cycle to the non-volatile memory. All
inputs are disabled during this write cycle and
EEPROM will not respond until the write cycle is com-
pleted. Refer to Byte write timing diagram.
Stop condition
A low-to-high transition of SDA with SCL high will be
interpreted as a stop condition. After a read se-
quence, the stop command will place the EEPROM in
a standby power mode - refer to Start and Stop Defini-
tion Timing Diagram.
·
Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has re-
ceived each word. This happens during the ninth clock
cycle.
·
Acknowledge polling
To maximise bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write com-
mand have been sent. If the device is still busy imple-
menting its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
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Read operations
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The data EEPROM supports three read operations,
namely, current address read, random address read
and sequential read. During read operation execution,
the read/write select bit should be set to ²1².
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Device Addressing
Current address read
All EEPROM devices require an 8-bit device address
word following a start condition to enable the EEPROM
for read or write operations. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits. Refer to the diagram showing
the Device Address. This is common to all the EEPROM
devices. The next three bits are all zero bits.
The internal data word address counter maintains the
last address accessed during the last read or write op-
eration, incremented by one. This address stays valid
between operations as long as the EEPROM power is
maintained. The address will roll over during a read
from the last byte of the last memory page to the first
byte of the first page. Once the device address with
the read/write select bit set to one is clocked in and ac-
knowledged by the EEPROM, the current address
data word is serially clocked out. The microcontroller
should respond a No ACK - High - signal and a follow-
ing stop condition - refer to Current read timing.
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
If the comparison of the device address is successful then
the EEPROM will output a zero as an ACK bit. If not, the
EEPROM will return to a standby state.
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Acknowledge Polling Flow
Rev. 1.00
16
December 15, 2009
HT82K74E/HT82K74EE
·
·
Sequential read
Random read
Arandom read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start con-
dition. The microcontroller now initiates a current ad-
dress read by sending a device address with the
read/write select bit high. The EEPROM acknowl-
edges the device address and serially clocks out the
data word. The microcontroller should respond with a
No ACK signal - high - followed by a stop condition.
Refer to Random read timing.
Sequential reads are initiated by either a current ad-
dress read or a random address read. After the
microcontroller receives a data word, it responds with an
acknowledgment. As long as the EEPROM receives an
acknowledgment, it will continue to increment the data
word address and serially clock out sequential data
words. When the memory address limit is reached, the
data word address will roll over and the sequential read
continues. The sequential read operation is terminated
when the microcontroller responds with a No ACK signal
- high - followed by a stop condition.
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Byte Write Timing
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Current Read Timing
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Random Read Timing
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Sequential Read Timing
Rev. 1.00
17
December 15, 2009
HT82K74E/HT82K74EE
Data EEPROM Timing Diagrams
t
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Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start
condition of sequential command.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of ev-
ery pin fully under user program control, pull-high op-
tions for all ports and Wake-up option for all I/O pins, the
user is provided with an I/O structure to meet the needs
of a wide range of application possibilities.
resulting in power being conserved, a feature that is im-
portant for battery and other low-power applications.
Various methods exist to wake-up the microcontroller,
one of which is to change the logic condition on one of
the port pins from high to low or low to high. After a
HALT instruction forces the microcontroller into the
Power Down Mode, the processor will remain in a
low-power state until the logic condition of the selected
wake-up pin on the port pin changes from high to low or
low to high. This function is especially suitable for appli-
cations that can be woken up via external switches.
Each pin on PA (by bit), PB, PC, PD, PE has the capabil-
ity to wake-up (by nibble) the device by falling and rising
edges. It means once there are one pin in is low or high
the I/O cannot wake-up the MCU.
The device provides 36-bit bidirectional input/output
lines labeled with port names PA, PB, PC, PD and PE.
These I/O ports are mapped to the Data Memory with
addresses as shown in the Special Purpose Data Mem-
ory table. All of these I/O lines can be used for input and
output operations. For input operation, these ports are
non-latching, which means the inputs must be ready at
the T2 rising edge of instruction ²MOV A,[m]², where m
denotes the port address. For output operation, all the
data is latched and remains unchanged until the output
latch is rewritten.
I/O Port Control Registers
Each I/O port has its own control register PAC, PBC,
PCC, PDC and PEC to control the input/output configu-
ration. With this control register, each CMOS output or
input with or without pull-high resistor structures can be
reconfigured dynamically under software control. Each
of the I/O ports is directly mapped to a bit in its associ-
ated port control register.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an exter-
nal resistor. To eliminate the need for these external re-
sistors, I/O pins, when configured as an input have the
capability of being connected to an internal pull-high re-
sistor. The pull-high resistors are selectable via configu-
ration options and are implemented using weak PMOS
transistors.
For the I/O pin to function as an input, the corresponding
bit of the control register must be written as a ²1². This
will then allow the logic state of the input pin to be di-
rectly read by instructions. When the corresponding bit
of the control register is written as a ²0², the I/O pin will
be setup as a CMOS output. If the pin is currently setup
as an output, instructions can still be used to read the
Port Pin Wake-up
If the HALT instruction is executed, the device will enter
the Power Down Mode, where the system clock will stop
Rev. 1.00
18
December 15, 2009
HT82K74E/HT82K74EE
V
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Input/Output Ports
PD3 has falling and rising edge wake-up function if its
wake-up function is enabled by related configuration
option. In halt mode if PD2 wakes up the MCU, the
bit6 named ZA_wakeup in the Wake-up Status Regis-
ter WSR will be set. Similarly, if PD3 wakes up the
MCU, the bit7 named ZB_wake-up in the Wake-up
Status Register WSR will be set. If the bit ZA_wake-up
or ZB_wakeup is read by application program, the bit
will be cleared.
output register. However, it should be noted that the pro-
gram will in fact only read the status of the output data
latch and not the actual logic status of the output pin.
Pin-shared Functions
The flexibility of the microcontroller range is greatly en-
hanced by the use of pins that have more than one func-
tion. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be over-
come. The chosen function of the multi-function I/O pins
is set by application program control.
I/O Pin Structures
The diagrams illustrate the I/O pin internal structures. As
the exact logical construction of the I/O pin may differ
from these drawings, they are supplied as a guide only
to assist with the functional understanding of the I/O
pins.
·
External Timer Clock Input
The external timer pin TMR is pin-shared with the I/O
pin PA2. To configure this pin to operate as timer input,
the corresponding control bits in the timer control reg-
ister must be correctly set. For applications that do not
require an external timer input, this pin can be used as
a normal I/O pin. Note that if used as a normal I/O pin
the timer mode control bits in the timer control register
must select the timer mode, which has an internal
clock source, to prevent the input pin from interfering
with the timer operation.
Programming Considerations
Within the user program, one of the first things to con-
sider is port initialisation. After a reset, all of the data and
port control register will be set high. This means that all
I/O pins will default to an input state, the level of which
depends on the other connected circuitry and whether
pull-high options have been selected. If the PAC, PBC,
PCC, PDC and PEC port control registers are pro-
grammed to setup some pins as outputs, these output
pins will have an initial high output value unless the as-
sociated PA, PB, PC, PD and PE port data registers are
first programmed. Selecting which pins are inputs and
which are outputs can be achieved byte-wide by loading
·
The VA/VB is for V-axis Function
The VA/VB pins are shared with the pins PD0/PD1.
PD0 or PD1 have falling and rising edge wake-up func-
tions if their wake-up function is enabled by the related
configuration option. In the Power-down mode, if PD0
wakes up the MCU, the bit3 named VA_wake-up in the
Wake-up Status Register WSR will be set. Similarly, if
PD1 wakes up the MCU, bit4 named VB_wakeup in the
Wake-up Status Register WSR will be set. If the bit
VA_wake-up or VB_wakeup is read by application pro-
gram, the bit will be cleared.
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The ZA/ZB is for Z-axis function
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The ZA/ZB pins are shared with the PD2/PD3, PD2 or
Read/Write Timing
Rev. 1.00
19
December 15, 2009
HT82K74E/HT82K74EE
the correct value into the port control register or by pro-
gramming individual bits in the port control register us-
ing the ²SET [m].i² and ²CLR [m].i² instructions. Note
that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then re-
write this data back to the output ports.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on shared pin PA2/TMR. Depending upon the condition
of the TE bit, each high to low, or low to high transition on
the PA2/TMR pin will increment the counter by one.
Timer Registers - TMRH, TMRL
The TMRH and TMRL registers are two 8-bit special
function register locations within the special purpose
Data Memory where the actual timer value is stored.
The value in the timer counter increases by one each
time an internal clock pulse is received or an external
transition occurs on the PA2/TMR pin. The timer will
count from the initial value loaded by the preload regis-
ter to the full count value of FFFFH at which point the
timer overflows and an internal interrupt signal gener-
ated. The timer value will then be reset with the initial
preload register value and continue counting. For a
maximum full range count of 0000H to FFFFH the
preload registers must first be cleared to 0000H. It
should be noted that after power-on the preload regis-
ters will be in an unknown condition. Note that if the
Timer/Event Counter is not running and data is written to
its preload registers, this data will be immediately written
into the actual counter. However, if the counter is en-
abled and counting, any new data written into the
preload registers during this period will remain in the
preload registers and will only be written into the actual
counter the next time an overflow occurs.
All I/O ports have the capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a transition of any of the selected
wake-up pins.
Timer/Event Counters
The provision of timers form an important part of any
microcontroller giving the designer a means of carrying
out time related functions. The device contains an inter-
nal 16-bit count-up timer which has three operating
modes. The timer can be configured to operate as a
general timer, external event counter or as a pulse width
measurement device.
There are three registers related to the Timer/Event
Counter, TMRL, TMRH and TMRC. The TMRL/TMRH
register pair are the registers that contains the actual
timing value. Writing to this register pair places an initial
starting value in the Timer/Event Counter preload regis-
ter while reading retrieves the contents of the
Timer/Event Counter. The TMRC register is a
Timer/Event Counter control register, which defines the
timer options, and determines how the timer is to be
used. The timer clock source can be configured to come
from the internal system clock divided by 4 or from an
external clock on shared pin PA2/TMR.
Accessing these registers is carried out in a specific
way. It must be noted that when using instructions to
preload data into the low byte register, namely TMRL,
the data will only be placed in a low byte buffer and not
directly into the low byte register. The actual transfer of
the data into the low byte register is only carried out
when a write to its associated high byte register, namely
TMRH, is executed. On the other hand, using instruc-
tions to preload data into the high byte timer register will
result in the data being directly written to the high byte
register. At the same time the data in the low byte buffer
will be transferred into its associated low byte register.
For this reason, when preloading data into the 16-bit
timer registers, the low byte should be written first. It
Configuring the Timer/Event Counter Input Clock
Source
The timer clock source can originate from either the sys-
tem clock divided by 4 or from an external clock source.
The system clock divided by 4 is used when the timer is
in the timer mode or in the pulse width measurement
mode.
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16-bit Timer/Event Counter Structure
Rev. 1.00
20
December 15, 2009
HT82K74E/HT82K74EE
must also be noted that to read the contents of the low
byte register, a read to the high byte register must first
be executed to latch the contents of the low byte buffer
from its associated low byte register. After this has been
done, the low byte register can be read in the normal
way. Note that reading the low byte timer register di-
rectly will only result in reading the previously latched
contents of the low byte buffer and not the actual con-
tents of the low byte timer register.
on/off control of the timer, setting the bit high allows the
counter to run, clearing the bit stops the counter. If the
timer is in the event count or pulse width measurement
mode the active transition edge level type is selected by
the logic level of the TE or bit 3 of the TMRC register.
Configuring the Timer Mode
In this mode, the timer can be utilised to measure fixed
time intervals, providing an internal interrupt signal each
time the counter overflows. To operate in this mode, bits
TM1 and TM0 of the TMRC register must be set to 1 and
0 respectively. In this mode, the internal clock is used as
the timer clock. The timer-on bit, TON, must be set high
to enable the timer to run. Each time an internal clock
high to low transition occurs, the timer increments by
one. When the timer is full and overflows, the timer will
be reset to the value already loaded into the preload reg-
ister and continue counting. If the timer interrupt is en-
abled, an interrupt signal will also be generated. The
timer interrupt can be disabled by ensuring that the ETI
bit in the INTC register is cleared to zero.
Timer Control Register - TMRC
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of the Timer Control Register TMRC. To-
gether with the TMRL and TMRH registers, these three
registers control the full operation of the Timer/Event
Counter. Before the timer can be used, it is essential that
the TMRC register is fully programmed with the right
data to ensure its correct operation, a process that is
normally carried out during program initialisation.
Note: The timer overflow can¢t wake-up the MCU from
Power Down Mode.
To choose which of the three modes the timer is to oper-
ate in, the timer mode, the event counting mode or the
pulse width measurement mode, bits TM0 and TM1
must be set to the required logic levels. The timer-on bit
TON or bit 4 of the TMRC register provides the basic
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Timer Mode Timing Chart
Rev. 1.00
21
December 15, 2009
HT82K74E/HT82K74EE
Configuring the Event Counter Mode
start counting until the PA2/TMR pin returns to its origi-
nal high level. At this point the TON bit will be automati-
cally reset to zero and the timer will stop counting. If the
TE bit is high, the timer will begin counting once a low to
high transition has been received on the PA2/TMR pin
and stop counting when the PA2/TMR pin returns to its
original low level. As before, the TON bit will be automat-
ically reset to zero and the timer will stop counting. It is
important to note that in the Pulse Width Measurement
Mode, the TON bit is automatically reset to zero when
the external control signal on the external timer pin re-
turns to its original level, whereas in the other two
modes the TON bit can only be reset to zero under pro-
gram control. The residual value in the timer, which can
now be read by the program, therefore represents the
length of the pulse received on pin PA2/TMR. As the
TON bit has now been reset any further transitions on
the PA2/TMR pin will be ignored. Not until the TON bit is
again set high by the program can the timer begin fur-
ther pulse width measurements. In this way single shot
pulse measurements can be easily made. It should be
noted that in this mode the counter is controlled by logi-
cal transitions on the PA2/TMR pin and not by the logic
level.
In this mode, a number of externally changing logic
events, occurring on external pin PA2/TMR, can be re-
corded by the internal timer. For the timer to operate in
the event counting mode, bits TM1 and TM0 of the
TMRC register must be set to 0 and 1 respectively. The
timer-on bit, TON must be set high to enable the timer to
count. With TE low, the counter will increment each time
the PA2/TMR pin receives a low to high transition. If the
TE bit is high, the counter will increment each time
PA2/TMR receives a high to low transition. As in the
case of the other two modes, when the counter is full
and overflows, the timer will be reset to the value al-
ready loaded into the preload register and continue
counting. If the timer interrupt is enabled, an interrupt
signal will also be generated. The timer interrupt can be
disabled by ensuring that the ETI bit in the INTC register
is cleared to zero. To ensure that the external pin
PA2/TMR is configured to operate as an event counter
input pin, two things have to happen. The first is to en-
sure that the TM0 and TM1 bits place the timer/event
counter in the event counting mode, the second is to en-
sure that the port control register configures the pin as
an input. In the Event Counting mode, the Timer/Event
Counter will continue to record externally changing logic
events on the timer input pin, even if the microcontroller
is in the Power Down Mode.
As in the case of the other two modes, when the counter
is full and overflows, the timer will be reset to the value
already loaded into the preload register. If the timer in-
terrupt is enabled, an interrupt signal will also be gener-
ated. To ensure that the external pin PA2/TMR is
configured to operate as a pulse width measuring input
pin, two things have to happen. The first is to ensure that
the TM0 and TM1 bits place the timer/event counter in
the pulse width measuring mode, the second is to en-
sure that the port control register configures the pin as
an input.
Configuring the Pulse Width Measurement Mode
In this mode, the width of external pulses applied to the
pin-shared external pin PA2/TMR can be measured. In
the Pulse Width Measurement Mode, the timer clock
source is supplied by the internal clock. For the timer to
operate in this mode, bits TM0 and TM1 must both be
set high. If the TE bit is low, once a high to low transition
has been received on the PA2/TMR pin, the timer will
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Pulse Width Measure Mode Timing Chart
Rev. 1.00
22
December 15, 2009
HT82K74E/HT82K74EE
I/O Interfacing
When the Timer/Event Counter is read, or if data is writ-
ten to the preload register, the clock is inhibited to avoid
errors, however as this may result in a counting error,
this should be taken into account by the programmer.
Care must be taken to ensure that the timers are prop-
erly initialised before using them for the first time. The
associated timer interrupt enable bits in the interrupt
control register must be properly set otherwise the inter-
nal interrupt associated with the timer will remain inac-
tive. The edge select, timer mode and clock source
control bits in timer control register must also be cor-
rectly set to ensure the timer is properly configured for
the required application. It is also important to ensure
that an initial value is first loaded into the timer registers
before the timer is switched on; this is because after
power-on the initial values of the timer registers are un-
known. After the timer has been initialised the timer can
be turned on and off by controlling the enable bit in the
timer control register. Note that setting the timer enable
bit high to turn the timer on, should only be executed af-
ter the timer mode bits have been properly setup. Set-
ting the timer enable bit high together with a mode bit
modification, may lead to improper timer operation if ex-
ecuted as a single timer control register byte write in-
struction.
The Timer/Event Counter, when configured to run in the
event counter or pulse width measurement mode, re-
quire the use of the external PA2 pin for correct opera-
tion. As this pin is a shared pin it must be configured
correctly to ensure it is setup for use as a Timer/Event
Counter input and not as a normal I/O pin. This is imple-
mented by ensuring that the mode select bits in the
Timer/Event Counter control register, select either the
event counter or pulse width measurement mode. Addi-
tionally the Port Control Register PAC bit 2 must be set
high to ensure that the pin is setup as an input. Any
pull-high resistor configuration option on this pin will re-
main valid even if the pin is used as a Timer/Event
Counter input.
Programming Considerations
When configured to run in the timer mode, the internal
system clock is used as the timer clock source and is
therefore synchronised with the overall operation of the
microcontroller. In this mode when the appropriate timer
register is full, the microcontroller will generate an inter-
nal interrupt signal directing the program flow to the re-
spective internal interrupt vector. For the pulse width
measurement mode, the internal system clock is also
used as the timer clock source but the timer will only run
when the correct logic condition appears on the external
timer input pin. As this is an external event and not syn-
chronised with the internal timer clock, the
microcontroller will only see this external event when the
next timer clock pulse arrives. As a result, there may be
small differences in measured values requiring pro-
grammers to take this into account during programming.
The same applies if the timer is configured to be in the
event counting mode, which again is an external event
and not synchronised with the internal system or timer
clock.
When the Timer/Event counter overflows, its corre-
sponding interrupt request flag in the interrupt control
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. But the timer
overflow can¢t wake-up the MCU if MCU is in a Power
down condition.
Rev. 1.00
23
December 15, 2009
HT82K74E/HT82K74EE
Timer Program Example
This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are en-
abled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The
Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the
Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source.
org 04h
reti
org 008h
jmp tmrint
:
; Timer/Event Counter interrupt vector
; jump here when Timer overflows
org 20h
; main program
;internal Timer/Event Counter interrupt routine
tmrint:
:
; Timer/Event Counter main program placed here
:
reti
:
:
begin:
;setup Timer registers
mov a,09bh
mov tmrl,a;
mov a, 0aah
mov tmrh,a
mov a,080h
mov tmrc,a
; setup Timer low register
; load low register first
; setup timer high register
; setup Timer control register
; timer mode is used
; setup interrupt register
mov a,005h
mov intc,a
set tmrc.4
; enable master interrupt and timer interrupt
; start Timer/Event Counter - note mode bits must be previously setup
Interrupts
Interrupts are an important part of any microcontroller
system. When an internal function such as a
Timer/Event Counter overflow, their corresponding in-
terrupt will enforce a temporary suspension of the main
program allowing the microcontroller to direct attention
to their respective needs. This device contains a single
internal Timer/Event counter interrupt.
ing interrupt vector. The microcontroller will then fetch
its next instruction from this interrupt vector. The instruc-
tion at this vector will usually be a JMP statement which
will jump to another section of program which is known
as the interrupt service routine. Here is located the code
to control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI statement,
which retrieves the original Program Counter address
from the stack and allows the microcontroller to continue
with normal execution at the point where the interrupt
occurred.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by a single inter-
rupt control register, which is located in the Data Mem-
ory. By controlling the appropriate enable bits in this
register the interrupt can be enabled or disabled. Also
when an interrupt occurs, the request flag will be set by
the microcontroller. The global enable flag if cleared to
zero will disable all interrupts.
Once an interrupt subroutine is serviced, other inter-
rupts will be blocked, as the EMI bit will be cleared auto-
matically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests oc-
cur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be re-
corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the rou-
tine, to allow interrupt nesting. If the stack is full, the in-
terrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
A Timer/Event Counter overflow, will generate an inter-
rupt request by setting its corresponding request flag, if
its interrupt enable bit is set. When this happens, the
Program Counter, which stores the address of the next
instruction to be executed, will be transferred onto the
stack. The Program Counter will then be loaded with a
new address which will be the value of the correspond-
Rev. 1.00
24
December 15, 2009
HT82K74E/HT82K74EE
Timer/Event Counter Interrupt
condition in the interrupt control register until the corre-
sponding interrupt is serviced or until the request flag is
cleared by a software instruction.
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and its corresponding timer in-
terrupt enable bit, ETI, must first be set. An actual
Timer/Event Counter interrupt will take place when the
Timer/Event Counter request flag, TF, is set, a situation
that will occur when the Timer/Event Counter overflows.
When the interrupt is enabled, the stack is not full and a
Timer/Event Counter overflow occurs, a subroutine call
to the timer interrupt vector at location 08H, will take
place. When the interrupt is serviced, the timer interrupt
request flag, TF, will be automatically reset and the EMI
bit will be automatically cleared to disable other inter-
rupts.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well con-
trolled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
Only the Program Counter is pushed onto the stack. If
the contents of the accumulator or status register are al-
tered by the interrupt service program, which may cor-
rupt the desired control sequence, then the contents
should be saved in advance.
Programming Considerations
By disabling the interrupt enable bit, the requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
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Interrupt Control Register
Rev. 1.00
25
December 15, 2009
HT82K74E/HT82K74EE
Reset and Initialisation
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, af-
ter a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program com-
mences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
V
D
D
0
.
D
9
D
V
R
E
S
t
R
S
T
D
S
S
T
T
i
m
e
-
o
u
t
I
n
t
e
r
n
a
l
R
e
s
e
t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected be-
tween VSS and the RES pin will provide a suitable ex-
ternal reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is force-
fully pulled low. In such a case, known as a normal oper-
ation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of re-
set operations result in different register conditions be-
ing setup.
V
R
D
D
S
1
0
W
0
k
E
0
m
. F 1
V
S
S
Basic Reset Circuit
For applications that operate within an environment
where more noise is present the Enhanced Reset Cir-
cuit shown is recommended.
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is imple-
mented in situations where the power supply voltage
falls below a certain threshold.
0
.
m
0
F
1
V
R
D
D
S
1
0
W
0
k
Reset Functions
E
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and ex-
ternally:
1
0
W
k
0
m
. F 1
V
S
S
·
Power-on Reset
Enhanced Reset Circuit
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory ad-
dress, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
·
RES Pin Reset
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initi-
ated from this point.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recom-
mended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
0
.
D
9
D
V
0
.
D
4
D
V
R
E
S
t
R
S
T
D
S
S
T
T
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e
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a
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R
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s
e
t
RES Reset Timing Chart
December 15, 2009
Rev. 1.00
26
HT82K74E/HT82K74EE
·
Low Voltage Reset - LVR
Reset Initial Conditions
The microcontroller contains a low voltage reset cir-
cuit in order to monitor the supply voltage of the de-
vice. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low sup-
ply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that spec-
ified by tLVR in the A.C. characteristics. If the low sup-
ply voltage state does not exceed this value, the LVR
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be se-
lected via configuration options.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
TO PDF
RESET Conditions
0
u
1
1
0
u
u
1
RES reset during power-on
RES or LVR reset during normal operation
WDT time-out reset during normal operation
WDT time-out reset during Power Down
L
V
R
Note: ²u² stands for unchanged
t
R
S
T
D
S
S
T
T
i
m
e
-
o
u
t
The following table indicates the way in which the vari-
ous components of the microcontroller are affected after
a power-on reset occurs.
I
n
t
e
r
n
a
l
R
e
s
e
t
Low Voltage Reset Timing Chart
Item
Condition After RESET
Program Counter Reset to zero
·
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal opera-
tion is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
Interrupts
WDT
All interrupts will be disabled
Clear after reset, WDT begins
counting
W
D
T
T
i
m
e
-
o
u
t
Timer/Event
Counter
t
R
S
T
D
Timer Counter will be turned off
S
S
T
T
i
m
e
-
o
u
t
Input/Output Ports I/O ports will be setup as inputs
I
n
t
e
r
n
a
l
R
e
s
e
t
Stack Pointer will point to the top
Stack Pointer
of the stack
WDT Time-out Reset during Normal Operation
Timing Chart
·
Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Pro-
gram Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
W
D
T
T
i
m
e
-
o
u
t
t
S
S
T
S
S
T
T
i
m
e
-
o
u
t
WDT Time-out Reset during Power Down
Timing Chart
Rev. 1.00
27
December 15, 2009
HT82K74E/HT82K74EE
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers.
Reset
WDT time-out
RES Reset
RES Reset
(HALT)
WDT Time-out
(HALT)*
Register
PCL
(Power-on)
(Normal Operation) (Normal Operation)
000H
000H
000H
000H
000H
MP
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
--00 xxxx
--0- -0-0
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--1u uuuu
--0- -0-0
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--00 uuuu
--0- -0-0
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--00 uuuu
--0- -0-0
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu
--11 uuuu
--u- -u-u
ACC
TBLP
TBLH
STATUS
INTC
TMRL
TMRH
TMRC
PA
xxxx xxxx
xxxx xxxx
00-0 1---
xxxx xxxx
xxxx xxxx
00-0 1---
xxxx xxxx
xxxx xxxx
00-0 1---
xxxx xxxx
xxxx xxxx
00-0 1---
uuuu uuuu
uuuu uuuu
uu-u u---
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
---- 1111
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
PAC
PB
PBC
PC
PCC
PD
PDC
PE
PEC
WSR
CTLR
OSCC
RFCTR
PTR
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
xxxx x---
xxxx x---
xxxx x---
xxxx x---
uuuu u---
0000 0x00
0000 0000
0000 0000
0000 0000
0000 0000
0000 0x00
0000 0000
0000 0000
0000 0000
0000 0uuu
0000 0x00
0000 0000
0000 0000
0000 0000
0000 uuuu
0000 0x00
0000 0000
0000 0000
0000 0000
0000 0uuu
uuuu uxuu
uuu0 uuuu
000u uuuu
uuuu uuuu
0000 0uuu
TBHP
Note:
²*² means ²warm reset²
²-² not implemented
²u² means ²unchanged²
²x² means ²unknown²
Rev. 1.00
28
December 15, 2009
HT82K74E/HT82K74EE
Oscillator
There are two oscillator circuits contained within the de-
vice. The first is the system oscillator which utilises an
external crystal and the second is the Watchdog timer
oscillator which is fully integrated and requires no exter-
nal components.
an extremely low standby current level. This occurs be-
cause when the device enters the Power Down Mode,
the system oscillator is stopped which reduces the
power consumption to extremely low levels, however,
as the device maintains its present internal condition, it
can be woken up at a later stage and continue running,
without requiring a full reset. This feature is extremely
important in application areas where the microcontroller
must have its power supply constantly maintained to
keep the device in a known condition but where the
power supply capacity is limited such as in battery appli-
cations.
System Clock Configurations
There is one oscillator mode Crystal. For Crystal mode
no built-in capacitor between OSC1, OSC2 and GND.
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feed-
back for oscillation, without requiring external capaci-
tors. However, for some crystal types and frequencies,
to ensure oscillation, it may be necessary to add two
small value capacitors, C1 and C2. Using a ceramic res-
onator will usually require two small value capacitors,
C1 and C2, to be connected as shown for oscillation to
occur. The values of C1 and C2 should be selected in
consultation with the crystal or resonator manufacturer's
specification. In most applications, resistor R1 is not re-
quired, however for those applications where the LVR
function is not used, R1 may be necessary to ensure the
oscillator stops running when VDD falls below its operat-
ing range.
Entering the Power Down Mode
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruc-
tion in the application program. When this instruction is
executed, the following will occur:
·
The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
·
The Data Memory contents and registers will maintain
their present condition.
·
The WDT will be cleared and resume counting if the
WDT is enabled and the clock source is selected to
come from the WDT oscillator.
More information regarding the oscillator is located in
Application Note HA0075E on the Holtek website.
·
The I/O ports will maintain their present condition.
·
In the status register, the Power Down flag, will be set
C
1
and the Watchdog time-out flag, TO, will be cleared.
O
S
C
1
R
1
Standby Current Considerations
O
S
C
2
As the main reason for entering the Power Down Mode
is to keep the current consumption of the microcontroller
to as low a value as possible, perhaps only in the order
of several micro-amps, there are other considerations
which must also be taken into account by the circuit de-
signer if the power consumption is to be minimised.
C
2
Crystal/Ceramic Oscillator
Watchdog Timer Oscillator
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 71ms at 3V
requiring no external components. When the device en-
ters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
Special attention must be made to the I/O pins on the
device. All high-impedance input pins must be con-
nected to either a fixed high or low level as any floating
input pins could create internal oscillations and result in
increased current consumption. Care must also be
taken with the loads, which are connected to I/O pins,
which are setup as outputs. These should be placed in a
condition in which minimum current is drawn or con-
nected only to external circuits that do not draw current,
such as other CMOS inputs.
Power Down Mode and Wake-up
Power Down Mode
If the configuration option has enabled the Watchdog
Timer internal oscillator, then this will continue to run
when in the Power Down Mode and will thus consume
some power.
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode. When the device enters this
mode, the normal operating current, will be reduced to
Rev. 1.00
29
December 15, 2009
HT82K74E/HT82K74EE
Wake-up
Watchdog Timer
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a de-
vice reset when the WDT counter overflows. The WDT
clock is supplied by its own internal dedicated internal
WDT oscillator. Note that if the WDT configuration op-
tion has been disabled, then any instruction relating to
its operation will result in no operation.
·
An external reset
·
An external falling or rising edge on any of the I/O pins
·
A system interrupt
·
A WDT overflow (if the contents of the PTR are zeros)
·
A PTR overflow occurs (if the contents of the PTR are
not equal to zeros)
If the system is woken up by an external reset, the de-
vice will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the ac-
tual source of the wake-up can be determined by exam-
ining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status. Note that the WDT time-out will not
occur if the contents of the Period Timer Register (PTR)
are not equal to zeros.
The WDT function is selected by a configuration option.
There is also an internal register associated with the
WDT named WDTS to select various WDT time-out pe-
riods in the device. The clock source of the WDT comes
from the internal WDT oscillator and its clock period may
vary with VDD, temperature and process variation. The
WDT clock is further divided by an internal 6-stage
counter followed by a 7-stage prescaler to obtain longer
WDT time-out period selected by the WDT prescaler
rate selection bits, WS2~WS0, in the associated WDT
register known as WDTS.
There is only one instruction to clear the Watchdog
Timer known as ²CLR WDT². As the instruction ²CLR
WDT² is executed, all contents of the 6-stage counter
and 7-stage prescaler will be clear. It makes the WDT
time-out period more accurate relatively.
Each pin on Port A or any nibble on other ports can be
setup via configuration options to permit a negative or
positive transition on the pin to wake-up the system.
When a port pin wake-up occurs, the program will re-
sume execution at the instruction following the ²HALT²
instruction.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. How-
ever, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instruc-
tions and the third is via a HALT instruction.
If the system is woken up by an interrupt, then two possi-
ble situations may occur. The first is where the interrupt
is disabled or the interrupt is enabled but the stack is full,
in which case the program will resume execution at the
instruction following the ²HALT² instruction. In this situa-
tion, the interrupt will not be immediately serviced, but
will rather be serviced later when the related interrupt is
finally enabled or when a stack level becomes free. The
other situation is where the related interrupt is enabled
and the stack is not full, in which case the regular inter-
rupt response takes place. If an interrupt request flag is
set to ²1² before entering the Power Down Mode, the
wake-up function of the related interrupt will be disabled.
Although the WDT overflow is a source to wake up the
MCU from the Power Down Mode, there are some limi-
tations on the conditions at which the WDT overflow oc-
curs. If the WDT function is enabled and the PTR
contents are equal to zeros, the WDT overflow will occur
to wake up the MCU from the Power Down Mode. If the
PTR contents are not equal to zeros, the WDT overflow
will not occur in Power Down Mode even if the WDT
function has been enabled.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 512
system clock periods will be required before normal sys-
tem operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt sub-
routine execution will be delayed by additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 512 system clock
period delay has ended.
Rev. 1.00
30
December 15, 2009
HT82K74E/HT82K74EE
b
7
b
0
W
S
2
W
S
W
1
S
0
W
D
T
S
R
e
g
i
s
t
e
r
W
D
T
p
r
e
s
c
a
l
e
r
r
a
t
e
s
e
l
W
S
W
S
1
W
S
0
W
W
1
1
1
1
1
1
1
D
T
R
a
t
e
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D
T
i
s
d
i
s
a
b
l
:
:
:
:
:
:
:
1
4
8
1
3
6
1
6
2
4
2
8
N
o
t
u
s
e
d
Watchdog Timer Register
C
L
R
W
D
T
F
l
a
g
C
L
R
C
L
R
6
-
b
i
t
C
r
o
u
n
t
e
r
7
-
b
i
t
P
r
e
s
c
a
W
D
T
O
s
c
i
l
l
a
t
o
8
-
t
o
-
1
M
W
U
S
X
0
~
W
S
2
W
D
T
T
i
m
e
-
o
u
t
Watchdog Timer Register
Bit No. MCU Name
Fun. Name
R/W
Description for mouse mode
0~2
3
PF0~PF2
PF3
Reserved bit
VA_wakeup
Always read 0
¾
1: VA change before VB
0: default
R
R
R
R
R
1: VB change before VA
0: default
4
5
6
7
PF4
PF5
PF6
PF7
VB_wakeup
CNT_WK
1: MCU wake-up by period counter overflow
0: MCU Wake-up not by period counter
1: ZA change before ZB
0: default
ZA_wakeup
ZB_wakeup
1: ZB change before ZA
0: default
Wakeup Status Register - WSR
Rev. 1.00
31
December 15, 2009
HT82K74E/HT82K74EE
MCU
Function
Name
Bit No.
R/W
Description for Mouse Mode
Name
Control AMP function
R/W 1: on AMP function
0: off AMP function (default)
0
PFC0
AMP_ctrl
This bit is used to decide whether the DC/DC circuit is in operation
R/W 0: enable the DC/DC circuit
1
2
PFC1
PFC2
DC_ctrl
LVDF
0: disable the DC/DC circuit
Flag for 2.2V/2.0V battery low signal coming from DC/DC block (the
battery low level 2.2V or 2.0V is selected by configuration option).
R
1: battery voltage £ 2.2V/2.0V
0: battery voltage > 2.2V/2.0V
1.8V Battery Low signal for DC/DC 1.8V
Always Off in Power Down Mode.
R
3
PFC3
LVD18
1: battery voltage £ 1.8V
0: battery voltage > 1.8V
4~7
PFC4~7 Reserved bit
R/W Always read 0
Control Register - CTLR
Bit No.
MCU Name
R/W
Description for mouse mode
0: no 2X pf capacitor connected to OSC1 (default)
1: has 2X pf capacitor connected to OSC1
0
OSC1_C0
R/W
R/W
0: no 4X pf capacitor connected to OSC1 (default)
1: has 4X pf capacitor connected to OSC1
1
OSC1_C1
0: no 8X pf capacitor connected to OSC1 (default)
1: has 8X pf capacitor connected to OSC1
2
3
4
OSC1_C2
Reserved bit
OSC2_C0
R/W
R/W
R/W
Always read 0
0: no 2X pf capacitor connected to OSC2 (default)
1: has 2X pf capacitor connected to OSC2
0: no 4X pf capacitor connected to OSC2 (default)
1: has 4X pf capacitor connected to OSC2
5
6
7
OSC2_C1
OSC2_C2
OSC2_C3
R/W
R/W
R/W
0: no 8X pf capacitor connected to OSC2 (default)
1: has 8X pf capacitor connected to OSC2
0: no 16X pf capacitor connected to OSC2 (default)
1: has 16X pf capacitor connected to OSC2
Where ²X² is 3pf capacitor.
OSC CAP Control Register - OSCC
Rev. 1.00
32
December 15, 2009
HT82K74E/HT82K74EE
Bit No.
Fun. Name
R/W
Description for mouse mode
MCU system clock division selection
00: system clock= system oscillator output clock/4 (6.75MHz)
0~1
CLK_DIV
R/W 01: system clock= system oscillator output clock/8 (3.3MHz)
10: system clock= system oscillator output clock/16 (1.68MHz)
11: system clock= system oscillator output clock/1 (only for 4MHz)
27MHz oscillator built-in capacitor enable control
0: disable the built-in capacitor connection to both OSC1 and OSC2 (default)
R/W 1: enable the built-in capacitor connection to both OSC1 and OSC2 where the
built-in capacitors for both OSC1 and OSC2 are defined by the OSC CAP con-
trol register OSCC.
2
3
CAP_EN
27MHz oscillator (OSC) operating mode control
OSC_MOD
R/W 0: OSC operates in normal mode without frequency modulation.
1: OSC operates in frequency modulation mode for RF transmission.
27MHz oscillator (OSC) current control when OSC operates in frequency modu-
lation mode.
4
I_SEL
R/W 0: normal current state is selected when the VDD voltage is equal to or higher
than 3V.
1: high current state is selected when the VDD voltage is lower than 3V.
5~7
Reserved bit
R/W Always read 0
27MHz Oscillator Control Register - RFCTR (21H)
Period Timer Register - PTR
This register is used to define the period of the timer which always counts in the Power Down Mode. Once the timer is
reached, the MCU will be woken-up by Period Timer Register overflow. Once the MCU is woken-up by the period timer,
the CNT_WK bit of the wake-up Register is set to ²1².
Function
Bit No.
R/W
Description
Name
The Period Timer is the time interval generator with one second as a unit. If
the bits [7:0] are equal to 00H, the MCU will be woken up by one of the
wake-up source mentioned in Wake-up Section except the PTR overflow
event. If the bits [7:0] are not equal to 00H, the MCU will be woken up from
the Power Down mode by the following events except WDT overflow event:
0~7
Period Timer
R/W
·
I/O Port wake-up
·
·
·
INT wake-up
Reset
The Period Timer is reached to the values specified by the PTR.
Period Timer Register - PTR
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HT82K74E/HT82K74EE
Amplifier Output for 27MHz
DC-to-DC Converter (DC/DC)
The RF_OUT pin is the signal output pin and is sourced
from the system oscillator clock output signal via a
power amplifier. The RF_OUT impedance is 50 for
which the user can design an antenna to transmit the
signal. The integrated power amplifier is used to supply
power to RF_OUT and can select either 0dBm for full
power or -3dBm for half power, via a configuration op-
tion. The amplifier can be enabled or disabled using the
Amplifier function control bit AMP_ctrl in the Control
Register CTLR.
This circuit is used to generate a stable 2.8V or 3.0V or
3.3V (error ±0.1V) power voltage for the whole device
and output to the IRPT. The DC/DC clock frequency is
130kHz. It can also detect the battery voltage. If the bat-
tery voltage drops to 2.2V or 2.0V, the choice of which is
determined by a configuration option (error ±0.1V), the
DC/DC circuit will output a Low Voltage Detect signal
LVD (2.2V/2.0V Low battery flag stored in LVDF bit of
the Control Register CTLR) to the MCU. There is also a
low voltage reset (LVR) circuit to check the DC/DC out-
put voltage. When the DC/DC output voltage drops to
2.4V, the MCU will be reset. The LVR function is con-
trolled by a configuration together with a software con-
trol bit named DC_ctrl in the Control Register CTLR. To
enable the LVR function, the configuration option of LVR
function has to be enabled and the control bit DC_ctrl
must be set to ²0² to enable the DC/DC circuit. If the
configuration option is selected to disable the LVR func-
tion or the DC_ctrl bit is set to ²1² to disable the DC/DC
circuit, then the LVR function will be disabled. If the LVR
function is enabled by appropriate setting of the configu-
ration option and software control bits as mentioned
above, then the LVR still operates even if the MCU en-
ters the Power Down Mode. It is recommended that the
LVR function is enabled when the MCU is in the Power
Down Mode.
S
y
s
t
e
m
O
s
c
i
l
l
o
r
C
l
o
c
k
A
M
P
.
R
F
_
O
A
M
P
_
c
t
r
l
This output is use to output the RF signal to the antenna.
Output Power= 0dBm (1±b) for full, -3dBm for half
Load Impedance= 50W
The RF-carrier is shifted in frequency according to the
data, which is known as Frequency Shift Keying (FSK).
The data recognition depends upon the method which
the RF receiver uses. The shifted frequency is imple-
mented by the 27MHz oscillator operating mode control
bit OSC_MOD in the RFCTR register. When the
OSC_MOD bit is set to 1, the oscillator operates in its
frequency modulation mode for RF transmission. To
achieve frequency modulation, built-in capacitors can
be selected which are connected to OSC1 and OSC2
using the built-in capacitor enable control bit CAP_EN in
the RFCTR register. If the CAP_EN bit is set to 1, the se-
lected built-in capacitors determined by the oscillator
capacitor control register OSCC can be connected to
OSC1 and OSC2. If the supply voltage drops lower than
3V when the oscillator operates in its frequency modula-
tion mode, the oscillator current control bit I_SEL in the
RFCTR register should be set to 1 to ensure that the os-
cillator can perform its frequency modulation normally.
As the voltage of the Battery-in pin drops to 2.2V, the
DC/DC converter can still operate correctly and is capa-
ble of outputting a drive current of at least 50mA.
B
A
T
_
I
N
2
.
4
V
L
V
R
D
C
_
O
u
t
D
C
/
D
C
w
i
t
h
V o
C
l
t
a
g
e
D
e
t
e
c
t
o
r
T
e
s
t
_
D
1
.
8
V
/
2
.
2
V
L
X
Output Port used Slew Rate Control I/O Pin
The I/O port output delay time of the rising and falling
transition is 100ns or 200ns. There is a configuration op-
tion bit to define the slew rate of all I/O pins.
Rev. 1.00
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December 15, 2009
HT82K74E/HT82K74EE
Configuration Options
No.
Options
PA0~PA7 pull-high by bit: pull-high or non-pull-high
PA0~PA7 wake-up by bit: wake-up or non-wake-up
1
2
3
4
5
6
7
8
9
PB0~PB7 wake-up by nibble: wake-up or non-wake-up
PB0~PB7 pull-high by nibble: pull-high or non-pull-high
PC0~PC7 wake-up by nibble: wake-up or non-wake-up
PC0~PC7 pull-high by nibble: pull-high or non-pull-high
PD0~PD7 wake-up by nibble: wake-up or non-wake-up
PD0~PD7 pull-high by nibble: pull-high or non-pull-high
PE0~PE3 wake-up by nibble: wake-up or non-wake-up
10 PE0~PE3 pull-high by nibble: pull-high or non-pull-high
11 WDT: enable or disable
12 TBHP function: enable or disable
13 DC-DC output voltage: 2.8V, 3.0V, 3.3V
14 LVR: enable or disable
15 LVD voltage: 2.2V or 2.0V
16 I/O Slew Rate: 100ns or 200ns
17 Power Amp: full or half
Application Circuits
1
2
3
4
5
6
7
8
9
3
3
3
2
2
2
2
2
2
2
2
2
2
1
1
1
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
P
P
P
P
P
P
P
P
R
P
P
P
P
P
P
V
A
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
P
P
B
B
0
1
/
/
V
V
A
B
A
B
C
A
P
P
P
B
B
2
3
/
/
Z
Z
P
P
P
P
B
B
B
B
4
5
6
7
V
D
D
/
T
M
R
1
0
W
0
k
E
S
5
4
3
2
1
0
D
L
X
V
D
D
G
N
D
1
1
1
1
1
1
1
0
1
2
3
4
5
6
0
m
. F 1
C
C
C
C
C
C
D
V
S
S
L
X
0
m
. F 1
B
A
T
_
I
N
V
D
D
4
m
7 F
R
F
_
O
U
T
V
S
S
2
7
M
H
z
O
O
S
S
C
C
1
2
V
D
D
H
T
8
2
K
7
4
E
/
H
T
8
2
K
7
4
E
E
Rev. 1.00
35
December 15, 2009
HT82K74E/HT82K74EE
Instruction Set
Introduction
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to en-
sure correct handling of carry and borrow data when re-
sults exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Central to the successful operation of any
microcontroller is its instruction set, which is a set of pro-
gram instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of pro-
gramming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several func-
tional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on pro-
gram requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruc-
tion cycle. The exceptions to this are branch, call, or ta-
ble read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be im-
plemented within 1ms. Although instructions which re-
quire one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instruc-
tions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to imple-
ment. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instruc-
tions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the re-
sult of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a sub-
routine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the sub-
routine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made re-
garding the condition of a certain data memory or indi-
vidual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the pro-
gram perhaps determined by the condition of certain in-
put switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific imme-
diate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.00
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December 15, 2009
HT82K74E/HT82K74EE
Bit Operations
Other Operations
The ability to provide single bit operations on Data Mem-
ory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The fea-
ture removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write pro-
cess is taken care of automatically when these bit oper-
ation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² in-
struction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electro-
magnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be con-
sulted as a basic instruction reference using the follow-
ing listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using regis-
ters. However, when working with large amounts of
fixed data, the volume involved often makes it inconve-
nient to store the fixed data in the Data Memory. To over-
come this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instruc-
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Arithmetic
Description
Cycles Flag Affected
ADD A,[m]
ADDM A,[m]
ADD A,x
Add Data Memory to ACC
1
1Note
1
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
Add ACC to Data Memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add Data Memory to ACC with Carry
1
1Note
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
1
1Note
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1Note
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1Note
1Note
1
OR A,x
1
XOR A,x
1
1Note
CPL [m]
CPLA [m]
Complement Data Memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment Data Memory with result in ACC
1
Z
Z
Z
Z
Increment Data Memory
1Note
DECA [m]
DEC [m]
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
Rev. 1.00
37
December 15, 2009
HT82K74E/HT82K74EE
Mnemonic
Rotate
Description
Cycles Flag Affected
RRA [m]
RR [m]
Rotate Data Memory right with result in ACC
Rotate Data Memory right
1
1Note
1
1Note
1
1Note
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
C
None
None
C
RLCA [m]
RLC [m]
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Branch
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if Data Memory is zero
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m]
TABRDL [m]
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
Miscellaneous
NOP
No operation
1
1Note
1Note
1
None
None
CLR [m]
Clear Data Memory
SET [m]
Set Data Memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO, PDF
TO, PDF
TO, PDF
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1
1Note
1
None
1
TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.00
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December 15, 2009
HT82K74E/HT82K74EE
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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December 15, 2009
HT82K74E/HT82K74EE
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then in-
crements by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruc-
tion.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Operation
Each bit of the specified Data Memory is cleared to 0.
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Description
Operation
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.00
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December 15, 2009
HT82K74E/HT82K74EE
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Operation
Data in the specified Data Memory is decremented by 1.
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
mulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.00
41
December 15, 2009
HT82K74E/HT82K74EE
INC [m]
Increment Data Memory
Description
Operation
Data in the specified Data Memory is incremented by 1.
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
lator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Description
Operation
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
Operation
The immediate data specified is loaded into the Accumulator.
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Description
Operation
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
ation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.00
42
December 15, 2009
HT82K74E/HT82K74EE
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
ation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the re-
stored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by set-
ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed be-
fore returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
main unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.00
43
December 15, 2009
HT82K74E/HT82K74EE
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.00
44
December 15, 2009
HT82K74E/HT82K74EE
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Operation
Each bit of the specified Data Memory is set to 1.
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is set to 1.
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.00
45
December 15, 2009
HT82K74E/HT82K74EE
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumu-
lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.00
46
December 15, 2009
HT82K74E/HT82K74EE
SWAP [m]
Description
Operation
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
tion.
Operation
Skip if [m] = 0
None
Affected flag(s)
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
None
Affected flag(s)
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.00
47
December 15, 2009
HT82K74E/HT82K74EE
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.00
48
December 15, 2009
HT82K74E/HT82K74EE
Package Information
28-pin SSOP (150mil) Outline Dimensions
2
8
1
1
5
4
A
B
1
C
C
'
G
H
D
a
E
F
Dimensions in mil
Symbol
Min.
228
150
8
Nom.
¾
Max.
244
157
12
A
B
C
C¢
D
E
F
¾
¾
386
54
¾
394
60
¾
¾
25
¾
4
10
¾
¾
¾
¾
G
H
a
22
7
28
10
0°
8°
Rev. 1.00
49
December 15, 2009
HT82K74E/HT82K74EE
SAW Type 32-pin (5mm´ 5mm) QFN Outline Dimensions
D
D
2
2
5
3
2
2
4
1
b
E
E
2
e
1
7
8
1
6
9
A
A
1
3
L
K
A
Dimensions in inch
Symbol
Min.
Nom.
¾
Max.
0.031
0.002
¾
A
A1
A3
b
0.028
0.000
¾
¾
0.008
0.007
¾
0.012
¾
¾
0.197
0.197
0.020
¾
D
E
¾
¾
e
¾
¾
D2
E2
L
0.049
0.049
0.012
¾
0.128
0.128
0.020
¾
¾
¾
K
¾
Dimensions in mm
Symbol
Min.
0.70
0.00
¾
Nom.
¾
Max.
0.80
0.05
¾
A
A1
A3
b
¾
0.20
0.18
¾
0.30
¾
¾
5.00
5.00
0.50
¾
D
E
¾
¾
e
¾
¾
D2
E2
L
1.25
1.25
0.30
¾
3.25
3.25
0.50
¾
¾
¾
K
¾
Rev. 1.00
50
December 15, 2009
HT82K74E/HT82K74EE
48-pin SSOP (300mil) Outline Dimensions
4
8
2
2
5
4
A
B
1
C
C
'
G
H
D
a
E
F
Dimensions in inch
Symbol
Min.
0.395
0.291
0.008
0.613
0.085
¾
Nom.
¾
Max.
0.420
0.299
0.012
0.637
0.099
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.025
0.004
0.025
0.004
0°
0.010
0.035
0.012
8°
¾
¾
¾
¾
G
H
a
Dimensions in mm
Symbol
Min.
10.03
7.39
0.20
15.57
2.16
¾
Nom.
¾
Max.
10.67
7.59
0.30
16.18
2.51
¾
A
B
C
C¢
D
E
F
¾
¾
¾
¾
0.64
0.10
0.64
0.10
0°
0.25
0.89
0.30
8°
¾
¾
¾
¾
G
H
a
Rev. 1.00
51
December 15, 2009
HT82K74E/HT82K74EE
48-pin LQFP (7mm´ 7mm) Outline Dimensions
C
D
H
G
3
6
2
5
I
3
7
2
4
F
A
B
E
4
8
1
3
a
K
J
1
1
2
Dimensions in mm
Symbol
Min.
8.90
6.90
8.90
6.90
¾
Nom.
¾
Max.
9.10
7.10
9.10
7.10
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
0.50
0.20
¾
¾
1.35
¾
1.45
1.60
¾
¾
¾
0.10
¾
¾
J
0.45
0.10
0°
0.75
0.20
7°
K
a
¾
¾
Rev. 1.00
52
December 15, 2009
HT82K74E/HT82K74EE
Product Tape and Reel Specifications
Reel Dimensions
D
T
2
C
A
B
T
1
SSOP 28S (150mil)
Symbol
Description
Dimensions in mm
330.0±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
100.0±1.5
+0.5/-0.2
13.0
C
D
2.0±0.5
+0.3/-0.2
16.8
T1
T2
Space Between Flange
Reel Thickness
22.2±0.2
SSOP 48W
Symbol
Description
Dimensions in mm
330.0±1.0
A
B
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
100.0±0.1
+0.5/-0.2
13.0
C
D
2.0±0.5
+0.3/-0.2
32.2
T1
T2
Space Between Flange
Reel Thickness
38.2±0.2
Rev. 1.00
53
December 15, 2009
HT82K74E/HT82K74EE
Carrier Tape Dimensions
SSOP 28S (150mil)
P
0
P
1
t
D
E
F
W
B
0
C
D
1
P
K
0
A
0
R
e
e
l
H
o
l
e
I
C
p
a
c
k
a
g
e
p
i
n
1
a
n
a
r
e
l
o
c
a
t
e
d
o
n
t
h
e
s
Symbol
Description
Dimensions in mm
16.0±0.3
W
P
Carrier Tape Width
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
7.5±0.1
+0.10/-0.00
D
1.55
+0.25/-0.00
D1
P0
P1
A0
B0
K0
t
1.50
4.0±0.1
2.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
6.5±0.1
Cavity Width
10.3±0.1
2.1±0.1
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.30±0.05
13.3±0.1
C
Rev. 1.00
54
December 15, 2009
HT82K74E/HT82K74EE
SSOP 48W
P
0
P
1
t
D
E
F
B
0
W
C
K
1
D
1
P
K
2
A
0
R
e
e
l
H
o
l
e
(
C
i
r
c
l
e
)
I
C
p
a
c
k
a
g
e
p
i
n
1
a
n
d
t
h
e
r
e
a
r
e
l
o
c
a
t
e
d
o
n
t
h
e
s
a
m
e
s
i
d
R
e
e
l
H
o
l
e
(
E
l
l
i
p
s
e
)
Symbol
Description
Dimensions in mm
32.0±0.3
W
P
Carrier Tape Width
Cavity Pitch
16.0±0.1
E
Perforation Position
1.75±0.10
14.2±0.1
F
Cavity to Perforation (Width Direction)
Perforation Diameter
D
2 Min.
+0.25/-0.00
D1
P0
P1
A0
B0
K1
K2
t
Cavity Hole Diameter
1.50
Perforation Pitch
4.0±0.1
2.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
12.0±0.1
16.2±0.1
2.4±0.1
Cavity Width
Cavity Depth
Cavity Depth
3.2±0.1
Carrier Tape Thickness
Cover Tape Width
0.35±0.05
25.5±0.1
C
Rev. 1.00
55
December 15, 2009
HT82K74E/HT82K74EE
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2009 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
56
December 15, 2009
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