HT82K95E(48SSOP)_技术文档

HT82K95E/HT82K95A

USB Multimedia Keyboard Encoder 8-Bit MCU

Technical Document

·

Tools Information

·

FAQs

·

Application Note

Features

·

Operating voltage:

4096´15 program memory ROM

f

_SYS=6M/12MHz: 3.3V~5.5V

·

160´8 data memory RAM

·

Low voltage reset function

·

All I/O ports support wake-up options

32 bidirectional I/O lines (max.)

·

HALT function and wake-up feature reduce power

consumption

8-bit programmable timer/event counter with over-

flow interrupt

·

8-level subroutine nesting

·

16-bit programmable timer/event counter and over-

flow interrupts

Up to 0.33ms instruction cycle with 12MHz system

clock at V_DD=5V

·

Crystal oscillator (6MHz or 12MHz)

Watchdog Timer

·

Bit manipulation instruction

15-bit table read instruction

PS2 and USB modes supported

USB 2.0 low speed function

63 powerful instructions

All instructions in one or two machine cycles

28-pin SOP, 48-pin SSOP package

3 endpoints supported (endpoint 0 included)

General Description

This device is an 8-bit high performance RISC architec-

ture microcontroller designed for USB product applica-

tions. It is particularly suitable for use in products such

as keyboards. A HALT feature is included to reduce

power consumption. The mask version HT82K95A is

fully pin and functionally compatible with the OTP ver-

sion HT82K95E device.

Rev. 1.80

1

December 28, 2007

HT82K95E/HT82K95A

Block Diagram

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5

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7

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7

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1

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2

A

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V

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S

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P

D

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P

O

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T

D

S

P

D

0

~

P

D

7

P

D

Rev. 1.80

2

December 28, 2007

HT82K95E/HT82K95A

Pin Assignment

P

C

5

1

2

3

4

5

6

7

8

9

1

2

4

3

2

8

7

6

5

4

3

2

1

0

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5

4

3

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6

5

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2

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A

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8

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O

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-

A

Pin Description

ROM Code

Option

Pin Name

I/O

Description

Bidirectional 8-bit input/output port. Each bit can be configured as a

wake-up input by ROM code option. The input or output mode is con-

trolled by PAC (PA control register).

PA0~PA5

PA6/TMR0

PA7/TMR1

Pull-high

Wake-up

I/O

Pull-high resistor options: PA0~PA7

CMOS/NMOS/PMOS CMOS/NMOS/PMOS options: PA0~PA7

Wake up options: PA0~PA7

PA6 and PA7 are pin-shared with TMR0 and TMR1 input, respectively.

Bidirectional 8-bit input/output port. Software instructions determine the

CMOS output or Schmitt trigger input with pull-high resistor (determined

by pull-high options).

Pull-high

Wake-up

PB0~PB7

I/O

Wake-up options: PB0~PB7

Bidirectional I/O lines. Software instructions determine the CMOS out-

put or Schmitt trigger input with pull-high resistor (determined by

pull-high options).

Pull-high

Wake-up

PD0~PD7

VSS

I/O

¾

Wake-up options: PD0~PD7

Negative power supply, ground

¾

Bidirectional I/O lines. Software instructions determine the CMOS out-

put or Schmitt trigger input with pull-high resistor (determined by

pull-high options).

Pull-high

Wake-up

PC0~PC7

I/O

Wake-up options: PC0~PC7

RES

VDD

I

Schmitt trigger reset input. Active low

Positive power supply

¾

Rev. 1.80

3

December 28, 2007

HT82K95E/HT82K95A

ROM Code

Option

Pin Name

V33O

USBD+/CLK

I/O

O

Description

3.3V regulator output

¾

USBD+ or PS2 CLK I/O line

I/O

USB or PS2 function is controlled by software control register

USBD- or PS2 DATA I/O line

USBD-/DATA I/O

¾

USB or PS2 function is controlled by software control register

OSC1

OSC2

I

OSC1, OSC2 are connected to a 6MHz or 12MHz Crystal/resonator

(determined by software instructions) for the internal system clock.

O

Absolute Maximum Ratings

Supply Voltage...........................V_SS-0.3V to V_SS+6.0V

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

Storage Temperature............................-50°C to 125°C

Operating Temperature...............................0°C to 70°C

I_OHTotal............................................................-100mA

I

_OLTotal ..............................................................150mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min. Typ. Max.

Unit

V_DD

f_SYS=6MHz

3.3

¾

5.5

12

V

¾

V_DD

Operating Voltage

¾

f

_SYS=12MHz

I_DD1

I_DD2

I_STB1

No load, f_SYS=6MHz

No load, f_SYS=12MHz

Operating Current (6MHz Crystal)

Operating Current (12MHz Crystal)

5V

6.5

7.5

mA

16

¾

No load, system HALT,

USB suspend

Standby Current (WDT Enabled)

Standby Current (WDT Disabled)

5V

250

230

¾

mA

No load, system HALT,

USB suspend

I_STB2

No load, system HALT,

I_STB3

Standby Current (WDT Enabled)

5V input/output mode,

set SUSPEND2 [1CH]

15

¾

mA

V_IL1

V_IH1

V_IL2

V_IH2

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES)

5V

0

0.8

5

V

¾

2

0

0.4V_DD

V_DD

0.9V_DD

Input High Voltage (RES)

I/O Port Sink Current for PA1~PA7, PB, PC,

PD

I_OL1

V

_OL=3.4V

_OL=0.4V

5V

10

15

20

mA

I/O Port Sink Current for PA1~PA7, PB, PC,

PD

I_OL2

I_OL3

I_OH1

V

2

7

4

8

mA

I/O Port Sink Current for PA0

5V V_OL=0.4V

10

-4

13

-8

I/O Port Source Current for PA1~PA7, PB,

PC, PD

V_OH=3.4V

5V

4

-2

Rev. 1.80

December 28, 2007

HT82K95E/HT82K95A

Test Conditions

Conditions

V_OH=3.4V

Symbol

Parameter

Min. Typ. Max.

Unit

V_DD

5V

¾

I_OH2

I/O Port Source Current for PA0

Pull-high Resistance for PA, PB, PC, PD

Low Voltage Reset

mA

kW

V

-12

25

2

-18

50

-24

80

R_PH

¾

V_LVR

V_V33O

C_OSC1

C_OSC2

2.6

3.3

15

3.2

3.6

20

¾

3.3V Regulator Output

5V

3.0

10

V

I_V33O=-5mA

Build_in Capacitance in OSC1

Build_in Capacitance in OSC2

pF

¾

15

20

A.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min. Typ. Max.

Unit

V_DD

5V

f_SYS

System Clock (Crystal OSC)

6

0

12

70

16

¾

MHz

¾

f_TIMER

t_WDTOSC

t_WDT1

t_WDT2

t_RES

Timer I/P Frequency (TMR)

5V

Watchdog Oscillator

5V

15

4

31

ms

Watchdog Time-out Period (WDT OSC)

Watchdog Time-out Period (System Clock)

External Reset Low Pulse Width

5V Without WDT prescaler

8

t_SYS

Without WDT prescaler

¾

1024

¾

1

ms

t_SYS

Wake-up from HALT

1024

¾

t_SST

System Start-up Timer Period

Interrupt Pulse Width

¾

Power-up, Watchdog

Time-out from normal

t_WDTOSC

1024

¾

t_INT

1

¾

ms

Rev. 1.80

5

December 28, 2007

HT82K95E/HT82K95A

Functional Description

Execution Flow

incremented by one. The program counter then points to

the memory word containing the next instruction code.

The system clock for the microcontroller is derived from

a crystal. The system clock is internally divided into four

non-overlapping clocks. One instruction cycle consists

of four system clock cycles.

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call or return

from subroutine, initial reset, internal interrupt, external

interrupt or return from interrupts, the PC manipulates

the program transfer by loading the address corre-

sponding to each instruction.

Instruction fetching and execution are pipelined in such

a way that a fetch takes an instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme allows each instruction

to be effectively executed in a cycle. If an instruction

changes the program counter, two cycles are required to

complete the instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get the proper instruction.

Otherwise proceed to the next instruction.

Program Counter - PC

The lower byte of the program counter (PCL) is a read-

able and writeable register (06H). Moving data into the

PCL performs a short jump. The destination will be

within the current program ROM page.

The program counter (PC) controls the sequence in

which the instructions stored in the program ROM are

executed and its contents specify a full range of pro-

gram memory.

When a control transfer takes place, an additional

dummy cycle is required.

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

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2

(

R

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P

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P

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+

1

P

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+

2

P

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F

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I

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S

T

(

P

C

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E

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S

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(

P

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1

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F

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(

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+

2

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E

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(

P

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+

1

)

Execution Flow

Program Counter

Mode

*11

0

*10

0

*9

0

*8

0

*7

0

*6

0

*5

0

*4

0

*3

0

*2

0

*1

0

*0

0

Initial reset

USB interrupt

0

1

0

Timer/Event Counter 0 overflow

Timer/Event Counter 1 overflow

Skip

0

1

0

1

0

Program Counter+2

@7 @6 @5 @4 @3 @2 @1 @0

Loading PCL

*11

*10

*9

#9

S9

*8

#8

S8

Jump, call branch

#11 #10

S11 S10

#7

S7

#6

S6

#5

S5

#4

S4

#3

S3

#2

S2

#1

S1

#0

S0

Return from subroutine

Program Counter

Note: *11~*0: Program counter bits

#11~#0: Instruction code bits

S11~S0: Stack register bits

@7~@0: PCL bits

Rev. 1.80

6

December 28, 2007

HT82K95E/HT82K95A

·

Location 00CH

Program Memory - ROM

This location is reserved for the Timer/Event Counter

1 interrupt service program. If a timer interrupt results

from a Timer/Event Counter 1 overflow, and the inter-

rupt is enabled and the stack is not full, the program

begins execution at location 00CH.

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

4096´15 bits, addressed by the program counter and ta-

ble pointer.

·

Table location

Certain locations in the program memory are reserved

for special usage:

Any location in the program memory can be used as

look-up tables. There are three method to read the

ROM data by two table read instructions: ²TABRDC²

and ²TABRDL², transfer the contents of the

lower-order byte to the specified data memory, and

the higher-order byte to TBLH (08H).

·

Location 000H

This area is reserved for program initialization. After

chip reset, the program always begins execution at lo-

cation 000H.

·

Location 004H

The three methods are shown as follows:

This area is reserved for the USB interrupt service

program. If the USB interrupt is activated, the interrupt

is enabled and the stack is not full, the program begins

execution at location 004H.

¨

The instructions ²TABRDC [m]² (the current page,

one page=256words), where the table locations is

defined by TBLP (07H) in the current page. And the

ROM code option TBHP is disabled (default).

¨

The instructions ²TABRDC [m]², where the table lo-

·

Location 008H

cations is defined by registers TBLP (07H) and

TBHP (01FH). And the ROM code option TBHP is

enabled.

This area is reserved for the Timer/Event Counter 0 in-

terrupt service program. If a timer interrupt results

from a Timer/Event Counter 0 overflow, and if the in-

terrupt is enabled and the stack is not full, the program

begins execution at location 008H.

¨

The instructions ²TABRDL [m]², where the table lo-

cations is defined by Registers TBLP (07H) in the

last page (0F00H~0FFFH).

0

H

Only the destination of the lower-order byte in the ta-

ble is well-defined, the other bits of the table word are

transferred to the lower portion of TBLH, and the re-

maining 1-bit words are read as ²0². The Table

Higher-order byte register (TBLH) is read only. The ta-

ble pointer (TBLP, TBHP) is a read/write register (07H,

1FH), which indicates the table location. Before ac-

cessing the table, the location must be placed in the

TBLP and TBHP (If the OTP option TBHP is disabled,

the value in TBHP has no effect). The TBLH is read

only and cannot be restored. If the main routine and

the ISR (Interrupt Service Routine) both employ the

table read instruction, the contents of the TBLH in the

main routine are likely to be changed by the table read

instruction used in the ISR. Errors can occur. In other

words, using the table read instruction in the main rou-

tine and the ISR simultaneously should be avoided.

However, if the table read instruction has to be applied

in both the main routine and the ISR, the interrupt

should be disabled prior to the table read instruction.

D

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Program Memory

Table Location

Instruction

*11

P11

1

*10

P10

1

*9

P9

1

*8

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

P8

1

@7

@6

@5

@4

@3

@2

@1

@0

Table Location

Note: *11~*0: Table location bits

@7~@0: Table pointer bits

P11~P8: Current program counter bits when TBHP is disabled

TBHP register bit3~bit0 when TBHP is enabled

Rev. 1.80

7

December 28, 2007

HT82K95E/HT82K95A

B

a

n

k

0

It will not be enabled until the TBLH has been backed

up. All table related instructions require two cycles to

complete the operation. These areas may function as

normal program memory depending on the require-

ments.

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A

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M

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M

s

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0

1

2

3

4

5

6

7

8

9

H

P

0

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t

A

d

r

s

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g

R

e

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1

P

1

B

P

Once TBHP is enabled, the instruction ²TABRDC [m]²

reads the ROM data as defined by TBLP and TBHP

value. Otherwise, the ROM code option TBHP is dis-

abled, the instruction ²TABRDC [m]² reads the ROM

data as defined by TBLP and the current program

counter bits.

A

C

P

C

L

T

B

L

P

T

B

L

H

W

D

T

S

T

A

T

U

S

0

A

B

H

I

N

T

C

Stack Register - STACK

0

C

D

H

T

M

R

0

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 8 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledge signal, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

T

M

R

0

1

C

H

0

E

H

0

F

H

S

p

e

c

i

a

l

P

u

r

p

o

s

e

D

a

t

a

M

e

m

o

r

y

T

M

R

1

L

1

0

1

2

3

4

5

6

7

8

9

T

M

R

1

C

P

A

P

A

C

P

B

P

B

C

P

C

P

C

D

C

D

P

C

1

A

B

H

U

S

C

U

S

R

C

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 8 return ad-

dresses are stored).

1

C

D

H

C

1

E

H

1

F

H

T

B

H

P

2

0

H

G

e

n

e

r

a

l

P

u

r

p

o

s

e

D

a

t

a

M

e

m

o

r

y

(

1

6

0

B

y

t

e

s

)

:

U

n

u

s

e

d

R

e

a

d

a

s

"

0

"

B

F

H

Data Memory - RAM for Bank 0

Bank 0 RAM Mapping

The data memory is designed with 190´8 bits. The

data memory is divided into two functional groups: spe-

cial function registers and general purpose data mem-

ory (160´8). Most are read/write, but some are read

only.

Watchdog Timer option setting register (WDTS;09H),

I/O registers (PA;12H, PB;14H, PC;16H, PD;18H), I/O

control registers (PAC;13H, PBC;15H, PCC;17H,

PDC;19H). USB/PS2 status and control register

(USC;1AH), USB endpoint interrupt status register

(USR;1BH), system clock control register (SCC;1CH).

The remaining space before the 20H is reserved for fu-

ture expansion usage and reading these locations will

get ²00H². The general purpose data memory, ad-

dressed from 20H to BFH, is used for data and control

information under instruction commands.

The special function registers include the indirect ad-

dressing registers (R0;00H, R1;02H), Bank register

(BP, 04H), Timer/Event Counter 0 (TMR0;0DH),

Timer/Event Counter 0 control register (TMR0C;0EH),

Timer/Event Counter 1 higher order byte register

(TMR1H;0FH), Timer/Event Counter 1 lower order byte

register (TMR1L;10H), Timer/Event Counter 1 control

register (TMR1C;11H), program counter lower-order

byte register (PCL;06H), memory pointer registers

(MP0;01H, MP1;03H), accumulator (ACC;05H), table

pointer (TBLP;07H, TBHP;1FH), table higher-order

byte register (TBLH;08H), status register

(STATUS;0AH), interrupt control register (INTC;0BH),

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP0 or MP1).

Rev. 1.80

8

December 28, 2007

HT82K95E/HT82K95A

Accumulator

Data Memory - RAM for Bank 1

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

The special function registers used in

interface are

located in RAM bank 1. In order to access the Bank1

register, only the Indirect addressing pointer MP1 can

be used and the Bank register BP should be set to ²1².

The mapping of RAM bank 1 is as shown.

Arithmetic and Logic Unit - ALU

Indirect Addressing Register

This circuit performs 8-bit arithmetic and logic opera-

tions. The ALU provides the following functions:

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] ([02H]) will access data memory pointed

to by MP0 (MP1). Reading location 00H (02H) itself indi-

rectly will return the result 00H. Writing indirectly results

in no operation.

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

·

Logic operations (AND, OR, XOR, CPL)

·

Rotation (RL, RR, RLC, RRC)

·

Increment and Decrement (INC, DEC)

·

The indirect addressing pointer (MP0) always point to

Bank0 RAM addresses regardless of the value of the

Bank Register (BP).

Branch decision (SZ, SNZ, SIZ, SDZ)

The ALU not only saves the results of a data operation

but also changes the status register.

The indirect addressing pointer (MP1) can access

Bank0 or Bank1 RAM data according to the value of BP

which is set to ²0² or ²1² respectively.

Status Register - STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PDF), and watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

The memory pointer registers (MP0 and MP1) are 8-bit

registers.

4

0

1

2

3

4

5

6

7

8

9

H

P

I

P

E

_

C

T

R

L

With the exception of the TO and PDF flags, bits in

the status register can be altered by instructions like

most other registers. Any data written into the status

register will not change the TO or PDF flag. In addi-

tion operations related to the status register may give

different results from those intended.

A

W

R

S

T

A

L

P

S

I

P

E

S

M

I

S

C

E

n

d

p

t

_

E

N

F

I

F

O

0

1

The TO flag can be affected only by system power-up, a

WDT time-out or executing the ²CLR WDT² or ²HALT²

instruction. The PDF flag can be affected only by ex-

ecuting the ²HALT² or ²CLR WDT² instruction or dur-

ing a system power-up.

F

I

F

O

2

4

A

B

H

4

C

H

U

n

d

e

f

i

n

e

d

,

r

e

s

e

r

v

e

d

f

o

r

f

u

t

u

r

e

x

p

a

n

s

i

o

n

F

H

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

Bank 1 RAM Mapping

Bit No.

Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

0

C

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

1

2

3

AC

Z

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

OV

PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by

executing the ²HALT² instruction.

4

PDF

TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.

5

TO

TO is set by a WDT time-out.

6~7

¾

Unused bit, read as ²0²

Status (0AH) Register

Rev. 1.80

9

December 28, 2007

HT82K95E/HT82K95A

In addition, on entering the interrupt sequence or exe-

cuting the subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status are important and if the subroutine can cor-

rupt the status register, precautions must be taken to

save it properly.

When the interrupt is enabled, the stack is not full and

the external interrupt is active, a subroutine call to loca-

tion 04H will occur. The interrupt request flag (USBF)

and EMI bits will be cleared to disable other interrupts.

When the PC Host access the FIFO of the HT82K95E/

HT82K95A, the corresponding request bit of the USR is

set, and a USB interrupt is triggered. So user can easily

decide which FIFO is accessed. When the interrupt has

been served, the corresponding bit should be cleared by

firmware. When the HT82K95E/HT82K95A receives a

USB Suspend signal from the Host PC, the suspend line

(bit0 of the USC) of the HT82K95E/HT82K95A is set

and a USB interrupt is also triggered.

Interrupt

The device provides an external interrupt and internal

timer/event counter interrupts. The Interrupt Control

Register (INTC;0BH) contains the interrupt control bits

to set the enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt requires servicing within the service routine, the

EMI bit and the corresponding bit of the INTC may be set

to allow interrupt nesting. If the stack is full, the interrupt

request will not be acknowledged, even if the related in-

terrupt is enabled, until the SP is decremented. If immedi-

ate service is desired, the stack must be prevented from

becoming full.

Also when the HT82K95E/HT82K95A receives a Re-

sume signal from the Host PC, the resume line (bit3 of

the USC) of HT82K95E/HT82K95A is set and a USB in-

terrupt is triggered.

Whenever a USB reset signal is detected, the USB in-

terrupt is triggered.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F; bit 5 of INTC), caused by a timer 0

overflow. When the interrupt is enabled, the stack is not

full and the T0F bit is set, a subroutine call to location

08H will occur. The related interrupt request flag (T0F)

will be reset and the EMI bit cleared to disable further in-

terrupts.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

(STATUS) are altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents should be saved in advance.

The internal Timer/Even Counter 1 interrupt is initialized

by setting the Timer/Event Counter 1 interrupt request

flag (T1F; bit 6 of INTC), caused by a timer 1 overflow.

When the interrupt is enabled, the stack is not full and

the T1F is set, a subroutine call to location 0CH will oc-

cur. The related interrupt request flag (T1F) will be reset

and the EMI bit cleared to disable further interrupts.

USB interrupts are triggered by the following USB

events and the related interrupt request flag (USBF; bit

4 of the INTC) will be set.

During the execution of an interrupt subroutine, other in-

terrupt acknowledge signals are held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set to ²1² (if the stack is not full).

To return from the interrupt subroutine, ²RET² or ²RETI²

may be invoked. RETI will set the EMI bit to enable an in-

terrupt service, but RET will not.

·

The corresponding USB FIFO is accessed from the

PC

·

The USB suspends signal from the PC

·

The USB resumes signal from the PC

·

The USB sends Reset signal

Bit No.

Label

EMI

EUI

Function

0

1

2

3

4

5

6

7

Controls the master (global) interrupt (1= enabled; 0= disabled)

Controls the USB interrupt (1= enabled; 0= disabled)

Controls the Timer/Event Counter 0 interrupt (1= enabled; 0= disabled)

Controls the Timer/Event Counter 1 interrupt (1= enabled; 0= disabled)

USB interrupt request flag (1= active; 0= inactive)

ET0I

ET1I

USBF

T0F

T1F

¾

Internal Timer/Event Counter 0 request flag (1= active; 0= inactive)

Internal Timer/Event Counter 1 request flag (1= active; 0= inactive)

Unused bit, read as ²0²

INTC (0BH) Register

Rev. 1.80

10

December 28, 2007

HT82K95E/HT82K95A

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

A crystal across OSC1 and OSC2 is needed to provide

the feedback and phase shift required for the oscillator.

No other external components are required. In stead of

a crystal, a resonator can also be connected between

OSC1 and OSC2 to get a frequency reference, but two

external capacitors in OSC1 and OSC2 are required.

These can be masked by resetting the

bit.

No.

a

Interrupt Source

USB interrupt

Priority Vector

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode, the system

clock is stopped, but the WDT oscillator still works within

a period of approximately 31ms. The WDT oscillator can

be disabled by ROM code option to conserve power.

1

2

3

04H

08H

0CH

b

Timer/Event Counter 0 overflow

Timer/Event Counter 1 overflow

c

The Timer/Event Counter 0/1 interrupt request flag

(T0F/T1F), USB interrupt request flag (USBF), enable

Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en-

able USB interrupt bit (EUI) and enable master interrupt

bit (EMI) constitute an interrupt control register (INTC)

which is located at 0BH in the data memory. EMI, EUI,

ETI are used to control the enabling/disabling of inter-

rupts. These bits prevent the requested interrupt from

being serviced. Once the interrupt request flags (TF,

USBF) are set, they will remain in the INTC register until

the interrupts are serviced or cleared by a software in-

struction.

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator), or instruction clock (sys-

tem clock divided by 4), determines the ROM code op-

tion. This timer is designed to prevent a software

malfunction or sequence from jumping to an unknown

location with unpredictable results. The Watchdog

Timer can be disabled by ROM code option. If the

Watchdog Timer is disabled, all the executions related

to the WDT result in no operation.

Once the internal WDT oscillator (RC oscillator, nor-

mally with a period of 31ms/5V) is selected, it is first di-

vided by 256 (8-stage) to get the nominal time-out

period of 8ms/5V. This time-out period may vary with

temperatures, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the

WDTS) can give different time-out periods. If WS2,

WS1, and WS0 are all equal to 1, the division ratio is up

to 1:128, and the maximum time-out period is 1s/5V. If

the WDT oscillator is disabled, the WDT clock may still

come from the instruction clock and operates in the

same manner except that in the HALT state the WDT

may stop counting and lose its protecting purpose. In

this situation the logic can only be restarted by external

logic. The high nibble and bit 3 of the WDTS are re-

served for user¢s defined flags, which can only be set to

²10000² (WDTS.7~WDTS.3).

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. In-

terrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications.

If only one stack is left and enabling the interrupt is not

well controlled, the original control sequence will be dam-

aged once the ²CALL² operates in the interrupt subrou-

tine.

Oscillator Configuration

There is an oscillator circuits in the microcontroller.

O

S

C

1

O

S

C

2

C

r

y

s

t

a

l

O

s

c

i

l

a

t

o

r

System Oscillator

If the device operates in a noisy environment, using the

on-chip 32kHz RC oscillator (WDT OSC) is strongly rec-

ommended, since the HALT will stop the system clock.

This oscillator is designed for system clocks. The HALT

mode stops the system oscillator and ignores an exter-

nal signal to conserve power.

W

D

T

P

r

e

s

c

a

l

e

r

S

y

s

t

e

m

C

l

o

c

k

/

4

R

O

M

8

-

b

i

t

C

o

u

n

t

e

r

7

-

b

i

t

C

o

u

n

t

e

r

C

o

d

e

O

p

t

i

o

n

W

D

T

S

e

l

e

c

t

O

S

C

8

-

t

o

-

1

M

U

X

W

S

0

~

W

S

2

W

D

T

i

m

e

-

o

u

t

Watchdog Timer

Rev. 1.80

11

December 28, 2007

HT82K95E/HT82K95A

WS2

WS1

WS0

Division Ratio

cuting the ²HALT² instruction. The TO flag is set if the

WDT time-out occurs, and causes a wake-up that only

resets the Program Counter and SP, the others remain

in their original status.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

1:4

The I/O ports wake-up and interrupt methods can be

considered as a continuation of normal execution. Each

bit in the Port A can be independently selected to wake

up the device by option. PB, PC and PD can also be se-

lected to wake up the device by option. Upon awakening

from an I/O port stimulus, the program will resume exe-

cution of the next instruction. If it awakens from an inter-

rupt, two sequence may occur. If the related interrupt is

disabled or the interrupt is enabled but the stack is full,

the program will resume execution at the next instruc-

tion. If the interrupt is enabled and the stack is not full,

the regular interrupt response takes place. If an interrupt

request flag is set to ²1² before entering the HALT mode,

the wake-up function of the related interrupt will be dis-

abled. Once a wake-up event occurs, it takes 1024 t_SYS

(system clock period) to resume normal operation. In

other words, a dummy period will be inserted after a

wake-up. If the wake-up results from an interrupt ac-

knowledge signal, the actual interrupt subroutine execu-

tion will be delayed by one or more cycles. If the wake up

results in the next instruction execution, this will be exe-

cuted immediately after the dummy period is completed.

1:8

1:16

1:32

1:64

1:128

WDTS (09H) Register

The WDT overflow under normal operation will initialize

a ²chip reset² and set the status bit ²TO². But in the

HALT mode, the overflow will initialize a ²warm reset²

and only the Program Counter and SP are reset to zero.

To clear the contents of the WDT (including the WDT

prescaler), three methods are employed; external reset

(a low level to RES), software instruction and a ²HALT²

instruction. The software instruction include ²CLR

WDT² and the other set - ²CLR WDT1² and ²CLR

WDT2². Of these two types of instruction, only one can

be active depending on the ROM code option - ²CLR

WDT times selection option². If the ²CLR WDT² is se-

lected (i.e. CLRWDT times equal one), any execution of

the ²CLR WDT² instruction will clear the WDT. In the

case wherein ²CLR WDT1² and ²CLR WDT2² are cho-

sen (i.e. CLRWDT times is equal to two), these two in-

structions must be executed to clear the WDT,

otherwise, the WDT may reset the chip as a result of

time-out.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Reset

Therearethreewaysinwhicharesetcanoccur:

·

RES reset during normal operation

·

RES reset during HALT

·

WDT time-out reset during normal operation

Power Down Operation - HALT

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the Program Counter and SP, leav-

ing the other circuits in their original state. Some regis-

ters remain unchanged during other reset conditions.

Most registers are reset to the ²initial condition² when

the reset conditions are met. By examining the PDF and

TO flags, the program can distinguish between different

²chip resets².

The HALT mode is initialized by the ²HALT² instruction

and results in the following:

·

The system oscillator will be turned off but the WDT

oscillator remains running (if the WDT oscillator is se-

lected).

·

The contents of the on-chip RAM and registers remain

unchanged.

·

WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

·

All of the I/O ports maintain their original status.

0

u

0

1

0

u

0

u

1

·

The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on I/O ports or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a ²warm reset². After the TO and PDF flags are

examined, the cause for chip reset can be determined.

The PDF flag is cleared by a system power-up or exe-

cuting the ²CLR WDT² instruction and is set when exe-

WDT time-out during normal operation

WDT wake-up HALT

Note: ²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

Rev. 1.80

12

December 28, 2007

HT82K95E/HT82K95A

H

A

L

T

extra delay of 1024 system clock pulses when the sys-

tem resets (power-up, WDT time-out or RES reset) or

when the system awakes from the HALT state.

W

a

r

m

R

e

s

e

t

W

D

T

When a system reset occurs, an SST delay is added

during the reset period. Any wake up from HALT will en-

able the SST delay.

R

E

S

C

o

l

d

R

e

s

e

t

S

T

1

0

-

b

i

t

R

i

p

l

e

O

S

C

1

C

o

u

n

t

e

r

V

D

R

E

S

t

S S T

S

y

s

t

e

m

R

e

s

e

t

S

T

i

m

e

-

o

u

t

Reset Configuration

C

h

i

p

R

e

s

e

t

The functional unit chip reset status are shown below.

Reset Timing Chart

Program Counter

Interrupt

000H

V

D

Disable

Clear

Prescaler

Clear. After master reset,

WDT begins counting

R

E

S

WDT

Timer/event Counter Off

Input/output Ports

Stack Pointer

Input mode

Points to the top of the stack

Reset Circuit

The status of the registers are summarized in the following table.

WDT

RES Reset

(Normal

Operation)

WDT

Time-Out

(HALT)*

Reset

(Power On)

Time-out

(Normal

Operation)

RES Reset

(HALT)

USB-Reset USB-Reset

(HALT)

Register

(Normal)

TMR0

xxxx xxxx

00-0 1000

xxxx xxxx

00-0 1---

0000 0000

00-0 1000

0000 0000

00-0 1---

0000 0000

00-0 1000

0000 0000

00-0 1---

0000 0000

00-0 1000

0000 0000

00-0 1---

uuuu uuuu

uu-u uuuu

uuuu uuuu

uu-u u---

uuuu uuuu

00-0 1000

uuuu uuuu

00-0 1---

uuuu uuuu

00-0 1000

uuuu uuuu

00-0 1---

TMR0C

TMR1H

TMR1L

TMR1C

Program

Counter

000H

MP0

MP1

ACC

TBLP

TBLH

STATUS

INTC

WDTS

PA

xxxx xxxx

-xxx xxxx

--00 xxxx

uuuu uuuu

-uuu uuuu

--1u uuuu

-000 0000

1000 0111

1111 1111

uuuu uuuu

-uuu uuuu

--uu uuuu

-000 0000

1000 0111

1111 1111

uuuu uuuu

-uuu uuuu

--00 uuuu

-000 0000

1000 0111

1111 1111

uuuu uuuu

-uuu uuuu

--11 uuuu

-uuu uuuu

uuuu uuuu

-uuu uuuu

--uu uuuu

-000 0000

1000 0111

1111 1111

uuuu uuuu

-uuu uuuu

--01 uuuu

-000 0000

1000 0111

1111 1111

-000 0000

1000 0111

1111 1111

PAC

PB

PBC

PC

PCC

PD

Rev. 1.80

13

December 28, 2007

HT82K95E/HT82K95A

WDT

RES Reset

(Normal

Operation)

WDT

Time-Out

(HALT)*

Reset

(Power On)

Time-out

(Normal

Operation)

RES Reset

(HALT)

USB-Reset USB-Reset

(HALT)

Register

(Normal)

PDC

1111 1111

uuuu uuuu

uuxx uuuu

uuuu uuuu

1111 1111

0000 0110

0000 0000

0000 0110

0x0x x000

0000 0000

0000 0111

uuuu uuuu

11xx 0000

0000 0000

1111 1111

0000 0110

0000 0000

0000 0110

0x0x x000

0000 0000

0000 0111

uuuu uuuu

11xx 0000

0000 0000

uuuu uuuu

uuxx uuuu

uuuu uuuu

1111 1111

0000 0110

0000 0000

0000 0110

0x0x x000

0000 0000

0000 0111

0000 0000

uu00 0u00

u1uu 0000

0uu0 u000

1111 1111

0000 0110

0000 0000

0000 0110

0x0x x000

0000 0000

0000 0111

0000 0000

uu00 0u00

u1uu 0000

0uu0 u000

PIPE_CTRL 0000 0110

AWR

0000 0000

0000 0110

0x0x x000

0000 0000

0000 0111

xxxx xxxx

11xx 0000

0000 0000

PIPE

STALL

SIES

MISC

Endpt_EN

FIFO0

FIFO1

FIFO2

USC

USR

SCC

Note:

²*² stands for ²warm reset²

²u² stands for ²unchanged²

²x² stands for ²unknown²

Timer/Event Counter

Two timer/event counters (TMR0, TMR1) are imple-

mented in the microcontroller. The Timer/Event Counter

0 contains an 8-bit programmable count-up counter and

the clock may comes from an external source or from

The Timer/Event Counter 1 contains an 16-bit program-

mable count-up counter and the clock may come from

an external source or from the system clock divided by

4.

f_SYS/4.

Bit No.

Label

Function

0~2, 5

¾

Unused bit, read as ²0²

To define the TMR0 active edge of Timer/Event Counter 0

(0=active on low to high; 1=active on high to low)

3

4

TE

TON

To enable/disable timer 0 counting (0=disabled; 1=enabled)

To define the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

6

7

TM0

TM1

TMR0C (0EH) Register

Bit No.

Label

Function

0~2, 5

¾

Unused bit, read as ²0²

To define the TMR1 active edge of Timer/Event Counter 1

(0=active on low to high; 1=active on high to low)

3

4

TE

TON

To enable/disable timer 1 counting (0=disabled; 1=enabled)

To define the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

6

7

TM0

TM1

TMR1C (11H) Register

Rev. 1.80

14

December 28, 2007

HT82K95E/HT82K95A

D

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Timer/Event Counter 0

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Timer/Event Counter 1

Using the internal clock source, there is only 1 reference

time-base for Timer/Event Counter 0. The internal clock

source is coming from f_SYS/4.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source comes from an external

(TMR0/TMR1) pin. The timer mode functions as a nor-

mal timer with the clock source coming from the f_SYS/4

(Timer0/Timer1). The pulse width measurement mode

can be used to count the high or low level duration of the

external signal (TMR0/TMR1). The counting is based on

the f_SYS/4 (Timer0/Timer1).

The external clock input allows the user to count exter-

nal events, measure time intervals or pulse widths.

Using the internal clock source, there is only 1 reference

time-base for Timer/Event Counter 1. The internal clock

source is coming from f_SYS/4. The external clock input

allows the user to count external events, measure time

intervals or pulse widths.

In the event count or timer mode, once the Timer/Event

Counter 0/1 starts counting, it will count from the current

contents in the Timer/Event Counter 0/1 to FFH or

FFFFH. Once overflow occurs, the counter is reloaded

from the Timer/Event Counter 0/1 preload register and

generates the interrupt request flag (T0F/T1F; bit 5/6 of

INTC) at the same time.

There are 2 registers related to the Timer/Event Counter

0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical regis-

ters are mapped to TMR0 location; writing TMR0 makes

the starting value be placed in the Timer/Event Counter

0 preload register and reading TMR0 gets the contents

of the Timer/Event Counter 0. The TMR0C is a

timer/event counter control register, which defines some

options.

In the pulse width measurement mode with the TON

and TE bits equal to one, once the TMR0/TMR1 has re-

ceived a transient from low to high (or high to low if the

TE bits is ²0²) it will start counting until the TMR0/TMR1

returns to the original level and resets the TON. The

measured result will remain in the Timer/Event Counter

0/1 even if the activated transient occurs again. In other

words, only one cycle measurement can be done. Until

setting the TON, the cycle measurement will function

again as long as it receives further transient pulse. Note

that, in this operating mode, the Timer/Event Counter

0/1 starts counting not according to the logic level but

according to the transient edges. In the case of counter

overflows, the counter 0/1 is reloaded from the

Timer/Event Counter 0/1 preload register and issues the

interrupt request just like the other two modes. To en-

able the counting operation, the timer ON bit (TON; bit 4

There are 3 registers related to Timer/Event Counter 1;

TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing

TMR1L will only put the written data to an internal

lower-order byte buffer (8 bits) and writing TMR1H will

transfer the specified data and the contents of the

lower-order byte buffer to TMR1H and TMR1L preload

registers, respectively. The Timer/Event Counter 1

preload register is changed by each writing TMR1H op-

erations. Reading TMR1H will latch the contents of

TMR1H and TMR1L counters to the destination and the

lower-order byte buffer, respectively. Reading the

TMR1L will read the contents of the lower-order byte

buffer. The TMR1C is the Timer/Event Counter 1 control

register, which defines the operating mode, counting en-

able or disable and active edge.

Rev. 1.80

15

December 28, 2007

HT82K95E/HT82K95A

of TMR0C/TMR1C) should be set to 1. In the pulse width

measurement mode, the TON will be cleared automati-

cally after the measurement cycle is completed. But in

the other two modes the TON can only be reset by in-

structions. The overflow of the Timer/Event Counter 0/1

is one of the wake-up sources. No matter what the oper-

ation mode is, writing a 0 to ET0I/ET1I can disable the

corresponding interrupt services.

or Schmitt trigger input with or without pull-high resistor

structures can be reconfigured dynamically under soft-

ware control. To function as an input, the corresponding

latch of the control register must write a ²1². The input

source also depends on the control register. If the con-

trol register bit is ²1², the input will read the pad state. If

the control register bit is ²0², the contents of the latches

will move to the internal bus. The latter is possible in the

²read-modify-write² instruction. For output function,

CMOS/NMOS/PMOS configurations can be selected

(NMOS and PMOS are available for PA only). These

control registers are mapped to locations 13H, 15H, 17H

and 19H.

In the case of Timer/Event Counter 0/1 OFF condition,

writing data to the Timer/Event Counter 0/1 preload reg-

ister will also reload that data to the Timer/Event Coun-

ter 0/1. But if the Timer/Event Counter 0/1 is turned on,

data written to it will only be kept in the Timer/Event

Counter 0/1 preload register. The Timer/Event Counter

0/1 will still operate until overflow occurs (a Timer/Event

Counter 0/1 reloading will occur at the same time).

When the Timer/Event Counter 0/1 (reading

TMR0/TMR1) is read, the clock will be blocked to avoid

errors. As clock blocking may results in a counting error,

this must be taken into consideration by the program-

mer.

After a chip reset, these input/output lines remain at high

levels or floating state (depending on the pull-high op-

tions). Each bit of these input/output latches can be set

or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H or 18H) instructions.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Input/Output Ports

There are 32 bidirectional input/output lines in the

microcontroller, labeled from PA to PD, which are

mapped to the data memory of [12H], [14H], [16H] and

[18H] respectively. All of these I/O ports can be used for

input and output operations. For input operation, these

ports are non-latching, that is, the inputs must be ready

at the T2 rising edge of instruction ²MOV A,[m]² (m=12H,

14H, 16H or 18H). For output operation, all the data is

latched and remains unchanged until the output latch is

rewritten.

Each line of all the I/O ports have the capability of wak-

ing up the device.

There are pull-high (PA only) options available for I/O

lines. Once the pull-high option of an I/O line is selected,

the I/O line have pull-high resistor. Otherwise, the

pull-high resistor is absent. It should be noted that a

non-pull-high I/O line operating in input mode will cause

a floating state.

Each I/O line has its own control register (PAC, PBC,

PCC, PDC) to control the input/output configuration.

With this control register, CMOS/NMOS/PMOS output

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

V

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Input/Output Ports

Rev. 1.80

16

December 28, 2007

HT82K95E/HT82K95A

Suspend Wake-Up and Remote Wake-Up

Low Voltage Reset - LVR

If there is no signal on the USB bus for over 3ms, the

HT82K95E/HT82K95A will go into suspend mode. The

Suspend line (bit 0 of the USC) will be set to ²1² and a

USB interrupt is triggered to indicate that the

HT82K95E/HT82K95A should jump to the suspend

state to meet the 500mA USB suspend current spec.

The microcontroller contains a low voltage reset circuit

in order to monitor the supply voltage of the device. If the

supply voltage of the device drops to within a range of

0.9V~V_LVRsuch as might occur when changing the bat-

tery, the LVR will automatically reset the device inter-

nally.

The LVR includes the following specifications:

In order to meet the 500mA suspend current, the firm-

ware should disable the USB clock by clearing the

USBCKEN (bit3 of the SCC) to ²0². The suspend cur-

rent is 400mA.

·

For a valid LVR signal, a low voltage i.e. a voltage in

the range between 0.9V~V_LVRmust exist for greater

than 1ms. If the low voltage state does not exceed

1ms, the LVR will ignore it and do not perform a reset

function.

User can further decrease the suspend current to 250mA

by setting the SUSP2 (bit4 of the SCC). If in USB mode

set this bit LVR OPT must disable

·

The LVR uses the ²OR² function with the external

RES signal to perform chip reset.

When the resume signal is sent out by the host, the

HT82K95E/HT82K95Awill wake up the MCU by USB in-

terrupt and the Resume line (bit 3 of the USC) is set. In

order to make the HT82K95E/HT82K95A function prop-

erly, the firmware must set the USBCKEN (bit 3 of the

SCC) to ²1² and clear the SUSP2 (bit4 of the SCC).

Since the Resume signal will be cleared before the Idle

signal is sent out by the host, the Suspend line (bit 0 of

the USC) will be set to ²0². So when the MCU is detect-

ing the Suspend line (bit0 of USC), the Resume line

should be remembered and taken into consideration.

The relationship between V_DDand V_LVRis shown below.

V

D

V

O P R

5

.

5

V

5

.

5

V

L

V

R

3

.

3

V

3

.

0

V

After finishing the resume signal, the suspend line will

go inactive and a USB interrupt is triggered. The follow-

ing is the timing diagram.

0

.

9

V

_OPRis the voltage range for proper chip opera-

Note:

tion at 4MHz system clock.

V

D

5

.

5

V

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*

1

*

2

Low Voltage Reset

Note: *1. To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system

clock pulses before entering the normal operation.

*2. Since low voltage has to be maintained for over 1ms in its original state, therefore there¢s a 1ms delay

before entering the reset mode

Rev. 1.80

17

December 28, 2007

HT82K95E/HT82K95A

To Configure the HT82K95E/HT82K95A as PS2 De-

vice

S

U

S

P

E

N

D

The HT82K95E/HT82K95A can be configured as a USB

interface or PS2 interface device, by configuring the

SPS2 (bit 4 of USR) and SUSB (bit 5 of the USR). If

SPS2=1, and SUSB=0, the HT82K95E/HT82K95A is

configured as a PS2 interface, pin USBD- is configured

as a PS2 Data pin and USBD+ is configured as a PS2

Clk pin. User can easily read or write to the PS2 Data or

PS2 Clk pin by accessing the corresponding bit PS2DAI

(bit 4 of the USC), PS2CKI (bit 5 of the USC), PS2DAO

(bit 6 of the USC) and S2CKO (bit 7 of the USC) respec-

tively.

U

S

B

R

e

s

u

m

e

S

i

g

n

a

l

U

S

B

_

I

N

T

The device with remote wake up function can wake up

the USB Host by sending a wake-up pulse through

RMWK (bit 1 of the USC). Once the USB Host receives

a wake-up signal from the HT82K95E/HT82K95A, it will

send a Resume signal to the device. The timing is as fol-

lows:

User should make sure that in order to read the data

properly, the corresponding output bit must be set to ²1².

For example, if it is desired to read the PS2 Data by

reading PS2DAI, the PS2DAO should set to ²1². Other-

wise it is always read as ²0².

S

U

S

P

E

N

D

M

i

n

.

1

U

S

B

C

L

K

R

M

W

K

M

i

n

.

2

.

5

m

s

If SPS2=0, and SUSB=1, the HT82K95E/HT82K95A is

configured as a USB interface. Both the USBD- and

USBD+ is driven by the SIE of the HT82K95E/

HT82K95A. User can only write or read the USB data

through the corresponding FIFO.

U

S

B

R

e

s

u

m

e

S

i

g

n

a

l

U

S

B

_

I

N

T

Both SPS2 and SUSB default is ²0².

USB Interface

There are ten registers, including PIPE_CTRL (41H in bank 1), AWR (address + remote wake-up 42H in bank 1),

STALL (43H in bank 1), PIPE (44H in bank 1), SIES (45H in bank 1), MISC (46H in bank 1), Endpt_EN (47H in bank 1),

FIFO0 (48H in bank 1), FIFO1 (49H in bank 1), and FIFO2 (4AH in bank 1) used for the USB function. AWR register

contains current address and a remote wake up function control bit. The initial value of AWR is ²00H². The address

value extracted from the USB command is not to be loaded into this register until the SETUP stage is completed.

Bit No.

0

Label

WKEN

R/W

W

Function

Remote wake-up enable/disable

USB device address

7~1

AD6~AD0

W

AWR (42H) Register

STALL and PIPE, PIPE_CTRL, Endpt_EN Registers

PIPE register represents whether the endpoint corresponding is accessed by host or not. After ACT_EN signal being

sent out, MCU can check which endpoint had been accessed. This register is set only after the time when host access

the corresponding endpoint.

STALL register shows whether the endpoint corresponding works or not. As soon as the endpoint work improperly, the

bit corresponding must be set.

PIPE_CTRL Register is used for configuring IN (Bit=1) or OUT (Bit=0)Pipe. The default is define IN pipe. Where Bit0

(DATA0) of the PIPE_CTRL Register is used to setting the data toggle of any endpoint (except endpoint0) using data

toggles to the value DATA0. Once the user want the any endpoint (except endpoint0) using data toggles to the value

DATA0. the user can output a LOW pulse to this bit. The LOW pulse period must at least 10 instruction cycle.

Endpt_EN Register is used to enable or disable the corresponding endpoint (except endpoint 0) Enable Endpoint

(Bit=1) or disable Endpoint (Bit=0)

Rev. 1.80

18

December 28, 2007

HT82K95E/HT82K95A

The bitmaps are list as follows :

Register

Name

Register

Default

Value

R/W

Bit7~Bit3 Reserved

Bit 2

Bit 1

Bit 0

Address

01000001B

01000011B

01000100B

01000001B

PIPE_CTRL

STALL

R/W

R

Pipe 2

Pipe 1

Pipe 0 00000110

Pipe 0 00000000

Pipe 0 00000111

¾

PIPE

Endpt_EN

R/W

PIPE_CTRL (41H), STALL (43H), PIPE (44H) and Endpt_EN (47H) Registers

The SIES Register is used to indicate the present signal state which the SIE receives and also defines whether the SIE

has to change the device address automatically.

Bit7

NMI

R/W

Bit6

Bit5

Bit4

NAK

R

Bit3

IN

Bit2

OUT

R/W

Bit1

F0_ERR

R/W

Bit0

Adr_set

R/W

Func.

R/W

Reserved CRC_ERR

R/W

R

¾

Reg_ Adr

01000101B

SIES (45H) Register Table

Func. Name

R/W

Description

This bit is used to configure the SIE to automatically change the device address with

the value of the Address+Remote_WakeUp Register (42H).

When this bit is set to ²1² by F/W, the SIE will update the device address with the value

of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully

read the data from the device by the IN operation. The SIE will clear the bit after updat-

ing the device address. Otherwise, when this bit is cleared to ²0², the SIE will update

the device address immediately after an address is written to the Address+Re-

mote_WakeUp Register (42H)

Adr_ set

R/W

Default 0

This bit is used to indicate that some errors have occurred when accessing the FIFO0.

F0_Err

Out

R/W

This bit is set by SIE and cleared by F/W.

Default 0

This bit is used to indicate that an OUT token (except for the OUT zero length) has

been received. The F/W clear the bit after the OUT data has been read. This bit will

also be cleared by the SIE after the next valid SETUP token is received.

Default 0

This bit is used to indicate that the current signal the USB is receiving from the PC

Host is IN token.

IN

R

This bit is used to indicate that the SIE is transmitting NAK signal to the Host in re-

sponse to the PC Host IN or OUT token.

NAK

This bit is used to indicate there are CRCerror (bit=1). Firmware must do something to

save the device and keep it in good condition.

CRC_ERR

R/W

This bit is set by SIE and cleared by F/W.

Reserved

¾

This bit is used to control whether the USB interrupt is output to the MCU in NAK re-

sponse to the PC Host IN or OUT token. Only for Endpoint0

1: has only USB interrupt, data is transmitted to the PC host or data is received from

the PC Host

NMI

R/W

0: always has USB interrupt if the USB accesses FIFO0

Default 0

SIES Function Table

Rev. 1.80

19

December 28, 2007

HT82K95E/HT82K95A

MISC register combines a command and status to control desired endpoint FIFO action and to show the status of the

desired endpoint FIFO. The MISC will be cleared by USB reset signal.

Bit No.

Label

R/W

Function

After setting the other status of the desired one in the MISC, endpoint FIFO can be

0

REQ

R/W requested by setting this bit to ²1². After the job has been done, this bit has to be

cleared to ²0².

This bit defines the direction of data transferring between MCU and endpoint FIFO.

When the TX is set to ²1², this means that the MCU wants to write data to the end-

point FIFO. After the job has been done, this bit has to be cleared to ²0² before termi-

1

2

TX

R/W

nating request to represent the end of transferring. For reading action, this bit has to

be cleared to ²0² to represent that MCU wants to read data from the endpoint FIFO

and has to be set to ²1² after the job is done.

CLEAR

R/W Clear the requested endpoint FIFO, even if the endpoint FIFO is not ready.

Defines which endpoint FIFO is selected, SELP1,SELP0:

00: endpoint FIFO0

4

3

SELP1

SELP0

R/W 01: endpoint FIFO1

10: endpoint FIFO2

11: reserved

Used to show that the data in endpoint FIFO is a SETUP command. This bit has to

R/W be cleared by firmware. That is to say, even the MCU is busy, the device will not miss

any SETUP commands from the host.

5

SCMD

Read only status bit, this bit is used to indicate that the desired endpoint FIFO is

6

7

READY

LEN0

R

ready to work.

Used to indicate that a 0-sized packet is sent from a host to the MCU. This bit should

R/W

be cleared by firmware.

MISC (46H) Register

The MCU can communicate with the endpoint FIFO by setting the corresponding registers, of which address is listed in

the following table. After reading the current data, next data will show after 2ms, used to check the endpoint FIFO status

and response to MISC register, if read/write action is still going on.

Registers

FIFO0

R/W

Bank

Address

48H

Bit7~Bit0

1

Data7~Data0

FIFO1

49H

FIFO2

4AH

There are some timing constrains and usages illustrated here. By setting the MISC register, MCU can perform reading,

writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing

and clearing.

Actions

Read FIFO0 sequence

MISC Setting Flow and Status

00H®01H®delay 2ms, check 41H®read* from FIFO0 register and

check not ready (01H)®03H®02H

0AH®0BH®delay 2ms, check 4BH®write* to FIFO1 register and

check not ready (0BH)®09H®08H

Write FIFO1 sequence

Check whether FIFO0 can be read or not

Check whether FIFO1 can be written or not

Read 0-sized packet sequence form FIFO0

Write 0-sized packet sequence to FIFO1

00H®01H®delay 2ms, check 41H (ready) or 01H (not ready)®00H

0AH®0BH®delay 2ms, check 4BH (ready) or 0BH (not ready)®0AH

00H®01H®delay 2ms, check 81H®read once (01H)®03H®02H

0AH®0BH®delay 2ms, check 0BH®0FH®0DH®08H

Note:

*: There are 2ms existing between 2 reading action or between 2 writing action

Rev. 1.80

20

December 28, 2007

HT82K95E/HT82K95A

The definitions of the USB/PS2 status and control register (USC; 1AH) are as shown.

Bit No.

Label

R/W

Function

Read only, USB suspend indication. When this bit is set to ²1² (set by SIE), it indi-

cates the USB bus enters suspend mode. The USB interrupt is also triggered on any

changes of this bit.

0

SUSP

R

USB remote wake up command. It is set by MCU to force the USB host leaving the

suspend mode. When this bit is set to ²1², 2ms delay for clearing this bit to ²0² is

needed to insure the RMWK command is accepted by SIE.

1

2

RMWK

URST

W

USB reset indication. This bit is set/cleared by USB SIE. This bit is used to detect

which bus (PS2 or USB) is attached. When the URST is set to ²1², this indicates that

a USB reset has occurred (the attached bus is USB) and a USB interrupt will be ini-

tialized.

R/W

USB resume indication. When the USB leaves the suspend mode, this bit is set to

²1² (set by SIE). This bit will appear 20ms waiting for the MCU to detect. When the

RESUME is set by the SIE, an interrupt will be generated to wake-up the MCU. In or-

der to detect the suspend state, the MCU should set the USBCKEN and clear

SUSP2 (in SCC register) to enable the SIE detecting function. The RESUME will be

cleared while the SUSP is going ²0². When the MCU is detecting the SUSP, the RE-

SUME (wakes-up the MCU ) should be remembered and taken into consideration.

3

RESUME

R

4

5

PS2DAI

PS2CKI

R

Read only, USBD-/DATA input

Read only, USBD+/CLK input

Data for driving the USBD-/DATA pin when working under 3D PS2 mouse function.

6

7

PS2DAO

PS2CKO

W

(Default=²1²)

Data for driving the USBD+/CLK pin when working under 3D PS2 mouse function.

(Default=²1²)

USC (1AH) Register

The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select

the serial bus (PS2 or USB). The endpoint request flags (EP0IF, EP1IF and EP2IF) are used to indicate which end-

points are accessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and the USB inter-

rupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served,

the endpoint request flag has to be cleared to ²0².

Bit No.

Label

R/W

Function

When this bit is set to ²1² (set by the SIE), it indicates the endpoint 0 is accessed and

a USB interrupt will occur. When the interrupt has been served, this bit should be

cleared by firmware.

0

EP0IF

R/W

When this bit is set to ²1² (set by the SIE), it indicates the endpoint 1 is accessed and

a USB interrupt will occur. When the interrupt has been served, this bit should be

cleared by firmware.

1

2

EP1IF

EP2IF

R/W

When this bit is set to ²1² (set by the SIE), it indicates the endpoint 2 is accessed and

a USB interrupt will occur. When the interrupt has been served, this bit should be

cleared by firmware.

3, 6

4

Reserved

¾

SPS2

SUSB

R/W

The PS2 function is selected when this bit is set to ²1². (Default=²0²)

The USB function is selected when this bit is set to ²1². (Default=²0²)

5

This flag is used to show the MCUis in USB mode. (Bit=1)

7

USB_flag R/W

This bit is R/W by FW and will be cleared to ²0² after power-on reset. (Default=²0²)

USR (1BH) Register

Rev. 1.80

21

December 28, 2007

HT82K95E/HT82K95A

There is a system clock control register implemented to select the clock used in the MCU. This register consists of the

USB clock control bit (USBCKEN), second suspend mode control bit (SUSP2) and system clock selection (SYSCLK).

Bit No.

Label

R/W

Function

2~0, 7

¾

Undefined, should be cleared to ²0²

USB clock control bit. When this bit is set to ²1², it indicates that the USB clock is en-

abled. Otherwise, the USB clock is turned-off. (Default=²0²)

3

USBCKEN R/W

This bit is used to reduce power consumption in the suspend mode. In the normal

mode this bit must be cleared to zero (Default=0). In the HALT mode this bit should

be set high to reduce power consumption. If in USB mode set this bit LVR OPT must

disable

4

SUSP2

R/W

This flag is used to show the MCUis under PS2 mode. (Bit=1)

5

6

PS2_flag R/W

This bit is R/W by FW and will be cleared to ²0² after power-on reset. (Default=²0²)

This bit is used to specify the system oscillator frequency used by the MCU. If a

SYSCLK R/W 6MHz crystal oscillator or resonator is used, this bit should be set to ²1². If a 12MHz

crystal oscillator or resonator is used, this bit should be cleared to ²0² (default).

SCC (1CH) Register

Table High Byte Pointer for Current Table Read TBHP (Address 0X1F)

Register

Bits

Labels

Read/Write

Option

Functions

TBHP (0X1F)

3~0

PGC3~PGC0

R

Store current table read bit11~bit8 data

¾

Options

The following table shows all kinds of option in the microcontroller. All of the options must be defined to ensure proper

system functioning.

No.

1

Option

Chip lock bit (by bit)

2

PA0~PA7 pull-high resistor enabled or disabled (by bit)

PB0~PB7 pull-high resistor enabled or disabled (by nibble)

PC0~PC7 pull-high resistor enabled or disabled (by nibble)

PD0~PD7 pull-high resistor enabled or disabled (by nibble)

LVR enable or disable

3

4

5

6

7

WDT enable or disable

8

WDT clock source: f_SYS/4 or WDTOSC

9

²CLRWDT² instruction(s): 1 or 2

10

11

12

13

14

15

PA0~PA7 output structures: CMOS/NMOS open-drain/PMOS open-drain (by bit)

PA0~PA7 wake-up enabled or disabled (by bit)

PB0~PB7 wake-up enabled or disabled (by nibble)

PC0~PC7 wake-up enabled or disabled (by nibble)

PD0~PD7 wake-up enabled or disabled (by nibble)

TBHP enable or disable (default disable)

Rev. 1.80

22

December 28, 2007

HT82K95E/HT82K95A

Application Circuits

Crystal or Ceramic Resonator for Multiple I/O Applications for HT82K95E

P

A

B

0

~

P

A

B

7

3

W

5

W

*

V

D

V

D

*

U

S

B

-

m

0 . 1 F

1

0

k

1

m

0 F

P

C

D

0

~

P

C

D

7

m

0 . 1 F

1

M

W

*

U

S

B

+

V

S

1

.

5

k

O

S

C

1

V

3

O

X

1

*

m

0 . 1 F

*

4

7

p

F

*

5

W

O

S

C

2

3

W

*

1

0

k

U

S

B

D

-

/

D

A

T

A

R

E

S

4

7

p

F

*

4

7

p

F

*

0

.

1

m

F

m

0 . 1 F

*

3

W

*

U

S

B

D

+

/

C

L

K

V

S

*

H

T

8

2

K

9

5

E

Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is

stable and remains within a valid operating voltage range before bringing RES to high.

X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible.

Components with * are used for EMC issue.

Components with ** are used for resonator only if necessary.

Components with *** are used for 12MHz application.

Crystal or Ceramic Resonator for Multiple I/O Applications for HT82K95A

P

A

B

0

~

P

A

B

7

V

D

V

D

U

S

B

-

m

0 . 1 F

1

0

k

1

m

0 F

P

C

D

0

~

P

C

D

7

U

S

B

+

V

S

1

.

5

k

O

S

C

1

V

3

O

X

1

*

m

0 . 1 F

O

S

C

2

U

S

B

D

-

/

D

A

T

A

R

E

S

m

0 . 1 F

U

S

B

D

+

/

C

L

K

V

S

H

T

8

2

K

9

5

A

Note: X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible.

Components with * are used for resonator only if necessary.

Rev. 1.80

23

December 28, 2007

HT82K95E/HT82K95A

Instruction Set

Introduction

subtract instruction mnemonics to enable the necessary

arithmetic to be carried out. Care must be taken to en-

sure correct handling of carry and borrow data when re-

sults exceed 255 for addition and less than 0 for

subtraction. The increment and decrement instructions

INC, INCA, DEC and DECA provide a simple means of

increasing or decreasing by a value of one of the values

in the destination specified.

Central to the successful operation of any

microcontroller is its instruction set, which is a set of pro-

gram instruction codes that directs the microcontroller to

perform certain operations. In the case of Holtek

microcontrollers, a comprehensive and flexible set of

over 60 instructions is provided to enable programmers

to implement their application with the minimum of pro-

gramming overheads.

Logical and Rotate Operations

For easier understanding of the various instruction

codes, they have been subdivided into several func-

tional groupings.

The standard logical operations such as AND, OR, XOR

and CPL all have their own instruction within the Holtek

microcontroller instruction set. As with the case of most

instructions involving data manipulation, data must pass

through the Accumulator which may involve additional

programming steps. In all logical data operations, the

zero flag may be set if the result of the operation is zero.

Another form of logical data manipulation comes from

the rotate instructions such as RR, RL, RRC and RLC

which provide a simple means of rotating one bit right or

left. Different rotate instructions exist depending on pro-

gram requirements. Rotate instructions are useful for

serial port programming applications where data can be

rotated from an internal register into the Carry bit from

where it can be examined and the necessary serial bit

set high or low. Another application where rotate data

operations are used is to implement multiplication and

division calculations.

Instruction Timing

Most instructions are implemented within one instruc-

tion cycle. The exceptions to this are branch, call, or ta-

ble read instructions where two instruction cycles are

required. One instruction cycle is equal to 4 system

clock cycles, therefore in the case of an 8MHz system

oscillator, most instructions would be implemented

within 0.5ms and branch or call instructions would be im-

plemented within 1ms. Although instructions which re-

quire one more cycle to implement are generally limited

to the JMP, CALL, RET, RETI and table read instruc-

tions, it is important to realize that any other instructions

which involve manipulation of the Program Counter Low

register or PCL will also take one more cycle to imple-

ment. As instructions which change the contents of the

PCL will imply a direct jump to that new address, one

more cycle will be required. Examples of such instruc-

tions would be ²CLR PCL² or ²MOV PCL, A². For the

case of skip instructions, it must be noted that if the re-

sult of the comparison involves a skip operation then

this will also take one more cycle, if no skip is involved

then only one cycle is required.

Branches and Control Transfer

Program branching takes the form of either jumps to

specified locations using the JMP instruction or to a sub-

routine using the CALL instruction. They differ in the

sense that in the case of a subroutine call, the program

must return to the instruction immediately when the sub-

routine has been carried out. This is done by placing a

return instruction RET in the subroutine which will cause

the program to jump back to the address right after the

CALL instruction. In the case of a JMP instruction, the

program simply jumps to the desired location. There is

no requirement to jump back to the original jumping off

point as in the case of the CALL instruction. One special

and extremely useful set of branch instructions are the

conditional branches. Here a decision is first made re-

garding the condition of a certain data memory or indi-

vidual bits. Depending upon the conditions, the program

will continue with the next instruction or skip over it and

jump to the following instruction. These instructions are

the key to decision making and branching within the pro-

gram perhaps determined by the condition of certain in-

put switches or by the condition of internal data bits.

Moving and Transferring Data

The transfer of data within the microcontroller program

is one of the most frequently used operations. Making

use of three kinds of MOV instructions, data can be

transferred from registers to the Accumulator and

vice-versa as well as being able to move specific imme-

diate data directly into the Accumulator. One of the most

important data transfer applications is to receive data

from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and

data manipulation is a necessary feature of most

microcontroller applications. Within the Holtek

microcontroller instruction set are a range of add and

Rev. 1.80

24

December 28, 2007

HT82K95E/HT82K95A

Bit Operations

Other Operations

The ability to provide single bit operations on Data Mem-

ory is an extremely flexible feature of all Holtek

microcontrollers. This feature is especially useful for

output port bit programming where individual bits or port

pins can be directly set high or low using either the ²SET

[m].i² or ²CLR [m].i² instructions respectively. The fea-

ture removes the need for programmers to first read the

8-bit output port, manipulate the input data to ensure

that other bits are not changed and then output the port

with the correct new data. This read-modify-write pro-

cess is taken care of automatically when these bit oper-

ation instructions are used.

In addition to the above functional instructions, a range

of other instructions also exist such as the ²HALT² in-

struction for Power-down operations and instructions to

control the operation of the Watchdog Timer for reliable

program operations under extreme electric or electro-

magnetic environments. For their relevant operations,

refer to the functional related sections.

Instruction Set Summary

The following table depicts a summary of the instruction

set categorised according to function and can be con-

sulted as a basic instruction reference using the follow-

ing listed conventions.

Table Read Operations

Table conventions:

Data storage is normally implemented by using regis-

ters. However, when working with large amounts of

fixed data, the volume involved often makes it inconve-

nient to store the fixed data in the Data Memory. To over-

come this problem, Holtek microcontrollers allow an

area of Program Memory to be setup as a table where

data can be directly stored. A set of easy to use instruc-

tions provides the means by which this fixed data can be

referenced and retrieved from the Program Memory.

x: Bits immediate data

m: Data Memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Mnemonic

Arithmetic

Description

Cycles Flag Affected

ADD A,[m]

ADDM A,[m]

ADD A,x

Add Data Memory to ACC

1

1^Note

1

Z, C, AC, OV

C

Add ACC to Data Memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add Data Memory to ACC with Carry

1

1^Note

Add ACC to Data memory with Carry

Subtract immediate data from the ACC

Subtract Data Memory from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

1

1^Note

Subtract Data Memory from ACC with result in Data Memory

Subtract Data Memory from ACC with Carry

Subtract Data Memory from ACC with Carry, result in Data Memory

Decimal adjust ACC for Addition with result in Data Memory

1

1^Note

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

Logical AND Data Memory to ACC

Logical OR Data Memory to ACC

Logical XOR Data Memory to ACC

Logical AND ACC to Data Memory

Logical OR ACC to Data Memory

Logical XOR ACC to Data Memory

Logical AND immediate Data to ACC

Logical OR immediate Data to ACC

Logical XOR immediate Data to ACC

Complement Data Memory

1

Z

1

1^Note

1

OR A,x

1

XOR A,x

1

1^Note

CPL [m]

CPLA [m]

Complement Data Memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment Data Memory with result in ACC

1

Z

Increment Data Memory

1^Note

DECA [m]

DEC [m]

Decrement Data Memory with result in ACC

Decrement Data Memory

1

1^Note

Rev. 1.80

25

December 28, 2007

HT82K95E/HT82K95A

Mnemonic

Rotate

Description

Cycles Flag Affected

RRA [m]

RR [m]

Rotate Data Memory right with result in ACC

Rotate Data Memory right

1

1^Note

1

1^Note

1

1^Note

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate Data Memory right through Carry with result in ACC

Rotate Data Memory right through Carry

Rotate Data Memory left with result in ACC

Rotate Data Memory left

C

None

C

RLCA [m]

RLC [m]

Rotate Data Memory left through Carry with result in ACC

Rotate Data Memory left through Carry

1

1^Note

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move Data Memory to ACC

Move ACC to Data Memory

Move immediate data to ACC

1

1^Note

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of Data Memory

Set bit of Data Memory

1^Note

None

Branch

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if Data Memory is zero

1^Note

1^note

1^Note

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if Data Memory is zero with data movement to ACC

Skip if bit i of Data Memory is zero

Skip if bit i of Data Memory is not zero

Skip if increment Data Memory is zero

Skip if decrement Data Memory is zero

Skip if increment Data Memory is zero with result in ACC

Skip if decrement Data Memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m]

TABRDL [m]

Read table (current page) to TBLH and Data Memory

Read table (last page) to TBLH and Data Memory

2^Note

None

Miscellaneous

NOP

No operation

1

1^Note

1

None

CLR [m]

Clear Data Memory

SET [m]

Set Data Memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO, PDF

None

Pre-clear Watchdog Timer

Swap nibbles of Data Memory

Swap nibbles of Data Memory with result in ACC

Enter power down mode

1

1^Note

1

None

1

TO, PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by

the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and

²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags

remain unchanged.

Rev. 1.80

26

December 28, 2007

HT82K95E/HT82K95A

Instruction Definition

ADC A,[m]

Add Data Memory to ACC with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the Accumulator.

Operation

ACC ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADCM A,[m]

Add ACC to Data Memory with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADD A,[m]

Add Data Memory to ACC

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

ADD A,x

Add immediate data to ACC

Description

The contents of the Accumulator and the specified immediate data are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + x

Affected flag(s)

OV, Z, AC, C

ADDM A,[m]

Add ACC to Data Memory

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

AND A,[m]

Logical AND Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

Z

AND A,x

Logical AND immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical AND

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

Z

ANDM A,[m]

Logical AND ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

Z

Rev. 1.80

27

December 28, 2007

HT82K95E/HT82K95A

CALL addr

Subroutine call

Description

Unconditionally calls a subroutine at the specified address. The Program Counter then in-

crements by 1 to obtain the address of the next instruction which is then pushed onto the

stack. The specified address is then loaded and the program continues execution from this

new address. As this instruction requires an additional operation, it is a two cycle instruc-

tion.

Operation

Stack ¬ Program Counter + 1

Program Counter ¬ addr

Affected flag(s)

None

CLR [m]

Clear Data Memory

Description

Operation

Each bit of the specified Data Memory is cleared to 0.

[m] ¬ 00H

Affected flag(s)

None

CLR [m].i

Clear bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

None

CLR WDT

Description

Operation

Clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared.

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT1

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT2 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT2

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT1 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

Rev. 1.80

28

December 28, 2007

HT82K95E/HT82K95A

CPL [m]

Complement Data Memory

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa.

Operation

[m] ¬ [m]

Affected flag(s)

Z

CPLA [m]

Complement Data Memory with result in ACC

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa. The complemented result

is stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

Z

DAA [m]

Decimal-Adjust ACC for addition with result in Data Memory

Description

Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-

sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or

if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble

remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of

6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-

ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C

flag may be affected by this instruction which indicates that if the original BCD sum is

greater than 100, it allows multiple precision decimal addition.

Operation

[m] ¬ ACC + 00H or

[m] ¬ ACC + 06H or

[m] ¬ ACC + 60H or

[m] ¬ ACC + 66H

Affected flag(s)

C

DEC [m]

Decrement Data Memory

Description

Operation

Data in the specified Data Memory is decremented by 1.

[m] ¬ [m] - 1

Affected flag(s)

Z

DECA [m]

Decrement Data Memory with result in ACC

Description

Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-

mulator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] - 1

Affected flag(s)

Z

HALT

Enter power down mode

Description

This instruction stops the program execution and turns off the system clock. The contents

of the Data Memory and registers are retained. The WDT and prescaler are cleared. The

power down flag PDF is set and the WDT time-out flag TO is cleared.

Operation

TO ¬ 0

PDF ¬ 1

Affected flag(s)

TO, PDF

Rev. 1.80

29

December 28, 2007

HT82K95E/HT82K95A

INC [m]

Increment Data Memory

Description

Operation

Data in the specified Data Memory is incremented by 1.

[m] ¬ [m] + 1

Affected flag(s)

Z

INCA [m]

Increment Data Memory with result in ACC

Description

Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-

lator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] + 1

Affected flag(s)

Z

JMP addr

Jump unconditionally

Description

The contents of the Program Counter are replaced with the specified address. Program

execution then continues from this new address. As this requires the insertion of a dummy

instruction while the new address is loaded, it is a two cycle instruction.

Operation

Program Counter ¬ addr

Affected flag(s)

None

MOV A,[m]

Description

Operation

Move Data Memory to ACC

The contents of the specified Data Memory are copied to the Accumulator.

ACC ¬ [m]

Affected flag(s)

None

MOV A,x

Move immediate data to ACC

Description

Operation

The immediate data specified is loaded into the Accumulator.

ACC ¬ x

Affected flag(s)

None

MOV [m],A

Description

Operation

Move ACC to Data Memory

The contents of the Accumulator are copied to the specified Data Memory.

[m] ¬ ACC

Affected flag(s)

None

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

No operation

None

OR A,[m]

Logical OR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-

ation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

Z

Rev. 1.80

30

December 28, 2007

HT82K95E/HT82K95A

OR A,x

Logical OR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

Z

ORM A,[m]

Logical OR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-

ation. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²OR² [m]

Affected flag(s)

Z

RET

Return from subroutine

Description

The Program Counter is restored from the stack. Program execution continues at the re-

stored address.

Operation

Program Counter ¬ Stack

Affected flag(s)

None

RET A,x

Return from subroutine and load immediate data to ACC

Description

The Program Counter is restored from the stack and the Accumulator loaded with the

specified immediate data. Program execution continues at the restored address.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

None

RETI

Return from interrupt

Description

The Program Counter is restored from the stack and the interrupts are re-enabled by set-

ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending

when the RETI instruction is executed, the pending Interrupt routine will be processed be-

fore returning to the main program.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

None

RL [m]

Rotate Data Memory left

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ [m].7

Affected flag(s)

None

RLA [m]

Rotate Data Memory left with result in ACC

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-

main unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ [m].7

Affected flag(s)

None

Rev. 1.80

31

December 28, 2007

HT82K95E/HT82K95A

RLC [m]

Rotate Data Memory left through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7

replaces the Carry bit and the original carry flag is rotated into bit 0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RLCA [m]

Rotate Data Memory left through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces

the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in

the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RR [m]

Rotate Data Memory right

Description

The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into

bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ [m].0

Affected flag(s)

None

RRA [m]

Rotate Data Memory right with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-

tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data

Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ [m].0

Affected flag(s)

None

RRC [m]

Rotate Data Memory right through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0

replaces the Carry bit and the original carry flag is rotated into bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

C

RRCA [m]

Rotate Data Memory right through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-

places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is

stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

C

Rev. 1.80

32

December 28, 2007

HT82K95E/HT82K95A

SBC A,[m]

Subtract Data Memory from ACC with Carry

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result

of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or

zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SBCM A,[m]

Subtract Data Memory from ACC with Carry and result in Data Memory

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-

sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is

positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SDZ [m]

Skip if decrement Data Memory is 0

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0 the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] - 1

Skip if [m] = 0

Affected flag(s)

None

SDZA [m]

Skip if decrement Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0, the program proceeds with the following instruction.

Operation

ACC ¬ [m] - 1

Skip if ACC = 0

Affected flag(s)

None

SET [m]

Set Data Memory

Description

Operation

Each bit of the specified Data Memory is set to 1.

[m] ¬ FFH

Affected flag(s)

None

SET [m].i

Set bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is set to 1.

[m].i ¬ 1

Affected flag(s)

None

Rev. 1.80

33

December 28, 2007

HT82K95E/HT82K95A

SIZ [m]

Skip if increment Data Memory is 0

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] + 1

Skip if [m] = 0

Affected flag(s)

None

SIZA [m]

Skip if increment Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0 the program proceeds with the following instruction.

Operation

ACC ¬ [m] + 1

Skip if ACC = 0

Affected flag(s)

None

SNZ [m].i

Skip if bit i of Data Memory is not 0

Description

If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is 0 the program proceeds with the following instruction.

Operation

Skip if [m].i ¹ 0

Affected flag(s)

None

SUB A,[m]

Subtract Data Memory from ACC

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUBM A,[m]

Subtract Data Memory from ACC with result in Data Memory

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUB A,x

Subtract immediate data from ACC

Description

The immediate data specified by the code is subtracted from the contents of the Accumu-

lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-

tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will

be set to 1.

Operation

ACC ¬ ACC - x

Affected flag(s)

OV, Z, AC, C

Rev. 1.80

34

December 28, 2007

HT82K95E/HT82K95A

SWAP [m]

Description

Operation

Swap nibbles of Data Memory

The low-order and high-order nibbles of the specified Data Memory are interchanged.

[m].3~[m].0 « [m].7 ~ [m].4

Affected flag(s)

None

SWAPA [m]

Swap nibbles of Data Memory with result in ACC

Description

The low-order and high-order nibbles of the specified Data Memory are interchanged. The

result is stored in the Accumulator. The contents of the Data Memory remain unchanged.

Operation

ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4

ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0

Affected flag(s)

None

SZ [m]

Skip if Data Memory is 0

Description

If the contents of the specified Data Memory is 0, the following instruction is skipped. As

this requires the insertion of a dummy instruction while the next instruction is fetched, it is a

two cycle instruction. If the result is not 0 the program proceeds with the following instruc-

tion.

Operation

Skip if [m] = 0

None

Affected flag(s)

SZA [m]

Skip if Data Memory is 0 with data movement to ACC

Description

The contents of the specified Data Memory are copied to the Accumulator. If the value is

zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-

tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the

program proceeds with the following instruction.

Operation

ACC ¬ [m]

Skip if [m] = 0

Affected flag(s)

None

SZ [m].i

Skip if bit i of Data Memory is 0

Description

If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is not 0, the program proceeds with the following instruction.

Operation

Skip if [m].i = 0

None

Affected flag(s)

TABRDC [m]

Read table (current page) to TBLH and Data Memory

Description

The low byte of the program code (current page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

TABRDL [m]

Read table (last page) to TBLH and Data Memory

Description

The low byte of the program code (last page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

Rev. 1.80

35

December 28, 2007

HT82K95E/HT82K95A

XOR A,[m]

Logical XOR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XORM A,[m]

Logical XOR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XOR A,x

Logical XOR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical XOR

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

Z

Rev. 1.80

36

December 28, 2007

HT82K95E/HT82K95A

Package Information

28-pin SOP (300mil) Outline Dimensions

2

8

1

5

A

B

1

4

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

394

290

14

697

92

¾

Max.

419

300

20

A

B

C

C¢

D

E

F

¾

50

¾

713

104

¾

4

¾

G

H

a

32

4

38

12

0°

10°

Rev. 1.80

37

December 28, 2007

HT82K95E/HT82K95A

48-pin SSOP (300mil) Outline Dimensions

4

8

2

5

4

A

B

1

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

395

291

8

Max.

420

299

12

A

B

C

C¢

D

E

F

¾

25

¾

613

85

¾

637

99

¾

4

10

G

H

a

25

4

35

12

0°

8°

Rev. 1.80

38

December 28, 2007

HT82K95E/HT82K95A

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SOP 28W (300mil)

Symbol

Description

Dimensions in mm

330±1

A

B

Reel Outer Diameter

Reel Inner Diameter

62±1.5

13+0.5

-0.2

C

D

Spindle Hole Diameter

Key Slit Width

2±0.5

24.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

30.2±0.2

SSOP 48W

Symbol

Description

Dimensions in mm

330±1

A

B

Reel Outer Diameter

Reel Inner Diameter

100±0.1

13+0.5

-0.2

C

D

Spindle Hole Diameter

Key Slit Width

2±0.5

32.2+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

38.2±0.2

Rev. 1.80

39

December 28, 2007

HT82K95E/HT82K95A

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

W

B

0

C

D

1

P

K

0

A

0

SOP 28W (300mil)

Symbol

Description

Dimensions in mm

24±0.3

W

P

Carrier Tape Width

Cavity Pitch

12±0.1

E

Perforation Position

1.75±0.1

11.5±0.1

1.5+0.1

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K0

t

1.5+0.25

4±0.1

Cavity to Perforation (Length Direction)

Cavity Length

2±0.1

10.85±0.1

18.34±0.1

2.97±0.1

0.35±0.01

21.3

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

C

Rev. 1.80

40

December 28, 2007

HT82K95E/HT82K95A

P

0

P

1

t

D

E

F

B

0

W

C

K

1

D

1

P

K

2

A

0

SSOP 48W

Symbol

Description

Dimensions in mm

32±0.3

W

P

Carrier Tape Width

Cavity Pitch

16±0.1

E

Perforation Position

1.75±0.1

14.2±0.1

2 Min.

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K1

K2

t

1.5+0.25

4±0.1

Cavity to Perforation (Length Direction)

Cavity Length

2±0.1

12±0.1

Cavity Width

16.2±0.1

2.4±0.1

3.2±0.1

0.35±0.05

25.5

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

C

Rev. 1.80

41

December 28, 2007

HT82K95E/HT82K95A

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233

Tel: 86-21-6485-5560

Fax: 86-21-6485-0313

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,

Shenzhen, China 518057

Tel: 86-755-8616-9908, 86-755-8616-9308

Fax: 86-755-8616-9722

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752

Fax: 86-10-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016

Tel: 86-28-6653-6590

Fax: 86-28-6653-6591

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538

Tel: 1-510-252-9880

Fax: 1-510-252-9885

http://www.holtek.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.80

42

December 28, 2007


型号：	HT82K95E(48SSOP)
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Microcontroller, 8-Bit, UVPROM, 12MHz, CMOS, PDSO48 可编程只读存储器控制器微控制器微控制器和处理器光电二极管
文件：	总42页 (文件大小：310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT82K95E(48SSOP) [HOLTEK]

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