HT82M9AA(20SSOP)_技术文档

HT82M9AE/HT82M9AA

USB Mouse Encoder 8-Bit MCU

Technical Document

·

Tools Information

FAQs

Application Note

Features

·

Flexible total solution for applications that combine

PS/2 and low-speed USB interface, such as mice,

joysticks, and many others

6MHz/12MHz internal CPU clock

4-level stacks

Two 8-bit indirect addressing registers

USB Specification Compliance

One 16-bit programmable timer counter with

overflow interrupt (shared with PA7, vector 0CH)

-

Conforms to USB specification V1.1

Conforms to USB HID specification V1.1

·

One USB interrupt input (vector 04H)

Supports 1 low-speed USB control endpoint and

2 interrupt endpoint

HALT function and wake-up feature reduce power

consumption

·

Each endpoint has 8´8 bytes FIFO

Integrated USB transceiver

·

PA0~PA7, PB4 and PB7 support wake-up function

Internal Power-On reset (POR)

Watchdog Timer (WDT)

3.3V regulator output

External 6MHz or 12MHz ceramic resonator or crystal

16 I/O ports

8-bit RISC microcontroller, with 4K´15 program

memory (000H~FFFH)

20/24-pin SOP/SSOP package

·

224 bytes RAM (20H~FFH)

General Description

The USB MCU OTP body is suitable for USB mouse

and USB joystick devices. It consists of a Holtek high

performance 8-bit MCU core for control unit, built-in

USB SIE, 4K´15 ROM and 224 bytes data RAM.

The HT82M9AA is under development and will be avail-

able soon.

The mask version HT82M9AA is fully pin and functionally

compatible with the OTP version HT82M9AE device.

Rev. 1.00

1

November 8, 2006

HT82M9AE/HT82M9AA

Block Diagram

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Pin Assignment

P

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6

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2

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1

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2

0

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H

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2

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4

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O

P

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A

Rev. 1.00

2

November 8, 2006

HT82M9AE/HT82M9AA

Pin Description

ROM Code

Option

Pin Name

I/O

Description

Bidirectional 8-bit input/output port. Each bit can be configured as a

wake-up input by ROM code option. The input or output mode is con-

trolled by PAC (PA control register).

Pull-high

Pull-low

PA0~PA7

I/O

Pull-high resistor options: PA0~PA7

Wake-up

Pull-low resistor options: PA0~PA3

CMOS/NMOS/PMOS

CMOS/NMOS/PMOS options: PA0~PA7

Falling edge wake-up options: PA0~PA7

Bidirectional 8-bit input/output port. Software instructions determine the

CMOS output or Schmitt trigger input with pull-high resistor (determined

by pull-high options).

Pull-high

Pull-low

Wake-up

PB0~PB7

I/O

Pull-high resistor options: PB0~PB7

Pull-low resistor for options: PB2, PB3

Falling edge wake-up options: PB4, PB7

VSS

RES

VDD

V33O

Negative power supply, ground

Schmitt trigger reset input. Active low.

Positive power supply

¾

I

¾

O

3.3V regulator output

USBD+ or PS2 CLK I/O line

USBD+/CLK

I/O

¾

USB or PS2 function is controlled by software control register

USBD- or PS2 DATA I/O line

USBD-/DATA I/O

USB or PS2 function is controlled by software control register

OSCI

I

OSCI, OSCO are connected to a 6MHz or 12MHz crystal/resonator (de-

termined by software instructions) for the internal system clock.

OSCO

O

Absolute Maximum Ratings

Supply Voltage...........................V_SS-0.3V to V_SS+6.0V

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

Storage Temperature............................-50°C to 125°C

Operating Temperature...............................0°C to 70°C

I_OHTotal............................................................-100mA

I

_OLTotal ..............................................................150mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

Rev. 1.00

3

November 8, 2006

HT82M9AE/HT82M9AA

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Operating Voltage

Min. Typ. Max. Unit

V_DD

¾

V_DD

I_DD

4

¾

5.5

9

V

mA

V

¾

7

No load, f_SYS=6MHz

Operating Current (6MHz Crystal)

Standby Current

5V

I_STB

V_IL1

V_IH1

V_IL2

V_IH2

5V No load, system HALT

300

1.2

¾

500

1.5

¾

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Input Low Voltage (RES)

Input High Voltage (RES)

5V

0

¾

1.7

0

5

V

0.8V_DD

V_DD

V

¾

0.9V_DD

V

¾

Output Sink Current for Other Ports

PA0~PA7, PB0~PB7

I_OL

V

_OL=0.4V

5V

¾

2

-2.5

10

4

mA

kW

V

¾

50

6

I_OH

V_OL=3.4V

Output Port Source Current

-4

30

4.7

50

2.4

Pull-down Resistance for PA0~PA3, PB2

and PB3

R_PD

R_PH1

R_PH2

V_LVR

¾

Pull-high Resistance for CLK and DATA(*)

2

Pull-high Resistance for PA0~PA7,

PB0~PB7

30

70

3

¾

Low Voltage Reset

5V

2.0

Note: ²*² The DATA pull-high must be implemented by the external 1.5kW

A.C. Characteristics

Ta=25°C

Min. Typ. Max. Unit

Test Conditions

Conditions

Symbol

Parameter

V_DD

5V

¾

f_SYS

f_RCSYS

t_WDT

t_RF

System Clock (Crystal OSC)

6

0

12

¾

MHz

kHz

t_RCSYS

ns

¾

32

RC Clock with 8-bit Prescaler Register

Watchdog Time-out Period (System Clock)

USBD+, USBD- Rising & falling Time

System Start-up Timer Period

Crystal Setup

Without WDT prescaler 1024

¾

75

¾

300

¾

Wake-up from HALT

¾

t_SST

t_SYS

ms

1024

5

¾

t_OSC

10

¾

Note: Power-on period=t_WDT+t_SST+t_OSC

WDT Time-out in normal mode=1/f_RCSYS´256´WDTS+t_WDT

WDT Time-out in HALT mode=1/f_RCSYS´256´WDTS+t_SST+t_OSC

Rev. 1.00

4

November 8, 2006

HT82M9AE/HT82M9AA

Functional Description

Execution Flow

After accessing a program memory word to fetch an in-

struction code, the contents of the program counter are

incremented by one. The program counter then points to

the memory word containing the next instruction code.

The system clock for the microcontroller is derived from

either 6MHz or 12MHz crystal oscillator, which used a

frequency that is determined by the SCLKSEL bit of the

SCC Register. The default system frequency is 12MHz.

The system clock is internally divided into four non-

overlapping clocks. One instruction cycle consists of

four system clock cycles.

When executing a jump instruction, conditional skip ex-

ecution, loading to the PCL register, performing a sub-

routine call or return from subroutine, initial reset,

internal interrupt, external interrupt or return from inter-

rupts, the PC manipulates the program transfer by load-

ing the address corresponding to each instruction.

Instruction fetching and execution are pipelined in such

a way that a fetch takes an instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to be effectively executed in a cycle. If an instruction

changes the program counter, two cycles are required to

complete the instruction.

The conditional skip is activated by instructions. Once

the condition is met, the next instruction, fetched during

the current instruction execution, is discarded and a

dummy cycle replaces it to get the proper instruction.

Otherwise proceed with the next instruction.

The lower byte of the program counter (PCL) is a read-

able and writeable register (06H). Moving data into the

PCL performs a short jump. The destination will be

within the current program ROM page.

Program Counter - PC

The program counter (PC) controls the sequence in

which the instructions stored in the program ROM are

executed and its contents specify a full range of pro-

gram memory.

When a control transfer takes place, an additional

dummy cycle is required.

T

1

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2

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4

S

y

s

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C

l

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2

(

R

C

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P

C

P

C

+

1

P

C

+

2

P

C

F

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t

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I

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T

(

P

C

)

E

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T

(

P

C

-

1

)

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P

C

+

1

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T

(

P

C

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F

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C

+

2

)

E

x

e

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t

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S

T

(

P

C

+

1

)

Execution Flow

Program Counter

Mode

*11

0

*10

0

*9

0

*8

0

*7

0

*6

0

*5

0

*4

0

*3

0

*2

0

*1

0

*0

0

Initial Reset

USB Interrupt

0

1

0

Timer/Event Counter Overflow

Skip

0

1

0

Program Counter+2

@7 @6 @5 @4 @3 @2 @1 @0

Loading PCL

*11

*10

*9

#9

S9

*8

#8

S8

Jump, Call Branch

Return from Subroutine

#11 #10

S11 S10

#7

S7

#6

S6

#5

S5

#4

S4

#3

S3

#2

S2

#1

S1

#0

S0

Program Counter

Note: *11~*0: Program counter bits

#11~#0: Instruction code bits

S11~S0: Stack register bits

@7~@0: PCL bits

Rev. 1.00

5

November 8, 2006

HT82M9AE/HT82M9AA

Program Memory - ROM

ROM data by two table read instructions: ²TABRDC²

and ²TABRDL², transfer the contents of the

lower-order byte to the specified data memory, and

the higher-order byte to TBLH (08H).

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

4096´15 bits, addressed by the program counter and ta-

ble pointer.

The three methods are shown as follows:

¨

The instructions ²TABRDC [m]² (the current page,

one page=256words), where the table locations is

defined by TBLP (07H) in the current page. And the

ROM code option TBHP is disabled (default).

Certain locations in the program memory are reserved

for special usage:

·

Location 000H

¨

The instructions ²TABRDC [m]², where the table lo-

cations is defined by registers TBLP (07H) and

TBHP (01FH). And the ROM code option TBHP is

enabled.

This area is reserved for program initialization. After a

chip reset, the program always begins execution at lo-

cation 000H.

¨

The instructions ²TABRDL [m]², where the table lo-

cations is defined by Registers TBLP (07H) in the

·

Location 004H

This area is reserved for the USB interrupt service

program. If the USB interrupt is activated, the interrupt

is enabled and the stack is not full, the program begins

execution at location 004H.

last page (0F00H~0FFFH).

Only the destination of the lower-order byte in the ta-

ble is well-defined, the other bits of the table word are

transferred to the lower portion of TBLH, and the re-

maining 1-bit words are read as ²0². The Table

Higher-order byte register (TBLH) is read only. The ta-

ble pointer (TBLP, TBHP) is a read/write register (07H,

1FH), which indicates the table location. Before ac-

cessing the table, the location must be placed in the

TBLP and TBHP (If the OTP option TBHP is disabled,

the value in TBHP has no effect). The TBLH is read

only and cannot be restored. If the main routine and

the ISR (Interrupt Service Routine) both employ the

table read instruction, the contents of the TBLH in the

main routine are likely to be changed by the table read

instruction used in the ISR. Errors can occur. In other

words, using the table read instruction in the main rou-

tine and the ISR simultaneously should be avoided.

However, if the table read instruction has to be applied

in both the main routine and the ISR, the interrupt

should be disabled prior to the table read instruction. It

will not be enabled until the TBLH has been backed

up. All table related instructions require two cycles to

complete the operation. These areas may function as

normal program memory depending on the require-

ments.

·

Location 00CH

This location is reserved for the Timer/Event Counter

interrupt service program. If a timer interrupt results

from a Timer/Event Counter overflow, and the inter-

rupt is enabled and the stack is not full, the program

begins execution at location 00CH.

·

Table location

Any location in the program memory can be used as

look-up tables. There are three method to read the

0

H

D

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v

i

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I

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i

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0

4

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U

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L

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-

u

p

T

a

b

l

e

(

2

5

6

W

o

r

d

s

)

n

F

H

Once TBHP is enabled, the instruction ²TABRDC [m]²

reads the ROM data as defined by TBLP and TBHP

value. Otherwise, the ROM code option TBHP is dis-

abled, the instruction ²TABRDC [m]² reads the ROM

data as defined by TBLP and the current program

counter bits.

L

o

k

-

u

p

T

a

b

l

e

(

2

5

6

W

o

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d

s

)

F

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1

5

B

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n

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0

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t

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Program Memory

Table Location

Instruction

*11

P11

1

*10

P10

1

*9

P9

1

*8

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

P8

1

@7

@6

@5

@4

@3

@2

@1

@0

Table Location

Note: *11~*0: Table location bits

@7~@0: TBLP bits

P11~P8: Current program counter bits when TBHP is disabled

TBHP register bit3~bit0 when TBHP is enabled

Rev. 1.00

6

November 8, 2006

HT82M9AE/HT82M9AA

B

a

n

k

0

Stack Register - STACK

I

n

d

i

r

e

c

t

A

d

r

e

M

e

M

s

i

n

g

R

e

g

i

s

t

e

r

0

1

2

3

4

5

6

7

8

9

H

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 4 levels and is neither part of the

data nor part of the program space, and is neither read-

able nor writeable. The activated level is indexed by the

stack pointer (SP) and is neither readable nor writeable.

At a subroutine call or interrupt acknowledge signal, the

contents of the program counter are pushed onto the

stack. At the end of a subroutine or an interrupt routine,

signaled by a return instruction (RET or RETI), the pro-

gram counter is restored to its previous value from the

stack. After a chip reset, the SP will point to the top of the

stack.

P

0

I

n

d

i

r

e

c

t

A

d

r

s

i

n

g

R

e

g

i

s

t

e

r

1

P

1

B

P

A

C

P

C

L

T

B

L

P

T

B

L

H

W

D

T

S

T

A

T

U

S

0

A

B

H

I

N

T

C

0

C

D

H

0

E

H

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag will be recorded but the

acknowledge signal will be inhibited. When the stack

pointer is decremented (by RET or RETI), the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

In a similar case, if the stack is full and a ²CALL² is sub-

sequently executed, stack overflow occurs and the first

entry will be lost (only the most recent 4 return ad-

dresses are stored).

T

M

R

H

C

0

F

H

T

M

R

L

1

0

1

2

3

4

5

6

7

8

9

P

A

B

P

A

B

C

Data Memory - RAM for Bank 0

U

S

C

R

1

A

B

H

The data memory is designed with 224´8 bits. The data

memory is divided into two functional groups: special

function registers and general purpose data memory

(224´8). Most are read/write, but some are read only.

C

1

C

D

H

1

E

H

The unused spaces before the 20H is reserved for fu-

ture expanded usage and reading these locations will

get ²00H². The general purpose data memory, ad-

dressed from 20H to FFH, is used for data and control

information under instruction commands.

T

B

H

P

1

F

H

2

0

H

G

e

n

e

r

a

l

P

u

r

p

o

s

e

D

a

t

a

M

e

m

o

r

y

(

2

4

B

y

t

e

s

)

F

H

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP0 or MP1).

Bank 0 RAM Mapping

Indirect Addressing Register

Locations 00H and 02H are indirect addressing regis-

ters that are not physically implemented. Any read/write

operation on [00H] ([02H]) will access the data memory

pointed to by MP0 (MP1). Reading location 00H (02H)

indirectly will return the result 00H. Writing indirectly re-

sults in no operation.

Data Memory - RAM for Bank 1

The special function registers used in the USB interface

are located in RAM Bank1. In order to access Bank1

register, only the Indirect addressing pointer MP1 can

be used and the Bank register BP should be set to 1.

The RAM bank 1 mapping is as shown.

The indirect addressing pointer (MP0) always points to

Bank0 RAM addresses no matter the value of Bank

Register (BP).

Address 00~1FH in RAM Bank0 and Bank1 are located

in the same Registers

The indirect addressing pointer (MP1) can access

Bank0 or Bank1 RAM data according to the value of BP

which is set to ²0² or ²1² respectively.

The memory pointer registers (MP0 and MP1) are 7-bit

registers.

Rev. 1.00

7

November 8, 2006

HT82M9AE/HT82M9AA

Accumulator

B

a

n

k

1

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e

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i

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t

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r

0

1

2

3

4

5

6

7

8

9

H

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

P

0

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A

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1

P

1

B

P

A

C

P

C

L

Arithmetic and Logic Unit - ALU

T

B

L

P

This circuit performs 8-bit arithmetic and logic opera-

tions. The ALU provides the following functions:

T

B

L

H

W

D

T

S

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

S

T

A

T

U

S

0

A

B

H

I

N

T

C

0

C

D

H

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ ....)

0

E

H

T

M

R

H

0

F

H

The ALU not only saves the results of a data operation

but also changes the status register.

T

M

R

L

1

0

1

2

3

4

5

6

7

8

9

T

M

R

C

P

A

Status Register - STATUS

P

A

C

This 8-bit register (0AH) contains the zero flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PDF), and watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

P

B

P

B

C

With the exception of the TO and PDF flags, bits in the

status register can be altered by instructions like most

other registers. Any data written into the status register

will not change the TO or PDF flag. In addition, opera-

tions related to the status register may give different re-

sults from those intended.

U

S

C

1

A

B

H

R

C

1

C

D

H

1

E

H

T

B

H

P

1

F

H

The TO flag can be affected only by a system power-up,

a WDT time-out or executing the ²CLR WDT² or ²HALT²

instruction. The PDF flag can be affected only by exe-

cuting the ²HALT² or ²CLR WDT² instruction or during a

system power-up.

2

4

0

1

2

3

4

5

H

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l

A

R

S

T

A

L

P

S

I

P

E

S

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

4

6

7

H

M

I

S

C

E

n

d

p

t

_

E

N

In addition, upon entering the interrupt sequence or exe-

cuting a subroutine call, the status register will not be

automatically pushed onto the stack. If the contents of

the status are important and if the subroutine can cor-

rupt the status register, precautions must be taken to

save it properly.

4

8

9

A

H

F

I

F

O

0

1

H

F

I

F

O

2

Bank 1 RAM Mapping

Rev. 1.00

8

November 8, 2006

HT82M9AE/HT82M9AA

Bit No.

Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

0

C

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

1

2

3

AC

Z

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

OV

PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by

executing the ²HALT² instruction.

4

PDF

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

5

TO

6~7

¾

Unused bit, read as ²0²

Status (0AH) Register

Interrupt

program which corrupts the desired control sequence,

the contents should be saved in advance.

The device provides an external interrupt and internal

timer/event counter interrupts. The Interrupt Control

Register (INTC;0BH) contains the interrupt control bits

to set the enable/disable and the interrupt request flags.

The USB interrupts are triggered by the following USB

events and the related interrupt request flag (USBF; bit

4 of the INTC) will be set.

·

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt requires servicing within the service routine, the

EMI bit and the corresponding bit of the INTC may be

set to allow interrupt nesting. If the stack is full, the inter-

rupt request will not be acknowledged, even if the re-

lated interrupt is enabled, until the SP is decremented. If

immediate service is desired, the stack must be pre-

vented from becoming full.

Access of the corresponding USB FIFO from PC

·

The USB suspend signal from PC

The USB resume signal from PC

USB Reset signal

When the interrupt is enabled, the stack is not full and

the external interrupt is active, a subroutine call to loca-

tion 04H will occur. The interrupt request flag (USBF)

and EMI bits will be cleared to disable other interrupts.

When the PC Host access the FIFO of the HT82M9AE/

HT82M9AA, the corresponding request bit of the USR is

set, and a USB interrupt is triggered. So user can easily

decide which FIFO is accessed. When the interrupt has

been served, the corresponding bit should be cleared by

firmware. When the HT82M9AE/HT82M9AA receives a

USB Suspend signal from the Host PC, the suspend line

(bit0 of the USC) of the HT82M9AE/HT82M9AA is set

and a USB interrupt is also triggered.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at a specified location in the

program memory. Only the program counter is pushed

onto the stack. If the contents of the register or status

register (STATUS) are altered by the interrupt service

Bit No.

Label

EMI

EUI

¾

Function

0

Controls the master (global) interrupt (1=enable; 0=disable)

1

Controls the USB interrupt (1=enable; 0= disable)

Unused bit, read as ²0²

2, 5, 7

3

4

6

ETI

Controls the Timer/Event Counter interrupt (1=enable; 0=disable)

USB interrupt request flag (1=active; 0=inactive)

Internal timer/event counter request flag (1:active; 0:inactive)

USBF

TF

INTC (0BH) Register

Rev. 1.00

9

November 8, 2006

HT82M9AE/HT82M9AA

When the HT82M9AE/HT82M9AA receives a Resume

signal from the Host PC, the resume line (bit3 of the

USC) of the HT82M9AE/HT82M9AA are set and a USB

interrupt is triggered.

This oscillator is designed for system clocks. The HALT

mode stops the system oscillator and ignores an exter-

nal signal to conserve power.

A crystal across OSC1 and OSC2 is needed to provide

the feedback and phase shift required for the oscillator.

No other external components are required. In stead of

a crystal, a resonator can also be connected between

OSC1 and OSC2 to get a frequency reference, but two

external capacitors in OSC1 and OSC2 are required.

Whenever a USB reset signal is detected, the USB in-

terrupt is triggered and URST_Flag bit of the USC regis-

ter is set. When the interrupt has been served, the bit

should be cleared by firmware.

The internal timer/event counter interrupt is initialized by

setting the timer/event counter interrupt request flag (bit

6 of the INTC), caused by a timer overflow. When the in-

terrupt is enabled, the stack is not full and the TF is set, a

subroutine call to location 0CH will occur. The related in-

terrupt request flag (TF) will be reset and the EMI bit

cleared to disable further interrupts.

The HT82M9AE/HT82M9AA can operate in 6MHz or

12MHz system clocks. In order to make sure that the

USB SIE functions properly, user should correctly con-

figure the SCLKSEL bit of the SCC Register. The default

system clock is 12MHz.

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode, the system

clock is stopped, but the WDT oscillator still works within

a period of approximately 31ms. The WDT oscillator can

be disabled by ROM code option to conserve power.

During the execution of an interrupt subroutine, other in-

terrupt acknowledge signals are held until the ²RETI² in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, ²RET² or ²RETI²

may be invoked. RETI will set the EMI bit to enable an

interrupt service, but RET will not.

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator), or instruction clock (sys-

tem clock divided by 4), determine by ROM code option.

This timer is designed to prevent a software malfunction

or sequence from jumping to an unknown location with

unpredictable results. The Watchdog Timer can be dis-

abled by ROM code option. If the Watchdog Timer is dis-

abled, all the executions related to the WDT result in no

operation.

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

USB interrupt

Timer/Event Counter overflow

Priority Vector

1

2

04H

0CH

Once the internal WDT oscillator (RC oscillator with a

period of 31ms at 5V normally) is selected, it is first di-

vided by 256 (8-stage) to get the nominal time-out pe-

riod of 8ms/5V. This time-out period may vary with

temperatures, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can be real-

ized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the

WDTS) can give different time-out periods. If WS2,

WS1, and WS0 are all equal to 1, the division ratio is up

to 1:128, and the maximum time-out period is 1s/5V. If

the WDT oscillator is disabled, the WDT clock may still

come from the instruction clock and operates in the

same manner except that in the HALT state the WDT

may stop counting and lose its protecting purpose. In

this situation the logic can only be restarted by external

logic. The high nibble and bit 3 of the WDTS are re-

served for user defined flags, which can only be set to

²10000² (WDTS.7~WDTS.3).

Once the interrupt request flags (TF, USBF) are set,

they will remain in the INTC register until the interrupts

are serviced or cleared by a software instruction.

It is recommended that a program does not use the

²CALL subroutine² within the interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only one

stack is left and enabling the interrupt is not well con-

trolled, the original control sequence will be damaged

once the ²CALL² operates in the interrupt subroutine.

Oscillator Configuration

There is an oscillator circuit in the microcontroller.

O

S

C

1

O

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2

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System Oscillator

Rev. 1.00

10

November 8, 2006

HT82M9AE/HT82M9AA

W

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8

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M

U

X

W

S

0

~

W

S

2

W

D

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t

Watchdog Timer

·

All of the I/O ports remain in their original status.

The PDF flag is set and the TO flag is cleared.

If the device operates in a noisy environment, using the

on-chip 32kHz RC oscillator (WDT OSC) is strongly rec-

ommended, since the HALT will stop the system clock.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a ²warm reset². After the TO and PDF flags are

examined, the cause for chip reset can be determined.

The PDF flag is cleared by a system power-up or exe-

cuting the ²CLR WDT² instruction and is set when exe-

cuting the ²HALT² instruction. The TO flag is set if the

WDT time-out occurs, and causes a wake-up that only

resets the program counter and SP; the others remain in

their original status.

WS2

WS1

WS0

Division Ratio

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake-up the

device by mask option. Awakening from an I/O port stim-

ulus, the program will resume execution of the next in-

struction. If it awakens from an interrupt, two sequence

may occur. If the related interrupt is disabled or the inter-

rupt is enabled but the stack is full, the program will re-

sume execution at the next instruction. If the interrupt is

enabled and the stack is not full, the regular interrupt re-

sponse takes place. If an interrupt request flag is set to

²1² before entering the HALT mode, the wake-up func-

tion of the related interrupt will be disabled. Once a

wake-up event occurs, it takes 1024 t_SYS(system clock

period) to resume normal operation. In other words, a

dummy period will be inserted after a wake-up. If the

wake-up results from an interrupt acknowledge signal,

the actual interrupt subroutine execution will be delayed

by one or more cycles. If the wake-up results in the next

instruction execution, this will be executed immediately

after the dummy period is finished.

WDTS (09H) Register

The WDT overflow under normal operation will initialize

a ²chip reset² and set the status bit ²TO². But in the

HALT mode, the overflow will initialize a ²warm reset²

and only the program counter and SP are reset to zero.

To clear the contents of the WDT (including the WDT

prescaler), three methods are adopted; external reset (a

low level to RES), software instruction and a ²HALT² in-

struction. The software instruction include ²CLR WDT²

and the other set - ²CLR WDT1² and ²CLR WDT2². Of

these two types of instruction, only one can be active de-

pending on the ROM code option - ²CLR WDT times se-

lection option². If the ²CLR WDT² is selected (i.e.

CLRWDT times is equal to one), any execution of the

²CLR WDT² instruction will clear the WDT. In the case

that ²CLR WDT² and ²CLR WDT² are chosen (i.e.

CLRWDT times is equal to two), these two instructions

must be executed to clear the WDT; otherwise, the WDT

may reset the chip as a result of time-out.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the HALT status.

Power Down Operation - HALT

The HALT mode is initialized by the ²HALT² instruction

and results in the following:

·

The system oscillator will be turned off but the WDT

oscillator remains running (if the WDT oscillator is se-

lected).

·

The contents of the on-chip RAM and registers remain

unchanged.

The WDT and WDT prescaler will be cleared and re-

counted again (if the WDT clock is from the WDT os-

cillator).

Rev. 1.00

11

November 8, 2006

HT82M9AE/HT82M9AA

Reset

The functional unit chip reset status are shown below.

Therearefourwaysinwhicharesetcanoccur:

Program Counter

Interrupt

000H

·

RES reset during normal operation

Disable

Clear

·

RES reset during HALT

Prescaler

·

WDT time-out reset during normal operation

Clear. After master reset,

WDT begins counting

·

USB reset

WDT

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the program counterand SP, leaving

the other circuits in their original state. Some registers

remain unchanged during other reset conditions. Most

registers are reset to the ²initial condition² when the re-

set conditions are met. By examining the PDF and TO

flags, the program can distinguish between different

²chip resets².

Timer/event Counter Off

Input/output Ports

Stack Pointer

Input mode

Points to the top of the stack

V

D

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

0

u

0

1

0

u

0

u

1

R

E

S

WDT time-out during normal operation

WDT wake-up HALT

Reset Circuit

Note: ²u² stands for ²unchanged²

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra delay of 1024 system clock pulses when the sys-

tem resets (power-up, WDT time-out or RES reset) or

the system awakes from the HALT state.

H

A

L

T

W

a

r

m

R

e

s

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t

W

D

T

R

E

S

When a system reset occurs, the SST delay is added

during the reset period. Any wake-up from HALT will en-

able the SST delay.

C

o

l

d

R

e

s

e

t

S

T

1

0

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D

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E

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t

S S T

S

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Reset Configuration

C

h

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Reset Timing Chart

Rev. 1.00

12

November 8, 2006

HT82M9AE/HT82M9AA

The registers status are summarized in the following table.

WDT

RES Reset

(Normal

Operation)

WDT

Time-Out

(HALT)*

Reset

(Power On)

Time-out

(Normal

Operation)

RES Reset

(HALT)

USB-Reset USB-Reset

(HALT)

Register

(Normal)

TMRH

xxxx xxxx

00-0 1---

0000 0000

00-0 1---

0000 0000

00-0 1---

0000 0000

00-0 1---

uuuu uuuu

uu-u u---

uuuu uuuu

00-0 1---

uuuu uuuu

00-0 1---

TMRL

TMRC

Program

Counter

000H

MP0

xxxx xxxx

0000 0000

xxxx xxxx

-xxx xxxx

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

0000 uuuu

--1u uuuu

-000 0000

1000 0111

xxxx xxxx

uuuu uuuu

0000 0000

0000 uuuu

uuuu uuuu

0000 0uuu

11xx xuux

u0uu 0u00

uu00 u000

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

0000 uuuu

--00 uuuu

-000 0000

1000 0111

1111 1111

0000 0000

0000 1110

0100 0000

0000 0000

uuuu uuuu

0000 0110

0000 0111

11xx 0000

0000 0000

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

0000 uuuu

--00 uuuu

-000 0000

1000 0111

1111 1111

0000 0000

0000 1110

0100 0000

0000 0000

uuuu uuuu

0000 0110

0000 0111

11xx 0000

0000 0000

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

0000 uuuu

--11 uuuu

-uuu uuuu

uuuu uuuu

xxxx xxxx

uuuu uuuu

0000 0000

0000 uuuu

uuuu uuuu

0000 0110

0000 0111

11xx xuux

u0uu uuuu

uu0u u000

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

0000 uuuu

--uu uuuu

-000 0000

1000 0111

1111 1111

0000 0000

0000 0110

0000 0111

1100 0u00

u1uu 0000

uu00 u000

uuuu uuuu

0000 0000

uuuu uuuu

-uuu uuuu

0000 uuuu

--01 uuuu

-000 0000

1000 0111

1111 1111

0000 0000

0000 0110

0000 0111

1100 0u00

u1uu 0000

uu00 u000

MP1

ACC

BP

TBLP

TBLH

TBHP

STATUS

INTC

WDTS

PA

xxxx xxxx

--00 xxxx

-000 0000

1000 0111

1111 1111

0000 0000

0000 0110

0100 0000

0x00 0000

xxxx xxxx

0000 0110

0000 0111

11xx 0000

0000 0000

PAC

PB

PBC

AWR

PIPE

STALL

SIES

MISC

FIFO0

FIFO1

FIFO2

Pipe_ctrl

Endpt_EN

USC

USR

SCC

Note:

²*² stands for ²warm reset²

²u² stands for ²unchanged²

²x² stands for ²unknown²

Rev. 1.00

13

November 8, 2006

HT82M9AE/HT82M9AA

Timer/Event Counter

nal (TMR) pin. The timer mode functions as a normal

timer with the clock source coming from the f_SYS/4

(Timer). The pulse width measurement mode can be

used to count the high or low level duration of the exter-

nal signal (TMR). The counting is based on the f_SYS/4.

A timer/event counter (TMR) is implemented in the

microcontroller.

The timer/event counter contains a 16-bit programma-

ble count-up counter and the clock may come from an

external source or from the system clock divided by 4.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFFFH. Once

overflow occurs, the counter is reloaded from the

timer/event counter preload register and generates the

interrupt request flag (TF; bit 6 of the INTC) at the same

time.

Using the internal clock source, there is only 1 reference

time-base for the timer/event counter. The internal clock

source is coming from f_SYS/4. The external clock input

allows the user to count external events, measure time

intervals or pulse widths.

There are 3 registers related to the timer/event counter;

TMRH (0FH), TMRL (10H), TMRC (11H). Writing TMRL

will only put the written data to an internal lower-order

byte buffer (8 bits) and writing TMRH will transfer the

specified data and the contents of the lower-order byte

buffer to TMRH and TMRL preload registers, respec-

tively. The timer/event counter preload register is

changed by each writing TMRH operations. Reading

TMRH will latch the contents of TMRH and TMRL coun-

ters to the destination and the lower-order byte buffer,

respectively. Reading the TMRL will read the contents of

the lower-order byte buffer. The TMRC is the

timer/event counter control register, which defines the

operating mode, counting enable or disable and active

edge.

In the pulse width measurement mode with the TON and

TE bits equal to one, once the TMR has received a tran-

sient from low to high (or high to low if the TE bit is ²0²) it

will start counting until the TMR returns to the original

level and resets the TON. The measured result will re-

main in the timer/event counter even if the activated

transient occurs again. In other words, only one cycle

measurement can be done. Until setting the TON, the

cycle measurement will function again as long as it re-

ceives further transient pulse. Note that, in this operat-

ing mode, the timer/event counter starts counting not

according to the logic level but according to the transient

edges. In the case of counter overflows, the counter is

reloaded from the timer/event counter preload register

and issues the interrupt request just like the other two

modes. To enable the counting operation, the timer ON

bit (TON; bit 4 of TMRC) should be set to 1. In the pulse

width measurement mode, the TON will be cleared au-

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which means that the clock source comes from an exter-

Bit No.

Label

Function

0~2, 5

¾

Unused bit, read as ²0²

Defines the TMR active edge of the timer/event counter

(0=active on low to high; 1=active on high to low)

3

4

TE

TON

Enable/disable the timer counting (0=disable; 1=enable)

Defines the operating mode

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

6

7

TM0

TM1

TMRC (11H) Register

D

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f

S Y S / 4

T

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1

6

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0

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6

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O

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Timer/Event Counter

Rev. 1.00

14

November 8, 2006

HT82M9AE/HT82M9AA

tomatically after the measurement cycle is completed.

But in the other two modes the TON can only be reset by

instructions. The overflow of the timer/event counter is

one of the wake-up sources. No matter what the opera-

tion mode is, writing a ²0² to ET can disable the corre-

sponding interrupt services.

of the control register must write a ²1². The input source

also depends on the control register. If the control regis-

ter bit is ²1², the input will read the pad state. If the con-

trol register bit is ²0², the contents of the latches will

move to the internal bus. The latter is possible in the

²read-modify-write² instruction. For output function,

CMOS/NMOS/PMOS configurations can be selected

(NMOS and PMOS are available for PA only). These

control registers are mapped to locations 13H and 15H.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register will also

reload that data to the timer/event counter. But if the

timer/event counter is turned on, data written to it will

only be kept in the timer/event counter preload register.

The timer/event counter will still operate until overflow

occurs (a timer/event counter reloading will occur at the

same time). When the timer/event counter (reading

TMR) is read, the clock will be blocked to avoid errors.

As clock blocking may result in a counting error, this

must be taken into consideration by the programmer.

After a chip reset, these input/output lines remain at high

levels or in a floating state (depending on the

pull-high/low options). Each bit of these input/output

latches can be set or cleared by ²SET [m].i² and ²CLR

[m].i² (m=12H or 14H) instructions.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Input/Output Ports

There are 16 bidirectional input/output lines in the

microcontroller, labeled from PA to PB, which are

mapped to the data memory of [12H] and [14H] respec-

tively. All of these I/O ports can be used for input and

output operations. For input operation, these ports are

non-latching, that is, the inputs must be ready at the T2

rising edge of instruction ²MOV A,[m]² (m=12H or 14H).

For output operation, all the data is latched and remains

unchanged until the output latch is rewritten.

Each line of PA0~PA7, PB4 and PB7 has the capability

of waking-up the device.

There are pull-high/low options available for I/O lines.

Once the pull-high/low option of an I/O line is selected,

the I/O line have pull-high/low resistor. Otherwise, the

pull-high/low resistor is absent. It should be noted that a

non-pull-high/low I/O line operating in input mode will

cause a floating state.

Each I/O line has its own control register (PAC and PBC)

to control the input/output configuration. With this con-

trol register, CMOS/NMOS/PMOS output or Schmitt

trigger input with or without pull-high/low resistor struc-

tures can be reconfigured dynamically under software

control. To function as an input, the corresponding latch

It is recommended that unused or not bonded out I/O

lines should be set as output pins by software instruction

to avoid consuming power under input floating state.

V

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7

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R

Input/Output Ports

Rev. 1.00

15

November 8, 2006

HT82M9AE/HT82M9AA

The relationship between V_DDand V_LVRis shown below.

Low Voltage Reset - LVR

The microcontroller contains a low voltage reset circuit

in order to monitor the supply voltage of the device. If the

supply voltage of the device drops to within the range of

0.9V~V_LVRsuch as might occur when changing the bat-

tery, the LVR will automatically reset the device inter-

nally.

V

D

V

O P R

5

.

5

V

5

.

5

V

L

V

R

2

.

7

V

The LVR includes the following specifications:

2

.

4

V

·

For a valid LVR signal, a low voltage (0.9V~V_LVR) must

exist for more than 1ms. If the low voltage state does

not exceed 1ms, the LVR will ignore it and will not per-

form a reset function.

0

.

9

V

·

The LVR uses the ²OR² function with the external

RES signal to perform a chip reset.

V

_OPRis the voltage range for proper chip opera-

Note:

tion at 6MHz or 12MHz system clock.

V

D

5

.

5

V

L

V

R

D

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0

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t

*

1

*

2

Low Voltage Reset

Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system

clock pulses before entering the normal operation.

*2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode.

Rev. 1.00

16

November 8, 2006

HT82M9AE/HT82M9AA

USB with MCU Interface

There are eight registers, including Pipe_ctrl, Address+Remote_WakeUp, STALL, PIPE, SIES, MISC, Endpt_EN and

FIFO 0~FIFO 2 in this buffer function.

Register

Name

Addr.+

Remote

Pipe_ctrl

STALL

PIPE

SIES

MISC Endpt_EN FIFO 0 FIFO 1 FIFO 2

46H 47H 48H 49H 4AH

Mem. Addr.

41H

42H

43H

44H

45H

Register Memory Mapping

Address+Remote_WakeUp register represents current address and remote wake-up function. The initial value is

²00000000² from MSB to LSB.

Register

Address

R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Remote Wake-up Function

0: Not this function

Address value

01000010B

R/W

Default value=00000000

1: The function exists

Address+Remote_WakeUp Register

STALL and PIPE, PPE_CTRL, Endpt_EN Registers

PIPE register represents whether the endpoint corresponding is accessed by host or not. After ACT_EN signal being

sent out, MCU can check which endpoint had been accessed. This register is set only after the time when host access

the corresponding endpoint.

STALL register shows whether the endpoint corresponding works or not. As soon as the endpoint work improperly, the

bit corresponding must be set.

Pipe_ctrl register is used for configuring IN (Bit=1) or OUT (Bit=0) pipe. The default is define IN pipe. Where Bit0

(DATA0) of the Pipe_ctrl register is used to setting the data toggle of any endpoint (except endpoint 0) using data tog-

gles to the value DATA0. Once the user want the any endpoint (except endpoint 0) using data toggles to the value

DATA0, the user can output a LOW pulse to this bit. The LOW pulse period must at least 10 instruction cycle.

Endpt_EN register is used to enable or disable the corresponding endpoint (except endpoint 0). Enable Endpoint

(Bit=1) or disable Endpoint (Bit=0).

The bitmaps are list as follows:

Register

Address

Default

Value

Register Name

R/W

Bit7~Bit3 Reserved

Bit 2

Bit 1

Bit 0

Pipe_ctrl

STALL

R/W

R

01000001B

01000011B

01000100B

01000111B

Pipe 2

Pipe 1

Pipe 0

0000 0111

0000 0000

0000 0111

¾

PIPE

Endpt_EN

R/W

Pipe_ctrl (41H), STALL (43H), PIPE (44H) and Endpt_EN (47H) Registers

Rev. 1.00

17

November 8, 2006

HT82M9AE/HT82M9AA

The SIES Register is used to indicate the present signal state which the USB SIE received and also determines

whether the USB SIE has to change the device address automatically.

Bit No.

Function

MNI

Read/Write

Register Address

7

6

5

4

3

2

1

0

R/W

R

EOT

CRC_ERR

NAK

R/W

R

01000101B

IN

R

OUT

R/W

F0_ERR

Adr_set

SIES (45H) Registers Table

Function

Name

Read/Write

Description

This bit is used to configure the USB SIE to automatically change the device address with

the value of the Address+Remote_WakeUp Register (42H).

When this bit is set to 1 by F/W, the USB SIE will update the device address with the value

of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully read

the data from the device by the IN operation. The USB SIE will clear the bit after updating

the device address.

Adr_set

R/W

Otherwise, when this bit is cleared to ²0², the USB SIE will update the device address im-

mediately after an address is written to the Address+Remote_WakeUp Register (42H).

This bit is used to indicate when there are some errors that occurred when the FIFO0 is

accessed.

F0_Err

Out

R/W

This bit is set by the USB SIE and cleared by F/W.

This bit is used to indicate that there are OUT token (except for the OUT zero) that has

been received. The F/W clears the bit after the OUT data has been read. Also, this bit will

be cleared by the USB SIE after the next valid SETUP token is received.

This bit is used to indicate that the current USB receiving signal from the PC Host is IN to-

ken.

IN

R

This bit is used to indicate that the USB SIE has transmitted the NAK signal to the Host in

response to the PC Host IN or OUT token.

NAK

This bit indicates that there are CRC error (bit=1). The programmer must do something to

save the device and keep it alive.

CRC_err

R/W

This bit is set by the USB SIE and cleared by F/W.

End of transient flag, normal status is ²1². If suspend=²1² line & EOT=²0² indicates that

something is wrong in the USB Interface. The programmer must do something to save the

device and keep it alive.

EOT

MNI

R

R/W

This bit is for masking the NAK interrupt when MNI=²1², the default value=²0²

SIES Function Table

Rev. 1.00

18

November 8, 2006

HT82M9AE/HT82M9AA

The MISC register is actually a command + status to control the desired FIFO action and to show the status of the de-

sired FIFO. Every bit¢s meaning and usage are listed as follows:

Bit No.

Function

Len0

Read/Write

R/W

Register Address

7

6

5

4

3

2

1

0

Ready

R

Set CMD

Sel_pipe1

Sel_pipe0

Clear

R/W

01000110B

R/W

Tx

R/W

Request

R/W

MISC (46H) Registers Table

Description

Function

Name

Read/Write

After setting the other desired status, FIFO can be requested by setting this bit high ac-

tive. After work has been done, this bit must be set low.

Request

R/W

Represents the direction and transition end of the MCU accesses. When being set as

logic 1, the MCU wants to write data to FIFO. After work has been done, this bit must be

set to logic 0 before terminating the request to represent a transition end. For reading

action, this bit must be set to logic 0 to indicate that the MCU wants to read and must be

set to logic 1 after work is done.

Tx

R/W

Clear

R/W

Represents MCU clear requested FIFO, even if FIFO is not ready.

Sel_pipe1

Sel_pipe0

Determines which FIFO is desired, ²00² for FIFO 0, ²01² for FIFO 1 and ²10² for FIFO 2

Shows that the data in FIFO is setup as command. This bit will be cleared by firmware.

So, even if the MCU is busy, nothing is missed by the SETUP command from the host.

Set CMD

Ready

R/W

R

Indicates that the desired FIFO is ready to work.

Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a

read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after

the next valid SETUP token is received.

Len0

R/W

MISC Function Table

HT82M9AE/HT82M9AA allows a maximum of 8 bytes of

The HT82M9AE/HT82M9AA have two 8´8 bidirectional

FIFO for the three endpoints (control and Interrupt).

User can easily read/write the FIFO data by accessing

the corresponding FIFO pointer register (FIFO0, FIFO1,

FIFO2). The following are two examples for reading and

writing the FIFO data:

data in each packet.

The HT82M9AE/HT82M9AA FIFO is written by packet.

To write to FIFO, the following should be followed:

·

Select a set of FIFO, set in the write mode (MISC TX

bit = 1), and set the REQ bit to ²1²

HT82M9AE/HT82M9AAFIFO is read by packet. To read

from FIFO, the following should be followed:

·

Check the ready bit until the status = 1

Write through the FIFO pointer register and take down

the data number that has been written

·

Select one set of FIFO, set in the read mode (MISC

TX bit = 0), and set the REQ bit to ²1².

·

Repeat steps 2 and 3 until writing is complete or the

ready bit becomes 0 which indicates that the FIFO no

longer allows any data writing.

·

Check the ready bit until the status = 1

Read through the FIFO pointer register, and record

the data number that has been read.

·

Set MISC TX bit = 0

·

Clear the REQ bit to 0. Complete writing.

Repeat steps 2 and 3 until the ready bit becomes 0

which indicates the end of the FIFO data reading.

User writes the data through the FIFO pointer register,

user has to record the number of bytes that have been

written. The HT82M9AE/HT82M9AA allows a maximum

of 8 bytes of data in each packet.

·

Set MISC TX bit = 1

Clear the REQ bit to 0. Complete reading.

User reads the data through the FIFO pointer register,

user has to record the number of bytes to be read. The

Rev. 1.00

19

November 8, 2006

HT82M9AE/HT82M9AA

There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform read-

ing, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writ-

ing and clearing.

Actions

Read FIFO0 sequence

MISC Setting Flow and Status

00H®01H®delay of 2ms, check 41H®read* from FIFO0 register

and check if not ready (01H)®03H®02H

0AH®0BH®delay of 2ms, check 4BH®write* to FIFO1 register and

check if not ready (0BH)®09H®08H

Write FIFO1 sequence

00H®01H®delay of 2ms, check 41H (if ready) or 01H (if not ready)

®00H

Check whether FIFO0 can be read or not

Check whether FIFO1 can be written to or not

0AH®0BH®delay of 2ms, check 4BH (if ready) or 0BH (if not ready)

®0AH

Write 0-sized packet sequence to FIFO 0

Note:

02H®03H®delay of 2ms, check 43H®01H®00H

*: There are 2ms gap existing between 2 reading actions or between 2 writing actions

Register Name

FIFO 0

R/W

Register Address

01001000B

Bit7~Bit0

Data7~Data0

FIFO 1

01001001B

FIFO 2

01001010B

FIFO Register Address Table

USB Active Pipe Timing

The USB active pipe accessed by the host cannot be used by the MCU simultaneously. When the host finishes its work,

the signal, a USB_INT will be produced to tell the MCU that the pipe can be used and the acted pipe No. will be shown

in the signal, ACT_PIPE as well. The timing is illustrated in the figure below.

L

a

s

t

A

c

t

e

d

P

i

p

e

A

C

T

_

P

I

P

E

U

S

B

_

I

N

T

USB Active Pipe Timing

Suspend Wake-Up and Remote Wake-Up

signal is sent out by the host and the Suspend line (bit 0

of the USC) is going to ²0². So when the MCU is detect-

ing the Suspend line (bit0 of the USC), the Resume line

should be remembered and taken into consideration.

If there is no signal on the USB bus for over 3ms, the

HT82M9AE/HT82M9AA will go into a suspend mode.

The Suspend line (bit 0 of the USC) will be set to 1 and a

USB interrupt is triggered to indicate that the

HT82M9AE/HT82M9AA should jump to the suspend

state to meet the 500mA USB suspend current spec.

After finishing the resume signal, the suspend line will

go inactive and a USB interrupt is triggered. The follow-

ing is the timing diagram:

In order to meet the 500mA suspend current, the pro-

grammer should disable the USB clock by clearing the

USBCKEN (bit3 of the SCC) to ²0². The suspend cur-

rent is 400mA.

S

U

S

P

E

N

D

U

S

B

R

e

s

u

m

e

S

i

g

n

a

l

When the resume signal is sent out by the host, the

HT82M9AE/HT82M9AA will wake-up the MCU by USB

interrupt and the Resume line (bit 3 of the USC) is set. In

order to make the HT82M9AE/HT82M9AA function

properly, the programmer must set the USBCKEN (bit 3

of the SCC) to 1 and clear the SUSP2 (bit4 of the SCC).

Since the Resume signal will be cleared before the Idle

U

S

B

_

I

N

T

The device with remote wake-up function can wake-up the

USB Host by sending a wake-up pulse through RMWK (bit

1 of USC). Once the USB Host receive the wake-up signal

from the HT82M9AE/HT82M9AA, it will send a Resume

Rev. 1.00

20

November 8, 2006

HT82M9AE/HT82M9AA

signal to the device. The timing is as follows:

pin and USBD+ is now defined as PS2 Clk pin. The user

can easily read or write to the PS2 Data or PS2 Clk pin

by accessing the corresponding bit PS2DAI (bit 4 of the

USC), PS2CKI (bit 5 of the USC), PS2DAO (bit 6 of the

USC) and S2CKO (bit 7 of the USC) respectively.

S

U

S

P

E

N

D

M

i

n

.

1

U

S

B

C

L

K

R

M

W

K

The user should make sure that in order to read the data

properly, the corresponding output bit must be set to ²1².

For example, if user wants to read the PS2 Data by

reading PS2DAI, the PS2DAO should be set to ²1². Oth-

erwise it always read a ²0².

M

i

n

.

2

.

5

m

s

U

S

B

R

e

s

u

m

e

S

i

g

n

a

l

U

S

B

_

I

N

T

If SPS2=0, and SUSB=1, the HT82M9AE/HT82M9AA is

defined as a USB interface. Both the USBD- and

USBD+ are driven by the USB SIE of the

HT82M9AE/HT82M9AA. User only writes or reads the

USB data through the corresponding FIFO.

Configuring the Device as a PS2 Device

The HT82M9AE/HT82M9AA can be defined as a USB

interface or a PS2 interface by configuring the SPS2 (bit

4 of the USR) and SUSB (bit 5 of the USR). If SPS2=1,

and SUSB=0, the HT82M9AE/HT82M9AA is defined as

PS2 interface, pin USBD- is now defined as PS2 Data

Both SPS2 and SUSB default is ²0².

I/O Port Special Registers Definition

·

Port-A (12H) - PA

Bit No.

Label

Read/Write Option

Functions

I/O (R/W) has pull-low and pull-high option.

Has falling edge wake-up option.

0~3

PA0~PA3

R/W

¾

I/O (R/W) has pull-high option.

Has falling edge wake-up option.

4~6

7

PA4~PA6

PA7

I/O (R/W) has pull-high option.

Has falling edge wake-up option, pin-shared with timer input pin.

PA (12H) Register

·

Port-A Control (13H) - PAC

This port configure the input or output mode of Port-A

Port-B Control (14H) - PB

Bit No.

Label

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

Read/Write Option

Functions

I/O (R/W), has pull-high option

0

1

2

3

4

5

6

7

R/W

¾

I/O (R/W), has pull-high option

I/O (R/W), has pull-low and pull-high option

I/O (R/W), has pull-high option, can wake-up

I/O (R/W), has pull-high option

I/O (R/W), has pull-high option, can wake-up

PB (14H) Register

·

Port-B Control (15H) - PBC

This port configures the input or output mode of Port-B for I/O mode

Rev. 1.00

21

November 8, 2006

HT82M9AE/HT82M9AA

USB/PS2 Status and Control Register - USC

Bit No.

Label

Read/Write

Option

Functions

USB suspend mode status bit. When 1, indicates that the USB

system entry is in suspend mode.

0

PE0

R

SUSPEND

1

2

PE1

PE2

W

RMOT_WK

USB remote wake-up signal. The default value is ²0².

USB bus reset event flag. The default value is ²0².

R/W

URST_FLAG

When RESUME_OUT EVENT, RESUME_O is set to ²1².

The default value is ²0².

3

PE3

R

RESUME_O

4

5

PE4

PE5

R

PS2_DAI USBD-/DATA input

PS2_CKI USBD+/CLK input

Output for driving USBD-/DATA pin, when working under 3D

6

7

PE6

PE7

W

PS2_DAO

PS2_CKO

PS2 mouse function. The default value is ²1².

Output for driving USBD-/DATA pin, when working under 3D

PS2 mouse function. The default value is ²1².

USC (0X1A) Register

Endpoint Interrupt Status Register - USR

The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select

the serial bus (PS2 or USB). The endpoint request flags (EP0IF, EP1IF) are used to indicate which endpoints are ac-

cessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and a USB interrupt will occur (If a

USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint request

flag has to be cleared to ²0².

Bit No.

Label

Read/Write

Option

Functions

When set to ²1², indicates an endpoint 0 interrupt event. Must

wait for the MCU to process the interrupt event and clear this

bit by firmware. This bit must be ²0², then the next interrupt

event will be processed. The default value is ²0².

0

PEC0

R/W

EP0IF

When set to ²1², indicates an endpoint 1 interrupt event. Must

wait for the MCU to process the interrupt event, then clear this

bit by firmware. This bit must be ²0², then the next interrupt

event will be processed. The default value is ²0².

1

PEC1

R/W

EP1IF

2~3,

6

PEC2~PEC3,

PEC6

R/W

¾

Reserved bit, set to ²0²

When set to ²1², indicates that the chip is working under PS2

mode. The default value is ²0².

4

5

PEC4

PEC5

SELPS2

When set to ²1², indicates that the chip is working under USB

mode. The default value is ²0².

SELUSB

USB_flag

This flag is used to show that the MCU is in USB mode (Bit=1).

This bit is R/W by FW and will be cleared to zero after power-on

reset. The default value is ²0².

7

PEC7

R/W

USR (0X1B) Register

Rev. 1.00

22

November 8, 2006

HT82M9AE/HT82M9AA

Clock Control Register - SCC

There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB

clock control bit (USBCKEN), second suspend mode control bit (SUSPEND2) and system clock selection (SCLKSEL).

Bit No.

Label

Read/Write

Option

Functions

Reserved, must set to ²0².

2~0,

4~5

PF2~PF0,

PF4~PF5

R/W

¾

USB clock control bit. When set to ²1², indicates a USBCK ON,

else USBCK OFF. The default value is ²0².

3

PF3

R/W

USBCKEN

System clock 6MHz or 12MHz option, when working on exter-

nal oscillator mode. The default value is ²0².

6

PF6

SCLKSEL 0: Operating at external 12MHz mode

1: Operating at external 6MHz mode

The default value is ²0².

This flag is used to show that the MCU is in PS2 mode (Bit=1).

This bit is R/W by FW and will be cleared to zero after power-on

7

PF7

R/W

PS2_flag

reset. The default value is ²0².

SCC (0X1C) Register

Table High Byte Pointer for Current Table Read - TBHP

Bit No.

Label

Read/Write

Option

Functions

3~0

PGC3~PGC0

R/W

Store current table read bit11~bit8 data

¾

TBHP (0X1F) Register

Options

No.

Option

1

2

WDT clock source: RC (system/4) (default: T1)

WDT clock source: enable/disable for normal mode (default: disable)

PA0~PA7 ,PB4, PB7 wake-up by bit (PA2, PA3 both wake-up by falling or rising edge)

(default: non wake-up)

3

4

5

PA0~PA7 pull-high by bit (default: pull-high)

PB pull-high by bit (default: pull-high)

6

LVR enable/disable (default: enable)

7

PA0~PA3, PB2, PB3 pull-low by bit (default: non pull-low 30kW)

²CLR WDT², 1 or 2 instructions

8

9

TBHP enable/disable (default: disable)

10

PA output mode (CMOS/NMOS/PMOS) by bit (default: CMOS)

Rev. 1.00

23

November 8, 2006

HT82M9AE/HT82M9AA

Application Circuits

Crystal or Ceramic Resonator for Multiple I/O Applications

3

W

*

5

W

*

V

D

P

A

B

0

~

P

A

B

7

V

D

*

U

S

B

-

0

.

1

m

F

1

0

m

F

1

0

k

W

0

.

1

m

F

1

M

W

*

U

S

B

+

V

S

2

p

F

1

.

5

k

W

O

S

C

1

2

V

3

O

X

1

*

0

.

1

m

F

*

2

p

F

4

7

p

F

*

5

W

3

W

1

0

k

W

*

U

S

B

D

-

/

D

A

T

A

R

E

S

*

4

7

p

F

0

.

1

m

F

0

.

1

m

F

*

4

7

p

F

*

3

W

*

V

S

U

S

B

D

+

/

C

L

K

*

H

T

8

2

M

9

A

E

/

H

T

8

2

M

9

A

Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD

is stable and remains within a valid operating voltage range before bringing RES to high.

X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible

Components with * are used for EMC issue.

Components with ** are used for resonator only.

Components with *** are used for 12MHz application.

Rev. 1.00

24

November 8, 2006

HT82M9AE/HT82M9AA

Instruction Set Summary

Mnemonic

Instruction

Cycle

Flag

Affected

Description

Arithmetic

ADD A,[m]

ADDM A,[m]

ADD A,x

Add data memory to ACC

1

1⁽¹⁾

1

Z,C,AC,OV

C

Add ACC to data memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add data memory to ACC with carry

1

1⁽¹⁾

Add ACC to data memory with carry

Subtract immediate data from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

Subtract data memory from ACC

1

1⁽¹⁾

Subtract data memory from ACC with result in data memory

Subtract data memory from ACC with carry

Subtract data memory from ACC with carry and result in data memory

Decimal adjust ACC for addition with result in data memory

1

1⁽¹⁾

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

AND data memory to ACC

1

Z

OR data memory to ACC

Exclusive-OR data memory to ACC

AND ACC to data memory

1

1⁽¹⁾

1

OR ACC to data memory

Exclusive-OR ACC to data memory

AND immediate data to ACC

OR immediate data to ACC

OR A,x

1

XOR A,x

Exclusive-OR immediate data to ACC

Complement data memory

1

1⁽¹⁾

CPL [m]

CPLA [m]

Complement data memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment data memory with result in ACC

1

Z

Increment data memory

1⁽¹⁾

DECA [m]

DEC [m]

Decrement data memory with result in ACC

Decrement data memory

1

1⁽¹⁾

Rotate

RRA [m]

RR [m]

Rotate data memory right with result in ACC

Rotate data memory right

1

1⁽¹⁾

1

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate data memory right through carry with result in ACC

Rotate data memory right through carry

Rotate data memory left with result in ACC

Rotate data memory left

1⁽¹⁾

C

1

None

C

1⁽¹⁾

1

RLCA [m]

RLC [m]

Rotate data memory left through carry with result in ACC

Rotate data memory left through carry

1⁽¹⁾

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move data memory to ACC

Move ACC to data memory

Move immediate data to ACC

1

1⁽¹⁾

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of data memory

Set bit of data memory

1⁽¹⁾

None

Rev. 1.00

25

November 8, 2006

HT82M9AE/HT82M9AA

Instruction

Cycle

Flag

Affected

Mnemonic

Branch

Description

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if data memory is zero

1⁽²⁾

1⁽³⁾

1⁽²⁾

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if data memory is zero with data movement to ACC

Skip if bit i of data memory is zero

Skip if bit i of data memory is not zero

Skip if increment data memory is zero

Skip if decrement data memory is zero

Skip if increment data memory is zero with result in ACC

Skip if decrement data memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC[M](⁵⁾Read ROM code (locate by TBLPand TBHP) to data memory and TBLH

TABRDC[m]⁽⁶⁾Read ROM code (current page) to data memory and TBLH

2⁽¹⁾

None

TABRDL [m]

Read ROM code (last page) to data memory and TBLH

Miscellaneous

NOP

No operation

1

1⁽¹⁾

1

None

CLR [m]

Clear data memory

SET [m]

Set data memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO,PDF

TO⁽⁴⁾,PDF⁽⁴⁾

None

Pre-clear Watchdog Timer

Swap nibbles of data memory

Swap nibbles of data memory with result in ACC

Enter power down mode

1

1⁽¹⁾

1

None

1

TO,PDF

Note: x: Immediate data

m: Data memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Ö: Flag is affected

-: Flag is not affected

⁽¹⁾: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle

(four system clocks).

⁽²⁾: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more

cycle (four system clocks). Otherwise the original instruction cycle is unchanged.

⁽¹⁾and ⁽²⁾

(3)

:

⁽⁴⁾: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the

²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.

Otherwise the TO and PDF flags remain unchanged.

⁽⁵⁾: ²ROM code TBHP option² is enabled

⁽⁶⁾: ²ROM code TBHP option² is disabled

Rev. 1.00

26

November 8, 2006

HT82M9AE/HT82M9AA

Instruction Definition

ADC A,[m]

Add data memory and carry to the accumulator

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADCM A,[m]

Add the accumulator and carry to data memory

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the specified data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,[m]

Add data memory to the accumulator

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the accumulator.

Operation

ACC ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,x

Add immediate data to the accumulator

Description

The contents of the accumulator and the specified data are added, leaving the result in the

accumulator.

Operation

ACC ¬ ACC+x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADDM A,[m]

Add the accumulator to the data memory

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the data memory.

Operation

[m] ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 1.00

27

November 8, 2006

HT82M9AE/HT82M9AA

AND A,[m]

Logical AND accumulator with data memory

Description

Data in the accumulator and the specified data memory perform a bitwise logical_AND op-

eration. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

AND A,x

Logical AND immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_AND operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ANDM A,[m]

Logical AND data memory with the accumulator

Description

Data in the specified data memory and the accumulator perform a bitwise logical_AND op-

eration. The result is stored in the data memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

CALL addr

Subroutine call

Description

The instruction unconditionally calls a subroutine located at the indicated address. The

program counter increments once to obtain the address of the next instruction, and pushes

this onto the stack. The indicated address is then loaded. Program execution continues

with the instruction at this address.

Operation

Stack ¬ Program Counter+1

Program Counter ¬ addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR [m]

Clear data memory

Description

Operation

The contents of the specified data memory are cleared to 0.

[m] ¬ 00H

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.00

28

November 8, 2006

HT82M9AE/HT82M9AA

CLR [m].i

Clear bit of data memory

Description

Operation

The bit i of the specified data memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR WDT

Clear Watchdog Timer

Description

The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are

cleared.

Operation

WDT ¬ 00H

PDF and TO ¬ 0

Affected flag(s)

TO

0

PDF

0

OV

Z

AC

C

¾

CLR WDT1

Preclear Watchdog Timer

Description

Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction just sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CLR WDT2

Preclear Watchdog Timer

Description

Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction, sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CPL [m]

Complement data memory

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa.

Operation

[m] ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.00

29

November 8, 2006

HT82M9AE/HT82M9AA

CPLA [m]

Complement data memory and place result in the accumulator

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa. The complemented result

is stored in the accumulator and the contents of the data memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DAA [m]

Decimal-Adjust accumulator for addition

Description

The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-

lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal

carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-

justment is done by adding 6 to the original value if the original value is greater than 9 or a

carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored

in the data memory and only the carry flag (C) may be affected.

Operation

If ACC.3~ACC.0 >9 or AC=1

then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC

else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0

and

If ACC.7~ACC.4+AC1 >9 or C=1

then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1

else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

DEC [m]

Decrement data memory

Description

Operation

Data in the specified data memory is decremented by 1.

[m] ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DECA [m]

Decrement data memory and place result in the accumulator

Description

Data in the specified data memory is decremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.00

30

November 8, 2006

HT82M9AE/HT82M9AA

HALT

Enter power down mode

Description

This instruction stops program execution and turns off the system clock. The contents of

the RAM and registers are retained. The WDT and prescaler are cleared. The power down

bit (PDF) is set and the WDT time-out bit (TO) is cleared.

Operation

Program Counter ¬ Program Counter+1

PDF ¬ 1

TO ¬ 0

Affected flag(s)

TO

0

PDF

1

OV

Z

AC

C

¾

INC [m]

Increment data memory

Description

Operation

Data in the specified data memory is incremented by 1

[m] ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

INCA [m]

Increment data memory and place result in the accumulator

Description

Data in the specified data memory is incremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

JMP addr

Directly jump

Description

The program counter are replaced with the directly-specified address unconditionally, and

control is passed to this destination.

Operation

Program Counter ¬addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV A,[m]

Description

Operation

Move data memory to the accumulator

The contents of the specified data memory are copied to the accumulator.

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.00

31

November 8, 2006

HT82M9AE/HT82M9AA

MOV A,x

Move immediate data to the accumulator

Description

Operation

The 8-bit data specified by the code is loaded into the accumulator.

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV [m],A

Move the accumulator to data memory

Description

The contents of the accumulator are copied to the specified data memory (one of the data

memories).

Operation

[m] ¬ACC

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

Program Counter ¬ Program Counter+1

TO

PDF

OV

Z

AC

C

¾

OR A,[m]

Logical OR accumulator with data memory

Description

Data in the accumulator and the specified data memory (one of the data memories) per-

form a bitwise logical_OR operation. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

OR A,x

Logical OR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_OR operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ORM A,[m]

Logical OR data memory with the accumulator

Description

Data in the data memory (one of the data memories) and the accumulator perform a

bitwise logical_OR operation. The result is stored in the data memory.

Operation

[m] ¬ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.00

32

November 8, 2006

HT82M9AE/HT82M9AA

RET

Return from subroutine

Description

Operation

Affected flag(s)

The program counter is restored from the stack. This is a 2-cycle instruction.

Program Counter ¬ Stack

TO

PDF

OV

Z

AC

C

¾

RET A,x

Return and place immediate data in the accumulator

Description

The program counter is restored from the stack and the accumulator loaded with the speci-

fied 8-bit immediate data.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RETI

Return from interrupt

Description

The program counter is restored from the stack, and interrupts are enabled by setting the

EMI bit. EMI is the enable master (global) interrupt bit.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RL [m]

Rotate data memory left

Description

Operation

The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RLA [m]

Rotate data memory left and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the

rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.00

33

November 8, 2006

HT82M9AE/HT82M9AA

RLC [m]

Rotate data memory left through carry

Description

The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-

places the carry bit; the original carry flag is rotated into the bit 0 position.

Operation

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RLCA [m]

Rotate left through carry and place result in the accumulator

Description

Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the

carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored

in the accumulator but the contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RR [m]

Rotate data memory right

Description

Operation

The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRA [m]

Rotate right and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving

the rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRC [m]

Rotate data memory right through carry

Description

The contents of the specified data memory and the carry flag are together rotated 1 bit

right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.

Operation

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 1.00

34

November 8, 2006

HT82M9AE/HT82M9AA

RRCA [m]

Rotate right through carry and place result in the accumulator

Description

Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces

the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is

stored in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBC A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBCM A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SDZ [m]

Skip if decrement data memory is 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. If the result is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, [m] ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SDZA [m]

Decrement data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. The result is stored in the accumulator but the data memory remains

unchanged. If the result is 0, the following instruction, fetched during the current instruction

execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-

cles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, ACC ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.00

35

November 8, 2006

HT82M9AE/HT82M9AA

SET [m]

Set data memory

Description

Operation

Each bit of the specified data memory is set to 1.

[m] ¬ FFH

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SET [m]. i

Set bit of data memory

Description

Operation

Bit i of the specified data memory is set to 1.

[m].i ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZ [m]

Skip if increment data memory is 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the fol-

lowing instruction, fetched during the current instruction execution, is discarded and a

dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with

the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, [m] ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZA [m]

Increment data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the next

instruction is skipped and the result is stored in the accumulator. The data memory re-

mains unchanged. If the result is 0, the following instruction, fetched during the current in-

struction execution, is discarded and a dummy cycle is replaced to get the proper

instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, ACC ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SNZ [m].i

Skip if bit i of the data memory is not 0

Description

If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data

memory is not 0, the following instruction, fetched during the current instruction execution,

is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-

wise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i¹0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.00

36

November 8, 2006

HT82M9AE/HT82M9AA

SUB A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the accumulator.

Operation

ACC ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUBM A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the data memory.

Operation

[m] ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUB A,x

Subtract immediate data from the accumulator

Description

The immediate data specified by the code is subtracted from the contents of the accumula-

tor, leaving the result in the accumulator.

Operation

ACC ¬ ACC+x+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SWAP [m]

Swap nibbles within the data memory

Description

The low-order and high-order nibbles of the specified data memory (1 of the data memo-

ries) are interchanged.

Operation

[m].3~[m].0 « [m].7~[m].4

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SWAPA [m]

Swap data memory and place result in the accumulator

Description

The low-order and high-order nibbles of the specified data memory are interchanged, writ-

ing the result to the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.3~ACC.0 ¬ [m].7~[m].4

ACC.7~ACC.4 ¬ [m].3~[m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.00

37

November 8, 2006

HT82M9AE/HT82M9AA

SZ [m]

Skip if data memory is 0

Description

If the contents of the specified data memory are 0, the following instruction, fetched during

the current instruction execution, is discarded and a dummy cycle is replaced to get the

proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZA [m]

Move data memory to ACC, skip if 0

Description

The contents of the specified data memory are copied to the accumulator. If the contents is

0, the following instruction, fetched during the current instruction execution, is discarded

and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed

with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZ [m].i

Skip if bit i of the data memory is 0

Description

If bit i of the specified data memory is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDC [m]

Description

Operation

Move the ROM code (locate by TBLP and TBHP) to TBLH and data memory (ROM code

TBHP is enabled)

The low byte of ROM code addressed by the table pointers (TBLPand TBHP) is moved to

the specified data memory and the high byte transferred to TBLH directly.

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDC [m]

Description

Operation

Move the ROM code (current page) to TBLH and data memory (ROM code TBHP is

disabled)

The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved

to the specified data memory and the high byte transferred to TBLH directly.

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.00

38

November 8, 2006

HT82M9AE/HT82M9AA

TABRDL [m]

Move the ROM code (last page) to TBLH and data memory

Description

The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to

the data memory and the high byte transferred to TBLH directly.

Operation

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

XOR A,[m]

Logical XOR accumulator with data memory

Description

Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-

sive_OR operation and the result is stored in the accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XORM A,[m]

Logical XOR data memory with the accumulator

Description

Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-

sive_OR operation. The result is stored in the data memory. The 0 flag is affected.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XOR A,x

Logical XOR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-

eration. The result is stored in the accumulator. The 0 flag is affected.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.00

39

November 8, 2006

HT82M9AE/HT82M9AA

Package Information

20-pin SOP (300mil) Outline Dimensions

2

0

1

A

B

1

0

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

394

290

14

490

92

¾

Max.

419

300

20

A

B

C

C¢

D

E

F

¾

50

¾

510

104

¾

4

¾

G

H

a

32

4

38

12

0°

10°

Rev. 1.00

40

November 8, 2006

HT82M9AE/HT82M9AA

20-pin SSOP (150mil) Outline Dimensions

2

0

1

A

B

1

0

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

228

150

8

Max.

244

158

12

A

B

C

C¢

D

E

F

¾

25

¾

335

49

¾

347

65

¾

4

10

G

H

a

15

7

50

10

0°

8°

Rev. 1.00

41

November 8, 2006

HT82M9AE/HT82M9AA

24-pin SOP (300mil) Outline Dimensions

2

4

1

3

A

B

1

2

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

394

290

14

590

92

¾

Max.

419

300

20

A

B

C

C¢

D

E

F

¾

50

¾

614

104

¾

4

¾

G

H

a

32

4

38

12

0°

10°

Rev. 1.00

42

November 8, 2006

HT82M9AE/HT82M9AA

24-pin SSOP (150mil) Outline Dimensions

2

4

1

3

A

B

1

2

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

228

150

8

Max.

244

157

12

A

B

C

C¢

D

E

F

¾

25

¾

335

54

¾

346

60

¾

4

10

G

H

a

22

7

28

10

0°

8°

Rev. 1.00

43

November 8, 2006

HT82M9AE/HT82M9AA

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SOP 20W

Symbol

Description

Dimensions in mm

330±1

A

B

Reel Outer Diameter

Reel Inner Diameter

62±1.5

13+0.5

C

D

Spindle Hole Diameter

Key Slit Width

-0.2

2±0.5

24.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

30.2±0.2

SOP 24W

Symbol

Description

Dimensions in mm

330±1

A

B

Reel Outer Diameter

Reel Inner Diameter

62±1.5

13+0.5

C

D

Spindle Hole Diameter

Key Slit Width

-0.2

2±0.5

24.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

30.2±0.2

Rev. 1.00

44

November 8, 2006

HT82M9AE/HT82M9AA

SSOP 20S (150mil)

Symbol

Description

Reel Outer Diameter

Reel Inner Diameter

Dimensions in mm

330±1

A

B

62±1.5

13+0.5

C

D

Spindle Hole Diameter

Key Slit Width

-0.2

2±0.5

16.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

22.2±0.2

SSOP 24S (150mil)

Symbol

Description

Reel Outer Diameter

Reel Inner Diameter

Dimensions in mm

330±1

A

B

62±1.5

13+0.5

C

D

Spindle Hole Diameter

Key Slit Width

-0.2

2±0.5

16.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

22.2±0.2

Rev. 1.00

45

November 8, 2006

HT82M9AE/HT82M9AA

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

W

B

0

C

D

1

P

K

0

A

0

SOP 20W

Symbol

Description

Dimensions in mm

24+0.3

W

Carrier Tape Width

-0.1

P

E

Cavity Pitch

12±0.1

1.75±0.1

11.5±0.1

1.5+0.1

1.5+0.25

4±0.1

Perforation Position

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

2±0.1

10.8±0.1

13.3±0.1

3.2±0.1

0.3±0.05

21.3

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

C

SOP 24W

Symbol

Description

Carrier Tape Width

Dimensions in mm

24±0.3

W

P

Cavity Pitch

12±0.1

E

Perforation Position

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

1.75±0.1

11.5±0.1

1.55+0.1

1.5+0.25

4±0.1

F

D

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

2±0.1

10.9±0.1

15.9±0.1

3.1±0.1

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

0.35±0.05

21.3

C

Rev. 1.00

46

November 8, 2006

HT82M9AE/HT82M9AA

SSOP 20S (150mil)

Symbol

Description

Carrier Tape Width

Cavity Pitch

Dimensions in mm

16+0.3

W

-0.1

P

E

8±0.1

1.75±0.1

7.5±0.1

1.5+0.1

1.5+0.25

4±0.1

Perforation Position

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

F

D

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

2±0.1

6.5±0.1

9±0.1

Cavity Width

Cavity Depth

2.3±0.1

0.3±0.05

13.3

Carrier Tape Thickness

Cover Tape Width

C

SSOP 24S (150mil)

Symbol

Description

Carrier Tape Width

Cavity Pitch

Dimensions in mm

16+0.3

W

-0.1

P

E

8±0.1

1.75±0.1

7.5±0.1

1.5+0.1

1.5+0.25

4±0.1

Perforation Position

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

F

D

D1

P0

P1

A0

B0

K0

t

Cavity to Perforation (Length Direction)

Cavity Length

2±0.1

6.5±0.1

9.5±0.1

2.1±0.1

0.3±0.05

13.3

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

C

Rev. 1.00

47

November 8, 2006

HT82M9AE/HT82M9AA

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233

Tel: 86-21-6485-5560

Fax: 86-21-6485-0313

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,

Shenzhen, China 518057

Tel: 86-755-8616-9908, 86-755-8616-9308

Fax: 86-755-8616-9533

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752

Fax: 86-10-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016

Tel: 86-28-6653-6590

Fax: 86-28-6653-6591

Holmate Semiconductor, Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538

Tel: 1-510-252-9880

Fax: 1-510-252-9885

http://www.holmate.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.00

48

November 8, 2006


型号：	HT82M9AA(20SSOP)
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Microcontroller 微控制器
文件：	总48页 (文件大小：292K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT82M9AA(20SSOP) [HOLTEK]

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