HT86R192(28SOP)_技术文档

HT86R192

Voice Synthesizer 8-Bit OTP MCU

Preliminary

Technical Document

·

Tools Information

FAQs

Application Note

Features

·

Operating voltage: 2.4V~5.2V

System clock: 4MHz~8MHz

Crystal or RC oscillator for system clock

23 I/O pins with 4 shared pins included

8K´16-bit program ROM

Built-in voice ROM in various capacity

One optional 32768Hz crystal oscillator for RTC time

base (8-bit counter with 3-bit prescaler)

·

Watchdog Timer

8-level subroutine nesting

HALT function and wake-up feature reduce power

consumption

208´8-bit RAM

4096K-bit voice ROM size

192 sec voice length

·

Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz)

system clock

One external interrupt input

·

Support 16-bit table read instruction (TBLP, TBHP)

63 powerful and efficient instructions

Three 16-bit programmable timer counter and over-

flow interrupts

28-pin SOP, 44/100-pin QFP package

·

12-bit high quality D/A output by transistor or

HT82V733

Applications

·

Intelligent educational leisure products

Alert and warning systems

High end leisure product controllers

Sound effect generators

General Description

The HT86R192 series are 8-bit high performance

microcontroller with voice synthesizer and tone genera-

tor. The HT86R192 is designed for applications on mul-

tiple I/Os with sound effects, such as voice and melody.

It can provide various sampling rates and beats, tone

levels, tempos for speech synthesizer and melody gen-

erator. It has a single built-in high quality, D/A output.

There is an external interrupt which can be triggered

with falling edge pulse or falling/rising edge pulse.

The HT86R192 is excellent for versatile voice and

sound effect product applications. The efficient MCU in-

structions allow users to program the powerful custom

applications. The system frequency of HT86R192 can

be up to 8MHz under 2.4V and include a HALT function

to reduce power consumption.

Rev. 0.00

1

October 23, 2006

Preliminary

HT86R192

Block Diagram

S

Y

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4

M

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1

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1

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6

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Rev. 0.00

2

October 23, 2006

Preliminary

HT86R192

Pin Assignment

N

C

1

2

3

4

5

6

7

8

9

1

2

1

8

7

6

5

4

3

2

1

0

9

8

7

6

5

N

O

I

R

A

T

V

C

1

0

9

8

9

7

9

6

9

5

9

4

9

3

9

2

9

1

9

0

8

9

8

7

8

6

8

5

8

4

8

3

8

2

8

1

P

A

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

8

9

1

2

3

N

C

N

O

N

O

N

I

N

R

C

8

7

0

9

8

7

6

5

S

C

2

1

N

T

E

S

D

4

3

0

1

2

3

4

U

7

6

E

S

T

2

1

0

9

8

7

6

5

4

D

S

D

A

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

N

C

V

S

A

H

T

8

6

R

1

9

2

H

T

8

6

R

1

9

2

8

S

O

P

-

A

1

0

Q

F

P

-

A

P

A

B

7

6

5

4

3

2

1

0

7

6

5

3

2

1

0

9

8

7

6

5

4

3

4

2

4

1

4

0

3

9

S

C

2

1

2

3

4

5

6

7

P

A

B

7

6

5

4

3

2

1

0

7

6

5

3

2

3

2

1

0

9

8

7

6

5

4

3

N

C

N

C

N

C

N

T

N

C

E

5

4

3

2

1

H

T

8

6

R

1

9

2

O

S

C

2

4

Q

F

P

-

A

O

S

C

1

P

B

6

S

8

9

I

N

T

3

1

3

2

3

4

3

5

3

6

3

7

3

8

3

9

4

0

4

1

4

2

4

3

4

5

4

6

4

7

4

8

4

9

5

0

R

E

S

D

1

0

A

V

U

1

D

A

1

2

1

3

1

4

1

5

1

6

1

7

1

8

1

9

2

0

2

1

2

Rev. 0.00

3

October 23, 2006

Preliminary

HT86R192

Pad Assignment

(

0

,

0

)

P

A

7

1

2

3

P

A

6

5

P

A

4

3

4

5

P

A

2

6

7

8

9

3

7

6

5

O

S

C

2

1

P

A

1

P

A

B

0

7

I

N

T

P

B

6

5

1

0

3

0

1

3 2

3 3

3

9

2

8

3

4

R

E

S

2

1

2 1 3 1 5

1 4

1 6

1

7

1

8

1

9

1

2

5

2

6

2

7

Chip size: 4280´5205 (mm)²

* The IC substrate should be connected to VSS in the PCB layout artwork.

Rev. 0.00

4

October 23, 2006

Preliminary

HT86R192

Pad Coordinates

Unit: mm

Pad No.

X

Y

Pad No.

X

Y

1

2

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

-1990.600

-1784.650

-1679.350

-1576.350

-1481.350

-1378.350

-1283.350

-1180.350

-1085.350

-1465.900

-1568.900

-1663.900

-1766.900

-1861.900

-1964.900

-2059.900

-2162.900

-2257.900

-2360.900

-2455.900

-2453.400

-982.350

-887.350

-784.350

-689.350

-586.350

-454.800

-364.800

-274.800

-23.900

81.110

-2453.400

-2467.000

-2414.250

-2399.950

-2390.750

-2384.950

-2384.000

-2404.700

-2232.500

-2119.776

-2016.174

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

186.100

291.100

397.100

508.900

1984.750

1990.900

1990.850

Pad Description

Pad Name I/O

OTP Option

Description

Wake-up,

Pull-high

or None

Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input

by OTP option. Software instructions determine the CMOS output or

Schmitt trigger input with or without pull-high resistor (OTP option).

PA0~PA7

PB0~PB7

I/O

Bidirectional 8-bit I/O port. Software instructions determine the CMOS

output or Schmitt trigger input (pull-high resistor depending on OTP op-

tion).

Pull-high

or None

Bidirectional 7-bit I/O port. Software instructions determine the CMOS

output or Schmitt trigger input (pull-high resistor depending on OTP op-

tion). XIN is pin-shared with PC6

PC0~PC5

PC6/XIN

Pull-high

or None

XOUT

VSS

32kHz RTC

Connected an external 32kHz crystal to XIN and XOUT.

Negative power supply, ground

¾

I

¾

VDD

Positive power supply

VDDA

VSSA

RES

DAC power supply

DAC negative power supply, ground

Schmitt trigger reset input, active low

External interrupt Schmitt trigger input without pull-high resistor. Choice

Falling Edge Trigger falling edge trigger or falling/rising edge trigger by OTP option. Falling

or Falling/Rising Edge edge triggered active on a high to low transition. Rising edge triggered

INT

I

Trigger

active on a low to high transition. Input voltage is the same as operating

voltage.

OSC1 and OSC2 are connected to an RC network or a crystal (by OTP

option) for the internal system clock. In the case of RC operation, OSC2

is the output terminal for 1/4 system clock.

OSC1

OSC2

RC or Crystal

¾

The system clock may come from the crystal, the two pins cannot be

floating.

AUD

NC

O

¾

Audio output for driving a external transistor or for driving HT82V733

¾

No connection

TEST

No connection (open)

Rev. 0.00

5

October 23, 2006

Preliminary

HT86R192

Absolute Maximum Ratings

Supply Voltage ..........................V_SS-0.3V to V_SS+5.5V

Input Voltage .............................V_SS-0_.3V to V_DD+0.3V

Storage Temperature ...........................-50°C to 125°C

Operating Temperature ..........................-40°C to 85°C

I_OHTotal............................................................-200mA

I

_OLTotal ..............................................................300mA

Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

V_DD

Parameter

Min.

Typ.

Max.

Unit

V_DD

¾

f_SYS=4MHz/8MHz

Operating Voltage

2.4

¾

20

10

5.2

1

V

mA

V

¾

4

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

3V

5V

I_STB1

Standby Current (Watchdog Off)

No load, system HALT

No load, f_SYS=4MHz

2

7

I_STB2

Standby Current (Watchdog On)

Operating Current (Crystal OSC)

I/O Port Sink Current

10

3

I_DD

7

¾

100

50

I_OL

V

_OL=0.1V_DD

10

-2

-5

-3

-6

1

I_OH

_OH=0.9V_DD

I/O Port Source Current

AUD Source Current

I_O

_OH=0.9V_DD

V_IL1

V_IH1

V_IL2

V_IH2

f_SYS

R_PH

Input Low Voltage for I/O Ports

Input High Voltage for I/O Ports

Reset Low Voltage (RES)

Reset High Voltage (RES)

System Frequency

¾

1.8

2

V

3

V

1.9

3.5

2.4

4.2

4.0

8.0

60

30

V

MHz

kW

R_OSC=300kW

3V

R_OSC=155kW

3V

5V

Pull-high Resistance

¾

Rev. 0.00

6

October 23, 2006

Preliminary

HT86R192

A.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min. Typ. Max. Unit

V_DD

¾

f_SYS1

f_SYS2

f_TIMER

System Clock (RC OSC)

System Clock (Crystal OSC)

Timer Input Frequency

2.4V~5.2V

4

8

MHz

¾

0

¾

3V

5V

3V

5V

45

32

11

8

90 180

65 130

ms

t_WDTOSC

Watchdog Oscillator Period

¾

23

17

46

33

ms

Watchdog Time-out Period

(WDT OSC)

t_WDT1

Without WDT prescaler

Watchdog Time-out Period

(System Clock)

t_WDT2

t_SYS

ms

Without WDT prescaler

1024

¾

Watchdog Time-out Period

(RTC OSC)

t_WDT3

7.812

t_RES

t_SST

t_INT

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

1

¾

1

¾

1024

¾

ms

t_SYS

Wake-up from HALT

¾

ms

t_DRT

t_DRR

Data ROM Access Timer

Data ROM enable Read

5

¾

Read after data ROM enable

30

¾

Characteristics Curves

HT86R192 R vs. F Characteristics Curve

H

T

8

6

R

1

9

2

R

v

s

.

F

C

h

a

r

t

1

0

8

6

4

2

3

4

.

0

5

V

1

5

0

2

0

2

5

0

3

0

3

5

0

4

0

4

5

0

R

(

k

W

)

Rev. 0.00

7

October 23, 2006

Preliminary

HT86R192

HT86R192 V vs. F Characteristics Curve

H

T

8

6

R

1

9

2

V

v

s

.

F

C

h

a

r

t

(

F

o

r

3

.

0

V

)

9

8

6

M

H

z

/

1

2

5

0

5

2

k

W

7

W

6

5

4

3

2

4

M

H

z

/

3

0

k

W

2

.

4

2

.

7

3

.

3

.

6

3

.

9

4

.

2

4

.

5

4

.

8

5

.

2

V

D

H

T

8

6

R

1

9

2

V

v

s

.

F

C

h

a

r

t

(

F

o

r

4

.

5

V

)

1

0

8

6

4

M

H

z

/

1

2

4

9

8

6

3

k

W

8

6

4

2

.

4

2

.

7

3

.

3

.

6

3

.

9

4

.

2

4

.

5

4

.

8

5

.

2

V

D

(

V

)

Rev. 0.00

8

October 23, 2006

Preliminary

HT86R192

Functional Description

Execution Flow

Program Counter - PC

The system clock for the HT86R192 series is derived

from either a crystal or an RC oscillator. It is internally di-

vided into four non-overlapping clocks. One instruction

cycle consists of four system clock cycles.

The 13-bit Program Counter (PC) controls the sequence

in which the instructions stored in program ROM are ex-

ecuted.

After accessing a program memory word to fetch an in-

struction code, the contents of the Program Counter are

incremented by one. The Program Counter then points

to the memory word containing the next instruction

code.

Instruction fetching and execution are pipelined in such

a way that a fetch takes one instruction cycle while de-

coding and execution takes the next instruction cycle.

However, the pipelining scheme causes each instruc-

tion to effectively execute within one cycle. If an instruc-

tion changes the Program Counter, two cycles are

required to complete the instruction.

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call, initial re-

set, internal interrupt, external interrupt or return from

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

S

y

s

t

e

m

C

l

o

c

k

O

S

C

(

R

C

o

n

l

y

)

P

1

2

3

4

I

P

n

t

e

r

n

a

l

h

a

s

e

C

l

o

c

k

s

P

C

P

C

+

1

P

C

+

2

P

C

F

e

t

c

h

I

N

S

T

(

P

C

)

E

x

e

c

u

t

e

I

N

S

T

(

P

C

-

1

)

F

e

t

c

h

I

N

S

T

(

P

C

+

1

)

E

x

e

c

u

t

e

I

N

S

T

(

P

C

)

F

e

t

c

h

I

N

S

T

(

P

C

+

2

)

E

x

e

c

u

t

e

I

N

S

T

(

P

C

+

1

)

Execution Flow

Program Counter

Mode

*12 *11 *10

*9

0

*8

0

*7

0

*6

0

*5

0

*4

0

1

*3

0

1

0

*2

0

1

0

1

0

1

*1

0

*0

0

Initial Reset

0

External or Serial Input Interrupt

Timer/Event Counter 0 Overflow

Timer/Event Counter 1 Overflow

Timer Counter 2 Overflow

Timer Counter 3 Overflow

Skip

Program Counter+2

@7 @6 @5 @4 @3 @2 @1 @0

Loading PCL

*12 *11 *10

*9

*8

#8

S8

Jump, Call Branch

#12 #11 #10 #9

S12 S11 S10 S9

#7

S7

#6

S6

#5

S5

#4

S4

#3

S3

#2

S2

#1

S1

#0

S0

Return from Subroutine

Program Counter

Note: *12~*0: Program Counter bits

#12~#0: Instruction code bits

S12~S0: Stack register bits

@7~@0: PCL bits

Rev. 0.00

9

October 23, 2006

Preliminary

HT86R192

·

Location 008H

subroutine, the PC manipulates the program transfer by

loading the address corresponding to each instruction.

This area is reserved for the 16-bit Timer/Event Coun-

ter 0 interrupt service program. If a timer interrupt re-

sults from a Timer/Event Counter 0 overflow, and if the

interrupt is enabled and the stack is not full, the pro-

gram will jump to location 008H and begins execution.

The conditional skip is activated by instruction. Once the

condition is met, the next instruction, fetched during the

current instruction execution, is discarded and a dummy

cycle takes its place while the correct instruction is ob-

tained.

·

Location 00CH

This area is reserved for the 16-bit Timer/Event Coun-

ter 1 interrupt service program. If a timer interrupt re-

sults from a Timer/Event Counter 1 overflow, and if the

interrupt is enabled and the stack is not full, the pro-

gram will jump to location 00CH and begins execution.

The lower byte of the Program Counter (PCL) is a

read/write register (06H). Moving data into the PCL per-

forms a short jump. The destination must be within 256

locations.

When a control transfer takes place, an additional

dummy cycle is required.

Location 010H

This area is reserved for the 16-bit Timer Counter 2 in-

terrupt service program. If a timer interrupt results

from a Timer Counter 2 overflow, and if the interrupt is

enabled and the stack is not full, the program will jump

to location 010H and begins execution.

Program Memory - ROM

The program memory stores the program instructions

that are to be executed. It also includes data, table and

interrupt entries, addressed by the Program Counter

along with the table pointer. The program memory size

for HT86R192 is 8192´16 bits. Certain locations in the

program memory are reserved for special usage:

Location 014H

This area is reserved for the 8-bit Timer Counter 3 in-

terrupt service program. If a timer interrupt results

from a Timer Counter 3 overflow, and if the interrupt is

enabled and the stack is not full, the program will jump

to location 014H and begins execution.

·

Location 000H

This area is reserved for program initialization. The

program always begins execution at location 000H

each time the system is reset.

Table Location

·

Location 004H

Any location in the ROM space can be used as look up

tables. The instructions ²TABRDC [m]² (used for any

bank) and ²TABRDL [m]² (only used for last page of pro-

gram ROM) transfer the contents of the lower-order byte

to the specified data memory [m], and the higher-order

byte to TBLH (08H). Only the destination of the

lower-order byte in the table is well-defined. The

higher-order bytes of the table word are transferred to

the TBLH. The table higher-order byte register (TBLH)

is read only.

This area is reserved for the external interrupt service

program. If the INT input pin is activated, and the inter-

rupt is enabled and the stack is not full, the program

will jump to location 004H and begins execution.

0

H

I

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i

t

i

a

l

A

d

r

e

s

0

4

H

E

x

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S

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t

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0

8

H

T

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0

1

2

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S

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b

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0

C

H

P

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o

g

r

a

m

The table pointer (TBHP, TBLP) is a read/write register,

which indicates the table location. Because TBHP is un-

known after power-on reset, TBHP must be set speci-

fied.

R

O

M

0

1

0

H

0

1

4

H

T

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r

3

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(

R

T

C

)

0

1

5

H

1

F

H

Program Memory

Table Location

Instruction

*12

TABRDC [m] P12

TABRDL [m]

*11

P11

1

*10

P10

1

*9

P9

1

*8

*7

*6

*5

*4

*3

*2

*1

*0

P8

1

@7

@6

@5

@4

@3

@2

@1

@0

1

Table Location

@7~@0: Write @7~@0 to TBLP pointer register

Note: *12~*0: Current program ROM table

P12~P8: Write P12~P8 to TBHP pointer register

Rev. 0.00

10

October 23, 2006

Preliminary

HT86R192

(MP0:01H), Accumulator (ACC:05H), Program Counter

lower-order byte register (PCL:06H), Table pointer

(TBLP:07H), Table higher-order byte register

(TBLH:08H), Status register (STATUS:0AH), Interrupt

control register 0 (INTC:0BH), Timer/Event Counter 0

(TMR0H:0CH,TMR0L:0DH), Timer/Event Counter 0

control register (TMR0C:0EH), Timer/Event Counter 1

(TMR1H:0FH, TMR1L:10H), Timer/Event Counter 1

control register (TMR1C:11H), I/O registers

(PA:12H,PB:14H,PC:16H), I/O control registers

(PAC:13H,PBC:15H,PCC:17H), Voice ROM address

latch0[19:0] (LATCH0H:18H, LATCH0M:19H,

LATCH0L:1AH), Voice ROM address latch1[19:0]

(LATCH1H:1BH, LATCH1M:1CH, LATCH1L:1DH), In-

terrupt control register 1 (INTCH:1EH), Table pointer

higher-order byte register (TBHP:1FH), Timer Counter 2

(TMR2H:20H, TMR2L:21H), Timer Counter 2 control

register (TMR2C:22H), Timer Counter 3 (TMR3L:24H),

Timer Counter 3 control register (TMR3C:25H), Voice

control register (VOICEC:26H), DAC output (DAH:27H,

DAL:28H), Volume control register (VOL:29H), Voice

ROM latch data register (LATCHD:2AH).

Stack Register - Stack

The stack register is a special part of the memory used

to save the contents of the Program Counter. This stack

is organized into eight levels. It is neither part of the data

nor part of the program space, and cannot be read or

written to. Its activated level is indexed by a stack

pointer (SP) and cannot be read or written to. At a sub-

routine call or interrupt acknowledgment, the contents of

the Program Counter are pushed onto the stack.

The Program Counter is restored to its previous value

from the stack at the end of subroutine or interrupt rou-

tine, which is signaled by return instruction (RET or

RETI). After a chip resets, SP will point to the top of the

stack.

The interrupt request flag will be recorded but the ac-

knowledgment will be inhibited when the stack is full and

a non-masked interrupt takes place. After the stack

pointer is decremented (by RET or RETI), the interrupt

request will be serviced. This feature prevents stack

overflow and allows programmers to use the structure

more easily. In a similar case, if the stack is full and a

²CALL² is subsequently executed, stack overflow oc-

curs and the first entry is lost.

The general purpose data memory, addressed from

30H~FFH, is used for data and control information un-

der instruction commands.

Data Memory - RAM

The areas in the RAM can directly handle the arithmetic,

logic, increment, decrement, and rotate operations. Ex-

cept some dedicated bits, each bit in the RAM can be

set and reset by ²SET [m].i² and ²CLR [m].i². They are

also indirectly accessible through the memory pointer

register 0 (MP0:01H) or the Memory Pointer register 1

(MP1:03H).

The data memory is designed with 208´8 bits. The data

memory is further divided into two functional groups,

namely, special function registers (00H~2AH) and gen-

eral purpose user data memory (30H~FFH). Although

most of them can be read or be written to, some are read

only.

The special function registers include an Indirect ad-

dressing register (R0:00H), Memory pointer register

Address RAM Mapping

Read/Write

R/W

Description

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

R0

Indirect addressing register 0

MP0

R/W

Memory pointer 0

R1

R/W

Indirect addressing register 1

Memory pointer 1

MP1

R/W

Unused

ACC

R/W

R

Accumulator

PCL

Program Counter lower-order byte address

Table pointer lower-order byte address

Table higher-order byte content register

Watchdog Timer option setting register

Status register

TBLP

TBLH

WDTS

STATUS

INTC

R/W

Interrupt control register 0

TMR0H

TMR0L

TMR0C

Timer/Event Counter 0 higher-byte register

Timer/Event Counter 0 lower-byte register

Timer/Event Counter 0 control register

Rev. 0.00

11

October 23, 2006

Preliminary

HT86R192

Address RAM Mapping

Read/Write

R/W

Description

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

20H

21H

22H

23H

24H

25H

26H

TMR1H

TMR1L

TMR1C

PA

Timer/Event Counter 1 higher-byte register

Timer/Event Counter 1 lower-byte register

Timer/Event Counter 1 control register

Port A I/O data register

PAC

Port A I/O control register

PB

Port B I/O data register

PBC

Port B I/O control register

PC

Port C I/O data register

PCC

Port C I/O control register

LATCH0H

LATCH0M

LATCH0L

LATCH1H

LATCH1M

LATCH1L

INTCH

TBHP

Voice ROM address latch 0 [A19~A16]

Voice ROM address latch 0 [A15~A8]

Voice ROM address latch 0 [A7~A0]

Voice ROM address latch 1 [A19~A16]

Voice ROM address latch 1 [A15~A8]

Voice ROM address latch 1 [A7~A0]

Interrupt control register 1

Table pointer higher-order byte register

Timer Counter 2 higher-byte register

Timer Counter 2 lower-byte register

Timer Counter 2 control register

TMR2H

TMR2L

TMR2C

Unused

TMR3L

TMR3C

VOICEC

R/W

Timer Counter 3 lower-byte register

Timer Counter 3 control register

Voice control register

R/W, higher-nibble

available only

27H

28H

29H

2AH

DAL

DAC output data D3~D0 to DAL7~DAL4

DAC output data D11~D4 to DAH7~DAH0

DAH

R/W

R/W, higher-nibble

available only

VOL

Volume control register, and volume controlled by VOL7~VOL5

Voice ROM data register

LATCHD

R

2BH~2FH Unused

30H~FFH User data RAM

R/W

User data RAM

Rev. 0.00

12

October 23, 2006

Preliminary

HT86R192

Indirect Addressing Register

Except the TO and PDF flags, bits in the status register

can be altered by instructions similar to other registers.

Data written into the status register does not alter the TO

or PDF flags. Operations related to the status register,

however, may yield different results from those in-

tended. The TO and PDF flags can only be changed by

a Watchdog Timer overflow, chip power-up, or clearing

the Watchdog Timer and executing the ²HALT² instruc-

tion. The Z, OV, AC, and C flags reflect the status of the

latest operations.

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] accesses the RAM pointed to

by MP0 (01H) and MP1 (03H), respectively. Reading lo-

cation 00H or 02H indirectly returns the result 00H.

While, writing it indirectly leads to no operation.

The function of data movement between two indirect ad-

dressing registers is not supported. The memory pointer

registers, MP0 and MP1, are both 8-bit registers used to

access the RAM by combining the corresponding indi-

rect addressing registers.

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack. If the contents of the status

is important, and if the subroutine is likely to corrupt the

status register, the programmer should take precautions

and save it properly.

Accumulator - ACC (05H)

The accumulator (ACC) is related to the ALU opera-

tions. It is also mapped to location 05H of the RAM and

is capable of operating with immediate data. The data

movement between two data memory locations must

pass through the ACC.

Interrupts

The HT86R192 provides an external interrupt, three

16-bit programmable timer interrupts, and an 8-bit pro-

grammable timer interrupt. The Interrupt Control regis-

ters (INTC:0BH, INTCH:1EH) contain the interrupt

control bits to set to enable/disable and the interrupt re-

quest flags.

Arithmetic and Logic Unit - ALU

This circuit performs 8-bit arithmetic and logic opera-

tions and provides the following functions:

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Once an interrupt subroutine is serviced, all other inter-

rupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may happen during this interval but

only the interrupt request flag is recorded. If a certain in-

terrupt needs servicing within the service routine, the

EMI bit and the corresponding INTC/INTCH bit may be

set to allow interrupt nesting. If the stack is full, the inter-

rupt request will not be acknowledged, even if the re-

lated interrupt is enabled, until the SP is decremented. If

immediate service is desired, the stack must be pre-

vented from becoming full.

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ etc)

Status Register - STATUS (0AH)

This 8-bit STATUS register (0AH) consists of a zero flag

(Z), carry flag (C), auxiliary carry flag (AC), overflow flag

(OV), power down flag (PDF), watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

Bit No.

Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

0

C

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

1

2

3

AC

Z

Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

OV

PDF is cleared by system power-up or executing the ²CLR WDT² instruction.

PDF is set by executing the ²HALT² instruction.

4

PDF

TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction.

TO is set by a WDT time-out.

5

TO

6~7

¾

Unused bit, read as ²0²

Status (0AH) Register

Rev. 0.00

13

October 23, 2006

Preliminary

HT86R192

As an interrupt is serviced, a control transfer occurs by

pushing the Program Counter onto the stack and then

branching to subroutines at the specified location(s) in

the program memory. Only the Program Counter is

pushed onto the stack. The programmer must save the

contents of the register or status register (STATUS) in

advance if they are altered by an interrupt service pro-

gram which corrupts the desired control sequence.

14H will occur. The related interrupt request flag (T3F)

will be reset and the EMI bit cleared to disable further in-

terrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledges are held until the RETI instruction

is executed or the EMI bit and the related interrupt con-

trol bit are set to 1 (of course, if the stack is not full). To

return from the interrupt subroutine, the RET or RETI in-

struction may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET will not.

External interrupt is triggered by a high-to-low/

low-to-high transition of INT pin which sets the related

interrupt request flag (EIF:bit 4 of INTC). When the inter-

rupt is enabled, and the stack is not full and the external

interrupt is active, a subroutine call to location 04H will

occur. The interrupt request flag (EIF) and EMI bits will

be cleared to disable other interrupts.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests,

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

The internal Timer/Event Counter 0 interrupt is initial-

ized by setting the Timer/Event Counter 0 interrupt re-

quest flag (T0F:bit 5 of INTC), caused by a Timer/Event

Counter 0 overflow. When the interrupt is enabled, and

the stack is not full and the T0F bit is set, a subroutine

call to location 08H will occur. The related interrupt re-

quest flag (T0F) will be reset and the EMI bit cleared to

disable further interrupts.

The Timer/Event Counter 0/1 interrupt request flag

(T0F/T1F) which enables Timer/Event Counter 0/1 con-

trol bit (ET0I/ET1I), the Timer Counter 2/3 interrupt re-

quest flag (T2F/T3F) which enables Timer Counter 2/3

control bit (ET2I/ET3I), and external interrupt request

flag (EIF) which enables external interrupt control bit

(EEI) form the interrupt control register (INTC:0BH and

INTCH:1EH). EMI, EEI, ET0I, ET1I, ET2I, and ET3I are

used to control the enabling/disabling of interrupts.

These bits prevent the requested interrupt begin ser-

viced. Once the interrupt request flags (T0F, T1F, T2F,

T3F, EIF) are set, they will remain in the INTC/INTCH

register until the interrupts are serviced or cleared by a

software instruction.

The internal Timer/Event Counter 1 interrupt is initial-

ized by setting the Timer/Event Counter 1 interrupt re-

quest flag (T1F:bit 6 of INTC), caused by a Timer/Event

Counter 1 overflow. When the interrupt is enabled, and

the stack is not full and the T1F bit is set, a subroutine

call to location 0CH will occur. The related interrupt re-

quest flag (T1F) will be reset and the EMI bit cleared to

disable further interrupts.

It is recommended that application programs do not use

²CALL² subroutines within an interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only

one stack is left and the interrupt enable is not well con-

trolled, once a ²CALL² subroutine if used in the interrupt

subroutine will corrupt the original control sequence.

The internal Timer Counter 2 interrupt is initialized by

setting the Timer Counter 2 interrupt request flag

(T2F:bit 0 of INTCH), caused by a Timer Counter 2 over-

flow. When the interrupt is enabled, and the stack is not

full and the T2F bit is set, a subroutine call to location

10H will occur. The related interrupt request flag (T2F)

will be reset and the EMI bit cleared to disable further in-

terrupts.

Interrupt Source

External Interrupt

Priority Vector

1

2

3

4

5

04H

08H

0CH

10H

14H

The internal Timer Counter 3 interrupt is initialized by

setting the Timer Counter 3 interrupt request flag

(T3F:bit 1 of INTCH), caused by a Timer Counter 3 over-

flow. When the interrupt is enabled, and the stack is not

full and the T3F bit is set, a subroutine call to location

Timer/Event Counter 0 Overflow

Timer/Event Counter 1 Overflow

Timer Counter 2 Overflow

Timer Counter 3 Overflow

Rev. 0.00

14

October 23, 2006

Preliminary

HT86R192

Bit No.

Label

EMI

EEI

Function

Controls the master (global) interrupt (1= enabled; 0= disabled)

Controls the external interrupt (1= enabled; 0= disabled)

Controls the Timer 0 interrupt (1= enabled; 0= disabled)

Controls the Timer 1 interrupt (1= enabled; 0= disabled)

External interrupt request flag (1= active; 0= inactive)

Timer 0 request flag (1= active; 0= inactive)

0

1

2

3

4

5

6

7

ET0I

ET1I

EIF

T0F

T1F

¾

Timer 1 request flag (1= active; 0= inactive)

Unused bit, read as ²0²

INTC (0BH) Register

Bit No.

Label

ET2I

ET3I

¾

Function

Controls the Timer 2 interrupt (1= enabled; 0= disabled)

Controls the Timer 3 interrupt (1= enabled; 0= disabled)

Unused bit, read as ²0²

0

1

2~3, 6~7

4

5

T2F

T3F

Timer 2 interrupt request flag (1= active; 0= inactive)

Timer 3 interrupt request flag (1= active; 0= inactive)

INTCH (1EH) 1 Register

the crystal and to get a frequency reference, but two ex-

ternal capacitors in OSC1 and OSC2 are required.

The HT86R192 provides two types of oscillator circuit

for the system clock, i.e., RC oscillator and crystal oscil-

lator. No matter what type of oscillator, the signal is used

for the system clock. The HALT mode stops the system

oscillator and ignores external signal to conserve power.

If the RC oscillator is used, an external resistor between

OSC1 and VSS is required, and the range of the resis-

tance should be from 155kW to 300kW. The system

clock, divided by 4, is available on OSC2 with pull-high

resistor, which can be used to synchronize external

logic. The RC oscillator provides the most cost effective

solution. However, the frequency of the oscillation may

vary with VDD, temperature, and the chip itself due to

process variations. It is therefore not suitable for timing

sensitive operations where accurate oscillator fre-

quency is desired.

There is another oscillator circuit designed for Timer3¢s

clock source as the RTC time base which is determined

by OTP option. If the OTP option determines that

Timer3¢s clock source is from a 32kHz crystal, then a

32kHz crystal should be connected to XIN and XOUT.

O

S

C

1

X

I

N

(

P

C

6

)

O

S

C

1

V

D

X

O

U

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4

O

S

C

2

O

S

C

2

R

C

O

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T

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C

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c

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System Oscillator

Watchdog Timer - WDT

The WDT clock source is implemented by a dedicated

RC oscillator (WDT oscillator) or instruction clock (sys-

tem clock divided by 4), decided by OTP options. This

timer is designed to prevent a software malfunction or

sequence jumping to an unknown location with unpre-

dictable results. The Watchdog Timer can be disabled

On the other hand, if the crystal oscillator is selected, a

crystal across OSC1 and OSC2 is needed to provide the

feedback and phase shift required for the oscillator, and

no other external components are required. A resonator

may be connected between OSC1 and OSC2 to replace

S

y

s

t

e

m

C

l

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4

W

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S

0

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W

S

2

W

D

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Watchdog Timer

Rev. 0.00

15

October 23, 2006

Preliminary

HT86R192

by OTP option. If the Watchdog Timer is disabled, all the

executions related to the WDT result in no operation.

flags, the reason for the chip reset can be determined.

The PDF flag is cleared when the system powers-up or

executes the ²CLR WDT² instruction, and is set when

the ²HALT² instruction is executed. The TO flag is set if a

WDT time-out occurs, and causes a wake-up that only

resets the Program Counter and SP. The other maintain

their original status.

Once the internal WDT oscillator (RC oscillator with pe-

riod 78ms normally) is selected, it is first divided by 256

(8-stages) to get the nominal time-out period of approxi-

mately 20 ms. This time-out period may vary with tem-

perature, VDD and process variations. By invoking the

WDT prescaler, longer time-out period can be realized.

Writing data to WS2, WS1, WS0 (bit 2,1,0 of

WDTS(09H)) can give different time-out period.

The port A wake-up and interrupt methods can be con-

sidered as a continuation of normal execution. Each bit

in port A can be independently selected to wake-up the

device by a OTP option. Awakening from an I/O port

stimulus, the program will resume execution of the next

instruction. If awakening from an interrupt, two se-

quences may happen. If the related interrupt is disabled

or the interrupt is enabled by the stack is full, the pro-

gram will resume execution at the next instruction. If the

interrupt is enabled and the stack is not full, the regular

interrupt response takes place.

If WS2, WS1, WS0 all equal to 1, the division ratio is up to

1:128, and the maximum time-out period is 2.6 seconds.

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

a ²chip reset² and set the status bit ²TO². Whereas in

the HALT mode, the overflow will initialize a ²warm re -

set² only the Program Counter and SP are reset to zero.

To clear the contents of the WDT (including the WDT

prescaler), three methods are adopted; external reset

(external reset (a low level to RES), software instruc-

tions, or a ²HALT² instruction. The software instruction

is ²CLR WDT² and execution of the ²CLR WDT² instruc-

tion will clear the WDT.

Once a wake-up event occurs, it takes 1024 system clock

period to resume normal operation. In other words, a

dummy cycle period will be inserted after a wake-up. If

the wake-up results from an interrupt acknowledge, the

actual interrupt subroutine will be delayed by one more

cycle. If the wake-up results in next instruction execution,

this will be executed immediately after a dummy period is

finished. If an interrupt request flag is set to ²1² before en-

tering the HALT mode, the wake-up function of the re-

lated interrupt will be disabled. To minimize power

consumption, all I/O pins should be carefully managed

before entering the HALT status.

WS2

WS1

WS0

Division Ratio

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1:1

1:2

1:4

Reset

1:8

There are 3 ways in which a reset can occur:

1:16

1:32

1:64

1:128

·

RES reset during normal operation

RES reset during HALT

WDT time-out reset during normal operation

The WDT time-out during HALT is different from other

chip reset conditions, since it can perform a ²warm re -

set² that resets only the Program Counter and SP, leav-

ing the other circuits in their original state. Some regis-

ters remain unchanged during any other reset

conditions. Most registers are reset to their ²initial condi-

tion² when the reset conditions are met. By examining

the PDF flag and TO flag, the program can distinguish

between different ²chip resets².

WDTS (09H) Register

Power Down - HALT

The HALT mode is initialized by a HALT instruction and

results in the following:

The system oscillator will be turned off but the WDT os-

cillator keeps running (if the WDT oscillator is selected).

·

The contents of the on chip RAM and registers remain

unchanged.

TO PDF

RESET Conditions

RES reset during power-up

RES reset during normal operation

RES wake-up HALT

·

WDT and WDT prescaler will be cleared and recount

again.

0

u

0

1

0

u

1

u

1

·

All I/O ports maintain their their original status.

The PDF flag is set and the TO flag is cleared.

The system can leave the HALT mode by means of an

external reset, an interrupt, an external falling edge sig-

nal on port A or a WDT overflow. An external reset

causes a device initialization and the WDT overflow per-

forms a ²warm reset². By examining the TO and PDF

WDT time-out during normal operation

WDT wake-up HALT

Note: ²u² stands for ²unchanged²

Rev. 0.00

16

October 23, 2006

Preliminary

HT86R192

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses after a system

power up or when awakening from a HALT state.

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When a system power up occurs, the SST delay is

added during the reset period. But when the reset co-

mes from the RES pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

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The function unit chip reset status are shown below.

Reset Configuration

Timer/Event Counter 0/1

Program Counter

Interrupt

000H

Disable

Clear

Prescaler

There are four timer counters are implemented in the

HT86R192. The Timer/Event Counter 0 and 1 contain

16-bit programmable count-up counters whose clock

may come from an external source or the system clock

divided by 4 (T1). Using the internal instruction clock

(T1), there is only one reference time base. The external

clock input allows the user to count external events,

measure time intervals or pulse width, or to generate an

accurate time base.

Clear. After master reset,

WDT begins counting

WDT

Timer/Event Counter Off

Input/output ports

Stack Pointer

Input mode

Points to the top of the stack

V

D

There are three registers related to Timer/Event Counter

0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH). Writing

to TMR0L only writes the data into a low byte buffer. Writ-

ing to TMR0H will write the data and the contents of the

low byte buffer into the Timer/Event Counter 0 preload

register (16-bit) simultaneously. The Timer/Event Coun-

ter 0 preload register is changed only by a write to

TMR0H operation. Writing to TMR0L will keep the

Timer/Event Counter 0 preload register unchanged.

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Reset Timing Chart

V

D

Reading TMR0H will also latch the TMR0L into the low

byte buffer to avoid false timing problems. Reading the

TMR0L only returns the value from the low byte buffer

which may be a previously loaded value. In other words,

the low byte of Timer/Event Counter 0 cannot be read di-

rectly. It must read the TMR0H first to ensure that the

low byte contents of Timer/Event Counter 0 are latched

into the buffer.

R

E

S

Reset Circuit

There are three registers related to the Timer/Event

Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H).

The Timer/Event Counter 1 operates in the same man-

ner as Timer/Event Counter 0.

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Timer/Event Counter 0/1

Rev. 0.00

17

October 23, 2006

Preliminary

HT86R192

Bit No.

Label

Function

0~2, 5

¾

Unused bit, read as ²0²

To define the TMR0/TMR1 active edge of Timer/Event Counter

(0=active on low to high; 1=active on high to low)

3

4

TE

TON

To enable/disable timer counting (0=disabled; 1=enabled)

To define the operating mode (TMR1, TMR0)

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

6

7

TM0,

TM1

TMR0C (0EH)/TMR1C (11H) Register

Bit No.

Label

Function

0~2, 5

¾

Unused bit, read as ²0²

To define the TMR0/TMR1 active edge of Timer/Event Counter

(0=active on low to high; 1=active on high to low)

3

4

TE

TON

To enable/disable timer counting (0=disabled; 1=enabled)

To define the operating mode (TMR1, TMR0)

01=Unused

6

7

TM0,

TM1

10=Timer mode (internal clock)

11=Unused

00=Unused

TMR2C (22H) Register

The TMR0C is the Timer/Event Counter 0 control regis-

ter, which defines the Timer/Event Counter 0 options.

The Timer/Event Counter 1 has the same options as the

Timer/Event Counter 0 and is defined by TMR1C.

only one cycle measurement can be done. When TON

is set again, the cycle measurement will function again

as long as it receives further transient pulses. Note that,

in this operating mode, the timer/event counter starts

counting not according to the logic level but according to

the transient edges. In the case of counter overflows,

the counter is reloaded from the timer/event counter

preload register and issues the interrupt request just like

in the other two modes.

The timer/event counter control registers define the oper-

ating mode, counting enable or disable and active edge.

The TM0, TM1 bits define the operating mode. The

event count mode is used to count external events,

which implies that the clock source comes from an ex-

ternal (TMR0/TMR1 is connected to PC4/PC5) pin. The

timer mode functions as a normal timer with the clock

source coming from the instruction clock. The pulse

width measurement mode can be used to count the high

or low level duration of an external signal

(TMR0/TMR1). The counting method is based on the in-

struction clock.

To enable the counting operation, the Timer ON bit

(TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the

pulse width measurement mode, TON will be cleared

automatically after the measurement cycle is complete.

But in the other two modes TON can only be reset by in-

struction. The overflow of the timer/event counter is one

of the wake-up sources. No matter what the operation

mode is, writing a 0 to ET0I/ET1I can disable the corre-

sponding interrupt service.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFFFH. Once an

overflow occurs, the counter is reloaded from the

timer/event counter preload register and generates a

corresponding interrupt request flag (T0F/T1F; bit 5/6 of

INTC) at the same time.

In the case of a Timer/Event Counter OFF condition,

writing data to the timer/event counter preload register

will also reload that data to the timer/event counter. But

if the timer/event counter is turned on, data written to the

timer/event counter will only be kept in the timer/event

counter preload register. The timer/event counter will

continue to operate until an overflow occurs.

In the pulse width measurement mode with the TON and

TE bits equal to one, once the TMR0/TMR1 has re-

ceived a transient from low to high (or high to low; if the

TE bit is 0) it will start counting until the TMR0/TMR1 re-

turns to the original level and resets TON. The mea-

sured result will remain in the timer/event counter even if

the activated transient occurs again. In other words,

When the Timer/Event Counter (reading TMR0H/

TMR1H) is read, the clock will be blocked to avoid er-

rors. As this may result in a counting error, this must be

taken into consideration by the programmer.

Rev. 0.00

18

October 23, 2006

Preliminary

HT86R192

Timer Counter 2

clock source of TMR3 can be from internal instruction

cycle (T1) or external 32kHz crystal which is connected

to XIN and XOUT. The TMR3¢s clock source is deter-

mined by OTP option. If the 32kHz crystal is enabled,

then TMR3¢s clock source is 32kHz which is from XIN

and XOUT. If the 32kHz crystal is disabled, then TMR3¢s

clock source is internal T1.

The timer counter TMR2 is also a 16-bit programmable

count-up counter. It operates in the same manner as

Timer/Event Counter 0/1, but the clock source of TMR2

is from only internal instruction cycle (T1). Therefore

only (TM1,TM0)=(1,0) is allowable.

Timer Counter 3 (RTC Time Base)

The TMR3 is internal clock source only, i.e.

(TM1,TM0)=(1,0). There is a 3-bit prescaler

(TMR3S2,TMR3S1,TMR3S0) which defines different

division ratio of TMR3¢s clock source.

The timer counter TMR3 is an 8-bit programmable

count-up counter. Its counting is as the same manner as

Timer Event Counter 0/1 and Timer Counter 2, but the

Bit No.

Label

Function

To define the operating clock source (TMR3S2, TMR3S1, TMR3S0)

000: clock source/2

001: clock source/4

TMR3S2, 010: clock source/8

TMR3S1, 011: clock source/16

TMR3S0 100: clock source/32

101: clock source/64

0~2

110: clock source/128

111: clock source/256

To define the TMR3 active edge of timer/event counter

3

TE

(0=active on low to high; 1=active on high to low)

To enable/disable timer counting (0=disabled; 1=enabled)

Unused bit, read as ²0²

4

5

TON

¾

To define the operating mode (TM1, TM0)

01=Unused

6

7

TM0,

TM1

10=Timer mode (internal clock)

11=Unused

00=Unused

TMR3C (25H) Register

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Timer Counter 2

(

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Timer Counter 3

Rev. 0.00

19

October 23, 2006

Preliminary

HT86R192

The registers states are summarized in the following table.

WDT Time-out

RES Reset

(Normal Operation) (Normal Operation)

RES Reset

(HALT)

WDT Time-out

(HALT)

Register Reset (Power-on)

PC

0000H

xxxx xxxx

0000 0111

--00 xxxx

-000 0000

xxxx xxxx

1111 1111

xxxx xxxx

00-0 1---

0000H

MP0

uuuu uuuu

0000 0111

--1u uuuu

-000 0000

xxxx xxxx

1111 1111

xxxx xxxx

00-0 1---

uuuu uuuu

0000 0111

--uu uuuu

-000 0000

xxxx xxxx

1111 1111

xxxx xxxx

00-0 1---

uuuu uuuu

0000 0111

--01 uuuu

-000 0000

xxxx xxxx

1111 1111

xxxx xxxx

00-0 1---

uuuu uuuu

--11 uuuu

-uuu uuuu

xxxx xxxx

uuuu uuuu

xxxx xxxx

uu-u u---

MP1

ACC

TBLP

TBLH

WDTS

STATUS

INTC

TMR0H

TMR0L

TMR0C

TMR1H

TMR1L

TMR1C

PA

PAC

PB

PBC

PC

PCC

TMR2H

TMR2L

TMR2C

TMR3L

TMR3C

INTCH

TBHP

xxxx xxxx

-000 ---0

xxxx xxxx

-000 ---0

xxxx xxxx

-000 ---0

xxxx xxxx

-000 ---0

xxxx xxxx

-uuu ---u

---x xxxx

---u uuuu

uuuu ----

---u uuuu

uuuu ----

---u uuuu

uuuu ----

---u uuuu

uuuu ----

DAL

xxxx ----

DAH

xxxx xxxx

xxx- ----

uuuu uuuu

uuu- ----

uuuu uuuu

uuu- ----

uuuu uuuu

uuu- ----

uuuu uuuu

uuu- ----

VOL

VOICEC

LATCH0H

LATCH0M

LATCH0L

LATCH1H

LATCH1M

LATCH1L

LATCHD

0--0 -00-

u--u -uu-

---- -xxx

---- -uuu

xxxx xxxx

---- -xxx

uuuu uuuu

---- -uuu

uuuu uuuu

---- -uuu

uuuu uuuu

---- -uuu

uuuu uuuu

---- -uuu

xxxx xxxx

uuuu uuuu

Note:

²u² means ²unchanged²

²x² means ²unknown²

²-² means ²undefined²

Rev. 0.00

20

October 23, 2006

Preliminary

HT86R192

Input/Output Ports

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

There are 23 bidirectional input/output lines in the

microcontroller, labeled from PA to PC, which are

mapped to the data memory of [12H], [14H], and [16H],

respectively. All of these I/O ports can be used for input

and output operations. For input operation, these ports

are non-latching, that is, the inputs must be ready at the

T2 rising edge of instruction ²MOV A, [m]² (m=12H,14H

or 16H). For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

Each line of port A has the capability of waking-up the

device. The wake-up capability of port A is determined

by OTP option. There is a pull-high option available for

all I/O lines. Once the pull-high option is selected, all I/O

lines have pull-high resistors. Otherwise, the pull-high

resistors are absent. It should be noted that a

non-pull-high I/O line operating in input mode will cause

a floating state.

Each I/O line has its own control register (PAC, PBC,

PCC) to control the input/output configuration. With this

control register, CMOS output or Schmitt trigger input

with or without pull-high resistor structures can be re-

configured dynamically (i.e. on-the-fly) under software

control. To function as an input, the corresponding latch

of the control register must write ²1². The input source

also depends on the control register. If the control regis-

ter bit is ²1², the input will read the pad state. If the con-

trol register bit is ²0², the contents of the latches will

move to the internal bus. The latter is possible in the

²read-modify-write² instruction.

By some different OTP options, there are 3 shared pins

(PC.4, PC.5, and PC.6) in PC. They can be normal I/O

pins or for special functions. The PC.4 is the external

clock source of timer/event counter TMR0 if TMR0 is set

to external clock mode, and the PC.5 is the external

clock source of timer/event counter TMR1 if TMR1 is set

to external clock mode. PC6 is pin-shared with XIN. The

XIN and XOUT can be connected to a 32kHz crystal as

the clock source of the timer counter TMR3 if the OTP

option is set to enable 32kHz (RTC) crystal.

Audio Output and Volume Control - DAL, DAH, VOL

For output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H, and 17H. Bit 7 which is mapped to location [17H] is

always written as ²1².

The HT86R192 provides one 12-bit voltage type DAC

device for driving external 8W speaker through an exter-

nal NPN transistor. The programmer must write the

voice data to register DAL (27H) and DAH (28H). The

12-bit audio output will be written to the higher nibble of

DAL and the whole byte of DAH, and the DAL3~DAL0 is

always read as ²0H². There are 8 scales of volume con-

trollable level that are provided for the voltage type DAC

output. The programmer can change the volume by only

writing the volume control data to the higher-nibble of

the VOL (29H), and the lower-nibble of VOL (29H) is al-

ways read as ²0H².

After a chip reset, these input/output lines remain at high

levels or floating state (dependent on pull-high options).

Each bit of these input/output latches can be set or

cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H) instructions.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

V

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Input/Output Ports

Rev. 0.00

21

October 23, 2006

Preliminary

HT86R192

Voice Control Register

where the voice codes are stored. One 8-bit of voice

ROM data will be addressed by setting 20-bit address

latch counter LATCH0H/LATCH0M/LATCH0L or

LATCH1H/LATCH1M/LATCH1L. After the 8-bit voice

ROM data is addressed, a few instruction cycles (4ms at

least) will be cost to latch the voice ROM data, then the

microcontroller can read the voice data from

LATCHD(2AH).

The voice control register controls the voice ROM circuit

and DAC circuit, selects voice ROM latch counter, and

controls 32kHz crystal to start in speed-up mode or not.

If the DAC circuit is not enabled, any DAH/DAL output is

invalid. Writing a ²1² to DAC bit is to enable DAC circuit,

and writing a ²0² to DAC bit is to disable DAC circuit. If

the voice ROM circuit is not enabled, then voice ROM

data cannot be accessed at all. Writing a ²1² to VROMC

bit is to enable the voice ROM circuit, and writing a ²0² to

VROMC bit is to disable the voice ROM circuit. The bit 4

(LATCHC) is to determine what voice ROM address

latch counter will be adopted as voice ROM address

latch counter. The bit 7 (FAST) is to determine how to

activate 32kHz crystal of TMR3¢s clock source.

Example: Read an 8-bit voice ROM data which is lo-

cated at address 000007H by address latch 0

set

clr

[26H].2

[26H].4

; Enable voice ROM circuit

; Select voice ROM address

; latch counter 0

mov

call

A, 07H

;

LATCH0L, A ; Set LATCH0L to 07H

A, 00H

LATCH0M, A ; Set LATCH0M to 00H

A, 00H

;

Voice ROM Data Address Latch Counter

LATCH0H(18H)/LATCH0M(19H)/LATCH0L(1AH),

LATCH1H(1BH)/LATCH1M(1CH)/LATCH1L(1DH) and

voice ROM data register(2AH)

;

LATCH0H, A ; Set LATCH0H to 00H

Delay Time ; Delay a short period of time

A, LATCHD ; Get voice data at 000007H

The voice ROM data address latch counter is the hand-

shaking between the microcontroller and voice ROM,

mov

Bit No.

Label

Function

0, 3, 5~6

¾

Unused bit, read as ²0²

Enable/disable DAC circuit

(0= disable DAC circuit; 1= enable DAC circuit)

1

DAC

The DAC circuit is not affected by the HALT instruction.

The software controls bit DAC (VoiceC.1) whether to enable/disable.

Enable/disable voice ROM circuit

2

4

7

VROMC

(0= disable voice ROM circuit; 1= enable voice ROM circuit)

LATCHC Select voice ROM counter (0= voice ROM address latch 0; 1= voice ROM address latch 1)

Enable/disable speed-up 32kHz crystal. Default to 0.

FAST

(0= speed-up 32kHz crystal; 1= non-speed-up 32kHz crystal)

VOICEC (26H) Register

OTP Option

Description

Enable/disable PA wake-up function

PA Wake-up

Enable/disable WDT function

Watchdog Timer (WDT)

One or two CLR instruction

WDT clock source is from WDTOSC or T1

External INT is triggered on falling edge only, or is triggered on falling and rising

edge.

External INT Trigger Edge

Timer 3 Clock Source

Timer3¢s clock source is from T1, or is from the external 32kHz crystal which is

connected to XIN and XOUT.

External Timer 0/1 Clock Source Enable/disable external timer of Timer 0 and Timer 1, share with PC4 and PC5.

PA Pull-high

PB Pull-high

PC Pull-high

Enable/disable PA pull-high

Enable/disable PB pull-high

Enable/disable PC pull-high

Rev. 0.00

22

October 23, 2006

Preliminary

HT86R192

f

_OSC- R_OSCTable (V_DD=3V)

f_OSC

R_OSC(Typical)

300kW

202kW

155kW

4MHz

6MHz

8MHz

Note: These oscillator resistor values are for reference purposes only as the actual frequency may vary due to tem-

perature and process variations within the device.

Application Circuits

V

D

1

0

W

4

m

7 F

m

0 . 1 F

V

D

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2

1

V

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1

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B

0

~

P

A

B

7

V

D

1

m

0 0 F

1

0

k

P

C

0

~

P

C

6

S

(

P

K

R

E

S

m

0 . 1 F

8

W

V

D

m

0 . 1 F

A

U

D

8

0

5

0

R

1

V

S

A

R

2

V

S

I

N

T

H

T

8

6

R

1

9

2

N

o

t

e

:

R

1

>

R

2

V

D

1

0

W

4

m

7 F

m

0 . 1 F

V

D

A

O

S

C

2

1

4

M

H

z

~

8

M

H

z

V

D

P

A

B

0

~

P

A

B

7

V

D

1

m

0 0 F

P

C

0

~

P

C

6

C

E

1

0

k

W

1

5

V

D

R

E

S

A

u

d

i

o

I

n

O

U

T

N

8

A

U

D

m

0 . 1 F

V

D

2

3

V

D

m

0 . 1 F

A

u

d

i

o

I

n

S

(

P

K

H

T

8

2

V

7

3

4

m

7 F

8

W

V

R

E

F

V

S

4

1

m

0 F

V

S

A

I

N

T

6

7

N

C

H

T

8

6

R

1

9

2

Rev. 0.00

23

October 23, 2006

Preliminary

HT86R192

Instruction Set Summary

Mnemonic

Instruction

Cycle

Flag

Affected

Description

Arithmetic

ADD A,[m]

ADDM A,[m]

ADD A,x

Add data memory to ACC

1

1⁽¹⁾

1

Z,C,AC,OV

C

Add ACC to data memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add data memory to ACC with carry

1

1⁽¹⁾

Add ACC to data memory with carry

Subtract immediate data from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

Subtract data memory from ACC

1

1⁽¹⁾

Subtract data memory from ACC with result in data memory

Subtract data memory from ACC with carry

Subtract data memory from ACC with carry and result in data memory

Decimal adjust ACC for addition with result in data memory

1

1⁽¹⁾

Logic Operation

AND A,[m]

OR A,[m]

AND data memory to ACC

1

Z

OR data memory to ACC

XOR A,[m]

ANDM A,[m]

ORM A,[m]

Exclusive-OR data memory to ACC

AND ACC to data memory

OR ACC to data memory

1

1⁽¹⁾

1

XORM A,[m] Exclusive-OR ACC to data memory

AND A,x

OR A,x

AND immediate data to ACC

OR immediate data to ACC

1

XOR A,x

CPL [m]

CPLA [m]

Exclusive-OR immediate data to ACC

Complement data memory

1

1⁽¹⁾

Complement data memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment data memory with result in ACC

1

Z

Increment data memory

1⁽¹⁾

DECA [m]

DEC [m]

Decrement data memory with result in ACC

Decrement data memory

1

1⁽¹⁾

Rotate

RRA [m]

RR [m]

Rotate data memory right with result in ACC

Rotate data memory right

1

1⁽¹⁾

1

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate data memory right through carry with result in ACC

Rotate data memory right through carry

Rotate data memory left with result in ACC

Rotate data memory left

1⁽¹⁾

C

1

None

C

1⁽¹⁾

1

RLCA [m]

RLC [m]

Rotate data memory left through carry with result in ACC

Rotate data memory left through carry

1⁽¹⁾

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move data memory to ACC

Move ACC to data memory

Move immediate data to ACC

1

1⁽¹⁾

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of data memory

Set bit of data memory

1⁽¹⁾

None

Rev. 0.00

24

October 23, 2006

Preliminary

HT86R192

Instruction

Cycle

Flag

Affected

Mnemonic

Branch

Description

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if data memory is zero

1⁽²⁾

1⁽³⁾

1⁽²⁾

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if data memory is zero with data movement to ACC

Skip if bit i of data memory is zero

Skip if bit i of data memory is not zero

Skip if increment data memory is zero

Skip if decrement data memory is zero

Skip if increment data memory is zero with result in ACC

Skip if decrement data memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m] Read ROM code (current page) to data memory and TBLH

TABRDL [m] Read ROM code (last page) to data memory and TBLH

2⁽¹⁾

None

Miscellaneous

NOP

No operation

1

1⁽¹⁾

1

None

CLR [m]

Clear data memory

SET [m]

Set data memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO,PDF

TO⁽⁴⁾,PDF⁽⁴⁾

None

Pre-clear Watchdog Timer

Swap nibbles of data memory

Swap nibbles of data memory with result in ACC

Enter power down mode

1

1⁽¹⁾

1

None

1

TO,PDF

Note: x: Immediate data

m: Data memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Ö: Flag is affected

-: Flag is not affected

⁽¹⁾: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle

(four system clocks).

⁽²⁾: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more

cycle (four system clocks). Otherwise the original instruction cycle is unchanged.

⁽¹⁾and ⁽²⁾

(3)

:

⁽⁴⁾: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the

²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.

Otherwise the TO and PDF flags remain unchanged.

Rev. 0.00

25

October 23, 2006

Preliminary

HT86R192

Instruction Definition

ADC A,[m]

Add data memory and carry to the accumulator

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADCM A,[m]

Add the accumulator and carry to data memory

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the specified data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,[m]

Add data memory to the accumulator

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the accumulator.

Operation

ACC ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,x

Add immediate data to the accumulator

Description

The contents of the accumulator and the specified data are added, leaving the result in the

accumulator.

Operation

ACC ¬ ACC+x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADDM A,[m]

Add the accumulator to the data memory

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the data memory.

Operation

[m] ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 0.00

26

October 23, 2006

Preliminary

HT86R192

AND A,[m]

Logical AND accumulator with data memory

Description

Data in the accumulator and the specified data memory perform a bitwise logical_AND op-

eration. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

AND A,x

Logical AND immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_AND operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ANDM A,[m]

Logical AND data memory with the accumulator

Description

Data in the specified data memory and the accumulator perform a bitwise logical_AND op-

eration. The result is stored in the data memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

CALL addr

Subroutine call

Description

The instruction unconditionally calls a subroutine located at the indicated address. The

program counter increments once to obtain the address of the next instruction, and pushes

this onto the stack. The indicated address is then loaded. Program execution continues

with the instruction at this address.

Operation

Stack ¬ Program Counter+1

Program Counter ¬ addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR [m]

Clear data memory

Description

Operation

The contents of the specified data memory are cleared to 0.

[m] ¬ 00H

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 0.00

27

October 23, 2006

Preliminary

HT86R192

CLR [m].i

Clear bit of data memory

Description

Operation

The bit i of the specified data memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR WDT

Clear Watchdog Timer

Description

The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are

cleared.

Operation

WDT ¬ 00H

PDF and TO ¬ 0

Affected flag(s)

TO

0

PDF

0

OV

Z

AC

C

¾

CLR WDT1

Preclear Watchdog Timer

Description

Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction just sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CLR WDT2

Preclear Watchdog Timer

Description

Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction, sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CPL [m]

Complement data memory

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa.

Operation

[m] ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 0.00

28

October 23, 2006

Preliminary

HT86R192

CPLA [m]

Complement data memory and place result in the accumulator

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa. The complemented result

is stored in the accumulator and the contents of the data memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DAA [m]

Decimal-Adjust accumulator for addition

Description

The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-

lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal

carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-

justment is done by adding 6 to the original value if the original value is greater than 9 or a

carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored

in the data memory and only the carry flag (C) may be affected.

Operation

If ACC.3~ACC.0 >9 or AC=1

then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC

else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0

and

If ACC.7~ACC.4+AC1 >9 or C=1

then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1

else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

DEC [m]

Decrement data memory

Description

Operation

Data in the specified data memory is decremented by 1.

[m] ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DECA [m]

Decrement data memory and place result in the accumulator

Description

Data in the specified data memory is decremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 0.00

29

October 23, 2006

Preliminary

HT86R192

HALT

Enter power down mode

Description

This instruction stops program execution and turns off the system clock. The contents of

the RAM and registers are retained. The WDT and prescaler are cleared. The power down

bit (PDF) is set and the WDT time-out bit (TO) is cleared.

Operation

Program Counter ¬ Program Counter+1

PDF ¬ 1

TO ¬ 0

Affected flag(s)

TO

0

PDF

1

OV

Z

AC

C

¾

INC [m]

Increment data memory

Description

Operation

Data in the specified data memory is incremented by 1

[m] ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

INCA [m]

Increment data memory and place result in the accumulator

Description

Data in the specified data memory is incremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

JMP addr

Directly jump

Description

The program counter are replaced with the directly-specified address unconditionally, and

control is passed to this destination.

Operation

Program Counter ¬addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV A,[m]

Description

Operation

Move data memory to the accumulator

The contents of the specified data memory are copied to the accumulator.

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 0.00

30

October 23, 2006

Preliminary

HT86R192

MOV A,x

Move immediate data to the accumulator

Description

Operation

The 8-bit data specified by the code is loaded into the accumulator.

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV [m],A

Move the accumulator to data memory

Description

The contents of the accumulator are copied to the specified data memory (one of the data

memories).

Operation

[m] ¬ACC

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

Program Counter ¬ Program Counter+1

TO

PDF

OV

Z

AC

C

¾

OR A,[m]

Logical OR accumulator with data memory

Description

Data in the accumulator and the specified data memory (one of the data memories) per-

form a bitwise logical_OR operation. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

OR A,x

Logical OR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_OR operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ORM A,[m]

Logical OR data memory with the accumulator

Description

Data in the data memory (one of the data memories) and the accumulator perform a

bitwise logical_OR operation. The result is stored in the data memory.

Operation

[m] ¬ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 0.00

31

October 23, 2006

Preliminary

HT86R192

RET

Return from subroutine

Description

Operation

Affected flag(s)

The program counter is restored from the stack. This is a 2-cycle instruction.

Program Counter ¬ Stack

TO

PDF

OV

Z

AC

C

¾

RET A,x

Return and place immediate data in the accumulator

Description

The program counter is restored from the stack and the accumulator loaded with the speci-

fied 8-bit immediate data.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RETI

Return from interrupt

Description

The program counter is restored from the stack, and interrupts are enabled by setting the

EMI bit. EMI is the enable master (global) interrupt bit.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RL [m]

Rotate data memory left

Description

Operation

The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RLA [m]

Rotate data memory left and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the

rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 0.00

32

October 23, 2006

Preliminary

HT86R192

RLC [m]

Rotate data memory left through carry

Description

The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-

places the carry bit; the original carry flag is rotated into the bit 0 position.

Operation

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RLCA [m]

Rotate left through carry and place result in the accumulator

Description

Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the

carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored

in the accumulator but the contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RR [m]

Rotate data memory right

Description

Operation

The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRA [m]

Rotate right and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving

the rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRC [m]

Rotate data memory right through carry

Description

The contents of the specified data memory and the carry flag are together rotated 1 bit

right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.

Operation

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 0.00

33

October 23, 2006

Preliminary

HT86R192

RRCA [m]

Rotate right through carry and place result in the accumulator

Description

Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces

the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is

stored in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBC A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBCM A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SDZ [m]

Skip if decrement data memory is 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. If the result is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, [m] ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SDZA [m]

Decrement data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. The result is stored in the accumulator but the data memory remains

unchanged. If the result is 0, the following instruction, fetched during the current instruction

execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-

cles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, ACC ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 0.00

34

October 23, 2006

Preliminary

HT86R192

SET [m]

Set data memory

Description

Operation

Each bit of the specified data memory is set to 1.

[m] ¬ FFH

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SET [m]. i

Set bit of data memory

Description

Operation

Bit i of the specified data memory is set to 1.

[m].i ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZ [m]

Skip if increment data memory is 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the fol-

lowing instruction, fetched during the current instruction execution, is discarded and a

dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with

the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, [m] ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZA [m]

Increment data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the next

instruction is skipped and the result is stored in the accumulator. The data memory re-

mains unchanged. If the result is 0, the following instruction, fetched during the current in-

struction execution, is discarded and a dummy cycle is replaced to get the proper

instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, ACC ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SNZ [m].i

Skip if bit i of the data memory is not 0

Description

If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data

memory is not 0, the following instruction, fetched during the current instruction execution,

is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-

wise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i¹0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 0.00

35

October 23, 2006

Preliminary

HT86R192

SUB A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the accumulator.

Operation

ACC ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUBM A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the data memory.

Operation

[m] ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUB A,x

Subtract immediate data from the accumulator

Description

The immediate data specified by the code is subtracted from the contents of the accumula-

tor, leaving the result in the accumulator.

Operation

ACC ¬ ACC+x+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SWAP [m]

Swap nibbles within the data memory

Description

The low-order and high-order nibbles of the specified data memory (1 of the data memo-

ries) are interchanged.

Operation

[m].3~[m].0 « [m].7~[m].4

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SWAPA [m]

Swap data memory and place result in the accumulator

Description

The low-order and high-order nibbles of the specified data memory are interchanged, writ-

ing the result to the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.3~ACC.0 ¬ [m].7~[m].4

ACC.7~ACC.4 ¬ [m].3~[m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 0.00

36

October 23, 2006

Preliminary

HT86R192

SZ [m]

Skip if data memory is 0

Description

If the contents of the specified data memory are 0, the following instruction, fetched during

the current instruction execution, is discarded and a dummy cycle is replaced to get the

proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZA [m]

Move data memory to ACC, skip if 0

Description

The contents of the specified data memory are copied to the accumulator. If the contents is

0, the following instruction, fetched during the current instruction execution, is discarded

and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed

with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZ [m].i

Skip if bit i of the data memory is 0

Description

If bit i of the specified data memory is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDC [m]

Move the ROM code (current page) to TBLH and data memory

Description

The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved

to the specified data memory and the high byte transferred to TBLH directly.

Operation

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDL [m]

Move the ROM code (last page) to TBLH and data memory

Description

The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to

the data memory and the high byte transferred to TBLH directly.

Operation

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 0.00

37

October 23, 2006

Preliminary

HT86R192

XOR A,[m]

Logical XOR accumulator with data memory

Description

Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-

sive_OR operation and the result is stored in the accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XORM A,[m]

Logical XOR data memory with the accumulator

Description

Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-

sive_OR operation. The result is stored in the data memory. The 0 flag is affected.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XOR A,x

Logical XOR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-

eration. The result is stored in the accumulator. The 0 flag is affected.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 0.00

38

October 23, 2006

Preliminary

HT86R192

Package Information

28-pin SOP (300mil) Outline Dimensions

2

8

1

5

B

4

A

1

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

394

290

14

697

92

¾

Max.

419

300

20

A

B

C

C¢

D

E

F

¾

50

¾

713

104

¾

4

¾

G

H

a

32

4

38

12

0°

10°

Rev. 0.00

39

October 23, 2006

Preliminary

HT86R192

44-pin QFP (10´10) Outline Dimensions

C

H

D

G

3

2

3

I

3

4

2

L

F

A

B

E

1

2

4

a

K

J

1

Dimensions in mm

Nom.

Symbol

Min.

13

Max.

13.4

10.1

13.4

10.1

¾

A

B

C

D

E

F

G

H

I

¾

9.9

13

¾

9.9

¾

0.8

0.3

¾

1.9

¾

2.2

2.7

¾

0.25

0.73

0.1

¾

0.5

¾

J

0.93

0.2

¾

K

L

¾

0.1

¾

a

0°

7°

Rev. 0.00

40

October 23, 2006

Preliminary

HT86R192

100-pin QFP (14´20) Outline Dimensions

C

H

D

G

8

0

5

1

I

8

1

5

0

F

A

B

E

1

0

3

1

a

K

J

1

3

0

Dimensions in mm

Nom.

Symbol

Min.

18.50

13.90

24.50

19.90

¾

Max.

19.20

14.10

25.20

20.10

¾

A

B

C

D

E

F

G

H

I

¾

0.65

0.30

¾

2.50

¾

3.10

3.40

¾

0.10

¾

J

1

1.40

0.20

7°

K

a

0.10

0°

¾

Rev. 0.00

41

October 23, 2006

Preliminary

HT86R192

Product Tape and Reel Specifications

Reel Dimensions

D

T

2

C

A

B

T

1

SOP 28W (300mil)

Symbol

Description

Dimensions in mm

A

B

Reel Outer Diameter

Reel Inner Diameter

330±1.0

62±1.5

13.0+0.5

-0.2

C

D

Spindle Hole Diameter

Key Slit Width

2.0±0.5

24.8+0.3

-0.2

T1

T2

Space Between Flange

Reel Thickness

30.2±0.2

Rev. 0.00

42

October 23, 2006

Preliminary

HT86R192

Carrier Tape Dimensions

P

0

P

1

t

D

E

F

W

B

0

C

D

1

P

K

0

A

0

SOP 28W (300mil)

Symbol

Description

Dimensions in mm

24.0±0.3

12.0±0.1

1.75±0.1

11.5±0.1

1.5+0.1

W

P

Carrier Tape Width

Cavity Pitch

E

Perforation Position

F

Cavity to Perforation (Width Direction)

Perforation Diameter

Cavity Hole Diameter

Perforation Pitch

D

D1

P0

P1

A0

B0

K0

t

1.5+0.25

4.0±0.1

Cavity to Perforation (Length Direction)

Cavity Length

2.0±0.1

10.85±0.1

18.34±0.1

2.97±0.1

0.35±0.01

21.3

Cavity Width

Cavity Depth

Carrier Tape Thickness

Cover Tape Width

C

Rev. 0.00

43

October 23, 2006

Preliminary

HT86R192

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233

Tel: 021-6485-5560

Fax: 021-6485-0313

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,

Shenzhen, China 518057

Tel: 0755-8616-9908, 8616-9308

Fax: 0755-8616-9533

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 010-6641-0030, 6641-7751, 6641-7752

Fax: 010-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016

Tel: 028-6653-6590

Fax: 028-6653-6591

Holmate Semiconductor, Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538

Tel: 510-252-9880

Fax: 510-252-9885

http://www.holmate.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 0.00

44

October 23, 2006


型号：	HT86R192(28SOP)
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	Microcontroller, LTE 微控制器
文件：	总44页 (文件大小：309K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT86R192(28SOP) [HOLTEK]

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