HT95L20P-100QEP-A_技术文档

HT95LXXX

LCD Type Phone 8-Bit MCU

Features

·

Provide MASK type and OTP type version

Programmable frequency divider (PFD)

Supported for HT95L400/40P, HT95L300/30P,

HT95L200/20P, HT95L100/10P

·

Operating voltage range: 2.4V~5.5V

·

Program ROM

·

Dual system clock: 32768Hz, 3.58MHz

-

HT95L400/40P: 16K´16 bits

·

Four operating modes: Idle mode, Sleep mode,

-

HT95L300/30P: 8K´16 bits

Green mode and Normal mode

-

HT95L200/20P: 8K´16 bits

-

·

HT95L100/10P: 4K´16 bits

Up to 1.117ms instruction cycle with 3.58MHz system

-

clock

HT95L000/00P: 4K´16 bits

·

All instructions in one or two machine cycles

Data RAM

-

HT95L400/40P: 2880´8 bits

·

Built-in 3.58MHz DTMF Generator

Built-in dialer I/O

-

HT95L300/30P: 2112´8 bits

-

HT95L200/20P: 1152´8 bits

Built-in low battery detector

-

HT95L100/10P: 1152´8 bits

Supported for HT95L400/40P, HT95L300/30P,

HT95L200/20P, HT95L100/10P

-

HT95L000/00P: 384´8 bits

·

Bidirectional I/O lines

-

·

LCD driver

-

HT95L400/40P: 40~28 I/O lines

LCD contrast can be adjusted by software or exter-

-

HT95L300/30P: 28~16 I/O lines

nal resistor

-

HT95L200/20P: 28~20 I/O lines

-

Support two LCD frame frequency 64Hz, 128Hz

-

HT95L100/10P: 20~16 I/O lines

-

Support 16 or 8 common driver pins

-

HT95L000/00P: 18~14 I/O lines

-

Some segments or commons can option to

·

bidirectional I/O lines

16-bit table read instructions

-

HT95L400/40P: 48 seg.´16 com.

·

Subroutine nesting

-

HT95L300/30P: 48 seg.´16 com.

HT95L400/40P: 12 levels

-

HT95L300/30P: 8 levels

HT95L200/20P: 24 seg.´16 com.

-

HT95L200/20P: 8 levels

-

HT95L100/10P: 20 seg.´8 com.

HT95L000/00P: 16 seg.´8 com.

-

HT95L100/10P: 8 levels

-

HT95L000/00P: 4 levels

·

HT95L400/40P: 128-pin QFP package

HT95L300/30P: 100-pin QFP package

HT95L200/20P: 100-pin QFP package

HT95L100/10P: 64-pin QFP package

HT95L000/00P: 56-pin SSOP package

·

Timer

-

Two 16-bit programmable Timer/Event Counter

-

Real time clock (RTC)

-

Watchdog Timer (WDT)

Applications

·

Deluxe Feature Phone

Fax and answering machines

Other communication system

·

Caller ID Phone

·

Cordless Phone

General Description

The HT95LXXX family MCU are 8-bit high performance

RISC-like microcontrollers with built-in DTMF generator

and dialer I/O which provide MCU dialer implementation

or system control features for telecom product applica-

tions. The phone controller has a built-in program ROM,

data RAM, LCD driver and I/O lines for high end prod-

ucts design. In addition, for power management pur-

pose, it has a built-in frequency up conversion circuit

(32768Hz to 3.58MHz) which provides dual system

clock and four types of operation modes. For example, it

can operate with low speed system clock rate of

32768Hz in green mode with little power consumption. It

can also operate with high speed system clock rate of

3.58MHz in normal mode for high performance opera-

tion. To ensure smooth dialer function and to avoid MCU

shut-down in extreme low voltage situation, the dialer

I/O circuit is built-in to generate hardware dialer signals

such as on-hook, hold-line and hand-free. Built-in real

time clock and programmable frequency divider are pro-

vided for additional fancy features in product develop-

ments. The device is best suited for feature phone

products that comply with versatile dialer specification

requirements of different areas or countries.

Rev. 1.20

1

May 26, 2004

HT95LXXX

Selection Table

Operating Program Data

Voltage Memory Memory

Normal Dialer

I/O

External

Interrupt Generator Receiver

DTMF

FSK

Part No.

LCD

Timer

Stack

Package

I/O

HT95A100

HT95A10P

2.4V~5.5V

20

6

4

8

3

4

3

4

28SOP

48SSOP

64QFP

4K´16

8K´16

384´8

1152´8

2112´8

¾

16-bit´2

Ö

¾

Ö

HT95A200

HT95A20P

2.4V~5.5V

28

8

6

8

¾

HT95A300

HT95A30P

28

8

HT95A400

HT95A40P

44

12

4

16K´16 2880´8

¾

HT95L000

HT95L00P

14~18

16~20

20~28

16~28

28~40

20~28

16~28

28~40

56SSOP

64QFP

4K´16

8K´16

384´8

1152´8

2112´8

12´8~16´8

16´8~20´8

HT95L100

HT95L10P

8

HT95L200

HT95L20P

8

100QFP

128QFP

24´8~24´16 16-bit´2

36´16~48´16 16-bit´2

24´8~24´16 16-bit´2

36´16~48´16 16-bit´2

HT95L300

HT95L30P

8

HT95L400

HT95L40P

12

8

16K´16 2880´8

HT95C200

HT95C20P

8K´16

1152´8

2112´8

HT95C300

HT95C30P

8

Ö

HT95C400

HT95C40P

12

16K´16 2880´8

Ö

Note: Part numbers suffixed with ²P² are OTP devices, all others are mask version devices.

Block Diagram (HT95L400/40P)

S

T

A

C

K

0

1

2

P

o

w

e

r

D

o

w

n

3

2

7

6

8

H

z

D

e

t

e

c

t

o

r

&

R

E

S

I

N

T

/

T

M

R

1

R

e

s

t

C

i

r

c

u

i

t

I

n

t

e

r

u

p

t

M

T

M

R

1

U

C

i

r

c

u

i

t

X

T

M

R

1

C

P

r

o

g

r

a

m

C

o

u

n

t

e

r

S

T

A

C

K

9

3

2

7

6

8

H

z

I

N

T

C

0

R

T

C

P

r

o

g

r

a

m

S

T

A

C

K

1

0

I

N

T

C

1

R

O

M

S

T

A

C

K

1

T

M

R

0

M

T

M

R

0

U

X

T

M

R

0

C

I

n

s

t

r

u

c

s

t

i

e

o

n

M

P

0

S

y

s

t

e

m

c

l

o

c

k

/

4

R

e

g

i

r

M

D

A

T

A

M

P

1

U

M

e

m

o

r

y

X

P

A

B

P

A

B

0

~

P

A

B

7

P

A

B

C

P

M

U

X

I

n

s

t

r

u

c

t

i

o

n

P

D

P

D

0

~

P

D

7

D

e

c

o

d

e

r

P

D

C

P

E

A

L

U

S

T

A

T

U

S

P

E

F

G

0

~

P

E

3

P

E

C

A

C

T

i

m

i

n

g

S

h

i

f

t

e

r

G

e

n

e

r

a

t

o

r

P

F

0

~

P

F

7

P

F

C

X

1

P

G

0

~

P

G

3

W

D

T

S

3

2

7

6

8

H

z

M

O

S

C

i

r

c

u

i

t

P

G

C

X

2

U

W

S

D

T

O

S

C

W

D

T

P

r

e

s

c

a

l

e

r

X

C

X

y

s

t

e

m

C

l

o

c

k

/

4

H

F

I

D

T

M

F

D

T

M

F

H

F

O

G

e

n

e

r

a

t

o

r

H

D

I

3

.

5

8

M

H

z

H

D

O

D

i

a

l

e

r

I

/

O

H

K

S

P

3

2

7

6

8

H

z

D

N

O

o

r

3

.

5

8

M

H

z

/

4

X

M

U

T

E

P

F

D

M

U

S

I

C

L

o

w

V

D

P

o

w

e

r

B

a

t

e

r

y

L

C

D

r

i

v

e

r

S

u

p

l

y

V

S

D

e

t

e

c

t

o

r

L

B

I

N

C

O

M

0

~

C

O

M

1

5

Rev. 1.20

2

May 26, 2004

HT95LXXX

Pin Assignment

HT95L400/40P

1

8

1

7

1

6

1

3

1

0

6

1

0

5

1

0

3

1

2

3

4

5

6

7

8

9

1

2

3

1

0

2

1

0

P

F

6

N

C

P

F

5

N

P

F

4

N

9

8

7

6

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

P

F

3

N

P

F

2

S

E

G

3

P

F

1

S

E

G

4

0

S

E

G

5

P

A

7

S

E

G

6

P

A

6

S

E

G

7

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

P

A

5

S

E

G

8

9

P

A

4

S

E

G

P

A

3

S

E

G

1

0

P

A

2

S

E

G

1

P

A

1

S

E

G

1

2

P

A

0

S

E

G

1

3

P

B

7

S

E

G

1

4

P

B

6

S

E

G

1

5

P

B

5

S

E

G

1

6

H

T

9

5

L

4

0

/

4

0

P

B

4

S

E

G

1

7

P

B

3

S

E

G

1

8

1

2

8

Q

F

P

-

A

P

B

2

S

E

G

1

9

P

B

1

0

S

E

G

2

0

S

E

G

2

1

X

M

U

T

E

S

E

G

2

D

N

P

O

S

E

G

2

3

P

S

E

G

2

4

H

K

S

E

G

2

5

H

D

O

S

E

G

2

6

H

D

I

S

E

G

2

7

H

F

O

S

E

G

2

8

H

F

I

S

E

G

2

9

V

S

E

G

3

0

V

M

D

S

E

G

3

1

2

I

N

T

/

T

R

1

S

N

C

N

C

3

9

4

0

4

1

4

2

4

3

4

5

4

6

4

7

4

8

4

9

5

0

5

1

5

2

5

3

5

4

5

6

5

7

5

8

5

9

6

0

6

1

6

2

6

3

6

4

Rev. 1.20

3

May 26, 2004

HT95LXXX

HT95L300/30P

1

0

9

8

9

7

9

6

9

5

9

4

9

3

9

2

9

1

9

0

8

9

8

7

8

6

8

5

8

4

8

3

8

2

8

1

C

O

M

0

1

2

3

4

5

6

7

8

9

1

2

3

8

7

6

5

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

S

E

G

E

G

5

6

7

8

9

1

2

3

P

A

B

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

H

T

9

5

L

3

0

/

3

0

P

E

G

1

0

Q

F

P

-

A

X

M

U

T

E

D

N

P

O

P

H

K

S

H

D

O

H

D

I

H

F

O

H

F

I

V

S

V

M

D

I

N

T

/

T

R

1

X

2

1

3

1

3

2

3

4

3

5

3

6

3

7

3

8

3

9

4

0

4

1

4

2

4

3

4

5

4

6

4

7

4

8

4

9

5

0

HT95L200/20P

1

0

9

8

9

7

9

6

9

5

9

4

9

3

9

2

9

1

9

0

8

9

8

7

8

6

8

5

8

4

8

3

8

2

8

1

N

C

1

2

3

4

5

6

7

8

9

1

2

3

8

7

6

5

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

N

C

S

N

C

O

M

1

0

1

2

3

4

5

P

B

5

4

3

2

1

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

0

E

G

0

1

2

3

4

5

6

7

8

9

1

X

M

U

T

E

H

T

9

5

L

2

0

/

2

0

P

D

N

P

O

P

1

0

Q

F

P

-

A

H

K

S

H

D

O

H

D

I

H

F

O

H

F

0

1

2

3

4

5

N

C

V

S

V

M

D

C

I

N

T

/

T

R

1

X

2

1

3

1

3

2

3

4

3

5

3

6

3

7

3

8

3

9

4

0

4

1

4

2

4

3

4

5

4

6

4

7

4

8

4

9

5

0

Rev. 1.20

4

May 26, 2004

HT95LXXX

HT95L100/10P, HT95L000/00P

P

A

B

3

2

1

0

5

4

P

A

4

1

2

3

4

5

6

7

8

9

1

2

5

4

3

2

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

2

1

0

9

P

A

5

P

A

6

7

P

A

X

1

2

C

X

V

S

X

6

4

6

3

6

2

6

1

6

0

5

9

5

8

5

7

5

6

5

4

5

3

5

2

S

V

M

R

T

D

E

L

G

6

7

8

9

1

C

O

M

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

2

3

4

5

6

7

8

9

1

5

4

3

1

0

9

8

7

6

5

4

3

2

1

0

9

8

7

6

5

4

3

N

C

P

B

3

2

1

0

P

A

B

V

D

S

R

E

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

D

T

M

F

0

1

2

3

4

5

6

7

8

9

I

N

T

N

C

O

M

0

1

2

3

4

5

6

7

N

C

H

F

I

O

H

X

M

U

T

E

H

T

9

5

L

1

0

/

1

0

P

0

1

2

3

4

5

6

7

8

9

D

N

P

O

6

4

Q

F

P

-

A

/

P

E

0

1

2

3

P

O

H

K

C

S

N

S

E

G

0

1

2

3

4

5

6

7

S

E

G

1

5

/

P

E

3

C

D

S

E

G

1

4

/

P

E

2

U

S

I

C

S

E

G

1

3

/

P

E

1

0

E

S

E

G

1

2

X

M

U

T

E

M

R

0

S

E

G

1

0

D

N

P

O

T

M

F

S

E

G

1

2

0

2

1

2

3

2

4

2

5

2

6

2

7

2

8

2

9

3

0

3

1

3

2

S

E

G

9

8

H

T

9

5

L

0

/

0

P

5

6

S

O

P

-

A

Pin Description

Pin Name

I/O

Description

CPU

VDD

VSS

X1

Positive power supply

Negative power supply, ground

¾

I

A 32768Hz crystal (or resonator) should be connected to this pin and X2.

A 32768Hz crystal (or resonator) should be connected to this pin and X1.

External low pass filter used for frequency up conversion circuit.

Schmitt trigger reset input, active low.

X2

O

I

XC

RES

I

Supported for HT95L000/00P

Schmitt trigger input for external interrupt

No internal pull-high resistor.

INT

I

Edge trigger activated on a falling edge.

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P

Schmitt trigger input for external interrupt or Timer/Event Counter 1.

No internal pull-high resistor.

INT/TMR1

TMR0

For INT: Edge trigger activated on a falling edge.

For TMR1: Activated on falling or rising transition edge, selected by software.

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P

Schmitt trigger input for Timer/Event Counter 0.

No internal pull-high resistor.

Activated on falling or rising transition edge, selected by software.

Rev. 1.20

5

May 26, 2004

HT95LXXX

Pin Name

LCD Driver

I/O

Description

LCD panel segment outputs.

O

or

Some segment outputs can be optioned to Bidirectional input/output ports by software.

SEG47~SEG0

COM15~COM0

I/O

(See the ²LCD Driver² function)

LCD panel common outputs.

O

or

Some common outputs can be optioned to Bidirectional input/output ports by software.

(See the ²LCD Driver² function)

I/O

VLCD

I

LCD driver power source.

Normal I/O

Bidirectional input/output ports.

PA7~PA0

PB7~PB0

I/O Schmitt trigger input and CMOS output.

See mask option table for pull-high and wake-up function

Bidirectional input/output ports.

I/O Schmitt trigger input and CMOS output.

See mask option table for pull-high function

Bidirectional input/output ports.

Schmitt trigger input and CMOS output.

I/O

PD7~PD0

PE3~PE0

See mask option table for pull-high function

Port D could be optioned to LCD signal output, see the ²Input/Output Ports² function

Bidirectional input/output ports.

Schmitt trigger input and CMOS output.

I/O

See mask option table for pull-high function

Port E could be optioned to LCD signal output, see the ²Input/Output Ports² function

Bidirectional input/output ports.

PF7~PF0

PG3~PG0

I/O Schmitt trigger input and CMOS output.

See mask option table for pull-high function

Bidirectional input/output ports.

I/O Schmitt trigger input and CMOS output.

See mask option table for pull-high function

Dialer I/O (See the ²Dialer I/O Function²)

Schmitt trigger input structure. An external RC network is recommended for input

debouncing.

HFI

I

O

I

This pin is pulled low with internal resistance of 200kW typ.

HFO

HDI

CMOS output structure.

Schmitt trigger input structure. An external RC network is recommended for input

debouncing.

This pin is pulled high with internal resistance of 200kW typ.

HDO

HKS

O

I

CMOS output structure.

This pin detects the status of the hook-switch and its combination with HFI/HDI can con-

trol the PO pin output to make or break the line.

CMOS output structure controlled by HKS and HFI/HDI pins and which determines

whether the dialer connects or disconnects the telephone line.

PO

O

DNPO

NMOS output structure.

NMOS output structure. Usually, XMUTE is used to mute the speech circuit when trans-

mitting the dialer signal.

XMUTE

Peripherals

DTMF

This pin outputs dual tone signals to dial out the phone number. The load resistor should

O

not be less than 5kW.

MUSIC

LBIN

O

I

This pin outputs the single tone that is generated by the PFD generator.

This pin detects battery low through external R1/R2 to determine threshold voltage.

Rev. 1.20

6

May 26, 2004

HT95LXXX

Absolute Maximum Ratings

Supply Voltage ..........................V_SS-0.3V to V_SS+5.5V

Input Voltage .............................. V_SS-0.3 to V_DD+0.3V

Storage Temperature ...........................-50°C to 125°C

Operating Temperature ..........................-20°C to 70°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those

listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-

ity.

Electrical Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

CPU

Parameter

Min.

Typ.

Max.

Unit

V_DD

32768Hz off, 3.58MHz off,

I_IDL

Idle Mode Current

5V CPU off, LCD off, WDT off,

no load

2

30

50

3

¾

mA

32768Hz on, 3.58MHz off,

5V CPU off, LCD off, WDT off,

no load

I_SLP

I_GRN

I_NOR

Sleep Mode Current

Green Mode Current

Normal Mode Current

32768Hz on, 3.58MHz off,

5V CPU on, LCD off, WDT off,

no load

32768Hz on, 3.58MHz on,

5V CPU on, LCD on, WDT on,

DTMF generator off, no load

V_IL

I/O Port Input Low Voltage

I/O Port Input High Voltage

I/O Port Sink Current

5V

0

4

1

V

¾

6

V_IH

I_OL

5

V

4

mA

kW

¾

I_OH

R_PH

I/O Port Source Current

Pull-high Resistor

-2

10

-3

30

Low Battery Detection

Reference voltage

V_LBIN

5V

1.10

1.15

1.20

V

¾

LCD Driver

V_LCD

I_LCD

LCD Panel Power Supply

LCD Operation Current

3

5

V

¾

V_LCD=5V, 32768Hz, no load

100

¾

mA

Dialer I/O

I_XMO

XMUTE Leakage Current

XMUTE Sink Current

HKS Input Current

2.5V XMUTE pin=2.5V

2.5V XMUTE pin=0.5V

2.5V HKS pin=2.5V

1

¾

0.1

¾

1

¾

mA

I_OLXM

I_HKS

¾

-1

1

¾

R_HFI

V_HFI=2.5V

V_HDI=0V

V_OH=2V

HFI Pull-low Resistance

HDI Pull-high Resistance

HFO Source Current

HFO Sink Current

2.5V

200

¾

kW

R_HDI

kW

I_OH2

mA

I_OL2

V_OL=0.5V

V_OH=2V

¾

I_OH3

HDO Source Current

HDO Sink Current

-1

1

¾

I_OL3

V_OL=0.5V

V_OH=2V

¾

I_OH4

PO Source Current

PO Sink Current

-1

1

¾

I_OL4

V_OL=0.5V

¾

I_OL5

DNPO Sink Current

1

¾

Rev. 1.20

7

May 26, 2004

HT95LXXX

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

DTMF Generator

V_TDC

V_TOL

V_TAC

R_L

0.45V_DD

0.7V_DD

DTMF Output DC Level

DTMF Sink Current

V

mA

¾

V_DTMF=0.5V

0.1

120

5

¾

180

¾

DTMF Output AC Level

DTMF Output Load

155

¾

mVrms

kW

Row group, R_L=5kW

THD£-23dB

A_CR

THD

Column Pre-emphasis

Tone Signal Distortion

Row group=0dB

R_L=5kW

1

2

3

dB

¾

-30

-23

Functional Description

Execution Flow

each instruction. The conditional skip is activated by

instructions. Once the condition is met, the next instruc-

tion, fetched during the current instruction execution, is

discarded and a dummy cycle replaces it to get the

proper instruction. Otherwise proceed to the next in-

struction.

The system clock for the telephone controller is derived

from a 32768Hz crystal oscillator. Abuilt-in frequency up

conversion circuit provides dual system clock, namely;

32768Hz and 3.58MHz. The system clock is internally

divided into four non-overlapping clocks. One instruc-

tion cycle consists of four system clock cycles. Instruc-

tion fetching and execution are pipelined in such a way

that a fetch takes an instruction cycle while decoding

and execution takes the next instruction cycle. The

pipelining scheme causes each instruction to be effec-

tively executed in a instruction cycle. If an instruction

changes the program counter, two instruction cycles are

required to complete the instruction.

The program counter lower order byte register

(PCL:06H) is a readable and write-able register. Moving

data into the PCL performs a short jump. The destina-

tion will be within 256 locations. When a control transfer

takes place, an additional dummy cycle is required.

Program Memory - ROM

The program memory is used to store the program in-

structions which are to be executed. It also contains

data, table, and interrupt entries, and is organized into

8K´16 bits´2 banks (HT95L400/40P), 8K´16 bits

(HT95L300/30P, HT95L200/20P) or 4K´16 bits

(HT95L100/10P, HT95L000/00P), addressed by the

program counter and table pointer.

Program Counter - PC

The program counter (PC) controls the sequence in

which the instructions stored in the program ROM are

executed and its contents specify a full range of pro-

gram memory. After accessing a program memory word

to fetch an instruction code, the contents of the program

counter are incremented by 1. The program counter

then points to the memory word containing the next in-

struction code.

For the HT95L400/40P, the program memory is divided

into 2 banks, each bank having a ROM Size 8K´16 bits.

To move from the present ROM bank to a different ROM

bank, the higher 1 bits of the ROM address are set by

the BP (Bank Pointer), while the remaining 13 bits of the

PC are set in the usual way by executing the appropriate

jump or call instruction. As the 14 address bits are

latched during the execution of a call or jump instruction,

the correct value of the BP must first be setup before a

When executing a jump instruction, conditional skip ex-

ecution, loading PCL register, subroutine call, initial re-

set, internal interrupt, external interrupt or return from

subroutine, the program counter manipulates the pro-

gram transfer by loading the address corresponding to

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

T

1

T

2

T

3

T

4

S

y

s

t

e

m

C

l

o

c

k

P

C

P

C

+

1

P

C

+

2

P

C

F

e

t

c

h

I

N

S

T

(

P

C

)

E

x

e

c

u

t

e

I

N

S

T

(

P

C

-

1

)

F

e

t

c

h

I

N

S

T

(

P

C

+

1

)

E

x

e

c

u

t

e

I

N

S

T

(

P

C

)

F

e

t

c

h

I

N

S

T

(

P

C

+

2

)

E

x

e

c

u

t

e

I

N

S

T

(

P

C

+

1

)

Execution Flow

Rev. 1.20

8

May 26, 2004

HT95LXXX

Program Counter

Mode

*13 *12 *11 *10 *9

*8

0

*7

0

*6

0

*5

0

*4

0

1

*3

0

1

0

1

*2

0

1

0

1

0

*1

0

*0

0

Initial reset

0

External interrupt

Timer/Event Counter 0 overflow

Timer/Event Counter 1 overflow

RTC interrupt

Dialer I/O interrupt

Skip

Program Counter+2 (within current bank)

*13 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Loading PCL

Jump, call branch

Return from subroutine

BP.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program ROM Address

Note: *13~*0: Program counter bits

S13~S0: Stack register bits

#12~#0: Instruction code bits

@7~@0: PCL bits

Available bits of program counter for HT95L400/40P: Bit 13~Bit 0

Available bits of program counter for HT95L300/30P: Bit 12~Bit 0

Available bits of program counter for HT95L200/20P: Bit 12~Bit 0

Available bits of program counter for HT95L100/10P: Bit 11~Bit 0

Available bits of program counter for HT95L000/00P: Bit 11~Bit 0

jump or call is executed. When either a software or hard-

0

4

8

H

D

e

v

i

c

e

I

n

i

t

i

a

l

i

z

a

t

i

o

n

P

r

o

g

r

a

m

ware interrupt is received, note that no matter which

ROM bank the program is in, the program will always

jump to the appropriate interrupt service address in

Bank 0. The original 14 bits address will be stored on the

stack and restored when the relevant RET/RETI instruc-

tion is executed, automatically returning the program to

the original ROM bank. This eliminates the need for pro-

grammers to manage the BP when interrupts occur.

Certain locations in the program memory are reserved

for special usage:

E

x

t

e

r

n

a

l

I

n

t

e

r

u

p

t

S

u

b

r

o

u

t

i

n

e

T

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

0

I

n

t

e

r

u

p

t

S

u

b

r

o

u

t

i

n

e

0

C

H

T

i

m

e

r

/

E

v

e

n

t

C

o

u

n

t

e

r

1

I

n

t

e

r

u

p

t

S

u

b

r

o

u

t

i

n

e

0

1

0

H

R

e

s

e

r

v

e

d

0

1

4

8

H

R

T

C

I

n

t

e

r

u

p

t

S

u

b

r

o

u

t

i

n

e

P

r

o

g

r

a

m

R

O

M

D

i

a

l

e

r

I

/

O

I

n

t

e

r

u

p

t

S

u

b

r

o

u

t

i

n

e

·

Location 0000H (Bank0)

1

0

H

L

o

k

-

u

p

T

a

b

l

e

(

2

5

6

W

o

r

d

s

)

This area is reserved for the initialization program. Af-

ter chip power-on reset or external reset or WDT

time-out reset, the program always begins execution

at location 0000H.

1

F

H

L

o

k

-

u

p

T

a

b

l

e

(

2

5

6

W

o

r

d

s

)

·

Location 0004H (Bank0)

(

L

a

s

t

P

a

g

e

s

)

This area is reserved for the external interrupt service

program. If the INT/TMR1 input pin is activated, the

external interrupt is enabled and the stack is not full,

the program begins execution at location 0004H.

1

6

b

i

t

s

N

o

t

e

:

T

h

e

L

a

s

t

p

a

g

e

f

o

r

H

T

9

5

L

4

0

/

4

0

P

i

s

3

F

0

H

~

3

F

H

T

h

e

L

a

s

t

p

a

g

e

f

o

r

H

T

9

5

L

3

2

1

0

/

3

2

1

0

P

i

s

1

0

F

0

H

~

1

0

F

H

e

o

r

0

Location 0008H (Bank0)

Program Memory

This area is reserved for the Timer/Event Counter 0 in-

terrupt service program. If a timer interrupt results

from a Timer/Event Counter 0 overflow, the

Timer/Event Counter 0 interrupt is enabled and the

stack is not full, the program begins execution at loca-

tion 0008H.

Rev. 1.20

9

May 26, 2004

HT95LXXX

·

Location 000CH (Bank0)

specified data memory, and the higher-order byte to

TBLH (08H). For the HT95L400/40P, the instruction

²TABRDC [m]² is used for any page of any bank. Only

the destination of the lower-order byte in the table is

well-defined, and the higher-order byte of the table word

is transferred to TBLH. The table pointer (TBLP) or

(TBHP, TBLP for the HT95L400/40P) is a read/write

register (07H) or (1FH, 07H for the HT95L400/40P),

which indicates the table location. Before accessing the

table, the location must be placed in the (TBLP) or

(TBHP, TBLP for the HT95L400/40P). The TBLH is read

only and cannot be restored. If the main routine and the

ISR (Interrupt Service Routine) both employ the table

read instruction, the contents of the TBLH in the main

routine are likely to be changed by the table read in-

struction used in the ISR. Errors will then occur. Hence,

simultaneously using the table read instruction in the

main routine and the ISR should be avoided. However, if

the table read instruction has to be applied in both the

main routine and the ISR, the interrupt should be dis-

abled prior to the table read instruction. It will not be en-

abled until the TBLH has been backed-up. All table

related instructions require two cycles to complete the

operation. These areas may function as normal pro-

gram memory depending on the requirements.

This location is reserved for the Timer/Event Counter

1 interrupt service program. If a timer interrupt results

from a Timer/Event Counter 1 overflow, the

Timer/Event Counter 1 interrupt is enabled and the

stack is not full, the program begins execution at loca-

tion 000CH.

·

Location 0014H (Bank0)

This location is reserved for real time clock (RTC) in-

terrupt service program. When RTC generator is en-

abled and time-out occurs, the RTC interrupt is

enabled and the stack is not full, the program begins

execution at location 0014H.

Location 0018H (Bank0)

This location is reserved for the HKS pin edge transi-

tion or HDI pin falling edge transition or HFI pin rising

edge transition. If this condition occurs, the dialer I/O

interrupt is enabled and the stack is not full, the pro-

gram begins execution at location 18H.

Table Location

Any location in the ROM space can be used as look-up

tables. The instructions ²TABRDC [m]² (the current

page, one page=256 words) and ²TABRDL [m]² (the last

page) transfer the contents of the lower-order byte to the

HT95L400/40P

Table Location

Instruction(s)

*13

#5

1

*12

#4

1

*11

#3

1

*10

#2

1

*9

#1

1

*8

#0

1

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

@7

@6

@5

@4

@3

@2

@1

@0

HT95L300/30P, HT95L200/20P

Table Location

Instruction(s)

*12

P12

1

*11

P11

1

*10

*9

*8

*7

*6

*5

@5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

P10

1

P9

1

P8

1

@7

@6

@4

@3

@2

@1

@0

HT95L100/10P, HT95L000/00P

Table Location

Instruction(s)

*11

P11

1

*10

P10

1

*9

*8

*7

*6

*5

*4

*3

*2

*1

*0

TABRDC [m]

TABRDL [m]

P9

1

P8

1

@7

@6

@5

@4

@3

@2

@1

@0

Note: *13~*0: Table location bits

@7~@0: TBLP register bit7~bit0

#7~#0: TBHP register bit7~bit0

P12~P8: Current program counter bits

Rev. 1.20

10

May 26, 2004

HT95LXXX

Stack Register

The special function registers are located from 00H to

1FH. The embedded control registers are located in the

memory areas from 20H to 3FH. The remaining spaces

which are not specified in the following table before the

40H are reserved for future expanded usage and read-

ing these locations will get ²00H². The general purpose

data memory is divided into 15 banks (HT95L400/40P),

11 banks (HT95L300/30P), 6 banks (HT95L200/20P,

HT95L100/10P) or 2 banks (HT95L000/00P). The

banks in the RAM are all addressed from 40H to 0FFH

and they are selected by setting the value of the bank

pointer (BP).

This is a special part of the memory which is used to

save the contents of the program counter only. The

stack is organized into 12 levels (HT95L400/40P), 8 lev-

els (HT95L300/30P, HT95L200/20P, HT95L100/10P) or

4 levels (HT95L000/00P) and is neither part of the data

nor part of the program space, and is neither readable

nor writable. The activated level is indexed by the stack

pointer (SP) and is neither readable nor writable. At a

subroutine call or interrupt acknowledge signal, the con-

tents of the program counter are pushed onto the stack.

At the end of a subroutine or an interrupt routine, sig-

naled by a return instruction (RET or RETI), the program

counter is restored to its previous value from the stack.

After a chip reset, the SP will point to the top of the stack.

If the stack is full and an interrupt takes place, the inter-

rupt request flag will be recorded but the acknowledge

signal will be inhibited even if this interrupt is enabled.

When the stack pointer is decremented (by RET or

RETI), the interrupt will be serviced. This feature pre-

vents stack overflow allowing the programmer to use the

structure more easily. If the stack is full and a ²CALL² is

subsequently executed, stack overflow occurs and the

first entry will be lost (only the most recent 12, 8 or 4, de-

pending on various MCU type, returned addresses are

stored).

All of the data memory areas can handle arithmetic,

logic, increment, decrement and rotate operations di-

rectly. Except for some dedicated bits, each bit in the

data memory can be set and reset by ²SET [m].i² and

²CLR [m].i². They are also indirectly accessible through

memory pointer registers (MP0 or MP1). The

bank1~bank14 and bank27 are only indirectly accessi-

ble through memory pointer 1 register (MP1).

The LCD display memory is located at bank 1BH. They

can be read and written to by the indirect addressing

mode using memory pointer 1 (MP1). To turn the display

On or Off, a ²1² or ²0² is written to the corresponding bit

of the memory area.

Data Memory

The data memory is divided into four functional groups:

special function registers, embedded control register,

LCD display memory and general purpose memory.

Most are read/write, but some are read only.

Special Register, Embedded Control Register, LCD Display Memory and General Purpose RAM

Supported for HT95LXXX

400/P 300/P 200/P 100/P 000/P

BP

(RAM Bank)

Address

Function

Description

Special Function Register

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

IAR0

MP0

Indirect addressing register 0

Memory pointer register 0

Indirect addressing register 1

Memory pointer register 1

Bank Pointer register

Ö

IAR1

MP1

BP

ACC

Accumulator

PCL

Program counter lower-order byte register

Table pointer

TBLP

TBLH

WDTS

STATUS

INTC0

Table higher-order byte register

Watchdog Timer option setting register

Status register

Interrupt control register 0

Timer/Event Counter 0 high-order byte

register

00H

0CH

TMR0H

Ö

Rev. 1.20

11

May 26, 2004

HT95LXXX

Supported for HT95LXXX

BP

(RAM Bank)

Address

Function

Description

400/P 300/P 200/P 100/P 000/P

Timer/Event Counter 0 low-order byte

register

00H

0DH

0EH

0FH

TMR0L

TMR0C

TMR1H

Ö

Timer/Event Counter 0 control register

Timer/Event Counter 1 high-order byte

register

Timer/Event Counter 1 low-order byte

register

00H

10H

TMR1L

Ö

00H

11H

12H

13H

14H

15H

16H

18H

19H

1AH

1BH

1EH

1FH

TMR1C

PA

Timer/Event Counter 1 control register

Port A data register

Ö

PAC

PB

Port A control register

Ö

Port B data register

Ö

PBC

Port B control register

Ö

DIALERIO Dialer I/O register

Ö

PD

PDC

PE

Port D data register

Ö

¾

Ö

¾

Ö

Port D control register

Port E data register

Ö

PEC

INTC1

TBHP

Port E control register

Interrupt control register 1

Table high-order byte pointer

Ö

¾

Embedded Control Register

00H

20H

21H

22H

24H

26H

28H

2DH

2EH

2FH

34H

35H

36H

37H

DTMFC

DTMFD

LINE

DTMF generator control register

DTMF generator data register

Line control register

Ö

¾

Ö

RTCC

MODE

LCDIO

LCDC

PFDC

PFDD

PF

Real time clock control register

Operation mode control register

LCD segment and I/O option register

LCD driver control register

PFD control register

Ö

¾

Ö

¾

PFD data register

Ö

Port F data register

¾

PFC

Port F control register

PG

Port G data register

PGC

Port G control register

General Purpose RAM

00H

01H

02H

03H

04H

05H

06H

07H

08H

40H~FFH BANK0 RAM General purpose RAM space

40H~FFH BANK1 RAM General purpose RAM space

40H~FFH BANK2 RAM General purpose RAM space

40H~FFH BANK3 RAM General purpose RAM space

40H~FFH BANK4 RAM General purpose RAM space

40H~FFH BANK5 RAM General purpose RAM space

40H~FFH BANK6 RAM General purpose RAM space

40H~FFH BANK7 RAM General purpose RAM space

40H~FFH BANK8 RAM General purpose RAM space

Ö

¾

Ö

¾

Rev. 1.20

12

May 26, 2004

HT95LXXX

Supported for HT95LXXX

BP

(RAM Bank)

Address

Function

Description

400/P 300/P 200/P 100/P 000/P

09H

0AH

0BH

0CH

0DH

0EH

40H~FFH BANK9 RAM General purpose RAM space

40H~FFH BANK10 RAM General purpose RAM space

40H~FFH BANK11 RAM General purpose RAM space

40H~FFH BANK12 RAM General purpose RAM space

40H~FFH BANK13 RAM General purpose RAM space

40H~FFH BANK14 RAM General purpose RAM space

Ö

¾

Ö

¾

LCD RAM Display Memory

1BH

40H~9FH LCD RAM

LCD RAM mapping space for COM0~COM15 (see ²LCD Driver² function)

Indirect Addressing Register

Arithmetic and Logic Unit - ALU

Location 00H and 02H are indirect addressing registers

that are not physically implemented. Any read/write op-

eration of [00H] and [02H] will access the memory

pointed to by MP0 and MP1, respectively. Reading loca-

tion [00H] or [02H] indirectly returns the result 00H,

while writing it leads to no operation. MP0 is indirectly

addressable in bank0, but MP1 is available for all banks

by switch BP [04H]. If BP is unequal to 00H, the indirect

addressing mode to read/write operation from 00H~3FH

will return the result as same as the value of bank0.

This circuit performs 8-bit arithmetic and logic opera-

tions and provides the following functions:

·

Arithmetic operations (ADD, ADC, SUB, SBC, DAA)

Logic operations (AND, OR, XOR, CPL)

Rotation (RL, RR, RLC, RRC)

Increment and Decrement (INC, DEC)

Branch decision (SZ, SNZ, SIZ, SDZ, etc.)

The ALU not only saves the results of a data operation

but also changes the status register.

The memory pointer registers MP0 and MP1 are 8-bits

registers, and the bank pointer register BP is 6-bits reg-

ister for the HT95L400/40P or 5-bits for the other de-

vices in the series.

Status Register - STATUS

This status register contains the carry flag (C), auxiliary

carry flag (AC), zero flag (Z), overflow flag (OV), power

down flag (PDF), and watchdog time-out flag (TO). It

also records the status information and controls the op-

eration sequence.

Accumulator

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can operate with immediate data. All data movement

between two data memory locations must pass through

the accumulator.

Except for the TO and PDF flags, bits in the status regis-

ter can be altered by instructions, similar to the other

registers. Data written into the status register will not

change the TO or PDF flag. Operations related to the

Register

Label

Bits

Function

C is set if the operation results in a carry during an addition operation or if a borrow

does not take place during a subtraction operation; otherwise C is cleared. Also it is

affected by a rotate through carry instruction.

C

0

AC is set if the operation results in a carry out of the low nibbles in addition or no bor-

row from the high nibble into the low nibble in subtraction; otherwise AC is cleared.

AC

Z

1

2

3

Z is set if the result of an arithmetic or logic operation is 0; otherwise Z is cleared.

STATUS

(0AH)

OV is set if the operation results in a carry into the highest-order bit but not a carry

out of the highest-order bit, or vice versa; otherwise OV is cleared.

OV

PDF is cleared when either a system power-up or executing the ²CLR WDT² in-

struction. PDF is set by executing the ²HALT² instruction.

PDF

4

TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² in-

struction. TO is set by a WDT time-out.

TO

5

6, 7

¾

Unused bit, read as ²0²

Rev. 1.20

13

May 26, 2004

HT95LXXX

status register may yield different results from those in-

tended. The TO flag can be affected only by system

power-up, a WDT time-out or executing the ²CLR WDT²

or ²HALT² instruction. The PDF flag can be affected

only by executing the ²HALT² or ²CLR WDT² instruction

or during a system power-up.

If the stack is full, any other interrupt request will not be

acknowledged, even if the related interrupt is enabled,

until the stack pointer is decremented. If immediate ser-

vice is desired, the stack must be prevented from be-

coming full.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register or status register

(STATUS) are altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents should be saved in advance.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

On entering the interrupt sequence or executing the

subroutine call, the status register will not be automati-

cally pushed onto the stack.

If the contents of the status are important and if the sub-

routine can corrupt the status register, precautions must

be taken to save it .

External interrupt is triggered by a high to low transition

of the INT/TMR1 pin and the interrupt request flag EIF

will be set. When the external interrupt is enabled, the

stack is not full and the external interrupt is active, a sub-

routine call to location 04H will occur. The interrupt re-

quest flag EIF and EMI bits will be cleared to disable

other interrupts.

Interrupt

The telephone controller provides an external interrupt,

internal timer/event counter interrupt, an internal real

time clock interrupt and internal dialer I/O interrupt. The

Interrupt Control Registers 0 and Interrupt Control Reg-

ister 1 both contains the interrupt control bits that set the

enable/disable and the interrupt request flags.

The Timer/Event Counter 0 interrupt is generated by a

timeout overflow and the interrupt request flag T0F will

be set. When the Timer/Event Counter 0 interrupt is en-

abled, the stack is not full and the T0F bit is set, a sub-

routine call to location 08H will occur. The interrupt

request flag T0F and EMI bits will be cleared to disable

further interrupts.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by hardware clearing the EMI

bit). This scheme may prevent any further interrupt nest-

ing. Other interrupt requests may occur during this inter-

val but only the interrupt request flag is recorded. If a

certain interrupt requires servicing within the service

routine, the EMI bit and the corresponding bit of the

INTC0 (INTC1) may be set to allow interrupt nesting.

The Timer/Event Counter 1 interrupt is generated by a

timeout overflow and the interrupt request flag T1F will

be set. When the Timer/Event Counter 1 interrupt is en-

abled, the stack is not full and the T1F bit is set, a sub-

Register

Bits

0

Label

EMI

EEI

R/W

RW

RO

Function

Controls the master (global) interrupt (1=enabled; 0=disabled)

Controls the external interrupt (1=enabled; 0=disabled)

Controls the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)

Controls the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)

External interrupt request flag (1=active; 0=inactive)

Timer/Event Counter 0 request flag (1=active; 0=inactive)

Timer/Event Counter 1 request flag (1=active; 0=inactive)

Unused bit, read as ²0²

1

2

ET0I

ET1I

EIF

3

INTC0

(0BH)

4

5

T0F

T1F

¾

6

7

0

RW

RO

Reserved, inhibit using

¾

1

ERTCI

EDRI

¾

Control the real time clock interrupt (1=enable; 0=disable)

Control the dialer I/O interrupt (1=enable; 0=disable)

Unused bit, read as ²0²

2

3

INTC1

(1EH)

4

RW

RO

Reserved, inhibit using

¾

5

RTCF

DRF

¾

Internal real time clock interrupt request flag (1=active; 0=inactive)

Internal dialer I/O interrupt request flag (1=active: 0=inactive)

Unused bit, read as ²0²

6

7

Rev. 1.20

14

May 26, 2004

HT95LXXX

routine call to location 0CH will occur. The interrupt

request flag T1F and EMI bits will be cleared to disable

further interrupts.

It is recommended that a program should not use the

²CALL subroutine² within the interrupt subroutine. Inter-

rupts often occur in an unpredictable manner or need to

be serviced immediately in some applications. If only

one stack is left and enabling the interrupt is not well

controlled, the original control sequence will be dam-

aged once the ²CALL² operates in the interrupt subrou-

tine.

The real time clock interrupt is generated by a 1Hz RTC

generator. When the RTC time-out occurs, the interrupt

request flag RTCF will be set. When the RTC interrupt is

enabled, the stack is not full and the RTCF is set, a sub-

routine call to location 14H will occur. The interrupt re-

quest flag RTCF and EMI bits will be cleared to disable

other interrupts.

Oscillator Configuration

There are two oscillator circuits in the controller, the ex-

ternal 32768Hz crystal oscillator and internal WDT

OSC.

The dialer I/O interrupt is triggered by any edge transi-

tion onto HKS pin or a falling edge transition onto HDI

pin or a rising edge transition onto HFI pin, the interrupt

request flag DRF will be set. When the dialer I/O inter-

rupt is enabled, the stack is not full and the DRF is set, a

subroutine call to location 18H will occur. The interrupt

request flag DRF and EMI bits will be cleared to disable

other interrupts.

The 32768Hz crystal oscillator and frequency-up con-

version circuit (32768Hz to 3.58MHz) are designed for

dual system clock source. It is necessary for frequency

conversion circuit to add external RC components to

make up the low pass filter that stabilize the output fre-

quency 3.58MHz (see the oscillator circuit).

Note: 1. If the dialer status is on-hook and hold-line,

the falling edge transition onto HDI pin will not

generate the dialer I/O interrupt.

The WDT OSC is a free running on-chip RC oscillator,

and no external components are required. Even if the

system enters the Idle mode (the system clock is

stopped), the WDT OSC still works within a period of

78ms normally. When the WDT is disabled or the WDT

source is not this RC oscillator, the WDT OSC will be

disabled.

2. The HDI input is supported for HT95L400/40P,

HT95L300/30P, HT95L200/20P,

HT95L100/10P.

3. The dialer I/O interrupt will be disabled when

the operation mode is in Idle mode.

During the execution of an interrupt subroutine, other in-

terrupt acknowledge signals are held until the RETI in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, ²RET² or ²RETI²

may be invoked. RETI will set the EMI bit to enable an

interrupt service, but RET will not.

X

1

X

2

1

5

k

X

C

3

n

F

5

0

n

F

System Oscillator Circuit

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Watchdog Timer - WDT

The WDT clock source is implemented by a WDT OSC

or external 32768Hz or an instruction clock (system

clock divided by 4), determined by the mask option. This

timer is designed to prevent a software malfunction or

sequence from jumping to an unknown location with un-

predictable results. The Watchdog Timer can be dis-

abled by mask option. If the Watchdog Timer is disabled,

all the executions related to the WDT result in no opera-

tion.

Interrupt Source

External interrupt

Priority Vector

1

2

3

4

5

04H

08H

0CH

14H

18H

Timer/Event Counter 0 interrupt

Timer/Event Counter 1 interrupt

Real time clock interrupt

Dialer I/O interrupt

If the device operates in a noisy environment, using the

on-chip WDT OSC or 32768Hz crystal oscillator is

strongly recommended.

Priority of the Interrupt

EMI, EEI, ET0I, ET1I, ERTCI and EDRI are used to con-

trol the enabling/disabling of interrupts. These bits pre-

vent the requested interrupt from being serviced. Once

the interrupt request flags (EIF, T0F, T1F, RTCF, DRF)

are set by hardware or software, they will remain in the

INTC0 or INTC1 registers until the interrupts are ser-

viced or cleared by a software instruction.

When the WDT clock source is selected, it will be first di-

vided by 512 (9-stage) to get the nominal time-out pe-

riod. By invoking the WDT prescaler, longer time-out

periods can be realized. Writing data to WS2, WS1,

WS0 can give different time-out periods.

Rev. 1.20

15

May 26, 2004

HT95LXXX

The WDT OSC period is 78ms. This time-out period may

vary with temperature, VDD and process variations. The

WDT OSC always works for any operation mode.

²CLR WDT1² and ²CLR WDT2² are chosen (i.e. Two

clear instructions), these two instructions must be exe-

cuted to clear the WDT; otherwise, the WDT may reset

the chip as a result of time-out.

If the instruction clock is selected as the WDT clock

source, the WDT operates in the same manner except in

the Sleep mode or Idle mode. In these two modes, the

WDT stops counting and lose its protecting purpose. In

this situation the logic can only be re-started by external

logic.

Controller Operation Mode

Holtek¢s telephone controllers support two system clock

and four operation modes. The system clock could be

32768Hz or 3.58MHz and operation mode could be Nor-

mal, Green, Sleep or Idle mode. These are all selected

by the software.

If the WDT clock source is the 32768Hz, the WDT also

operates in the same manner except in the Idle mode.

When in the Idle mode, the 32768Hz stops, the WDT

stops counting and lose its protecting purpose. In this

situation the logic can only be re-started by external

logic.

The following conditions will force the operation mode to

change to Green mode:

·

Any reset condition from any operation mode

Any interrupt from Sleep mode or Idle mode

Port A wake-up from Sleep mode or Idle mode

The high nibble and bit3 of the WDTS are reserved for

user defined flags, which can be used to indicate some

specified status.

How to change the Operation Mode

·

Normal mode to Green mode:

The WDT time-out under Normal mode or Green mode

will initialize ²chip reset² and set the status bit ²TO². But

in the Sleep mode or Idle mode, the time-out will initial-

ize a ²warm reset² and only the program counter and

stack pointer are reset to 0. To clear the WDT contents

(including the WDT prescaler), three methods are

adopted; external reset (a low level to RES pin), soft-

ware instruction and a ²HALT² instruction.

Clear MODE1 to 0, then operation mode is changed to

Green mode but the UPEN status is not changed.

However, UPEN can be cleared by software.

·

Normal mode or Green mode to Sleep mode:

Step 1: Clear MODE0 to 0

Step 2: Clear MODE1 to 0

Step 3: Clear UPEN to 0

Step 4: Execute HALT instruction

After Step 4, operation mode is changed to Sleep

mode.

The software instruction include ²CLR WDT² and the

other set ²CLR WDT1² and ²CLR WDT2². Of these two

types of instruction, only one can be active depending

on the mask option ²WDT instr². If the ²CLR WDT² is se-

lected (i.e. One clear instruction), any execution of the

CLR WDT instruction will clear the WDT. In the case that

·

Normal mode or Green mode to Idle mode:

Step 1: Set MODE0 to 1

Step 2: Clear MODE1 to 0

Step 3: Clear UPEN to 0

Step 4: Execute HALT instruction

After Step 4, operation mode is changed to Idle mode.

3

2

7

6

8

H

z

W

D

T

O

S

C

W

D

T

P

r

e

s

c

a

l

e

r

M

a

s

k

Green mode to Normal mode:

Step 1: Set UPEN to 1

O

p

t

i

o

n

9

-

b

i

t

C

o

u

n

t

e

r

7

-

b

i

t

C

o

u

n

t

e

r

S

y

s

t

e

m

C

l

o

c

k

/

4

S

e

l

e

c

t

Step 2: Software delay 20ms

Step 3: Set MODE1 to 1

8

-

t

o

-

1

M

U

X

W

S

0

~

W

S

2

After Step 3, operation mode is changed to Normal

mode.

W

D

T

i

m

e

-

o

u

t

Watchdog Timer

Register

Label

Bits

R/W

Function

Watchdog Timer division ratio selection bits

Bit 2, 1, 0=000, Division ratio=1:1

Bit 2, 1, 0=001, Division ratio=1:2

Bit 2, 1, 0=010, Division ratio=1:4

WS0

WS1

WS2

0

1

2

RW Bit 2, 1, 0=011, Division ratio=1:8

Bit 2, 1, 0=100, Division ratio=1:16

Bit 2, 1, 0=101, Division ratio=1:32

Bit 2, 1, 0=110, Division ratio=1:64

Bit 2, 1, 0=111, Division ratio=1:128

WDTS

(09H)

7~3

RW Unused bit. These bits are read/write-able.

¾

Rev. 1.20

16

May 26, 2004

HT95LXXX

Register

Label

Bits

R/W

Function

4~0

RO

¾

Unused bit, read as ²0²

1: Enable frequency up conversion function to generate 3.58MHz

0: Disable frequency up conversion function to generate 3.58MHz

UPEN

MODE0

MODE1

5

6

7

RW

1: Disable 32768Hz oscillator while the HALT instruction is executed

MODE

(26H)

(Idle mode)

0: Enable 32768Hz oscillator while the HALT instruction is executed

(Sleep mode)

1: Select 3.58MHz as CPU system clock

0: Select 32768Hz as CPU system clock

Operation Mode Description

HALT

MODE1

Operation

Mode

System

MODE0

UPEN

32768Hz

3.58MHz

Instruction

Clock

3.58MHz

32768Hz

HALT

Not execute

Be executed

1

0

X

0

1

0

Normal

Green

Sleep

Idle

ON

OFF

ON

OFF

HALT

Note: ²X² means don¢t care

·

Sleep mode or Idle mode to Green mode:

resume to Green mode. In other words, a dummy period

is inserted after a wake-up. If the wake-up results from

an interrupt acknowledge signal, the actual interrupt

subroutine execution will be delayed by one or more cy-

cles. If the wake-up results in the next instruction execu-

tion, this will be executed immediately after the dummy

period is finished.

Method 1: Any reset condition occurred

Method 2: Any interrupt is active

Method 3: Port A wake-up

Note:The Timer 0, Timer 1, RTC and dialer I/O inter-

rupt function will not work at the Idle mode be-

cause the 32768Hz crystal is stopped.

The reset conditions include power on reset, external re-

set, WDT time-out reset. By examining the processor

status flag, PDF and TO, the program can distinguish

between different ²reset conditions². Refer to the Reset

function for detailed description.

To minimize power consumption, all the I/O pins should

be carefully managed before entering the Sleep mode

or Idle mode.

The Sleep mode or Idle mode is initialized by the HALT

instruction and results in the following.

The port A wake-up and interrupt can be considered as

a continuation of normal execution. Each bit in port A

can be independently selected to wake-up the device by

mask option. Awakening from Port A stimulus, the pro-

gram will resume execution of the next instruction.

·

The system clock will be turned off.

The WDT function will be disabled if the WDT clock

source is the instruction clock.

·

The WDT function will be disabled if the WDT clock

source is the 32768Hz in Idle mode.

Any valid interrupts from Sleep mode or Idle mode may

cause two sequences. One is if the related interrupt is

disabled or the interrupt is enabled but the stack is full,

the program will resume execution at the next instruc-

tion. The other is if the interrupt is enabled and the stack

is not full, the regular interrupt response takes place. It is

necessary to mention that if an interrupt request flag is

set to ²1² before entering the Sleep mode or Idle mode,

the wake-up function of the related interrupt will be dis-

abled.

The WDT will still function if the WDT clock source is

the WDT OSC.

If the WDT function is still enabled, the WDT counter

and WDT prescaler will be cleared and recounted

again.

·

The contents of the on chip RAM and registers remain

unchanged.

·

All the I/O ports maintain their original status.

Once a Sleep mode or Idle mode wake-up event occurs,

it will take SST delay time (1024 system clock period) to

The flag PDF is set and the flag TO is cleared by hard-

ware.

Rev. 1.20

17

May 26, 2004

HT95LXXX

Reset

V

D

There are three ways in which a reset can occur.

R

E

S

t

S S T

·

Power on reset.

S

T

i

m

e

-

o

u

t

A low pulse onto RES pin.

WDT time-out.

C

h

i

p

R

e

s

e

t

After these reset conditions, the Program Counter and

Stack Pointer will be cleared to 0.

Reset Timing Chart

By examining the processor status flags PDF and TO,

the software program can distinguish between the dif-

ferent ²chip resets².

To guarantee that the system oscillator is started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses when the sys-

tem is reset or awakes from the Sleep or Idle operation

mode.

TO PDF

Reset Condition

Power on reset

0

u

0

u

V

D

External reset during Normal mode or

Green mode

External reset during Sleep mode or Idle

mode

1

0

k

0

1

u

1

R

E

S

WDT time-out during Normal mode or

Green mode

m

0 . 1 F

WDT time-out during Sleep mode or Idle

mode

Reset Circuit

Note: ²u² means ²unchanged²

The functional units chip reset status are shown below:

H

A

L

T

W

a

r

m

R

e

s

e

t

Program Counter

Interrupt

000H

W

D

T

t

i

m

e

-

o

u

t

W

D

T

Disabled

Cleared

Prescaler

C

o

l

d

R

e

s

e

t

Cleared

E

x

t

e

r

n

a

l

R

E

S

After a master reset,

WDT begins counting.

(If WDT function is enabled

by mask option)

S

T

1

0

-

b

i

t

R

i

p

l

e

S

Y

S

C

L

K

WDT

C

o

u

n

t

e

r

S

y

s

t

e

m

R

e

s

e

t

Timer/Event Counter 0/1 Off

Reset Configuration

Input/output Port

Stack Pointer

Input mode

Points to the top of the stack

When the reset conditions occurred, some registers may be changed or unchanged. (HT95L400/40P)

Reset Conditions

Register

Addr.

RES Pin

(Sleep/Idle)

WDT

(Sleep/Idle)

Power On

RES Pin

WDT

IAR0

MP0

IAR1

MP1

BP

00H

01H

02H

03H

04H

05H

06H

07H

08H

xxxx xxxx

---0 0000

xxxx xxxx

0000H

uuuu uuuu

---0 0000

uuuu uuuu

0000H

uuuu uuuu

---0 0000

uuuu uuuu

0000H

uuuu uuuu

---0 0000

uuuu uuuu

0000H

uuuu uuuu

---u uuuu

uuuu uuuu

0000H

ACC

PCL

TBLP

TBLH

xxxx xxxx

uuuu uuuu

Rev. 1.20

18

May 26, 2004

HT95LXXX

Reset Conditions

Register

Addr.

RES Pin

(Sleep/Idle)

WDT

(Sleep/Idle)

Power On

RES Pin

WDT

WDTS

STATUS

INTC0

TMR0H

TMR0L

TMR0C

TMR1H

TMR1L

TMR1C

PA

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

18H

19H

1AH

1BH

1EH

1FH

20H

21H

22H

24H

26H

28H

2DH

2EH

2FH

34H

35H

36H

37H

0000 0111

--00 xxxx

-000 0000

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

1111 1111

111x xxxx

1111 1111

---- 1111

-000 -000

--xx xxx

0000 0111

--uu uuuu

-000 0000

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

1111 1111

111x xxxx

1111 1111

---- 1111

-000 -000

--uu uuuu

---- -0-1

0000 0111

--01 uuuu

-000 0000

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

1111 1111

111x xxxx

1111 1111

---- 1111

-000 -000

--uu uuuu

---- -0-1

0000 0111

--1u uuuu

-000 0000

xxxx xxxx

00-0 1---

xxxx xxxx

00-0 1---

1111 1111

111x xxxx

1111 1111

---- 1111

-000 -000

--uu uuuu

---- -0-1

uuuu uuuu

--11 uuuu

-uuu uuuu

uuuu uuuu

uu-u u---

uuuu uuuu

uu-u u---

uuuu uuuu

---- uuuu

-uuu -uuu

--uu uuuu

---- -u-u

PAC

PB

PBC

DialerIO

PD

PDC

PE

PEC

INTC1

TBHP

DTMFC

DTMFD

LINE

---- -0-1

0000 0000

0--- ----

0000 0000

u--- ----

0000 0000

u--- ----

0000 0000

u--- ----

uuuu uuuu

u--- ----

RTCC

MODE

LCDIO

LCDC

PFDC

PFDD

PF

0-0- ----

u-u- ----

000- ----

00u- ----

000- ----

uuu- ----

0000 -000

0000 ----

0000 0000

1111 1111

---- 1111

x

uuuu -uuu

0000 ----

0000 0000

1111 1111

---- 1111

u

uuuu -uuu

0000 ----

0000 0000

1111 1111

---- 1111

u

uuuu -uuu

0000 ----

0000 0000

1111 1111

---- 1111

u

uuuu -uuu

uuuu ----

uuuu uuuu

---- uuuu

u

PFC

PG

PGC

RAM(Data&LCD)

Note:

²u² means ²unchanged²

²x² means ²unknown²

²-² means ²unused²

Rev. 1.20

19

May 26, 2004

HT95LXXX

Timer/Event Counter

of the low byte buffer into the Timer/Event Counter 0

preload register (16-bit). The Timer/Event Counter 0

preload register is changed by writing TMR0H opera-

tions. Writing TMR0L will keep the Timer/Event Counter

0 preload register unchanged.

Two timer/event counters (TMR0, TMR1) are imple-

mented in the telephone controller series. The

Timer/Event Counter 0 and Timer/Event Counter 1 con-

tain 16-bits programmable count-up counter and the

clock may come from an external or internal source. For

TMR0, the internal source is the instruction clock (sys-

tem clock/4). For TMR1, the internal source is 32768Hz.

Reading TMR0H latches the TMR0L into the low byte

buffer to avoid a false timing problem. Reading TMR0L

returns the contents of the low byte buffer. In other

words, the low byte of the Timer/Event Counter 0 can

not be read directly. It must read the TMR0H first to

make the low byte contents of Timer/Event Counter 0 be

latched into the buffer.

Using the 32768Hz clock or instruction clock, there is

only one reference time-base. The external clock input

allows the user to count external events, measure time

intervals or pulse width, or generate an accurate time

base.

There are 3 registers related to the Timer/Event Counter

1; TMR1H, TMR1L and TMR1C. The Timer/Event

Counter 1 operates in the same manner as the

Timer/Event Counter 0.

There are 3 registers related to the Timer/Event Counter

0; TMR0H, TMR0L and TMR0C. Writing TMR0L only

writes the data into a low byte buffer, but writing TMR0H

simultaneously writes the data along with the contents

T

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5

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P

.

Timer/Event Counter 0/1

Register

Label

Bits R/W

Function

0~2

RO

¾

Unused bit, read as ²0²

To define the TMR0/TMR1 active edge of timer

For event count or Timer mode

T0E/T1E

3

RW (0=active on low to high; 1=active on high to low)

For pulse width measurement mode

TMR0C

(0EH)

/

(0=measures low pulse width; 1=measures high pulse width)

T0ON/T1ON

4

5

RW To enable/disable timer counting (0=disabled; 1=enabled)

RO

TMR1C

(11H)

¾

Unused bit, read as ²0²

To define the operating mode

Bit 7, 6=01, Event count mode (external clock)

Bit 7, 6=10, Timer mode

T0M0/T1M0

T0M1/T1M1

6

7

RW

Bit 7, 6=11, Pulse width measurement mode

Bit 7, 6=00, Unused

Only Timer mode is available for HT95L000/00P.

Register

Bits

0~7

R/W

Function

TMR0H (0CH)

TMR0L (0DH)

TMR1H (0FH)

TMR1L (10H)

RW

Timer/Event Counter 0 higher-order byte register

Timer/Event Counter 0 lower-order byte register

Timer/Event Counter 1 higher-order byte register

Timer/Event Counter 1 lower-order byte register

Rev. 1.20

20

May 26, 2004

HT95LXXX

The TMR0C is the Timer/Event Counter 0 control regis-

ter, which defines the Timer/Event Counter 0 options.

The Timer/Event Counter 1 has the same options as the

Timer/Event Counter 0 and is defined by TMR1C. The

timer/event counter control registers define the operat-

ing mode, counting enable or disable and active edge.

In the case of timer/event counter off condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turned on, data written to the

timer/event counter is reserved only in the timer/event

counter preload register. The timer/event counter will go

on operating until an overflow occurs.

The T0M0/T1M0, T0M1/T1M1 bits define the operating

mode. The event count mode is used to count external

events, which means the clock source comes from an

external (TMR0 or INT/TMR1) pin. The timer mode func-

tions as a normal timer with the clock source coming

from instruction clock (TMR0) or 32768Hz (TMR1). The

pulse width measurement mode can be used to count

the high or low level duration of the external signal

(TMR0 or INT/TMR1). The counting is based on the

32768Hz clock for TMR1 or instruction clock for TMR0.

Input/Output Ports

There is a maximum of 40 bidirectional input/output

lines in the HT95LXXX family MCU, labeled as PA, PB,

PD, PE, PF and PG. All of these I/O ports can be used

for input and output operations. For input operation,

these ports are non-latching, that is, the inputs must be

ready at the T2 rising edge of instruction “MOV A,[m]”

(m=12H, 14H, 18H, 1AH, 34H or 36H). For output oper-

ation, all the data is latched and remains unchanged un-

til the output latch is rewritten.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFFFH. If an over-

flow occurs, the counter is reloaded from the timer/event

counter preload register and generates the correspond-

ing interrupt request flag (T0F/T1F) at the same time.

Note that the event count mode is not available for

HT95L000/00P.

Each I/O line has its own control register (PAC, PBC,

PDC, PEC, PFC, PGC) to control the input/output con-

figuration. With this control register, CMOS output or

Schmitt trigger input can be reconfigured dynamically

under software control. To make one I/O line to function

as an input line, the corresponding latch of the control

register must be written with a ²1². The pull-high resis-

tance shows itself automatically if the pull-high option is

selected. The input source also depends on the control

register. If the control register bit is ²1², the input will

read the pad state. If the control register bit is ²0², the

contents of the latches will move to the internal bus. The

latter is possible in the ²read-modify-write² instruction.

For output function, CMOS is the only configuration.

Each bit of these input/output latches can be set or

cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

18H, 1AH, 34H or 36H) instructions.

In pulse width measurement mode with the

T0ON/T1ON and T0E/T1E bits equal to 1, once the

TMR0/TMR1 pin has received a transient from low to

high (or high to low; if the T0E/T1E bit is 0) it will start

counting until the TMR0/TMR1 pin returns to the original

level and resets the T0ON/T1ON. The measured result

will remain in the timer/event counter even if the acti-

vated transient occurs again. In other words, only 1 cy-

cle measurement can be done. Until setting the

T0ON/T1ON, the cycle measurement will function again

as long as it receives further transient pulse. Note that,

in this operating mode, the timer/event counter starts

counting not according to the logic level but according to

the transient edges. In the case of counter overflows,

the counter is reloaded from the timer/event counter

preload register and continue to measure the width and

issues the interrupt request just like the other two

modes. Note that this mode is not available for

HT95L000/00P.

Some instructions first input data and then follow the

output operations. For example, ²SET [m].i², ²CLR

[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device. They are selected by mask option per bit.

To enable the counting operation, the timer on bit

(T0ON/T1ON) should be set to 1. In the pulse width

measurement mode, the T0ON/T1ON will be cleared

automatically after the measurement cycle is com-

pleted. But in the other two modes the T0ON/T1ON can

only be reset by instruction. The overflow of the

timer/event counter is one of the wake-up sources. No

matter what the operation mode is, writing a 0 to

ET0I/ET1I can disable the corresponding interrupt ser-

vice.

There is a pull-high option available for all I/O lines.

Once the pull-high option of an I/O line is selected, the

I/O lines have pull-high resistor. Otherwise, the pull-high

resistor is absent. It should be noted that a non-pull-high

I/O line operating in input mode may cause a floating

state.

Rev. 1.20

21

May 26, 2004

HT95LXXX

I/O port pull-high, wake-up function are selected by mask option

Input

Supported for HT95LXXX

I/O Port

Output

Pull-high Resistor Wake-up Function 400/40P 300/30P 200/20P 100/10P 000/00P

PA7~PA0 CMOS

PB7~PB0 CMOS

Selected per bit

Ö

*

¾

PD7~PD0 CMOS Selected per nibble

PE3~PE0 CMOS Selected per nibble

Ö

¾

Ö

¾

Ö

PF7~PF0

CMOS Selected per nibble

¾

PG3~PG0 CMOS Selected per nibble

Note:

²¾² means unavailable

V

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0

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7

(

P

A

o

n

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y

)

Input/Output Ports

Some input/output pins can be optioned to LCD outputs by software.

Register Bits R/W Label Value

400/40P

300/30P

200/20P

100/10P

000/00P

0

SEG47~SEG44

SEG19~SEG16 SEG15~SEG12

¾

5

7

6

1

RW SPE0

RW SPD1

RW SPD0

RW VBIAS

1

0

1

0

1

0

1

PE3~PE0

SEG43~SEG40

PD7~PD4

PE3~PE0

¾

LCDIO

(28H)

SEG39~SEG36

PD3~PD0

COM7~COM0

PD7~PD0

LCDC

(2DH)

COM7~COM0 are unavailable

When the PD0~PD7 or the PE0~PE3 are not selected, the I/O port control register PDC(19H), PEC(1BH) could be

readable/writable and be used as a general user RAM, but this function is not available for register PD(18H) and PE

(1AH).

Rev. 1.20

22

May 26, 2004

HT95LXXX

DTMF Generator

The DTMF (Dual Tone Multiple-Frequency) signal generator is implemented in the telephone controller. It can generate

16 dual tones and 8 single tones from the DTMF pin. This generator also supports power down, tone on/off function.

The DTMF generator clock source is 3.58MHz, before using this function, the system operation mode must be at Nor-

mal mode.

The power down mode (D_PWDN=1) will terminate all the DTMF generator function, however, the registers DTMFC

and DTMFD are accessible at this power down mode. The duration of DTMF output should be handled by the software.

DTMFD register value could be changed as desired, the DTMF pin will output the new dual-tone simultaneously.

Register

Label

D_PWDN

¾

Bits

R/W

Function

DTMF generator power down

0

RW 1: DTMF generator is at power down mode.

0: DTMF generator is at operation mode.

1

RO

Unused bit, read as ²0²

Tone output enable

TONE

2

RW 1: DTMF signal output is enabled.

0: DTMF signal output is disabled.

DTMFC

(20H)

3

4

5

6

7

RW Reserved, inhibit using.

¾

RO

RW Reserved, inhibit using.

RO

Unused bit, read as ²0²

TC4~TC1 3~0

TR4~TR1 7~4

RW To set high group frequency

RW To set low group frequency

DTMFD

(21H)

Note: Bit3, 4, 6 of DTMFC are reserved, always keep the initial value.

The DTMFpin output is controlled by the combination of the D_PWDN, TONE, TR~TC value.

Control Register Bits

DTMF Pin Output Status

D_PWDN

TONE

TR4~TR1/TC4~TC1

1

0

x

0

1

x

0

x

1/2 VDD

0

Any valid value

16 dual tones or 8 signal tones, bias with 1/2 VDD

D

_

P

D

W

N

=

1

D

_

P

D

W

N

=

0

1

/

2

V

D

T

A

O

N

E

=

1

T

O

N

E

=

0

T

O

N

E

=

0

T

O

N

E

=

0

T

O

N

E

=

1

T

O

N

E

=

1

l

t

h

e

t

i

m

i

n

g

o

f

t

h

e

T

O

N

E

=

1

a

n

d

T

O

N

E

=

0

a

r

e

d

e

t

e

r

m

i

n

e

d

b

y

s

o

f

t

w

a

r

e

DTMF Output

Tone frequency

Output Frequency (Hz)

% Error

Specified

697

Actual

699

+0.29%

-0.52%

-0.59%

+0.74%

+0.50%

-0.30%

-0.34%

770

766

852

847

941

948

1209

1336

1477

1215

1332

1472

% Error does not contain the crystal frequency shift

Rev. 1.20

23

May 26, 2004

HT95LXXX

DTMF frequency selection table: register DTMFD[21H]

Low Group

High Group

DTMF Output

DTMF

Code

TR4

0

TR3

0

TR2

0

TR1

1

TC4

0

TC3

0

TC2

TC1

1

Low

697

770

852

941

High

1209

1336

1477

1633

1209

1336

1477

1633

1209

1336

1477

1633

1209

1336

1477

1633

0

1

0

1

0

1

0

1

0

1

2

3

A

4

5

6

B

7

8

9

C

*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

#

D

1

0

1

0

1

0

1

0

Single tone for testing only

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

697

770

852

941

1209

1336

1477

1633

Writing other values to TR4~TR1, TC4~TC1 may generate an unpredictable tone.

Rev. 1.20

24

May 26, 2004

HT95LXXX

Dialer I/O Function

A special dialer I/O circuit is built into the telephone controller for dialing application. These specially designed I/O cells

allows the controller to work under a low voltage condition that usually happens when the subscriber¢s loop is long.

Dialer I/O pin function:

Name

I/O

Description

XMUTE pin output is controlled by software. This is an NMOS open drain structure

XMUTE

NMOS Output pulled to VSS during dialing signal transmission. Otherwise, it is an open circuit.

XMUTE is used to mute the speech circuit when transmitting the dialer signal.

DNPO pin is an NMOS output, usually by means of software to make/break the line.

DNPO

PO

NMOS Output

This pin is only controlled by software.

This pin is controlled by the HKS, HFI and HDI pins.

CMOS Output When PO pin is high, the telephone line is make.

When PO pin is low, the telephone line is break.

This pin controls the PO pin directly.

This pin is used to monitor the status of the hook-switch and its combination with

HFI/HDI can control the PO pin output to make or break the line.

Schmitt Trigger

HKS

A rising edge to HKS pin will cause the dialer I/O to be on-hook status and generate

Input

an interrupt, its vector is 18H.

A falling edge to HKS pin will cause the dialer I/O to be off-hook status and clear HFO

and HDO flags to 0. This falling edge will also generate an interrupt, its vector is 18H.

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P

This pin is controlled directly by HDI, HKS and HFI pin.

CMOS Output

HDO

HDI

When HDO pin is high, the hold-line function is enabled and PO outputs a high signal

to make the line.

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P

A low pulse to HDI pin (hold-line function request) will clear HFO to 0 and toggle HDO

Schmitt Trigger and generates an interrupt, its vector is 18H.

Input

This pin controls the HFO and HDO pins directly.

This pin is functional only when the line is made, that is, off-hook or hand-free

(PO output high signal).

This pin is controlled directly by HFI, HDI and HKS pins.

HFO

HFI

CMOS Output When HFO pin is high, the hand-free function is enabled and PO outputs a high

signal to make the line.

A high pulse to HFI pin (hand-free function request) will clear HDO to 0 and toggle

Schmitt Trigger

HFO and generates an interrupt, its vector is 18H.

Input

This pin controls the PO, HFO and HDO pins directly.

The following are the recommended circuit for HFI and HDI pins.

V

D

V

D

1

0

k

I

n

t

e

r

n

a

l

P

u

l

-

h

i

g

h

2

0

k

H

F

I

P

i

n

H

D

I

P

i

n

0

.

1

m

F

I

n

t

e

r

n

a

l

P

u

l

-

l

o

w

2

0

k

1

0

k

W

m

0 . 1 F

Rev. 1.20

25

May 26, 2004

HT95LXXX

Phone controller also supports the dialer I/O flag to monitor the dialer status.

Register Label Bits R/W Function

1: The HFI pin level is 1.

0: The HFI pin level is 0.

HFI

0

1

RO

1: The HFO pin level is 1.

0: The HFO pin level is 0.

HFO

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P

HDI

2

3

RO 1: The HDI pin level is 1.

0: The HDI pin level is 0.

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P

RO 1: The HDO pin level is 1.

HDO

DIALERIO

(16H)

0: The HDO pin level is 0.

1: The HKS pin level is 1.

RO

HKS

SPO

4

5

6

7

0: The HKS pin level is 0.

1: The PO pin is controlled by the combination of the HKS, HFI and HDI pin.

RW

0: The PO pin level is set to 0 by software.

1: The DNPO pin level is set to floating by software.

RW

SDNPO

XMUTE

0: The DNPO pin level is set to 0 by software.

1: The XMUTE pin is set to floating by software.

RW

0: The XMUTE pin is set to 0 by software.

The SPO flag is special designed to control the PO. When the flag SPO is set to 1, the PO pin is controlled by the combi-

nation of the HKS pin, HFI pin and HDI pin. The PO pin will always be 0 if the flag SPO=0.

The relation between the Dialer I/O function (SPO=1)

Dialer I/O Pin (Flag) Status

Result

Telephone Line

Dialer Function

On-hook

HKS

HFO

HDO

PO

0

DNPO

floating

1

0

1

0

1

0

1

0

1

break

make

On-hook & Hand-free

On-hook & Hold-line

Off-hook

1

Off-hook & Hand-free

Off-hook & Hold-line

1

The following describes the dialer I/O function status machine figure (Available on Normal mode, Green mode or Sleep

mode):

Off-hook: A falling edge to HKS pin

On-hook: A rising edge to HKS pin

H

D

I

HFI: A high pulse to HFI pin (Hand-free request is generated.)

HDI: A low pulse to HDI pin (Hold-line request is generated.)

O

n

-

h

o

k

H

F

I

O

f

-

h

o

k

O

f

-

h

o

k

O

n

-

h

o

k

O

n

-

h

o

k

H

a

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d

-

f

r

e

H

a

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d

-

f

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O

f

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o

k

O

n

-

h

o

k

H

F

I

H

D

I

H

F

I

H

D

I

H

F

I

H

D

I

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f

-

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k

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f

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D

I

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h

o

k

O

n

-

h

o

k

H

o

l

d

-

l

i

n

e

H

o

l

d

-

l

i

n

e

Note: 1. If the dialer status is on-hook and hold-line, the falling edge transition onto HDI pin will not generate the dialer

I/O interrupt.

2. Dialer I/O function is not available in Idle mode

Rev. 1.20

26

May 26, 2004

HT95LXXX

Line Control Function (Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P)

Register

Label

Bits

R/W

Function

6~0

RO

¾

Unused bit, read as ²0²

LINE

1: Enable the line control function

0: Disable the line control function

(22H)

LINEC

7

RW

The line control function is enabled by flag LINEC

Conditions

Source to Enable

Line Control Function

LINEC

Operation Mode

1

Normal or Green mode

RTC time out interrupt

Port A wake-up

1

Sleep mode

Idle mode

RTC time out interrupt

Port A wake-up

When the line control source is activated, the PO pin will be set to high signal. Clearing LINEC to 0 will terminate the line

control function and drive PO pin outputs low signal.

R

T

C

I

n

t

e

r

u

p

t

L

i

n

e

C

o

n

t

r

o

l

P

O

=

1

C

i

r

c

u

i

t

P

o

r

t

A

W

a

k

e

-

u

p

F

u

n

c

t

i

o

n

L

I

N

E

C

=

1

RTC Function

Register

Label

Bits

R/W

Function

6, 4~0 RO

¾

Unused bit, read as ²0²

1: Enable RTC function

0: Disable RTC function

RTCC

(24H)

RTCEN

RTCTO

5

7

RW

1: RTC time-out occurs

0: RTC time-out not occurs

The real time clock (RTC) is used to supply a regular in-

ternal interrupt. Its time-out period is 1000ms. If the RTC

time-out occurs, the interrupt request flag RTCF and the

RTCTO flag will be set to 1. The interrupt vector for the

RTC is 14H. When the interrupt subroutine is serviced,

the interrupt request flag (RTCF) will be cleared to 0, but

the flag RTCTO remain in its original value. If the

RTCTO flag is not cleared, next RTC time-out interrupt

will occur.

V

D

E

T

1

.

1

5

V

R

e

f

e

r

e

n

c

e

V

o

l

t

a

g

e

R

1

L

B

F

G

L

B

I

N

R

2

L

B

E

N

The battery low threshold is determined by external R1

and R2 resistors.

Low Battery Detection

V_DETxR2

R1+ R2

1.15x(R1+ R2)

R2

(Supported for HT95L400/40P, HT95L300/30P,

HT95L200/20P, HT95L100/10P)

1.15=

® V_DET=

The phone controller provides a circuit that detects the

LBIN pin voltage level. To enable this detection func-

tion, the LBEN should be written as 1. Once this function

is enabled, the detection circuit needs 50ms to be stable.

After that, the user could read the result from LBFG. The

low battery detect function will consume power. For

power saving, write 0 to LBEN if the low battery detec-

tion function is unnecessary.

If we want to detect V_DET=2.4V

1.15x(R1+ R2)

then 2.4V=

® R1=1.087R2

R2

Rev. 1.20

27

May 26, 2004

HT95LXXX

LCD Driver

The LCD driver can directly drive an LCD panel with 1/8 duty and 1/4 bias or with 1/16 duty and 1/5 bias, this function is

selected by the flag VBIAS. The frame of this LCD driver may select a 64Hz or 128Hz by flag FRAME.

LCD driver uses the voltage of the VLCD pin as the power source. To adjust the view angle, the programmer can select

the real LCD power by the flags VCON0 and VCON1. The flag LCDON is used to turn On/Off the LCD display. Note that

the VLCD voltage must equal or be less than VDD.

Segment/Common to I/O Selection

For the flexible purpose, some of the LCD COMMON and SEGMENT pins are shared with the input/output port.

Both of the HT95L400/40P and HT95L300/30P provide 12 pins to be selected to SEGMENT output pins or I/O pins.

HT95L200/20P provides 8 pins to be selected for COMMON output pins or I/O pins. Both of the HT95L100/10P and

HT95L000/00P provide 4 pins to be selected for SEGMENT output pins or I/O pins.

All of the HT95L400/40P, HT95L300/30P and HT95L200/20P provide the LCD COMMON output pins for 8 COMMON

or 16 COMMON. The description of the relation between segment pins, common pins and I/O pins are shown on the

below.

Register Label Bits R/W

Function

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P

LCD frame selection

FRAME

0

RW 0: LCD frame is 64Hz

1: LCD frame is 128Hz

The frame frequency is fixed to 64Hz for HT95L100/10P and HT95L000/00P

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P

LCD BIAS selection

0: select 1/16 duty and 1/5 bias, COM15~COM0 are available

1: select 1/8 duty and 1/4 bias, only COM15~COM8 are available

VBIAS

1

RW

When the 8 COM is selected

HT95L400/40P: COM7~COM0 will be optioned to unused pins

HT95L300/30P: COM7~COM0 will be optioned to unused pins

HT95L200/20P: COM7~COM0 are disabled, PD7~PD0 are available

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P

Low battery detection switch

RW

LCDC

(2DH)

LBEN

¾

2

3

4

0: disable the low battery detection

1: enable the low battery detection

RO

Unused bit, read as ²0²

Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P

Low battery detection flag

LBFG

ROS

1: LBIN pin voltage is less than 1.15V

0: LBIN pin voltage is not less than 1.15V

LCD contrast adjusting

Bit6,5=00: LCD voltage supply is 0.66´VLCD

VCON0

VCON1

5

6

RW Bit6,5=10: LCD voltage supply is 0.82´VLCD

Bit6,5=01: LCD voltage supply is 0.93´VLCD

Bit6,5=11: LCD voltage supply is 1.00´VLCD

1: Turn on the LCD display

RW

LCDON

7

0: Turn off the LCD display

Rev. 1.20

28

May 26, 2004

HT95LXXX

Register Label Bits R/W

Function

0~4 RO

¾

Unused bit, read as ²0²

Supported for HT95L400/40P, HT95L300/30P, HT95L100/10P, HT95L000/00P

Bit value is 0:

HT95L400/40P: SEG47~SEG44 output are available

HT95L300/30P: SEG47~SEG44 output are available

HT95L100/10P: SEG19~SEG16 output are available

SPE0

5

RW HT95L000/00P: SEG15~SEG12 output are available

Bit value is 1:

HT95L400/40P: PE3~PE0 output are available

HT95L300/30P: PE3~PE0 output are available

HT95L100/10P: PE3~PE0 output are available

HT95L000/00P: PE3~PE0 output are available

LCDIO

(28H)

Supported for HT95L400/40P, HT95L300/30P

RW Bit value is 0: SEG39~SEG36 output are available

Bit value is 1: PD3~PD0 output are available

SPD0

SPD1

6

7

Supported for HT95L400/40P, HT95L300/30P

RW Bit value is 0: SEG43~SEG40 output are available

Bit value is 1: PD7~PD4 output are available

LCD Display Memory

The phone controller provides an area on embedded data memory for LCD display. The LCD display memory are lo-

cated at bank 1BH and can be read and written to, only by indirect addressing mode using MP1. When data is written

into the display data area it is automatically read by the LCD driver which then generates the corresponding LCD driv-

ing signals, to turn the display On or Off, a ²1² or ²0² is written to the corresponding bit of the display memory, respec-

tively. All of the LCD display memories are with random values after the power on reset and unchanged after other reset

conditions.

COM7 to COM0 for HT95L400/40P, HT95L300/30P

Address

40H

Register Name

SEG0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

41H

SEG1

¾

6EH

6FH

SEG46

SEG47

COM15 to COM8 for HT95L400/40P, HT95L300/30P

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

Address

70H

Register Name

SEG0

Bit 2

Bit 1

Bit 0

COM15 COM14 COM13 COM12 COM11 COM10 COM9

COM8

71H

SEG1

¾

9EH

9FH

SEG46

SEG47

Note: When VBIAS bit set to 1 for 8 COM operation (48´8), the LCD RAM only map to (70H~9FH).

Rev. 1.20

29

May 26, 2004

HT95LXXX

COM7 to COM0 for HT95L200/20P

Address

40H

Register Name

SEG0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

41H

SEG1

¾

56H

SEG22

SEG23

57H

COM15 to COM8 for HT95L200/20P

Bit 7 Bit 6 Bit 5 Bit 4

Address

70H

Register Name

SEG0

Bit 3

Bit 2

Bit 1

Bit 0

COM15 COM14 COM13 COM12 COM11 COM10 COM9

COM8

71H

SEG1

¾

86H

SEG22

SEG23

87H

Note: When VBIAS bit is set to 1 for 8 COM operation (24´8), the LCD RAM only map to (70H~87H).

COM7 to COM0 for HT95L100/10P

Address

8CH

8DH

¾

Register Name

SEG0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

SEG1

¾

9EH

9FH

SEG18

SEG19

COM7 to COM0 for HT95L000/00P

Address

90H

Register Name

SEG0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

COM7

COM6

COM5

COM4

COM3

COM2

COM1

COM0

91H

SEG1

¾

9EH

9FH

SEG14

SEG15

PFD Generator (Supported for HT95L400/40P, HT95L300/30P, HT95L200/20P, HT95L100/10P)

Register

Label

Bits

R/W

Function

3~0

RO

¾

Unused bit, read as ²0²

1: Enable PFD output

PFDEN

4

RW

0: Disable PFD output, the MUSIC pin output low level.

Bit6, 5=00: Prescaler output= PFD frequency source/1

Bit6, 5=01: Prescaler output= PFD frequency source/2

Bit6, 5=10: Prescaler output= PFD frequency source/4

Bit6, 5=11: Prescaler output= PFD frequency source/8

PFDC

(2EH)

PRES0

PRES1

5

6

1: The PFD frequency source is 3.58MHz/4

0: The PFD frequency source is 32768Hz

FPFD

7

PFDD

(2FH)

7~0

RW PFD data register

¾

Rev. 1.20

30

May 26, 2004

HT95LXXX

The PFD (programmable frequency divider) is implemented in the phone controller. It is composed of two portions: a

prescaler and a general counter.

The prescaler is controlled by the register bits, PRES0 and PRES1. The general counter is programmed by an 8-bit

register PFDD.

The source for this generator can be selected from 3.58MHz/4 or 32768Hz. To enable the PFD output, write 1 to the

PFDEN bit.

The PFDD is inhibited to write while the PFD is disabled. To modify the PFDD contents, the PFD must be enabled.

When the generator is disabled, the PFDD is cleared by hardware.

P

r

e

s

c

a

l

e

r

P

F

D

3

2

7

6

8

H

z

O

u

t

p

u

t

O

u

t

p

u

t

P

r

e

s

c

a

l

e

r

P

F

D

M

U

S

I

C

3

.

5

8

M

H

z

/

4

C

l

e

a

r

P

R

E

S

1

,

P

R

E

S

0

P

F

D

E

N

P

F

D

E

N

Prescaler output

2x(N+ 1)

PFD output frequency=

, where N=the value of the PFDD

Mask Option Table

The following shows many kinds of mask options in the telephone controller. All these options should be defined in or-

der to ensure proper system functions.

Name

Mask Option

WDT source selection

RC®Select the WDT OSC to be the WDT source.

T1®Select the instruction clock to be the WDT source.

32kHz®Select the external 32768Hz to be the WDT source.

Disable®Disable WDT function.

WDT

This option defines how to clear the WDT by instruction.

One clear instruction®The ²CLR WDT² can clear the WDT.

Two clear instructions®Only when both of the ²CLR WDT1² and ²CLR WDT2² have been

executed, then WDT can be cleared.

CLRWDT

Port A wake-up selection.

Define the activity of wake-up function.

All port A have the capability to wake-up the chip from a HALT.

This wake-up function is selected per bit.

Wake-up PA

Pull-high option.

This option determines whether the pull-high resistance is viable or not.

Port A pull-high option is selected per bit.

Pull-high PA

Pull-high PB

Pull-high PD

Pull-high PE

Pull-high PF

Pull-high PG

Port B pull-high option is selected per bit.

Port D pull-high option is selected per nibble.

(Note: Port D pull-high option is selected per byte for HT95L200/20P.)

Port E pull-high option is selected per nibble.

Port F pull-high option is selected per nibble.

Port G pull-high option is selected per nibble.

Rev. 1.20

31

May 26, 2004

HT95LXXX

Application Circuits

2

M

1

0

k

O

f

-

h

o

k

T

i

p

O

n

-

h

o

k

A

9

2

1

N

4

1

4

8

1

0

k

3

0

k

R

i

n

g

2

0

k

2

.

2

k

1

m

0 F

3

k

3

.

3

k

2

0

k

1

m

F

1

0

k

1

.

5

k

W

1

5

0

k

4

7

k

A

4

2

H

a

n

d

f

r

e

2

0

k

W

m

1 F

B

1

=

a

t

e

r

y

1

0

k

m

0 . 0 2 F

´

. 5 3

2

7

0

k

4

.

5

V

S

p

e

c

h

N

e

t

w

o

r

k

V

D

5

.

1

V

1

0

k

m

0 . 1 F

m

0 . 1 F

1

m

0 0 F

V

D

0

.

1

m

F

H

F

I

P

O

H

D

O

H

D

I

V

D

H

K

S

H

F

O

D

T

M

F

X

M

U

T

E

I

/

O

M

U

S

I

C

V

D

V

L

C

D

1

0

k

R

E

S

m

0 . 1 F

H

T

9

5

L

X

V

D

L

B

I

N

S

U

N

M

O

N

T

U

E

W

E

D

T

H

R

F

R

I

S

A

T

A

B

R

M

E

M

O

R

Y

S

H

T

O

R

E

A

M

C

O

M

O

N

D

I

A

L

I

N

G

O

L

D

P

M

S

E

G

M

E

N

T

L

C

D

P

a

n

e

l

I

/

O

I

/

O

X

1

X

2

X

C

V

S

1

5

k

1

4

7

2

5

8

0

3

6

9

#

K

e

y

1

2

3

4

K

e

y

5

6

7

8

K

e

y

9

3

n

F

5

0

n

F

3

2

7

6

8

H

z

K

e

y

1

0

K

e

y

1

2

*

/

T

K

e

y

M

a

t

r

i

x

Note: Some floating input pins (INT/TMR1, TMR0, etc.) are not shown in this circuit.

Rev. 1.20

32

May 26, 2004

HT95LXXX

Instruction Set Summary

Mnemonic

Instruction

Cycle

Flag

Affected

Description

Arithmetic

ADD A,[m]

ADDM A,[m]

ADD A,x

Add data memory to ACC

1

1⁽¹⁾

1

Z,C,AC,OV

C

Add ACC to data memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add data memory to ACC with carry

1

1⁽¹⁾

Add ACC to data memory with carry

Subtract immediate data from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

Subtract data memory from ACC

1

1⁽¹⁾

Subtract data memory from ACC with result in data memory

Subtract data memory from ACC with carry

Subtract data memory from ACC with carry and result in data memory

Decimal adjust ACC for addition with result in data memory

1

1⁽¹⁾

Logic Operation

AND A,[m]

OR A,[m]

AND data memory to ACC

1

Z

OR data memory to ACC

XOR A,[m]

ANDM A,[m]

ORM A,[m]

Exclusive-OR data memory to ACC

AND ACC to data memory

OR ACC to data memory

1

1⁽¹⁾

1

XORM A,[m] Exclusive-OR ACC to data memory

AND A,x

OR A,x

AND immediate data to ACC

OR immediate data to ACC

1

XOR A,x

CPL [m]

CPLA [m]

Exclusive-OR immediate data to ACC

Complement data memory

1

1⁽¹⁾

Complement data memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment data memory with result in ACC

1

Z

Increment data memory

1⁽¹⁾

DECA [m]

DEC [m]

Decrement data memory with result in ACC

Decrement data memory

1

1⁽¹⁾

Rotate

RRA [m]

RR [m]

Rotate data memory right with result in ACC

Rotate data memory right

1

1⁽¹⁾

1

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate data memory right through carry with result in ACC

Rotate data memory right through carry

Rotate data memory left with result in ACC

Rotate data memory left

1⁽¹⁾

C

1

None

C

1⁽¹⁾

1

RLCA [m]

RLC [m]

Rotate data memory left through carry with result in ACC

Rotate data memory left through carry

1⁽¹⁾

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move data memory to ACC

Move ACC to data memory

Move immediate data to ACC

1

1⁽¹⁾

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of data memory

Set bit of data memory

1⁽¹⁾

None

Rev. 1.20

33

May 26, 2004

HT95LXXX

Instruction

Cycle

Flag

Affected

Mnemonic

Branch

Description

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if data memory is zero

1⁽²⁾

1⁽³⁾

1⁽²⁾

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if data memory is zero with data movement to ACC

Skip if bit i of data memory is zero

Skip if bit i of data memory is not zero

Skip if increment data memory is zero

Skip if decrement data memory is zero

Skip if increment data memory is zero with result in ACC

Skip if decrement data memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m] Read ROM code (current page) to data memory and TBLH

TABRDL [m] Read ROM code (last page) to data memory and TBLH

2⁽¹⁾

None

Miscellaneous

NOP

No operation

1

1⁽¹⁾

1

None

CLR [m]

Clear data memory

SET [m]

Set data memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO,PDF

TO⁽⁴⁾,PDF⁽⁴⁾

None

Pre-clear Watchdog Timer

Swap nibbles of data memory

Swap nibbles of data memory with result in ACC

Enter power down mode

1

1⁽¹⁾

1

None

1

TO,PDF

Note: x: Immediate data

m: Data memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Ö: Flag is affected

-: Flag is not affected

⁽¹⁾: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle

(four system clocks).

⁽²⁾: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more

cycle (four system clocks). Otherwise the original instruction cycle is unchanged.

⁽¹⁾and ⁽²⁾

(3)

:

⁽⁴⁾: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the

²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.

Otherwise the TO and PDF flags remain unchanged.

Rev. 1.20

34

May 26, 2004

HT95LXXX

Instruction Definition

ADC A,[m]

Add data memory and carry to the accumulator

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADCM A,[m]

Add the accumulator and carry to data memory

Description

The contents of the specified data memory, accumulator and the carry flag are added si-

multaneously, leaving the result in the specified data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,[m]

Add data memory to the accumulator

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the accumulator.

Operation

ACC ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADD A,x

Add immediate data to the accumulator

Description

The contents of the accumulator and the specified data are added, leaving the result in the

accumulator.

Operation

ACC ¬ ACC+x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

ADDM A,[m]

Add the accumulator to the data memory

Description

The contents of the specified data memory and the accumulator are added. The result is

stored in the data memory.

Operation

[m] ¬ ACC+[m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 1.20

35

May 26, 2004

HT95LXXX

AND A,[m]

Logical AND accumulator with data memory

Description

Data in the accumulator and the specified data memory perform a bitwise logical_AND op-

eration. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

AND A,x

Logical AND immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_AND operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ANDM A,[m]

Logical AND data memory with the accumulator

Description

Data in the specified data memory and the accumulator perform a bitwise logical_AND op-

eration. The result is stored in the data memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

CALL addr

Subroutine call

Description

The instruction unconditionally calls a subroutine located at the indicated address. The

program counter increments once to obtain the address of the next instruction, and pushes

this onto the stack. The indicated address is then loaded. Program execution continues

with the instruction at this address.

Operation

Stack ¬ PC+1

PC ¬ addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR [m]

Clear data memory

Description

Operation

The contents of the specified data memory are cleared to 0.

[m] ¬ 00H

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

36

May 26, 2004

HT95LXXX

CLR [m].i

Clear bit of data memory

Description

Operation

The bit i of the specified data memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

CLR WDT

Clear Watchdog Timer

Description

The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are

cleared.

Operation

WDT ¬ 00H

PDF and TO ¬ 0

Affected flag(s)

TO

0

PDF

0

OV

Z

AC

C

¾

CLR WDT1

Preclear Watchdog Timer

Description

Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction just sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CLR WDT2

Preclear Watchdog Timer

Description

Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution

of this instruction without the other preclear instruction, sets the indicated flag which im-

plies this instruction has been executed and the TO and PDF flags remain unchanged.

Operation

WDT ¬ 00H*

PDF and TO ¬ 0*

Affected flag(s)

TO

0*

PDF

0*

OV

Z

AC

C

¾

CPL [m]

Complement data memory

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa.

Operation

[m] ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.20

37

May 26, 2004

HT95LXXX

CPLA [m]

Complement data memory and place result in the accumulator

Description

Each bit of the specified data memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa. The complemented result

is stored in the accumulator and the contents of the data memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DAA [m]

Decimal-Adjust accumulator for addition

Description

The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-

lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal

carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-

justment is done by adding 6 to the original value if the original value is greater than 9 or a

carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored

in the data memory and only the carry flag (C) may be affected.

Operation

If ACC.3~ACC.0 >9 or AC=1

then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC

else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0

and

If ACC.7~ACC.4+AC1 >9 or C=1

then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1

else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

DEC [m]

Decrement data memory

Description

Operation

Data in the specified data memory is decremented by 1.

[m] ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

DECA [m]

Decrement data memory and place result in the accumulator

Description

Data in the specified data memory is decremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]-1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.20

38

May 26, 2004

HT95LXXX

HALT

Enter power down mode

Description

This instruction stops program execution and turns off the system clock. The contents of

the RAM and registers are retained. The WDT and prescaler are cleared. The power down

bit (PDF) is set and the WDT time-out bit (TO) is cleared.

Operation

PC ¬ PC+1

PDF ¬ 1

TO ¬ 0

Affected flag(s)

TO

0

PDF

1

OV

Z

AC

C

¾

INC [m]

Increment data memory

Description

Operation

Data in the specified data memory is incremented by 1

[m] ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

INCA [m]

Increment data memory and place result in the accumulator

Description

Data in the specified data memory is incremented by 1, leaving the result in the accumula-

tor. The contents of the data memory remain unchanged.

Operation

ACC ¬ [m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

JMP addr

Directly jump

Description

The program counter are replaced with the directly-specified address unconditionally, and

control is passed to this destination.

Operation

PC ¬addr

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV A,[m]

Description

Operation

Move data memory to the accumulator

The contents of the specified data memory are copied to the accumulator.

ACC ¬ [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

39

May 26, 2004

HT95LXXX

MOV A,x

Move immediate data to the accumulator

Description

Operation

The 8-bit data specified by the code is loaded into the accumulator.

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

MOV [m],A

Move the accumulator to data memory

Description

The contents of the accumulator are copied to the specified data memory (one of the data

memories).

Operation

[m] ¬ACC

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

PC ¬ PC+1

TO

PDF

OV

Z

AC

C

¾

OR A,[m]

Logical OR accumulator with data memory

Description

Data in the accumulator and the specified data memory (one of the data memories) per-

form a bitwise logical_OR operation. The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

OR A,x

Logical OR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical_OR operation.

The result is stored in the accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

ORM A,[m]

Logical OR data memory with the accumulator

Description

Data in the data memory (one of the data memories) and the accumulator perform a

bitwise logical_OR operation. The result is stored in the data memory.

Operation

[m] ¬ACC ²OR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.20

40

May 26, 2004

HT95LXXX

RET

Return from subroutine

Description

Operation

Affected flag(s)

The program counter is restored from the stack. This is a 2-cycle instruction.

PC ¬ Stack

TO

PDF

OV

Z

AC

C

¾

RET A,x

Return and place immediate data in the accumulator

Description

The program counter is restored from the stack and the accumulator loaded with the speci-

fied 8-bit immediate data.

Operation

PC ¬ Stack

ACC ¬ x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RETI

Return from interrupt

Description

The program counter is restored from the stack, and interrupts are enabled by setting the

EMI bit. EMI is the enable master (global) interrupt bit.

Operation

PC ¬ Stack

EMI ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RL [m]

Rotate data memory left

Description

Operation

The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RLA [m]

Rotate data memory left and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the

rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

41

May 26, 2004

HT95LXXX

RLC [m]

Rotate data memory left through carry

Description

The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-

places the carry bit; the original carry flag is rotated into the bit 0 position.

Operation

[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RLCA [m]

Rotate left through carry and place result in the accumulator

Description

Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the

carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored

in the accumulator but the contents of the data memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

RR [m]

Rotate data memory right

Description

Operation

The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRA [m]

Rotate right and place result in the accumulator

Description

Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving

the rotated result in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

RRC [m]

Rotate data memory right through carry

Description

The contents of the specified data memory and the carry flag are together rotated 1 bit

right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.

Operation

[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

Rev. 1.20

42

May 26, 2004

HT95LXXX

RRCA [m]

Rotate right through carry and place result in the accumulator

Description

Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces

the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is

stored in the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBC A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the accumulator.

Operation

ACC ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SBCM A,[m]

Subtract data memory and carry from the accumulator

Description

The contents of the specified data memory and the complement of the carry flag are sub-

tracted from the accumulator, leaving the result in the data memory.

Operation

[m] ¬ ACC+[m]+C

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SDZ [m]

Skip if decrement data memory is 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. If the result is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, [m] ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SDZA [m]

Decrement data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are decremented by 1. If the result is 0, the next

instruction is skipped. The result is stored in the accumulator but the data memory remains

unchanged. If the result is 0, the following instruction, fetched during the current instruction

execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-

cles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]-1)=0, ACC ¬ ([m]-1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

43

May 26, 2004

HT95LXXX

SET [m]

Set data memory

Description

Operation

Each bit of the specified data memory is set to 1.

[m] ¬ FFH

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SET [m]. i

Set bit of data memory

Description

Operation

Bit i of the specified data memory is set to 1.

[m].i ¬ 1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZ [m]

Skip if increment data memory is 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the fol-

lowing instruction, fetched during the current instruction execution, is discarded and a

dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with

the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, [m] ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SIZA [m]

Increment data memory and place result in ACC, skip if 0

Description

The contents of the specified data memory are incremented by 1. If the result is 0, the next

instruction is skipped and the result is stored in the accumulator. The data memory re-

mains unchanged. If the result is 0, the following instruction, fetched during the current in-

struction execution, is discarded and a dummy cycle is replaced to get the proper

instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if ([m]+1)=0, ACC ¬ ([m]+1)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SNZ [m].i

Skip if bit i of the data memory is not 0

Description

If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data

memory is not 0, the following instruction, fetched during the current instruction execution,

is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-

wise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i¹0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

44

May 26, 2004

HT95LXXX

SUB A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the accumulator.

Operation

ACC ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUBM A,[m]

Subtract data memory from the accumulator

Description

The specified data memory is subtracted from the contents of the accumulator, leaving the

result in the data memory.

Operation

[m] ¬ ACC+[m]+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SUB A,x

Subtract immediate data from the accumulator

Description

The immediate data specified by the code is subtracted from the contents of the accumula-

tor, leaving the result in the accumulator.

Operation

ACC ¬ ACC+x+1

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

SWAP [m]

Swap nibbles within the data memory

Description

The low-order and high-order nibbles of the specified data memory (1 of the data memo-

ries) are interchanged.

Operation

[m].3~[m].0 « [m].7~[m].4

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SWAPA [m]

Swap data memory and place result in the accumulator

Description

The low-order and high-order nibbles of the specified data memory are interchanged, writ-

ing the result to the accumulator. The contents of the data memory remain unchanged.

Operation

ACC.3~ACC.0 ¬ [m].7~[m].4

ACC.7~ACC.4 ¬ [m].3~[m].0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

45

May 26, 2004

HT95LXXX

SZ [m]

Skip if data memory is 0

Description

If the contents of the specified data memory are 0, the following instruction, fetched during

the current instruction execution, is discarded and a dummy cycle is replaced to get the

proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZA [m]

Move data memory to ACC, skip if 0

Description

The contents of the specified data memory are copied to the accumulator. If the contents is

0, the following instruction, fetched during the current instruction execution, is discarded

and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed

with the next instruction (1 cycle).

Operation

Skip if [m]=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

SZ [m].i

Skip if bit i of the data memory is 0

Description

If bit i of the specified data memory is 0, the following instruction, fetched during the current

instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-

tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).

Operation

Skip if [m].i=0

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDC [m]

Move the ROM code (current page) to TBLH and data memory

Description

The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved

to the specified data memory and the high byte transferred to TBLH directly.

Operation

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

TABRDL [m]

Move the ROM code (last page) to TBLH and data memory

Description

The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to

the data memory and the high byte transferred to TBLH directly.

Operation

[m] ¬ ROM code (low byte)

TBLH ¬ ROM code (high byte)

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Rev. 1.20

46

May 26, 2004

HT95LXXX

XOR A,[m]

Logical XOR accumulator with data memory

Description

Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-

sive_OR operation and the result is stored in the accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XORM A,[m]

Logical XOR data memory with the accumulator

Description

Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-

sive_OR operation. The result is stored in the data memory. The 0 flag is affected.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

XOR A,x

Logical XOR immediate data to the accumulator

Description

Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-

eration. The result is stored in the accumulator. The 0 flag is affected.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

TO

PDF

OV

Z

AC

C

¾

Ö

¾

Rev. 1.20

47

May 26, 2004

HT95LXXX

Package Information

56-pin SSOP (300mil) Outline Dimensions

2

9

8

5

6

A

B

1

C

'

G

H

D

a

E

F

Dimensions in mil

Nom.

Symbol

Min.

395

291

8

Max.

420

299

12

A

B

C

C¢

D

E

F

¾

25

¾

720

89

¾

730

99

¾

4

10

G

H

a

25

4

35

12

0°

8°

Rev. 1.20

48

May 26, 2004

HT95LXXX

64-pin QFP (14´20) Outline Dimensions

C

D

H

G

5

1

3

I

5

2

3

2

F

A

B

E

2

0

6

4

K

a

J

1

9

Dimensions in mm

Nom.

Symbol

Min.

18.80

13.90

24.80

19.90

¾

Max.

19.20

14.10

25.20

20.10

¾

A

B

C

D

E

F

G

H

I

¾

1

0.40

¾

2.50

¾

3.10

3.40

¾

0.10

¾

J

1.15

0.10

0°

1.45

0.20

7°

K

a

¾

Rev. 1.20

49

May 26, 2004

HT95LXXX

100-pin QFP (14´20) Outline Dimensions

C

H

D

G

8

0

5

1

I

8

1

5

0

F

A

B

E

1

0

3

1

a

K

J

1

3

0

Dimensions in mm

Nom.

Symbol

Min.

18.50

13.90

24.50

19.90

¾

Max.

19.20

14.10

25.20

20.10

¾

A

B

C

D

E

F

G

H

I

¾

0.65

0.30

¾

2.50

¾

3.10

3.40

¾

0.10

¾

J

1

1.40

0.20

7°

K

a

0.10

0°

¾

Rev. 1.20

50

May 26, 2004

HT95LXXX

128-pin QFP (14´20) Outline Dimensions

C

D

H

G

1

0

2

6

5

I

1

0

3

6

4

F

A

B

E

1

2

8

3

9

a

K

J

1

3

8

Dimensions in mm

Nom.

Symbol

Min.

17.00

13.90

23.00

19.90

¾

Max.

17.50

14.10

23.50

20.10

¾

A

B

C

D

E

F

G

H

I

¾

0.50

0.20

¾

2.50

¾

3.10

3.40

¾

0.10

¾

J

0.65

0.10

0°

0.95

0.20

7°

K

a

¾

Rev. 1.20

51

May 26, 2004

HT95LXXX

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233

Tel: 021-6485-5560

Fax: 021-6485-0313

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031

Tel: 0755-8346-5589

Fax: 0755-8346-5590

ISDN: 0755-8346-5591

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 010-6641-0030, 6641-7751, 6641-7752

Fax: 010-6641-0125

Holmate Semiconductor, Inc. (North America Sales Office)

46712 Fremont Blvd., Fremont, CA 94538

Tel: 510-252-9880

Fax: 510-252-9885

http://www.holmate.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.20

52

May 26, 2004


型号：	HT95L20P-100QEP-A
厂家：	HOLTEK SEMICONDUCTOR INC
描述：	LCD Type Phone 8-Bit MCU 液晶屏类型手机的8位MCU CD 手机
文件：	总52页 (文件大小：359K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT95L20P-100QEP-A [HOLTEK]

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