HT95R45 [HOLTEK]
Phone 8-Bit MCU with DTMF Receiver & CPT; 电话8位单片机DTMF接收器与CPT型号: | HT95R45 |
厂家: | HOLTEK SEMICONDUCTOR INC |
描述: | Phone 8-Bit MCU with DTMF Receiver & CPT |
文件: | 总76页 (文件大小:473K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HT95R45
Phone 8-Bit MCU with DTMF Receiver & CPT
Features
Serial Interfaces Module: SIM for SPI or I2C
·
·
Operating voltage:
f
f
f
f
SYS=3.58MHz: 2.2V~5.5V
SYS=7.16MHz: 3.0V~5.5V
SYS=10.74MHz: 3.0V~5.5V
SYS=14.32MHz: 4.5V~5.5V
·
Internal DTMF generator
·
Internal DTMF receiver
·
12-bit Audio DAC output
·
Power-down and wake-up feature for power-saving
·
·
·
·
·
·
·
·
·
·
·
·
·
Program Memory: 16K´16
2112´8 Data Memory
operation: Idle mode, Sleep mode, Green mode
and Normal mode
42 bidirectional I/Os with pull-high options
2 NMOS output-only lines
External interrupt input
·
Up to 0.28ms instruction cycle with 14.32MHz
system clock at VDD=4.5V~5.5V
·
·
·
·
·
·
Bit manipulation instructions
Table read function
Three 16-bit timers with interrupts
Timer external input
63 powerful instructions
8-level stack
All instructions executed in 1 or 2 machine cycles
Low voltage reset function
32768Hz system oscillator
32768Hz up to 14.32MHz frequency-up circuit
Real time clock function
Supported by comprehensive suite of hardware
and software tools
·
·
Internal Call Progress Tone (CPT) detector
64/80-pin LQFP package
Watchdog timer function
PFD driver output
General Description
The phone MCU is a 8-bit high performance, RISC ar-
chitecture microcontroller devices specially designed
for telephone applications. Devices flexibility are en-
hanced with their internal special features such as
power-down and wake-up functions, DTMF generator,
DTMF receiver, CPT detector, PFD driver, SPI and I2C
interface, audio DAC output, etc. These features com-
bine to ensure applications require a minimum of exter-
nal components and therefore reduce overall product
costs.
The call progress tone detector is for Auto-dialing sys-
tem use. Switched capacitors technology is imple-
mented into the chip to get good performance
characteristics of band pass filter in the range of 305Hz
to 640Hz call progress tone which is dual tone
multi-frequency signal. When it detected CPT signal
then it generates relative envelopes for external
microcontroller decision to finish different kinds of CPT
signal detection such as dial tone, busy tone, ring-back
tone and reorder tone.
Having the advantages of low-power consumption,
high-performance, I/O flexibility as well as low-cost,
these devices have the versatility to suit a wide range of
application possibilities such as DTMF mode Caller ID
phone, Home Security products, deluxe feature
phones, cordless phones, fax and answering machines,
etc.
The device will be ideally suited for phone products that
comply with versatile dialer specification requirements
for different areas or countries. The device is fully sup-
ported by the Holtek range of fully functional develop-
ment and programming tools, providing a means for fast
and efficient product development cycles.
Rev. 1.00
1
March 12, 2010
HT95R45
Block Diagram
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Pin Assignment
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Rev. 1.00
2
March 12, 2010
HT95R45
Pin Description
Pad Name
I/O
Options
Description
Bidirectional 8-bit input/output port. Each individual pin on this port can
be configured as a wake-up input by a configuration option. Software in-
structions determine if the pin is a CMOS output or Schmitt Trigger input.
Configuration options determine which pins on the port have pull-high re-
sistors.
Pull-high
Wake-up
PA0~PA7
I/O
Bidirectional input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. Configuration options deter-
mine which pins on the port have pull-high resistors. When the
multi-function interrupt is enabled an interrupt will be generated when-
ever PC0 or PC5 has a falling edge, or PC7 has a rising edge.When in
the idle mode such an interrupt will wake up the device.
PC0, PC5, PC7 I/O
Pull-High
Bidirectional input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. Configuration options deter-
mine which pins on the port have pull-high resistors. PC1 is also D/A pin
for audio output for driving external transistor or power amplifier.
PC1/AUD,
I/O
DAC Output
Pull-High
PC4, PC6
PC2, PC3
PD0~PD7
O
NMOS output structures
¾
Bidirectional 8-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt Trigger input. Configuration options
determine which nibble on the port have pull-high resistors.
I/O
Pull-High
Schmitt Trigger input and CMOS output. I2C and SPI functional pins:
SDO, SCK/SCL, SCS, SDI/SDA, PCLK, PINT are pin-shared with PE0~
PE5 respectively.
For I2C, PE1 and PE3 used as SCL and SDA of I2C respectively.
For use as SPI, PE0~3 used as SDO, SCK, SCS, SDI of SPI respec-
tively. SDO is a serial interface data output. SCK is a serial interface
clock input/output (Initial is input). SCS is a chip select pin of the serial
peripheral interface, input for slave mode and output for master mode.
SDI is a serial interface data input.
PE0/SDO
PE1/SCK/SCL
PE2/SCS
PE3/SDI/SDA
PE4/PCLK
PE5/PINT
I/O
Pull-High
PE6~PE7
PCLK is a peripheral clock. PINT is external peripheral interrupt pin.
Once the SPI/I2C bus function is used, the PE0~PE3 could not be used
as normal I/O pins.
Bidirectional 8-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt Trigger input. Configuration options
determine which nibble on the port have pull-high resistors.
PF0~PF7
I/O
Pull-High
Bidirectional 4-bit input/output port. Software instructions determine if
the pin is a CMOS output or Schmitt Trigger input. Configuration options
determine if all the pins on the port have pull-high resistors.
PG0~PG3
INT
I/O
I
Pull-High
External interrupt Schmitt trigger input. Edge trigger activated on high to
low transition. No pull-high resistor.
¾
TMR0
TMR1
DTMF
MUSIC
I
Timer/Event Counter 0 Schmitt trigger input . No pull-high resistor.
Timer/Event Counter 1 Schmitt trigger input . No pull-high resistor.
Dual Tone Multi Frequency Output
¾
¾
¾
¾
I
O
O
CMOS output structure Programmable Frequency Divider pin.
Tone acquisition time and release time can be set through connection
with external resistor and capacitor CMOS IN/OUT
RT/GT
I/O
¾
EST
VP
O
I
Early steering output CMOS out
¾
¾
¾
¾
Operational amplifier non-inverting input
Operational amplifier inverting input
Operational amplifier output terminal
VN
I
GS
O
Rev. 1.00
3
March 12, 2010
HT95R45
Pad Name
VREF
I/O
Options
Description
Reference voltage output, normally VDD/2
O
¾
While an input signal for CPT detector is within specification, this pin will
output the envelope relative to the input signal with a typical 40ms timing
delay.
CPTENV
O
1/2 VDD reference voltage output pin for CPT detector.
When CPTENB = VDD, the device will be turned off and CPTVREF dis-
abled.
CPTVREF
CPTSIN
I
I
I
AC coupled analog signal input pin for CPT detector.
CPT detector enable control pin.
CPTENB = VSS: normal operation mode.
CPTENB = VDD: disabled mode.
CPTENB
CPTX1 and CPTX2 are connected to an external 32768Hz crystal or res-
onator for the CPT detector clock source.
CPTX1
CPTX2
I
O
The oscillator is turned off in the CPT detector disabled mode.
X1
X2
I
X1 and X2 are connected to an external 32768Hz crystal or resonator for
the system clock.
¾
O
XC
External low pass filter pin used for the frequency up conversion circuit.
Schmitt trigger reset input. Active low.
Positive power supply
¾
I
¾
¾
¾
¾
¾
¾
¾
¾
RES
VDD
VSS
¾
¾
¾
¾
¾
¾
Negative power supply, ground.
VDD2
VSS2
VDD4
VSS4
DTMF receiver positive power supply
DTMF receiver negative power supply
Positive power supply for CPT detector
Negative power supply for CPT detector
Note: Each pin on PA can be programmed through a configuration option to have a wake-up function.
Absolute Maximum Ratings
Supply Voltage...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
Storage Temperature............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
I
OL Total ..............................................................150mA
I
OH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
4
March 12, 2010
HT95R45
D.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
General
VDD
Operating Voltage
2.2
5.5
V
¾
¾
¾
CPU
32768Hz and 3.58MHz
oscillator off, system HALT,
WDT off, no load
1.5
2
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
3V
5V
IIDL1
Idle Mode Current 1
Idle Mode Current 2
mA
mA
32768Hz and 3.58MHz
oscillator off, system HALT,
WDT on, no load
5
3V
5V
IIDL2
10
15
32768Hz on, 3.58MHz
oscillator off, system HALT,
no load
3V
5V
3V
5V
ISLP
Sleep Mode Current
Green Mode Current
mA
mA
30
25
50
¾
¾
¾
¾
¾
¾
32768Hz on, 3.58MHz oscilla-
tor off, system on, no load
IGRN
32768Hz on, 3.58MHz
oscillator on, system on,
DTMF generator off,
receiver off, no load
2
3
¾
¾
¾
¾
¾
¾
¾
¾
3V
5V
INOR1
Normal Mode Current 1
mA
32768Hz on, 3.58MHz
oscillator off, system on,
DTMF generator off,
receiver on, no load
8
3V
5V
INOR2
Normal Mode Current 2
Pull-high Resistor
mA
10
3V
5V
¾
66
33
200
100
¾
¾
4
330
166
RPH
¾
kW
VIL
VIH
0.3VDD
VDD
I/O Port Input Low Voltage
I/O Port Input High Voltage
0
V
V
¾
¾
0.7VDD
¾
3V
5V
3
4
¾
¾
¾
¾
¾
2.5
IOL1
IOL2
IOH1
IOH2
VOL= 0.1VDD
I/O Port Sink Current
mA
mA
mA
mA
6
PC2, PC3 Sink Current
I/O Port Source Current
PC2, PC3 Leakage Current
5V PC2/PC3= 0.5V
2.5
-1
-2
¾
¾
-2
-3
¾
3V
V
OH= 0.9VDD
5V
5V PC2/PC3= 5V
DTMF Generator (Operating Temperature: -20°C to 85°C
VTDC
0.45VDD
0.1
0.7VDD
DTMF Output DC Level
V
¾
¾
¾
¾
¾
VTOL
VDTMF= 0.5V
DTMF Sink Current
mA
¾
¾
DTMF Receiver
RIN
Input Impedance (VP, VN)
Sink Current (EST)
5V
5V
5V
10
2.5
¾
1
¾
¾
¾
MW
mA
mA
IOL3
IOH3
V
V
OUT= 0.5V
OUT= 4.5V
Source Current (EST)
-0.4
-0.8
Rev. 1.00
5
March 12, 2010
HT95R45
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Low-voltage Reset
VLVR1
VLVR2
VLVR3
Low Voltage Reset 1
Low Voltage Reset 2
Low Voltage Reset 3
Configuration option= 4.2V
Configuration option= 3.15V
Configuration option= 2.1V
3.98
2.98
1.98
4.2
3.15
2.1
4.42
3.32
2.22
V
V
V
¾
¾
¾
A.C. Characteristics
Ta=25°C
Test Conditions
Conditions
Symbol
General
Parameter
Min.
Typ.
Max.
Unit
VDD
Normal mode
3.5795
MHz
¾
¾
¾
32768Hz crystal oscillator
Normal Mode, X2 PLL
Normal Mode, X3 PLL
Normal Mode, X4 PLL
7.16
10.74
14.32
MHz
MHz
MHz
¾
¾
¾
¾
¾
¾
fSYS1
System Clock 1
System Clock 2
Green mode
fSYS2
32
kHz
¾
¾
¾
32768Hz crystal oscillator
Power-up, Reset or wake-up
from HALT
tSST
tSYS
ms
System Start-up Timer Period
Low Voltage Width to Reset
1024
1
¾
¾
¾
¾
¾
¾
¾
tLVR
¾
Wake-up Time for 32768Hz
Crystal OSC
tWAKE
3V
200
ms
32kHz oscillator OFF ® ON
¾
32kHz oscillator is ON;
3.58MHz oscillator OFF ®
ON
Settling Time for 32768Hz to
tFUP
3.58MHz PLL (Frequency Up 3V
Conversion)
20
ms
ms
¾
¾
¾
Time from Sleep Mode to
tS2G
Wake-up from Sleep Mode
0
¾
¾
Green Mode
MCU
3V
Watchdog Oscillator Period
5V
45
32
90
65
180
130
¾
¾
tWDTOSC
ms
External Reset Low Pulse
tRES
tINT
1
1
¾
¾
¾
¾
¾
¾
¾
ms
ms
Width
Interrupt Pulse Width
¾
Rev. 1.00
6
March 12, 2010
HT95R45
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
DTMF Generator (Operating Temperature: -20°C to 85°C
690
762
843
932
1197
1323
1462
1617
120
5
704
778
861
950
1221
1349
1492
1649
180
¾
¾
¾
¾
Microcontroller normal mode;
¾
Single Tone Output
Frequency
fDTMFO
2.5V DTMF generator single tone
test mode
Hz
¾
¾
¾
¾
VTAC
RL
mVrms
DTMF Output AC Level
DTMF Output Load
155
¾
¾
¾
¾
¾
Row group, RL= 5kW
T.H.D. £ -23dB
Row group= 0dB
RL= 5kW
kW
dB
dB
ACR
THD
Column Pre-emphasis
Tone Signal Distortion
1
2
3
¾
-30
-23
DTMF Receiver - Signal (fSYS= 3.5795MHz)
3V
¾
¾
-36
-29
¾
¾
-6
Input Signal Level
5V
dBm
1
Twisted Accept Limit
5V
10
10
dB
dB
¾
¾
¾
¾
¾
¾
(Positive)
Twisted Accept Limit
5V
(Negative)
Dial Tone Tolerance
Noise Tolerance
5V
5V
5V
18
dB
dB
dB
¾
¾
¾
¾
¾
¾
¾
¾
¾
-12
-16
Third Tone Tolerance
Frequency Deviation
Acceptance
5V
%
¾
¾
¾
±1.5
Frequency Deviation
Rejection
5V
5V
%
¾
¾
±3.5
¾
¾
¾
tPU
Power-up Time
30
ms
¾
Rev. 1.00
7
March 12, 2010
HT95R45
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
DTMF Receiver - Gain Setting Amplifier (fSYS= 3.5795MHz)
RIN
Input Resistance
Input Leakage Current
Offset Voltage
5V
10
0.1
±25
¾
¾
¾
¾
¾
¾
¾
MW
mA
IIN
5V VSS<(WP, WN)<VDD
VOS
5V
5V
mV
¾
100Hz;
PSRR
Power Supply Rejection
60
dB
¾
¾
-3V<VIN<+3V
CMRR
AVO
fT
Common Mode Rejection
Open Loop Gain
5V
5V
5V
5V
5V
5V
60
60
dB
dB
100Hz; -3V<VIN<+3V
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
100Hz; -3V<VIN<+3V
Gain Bandwidth
1.5
4.5
50
MHz
VPP
¾
VOUT
RL
Output Voltage Swing
Load Resistance (GS)
Load Capacitance (GS)
Common Mode Range
RL>100kW
¾
¾
kW
pF
CL
100
3
VCM
VPP
5V No load
DTMF Receiver - Steering Control (fSYS= 3.5795MHz)
tDP
tDA
tACC
tREJ
tIA
Tone Present Detection Time 5V
5
11
4
14
8.5
42
¾
ms
ms
ms
ms
ms
ms
¾
¾
¾
¾
¾
¾
Tone Absent Detection Time 5V
¾
¾
20
¾
20
Acceptable Tone Duration
Rejected Tone Duration
5V
5V
¾
¾
¾
¾
Acceptable Inter-Digit Pause 5V
Rejected Inter-Digit Pause 5V
42
¾
tIR
CPT Detector Electrical Characteristics
Test Conditions
Conditions
¾
Symbol
VDD
Parameter
Operating Voltage
Operating Current
Min.
Typ.
Max.
Unit
VDD
2.5
¾
5.5
2
V
¾
¾
¾
¾
5V Functions enabled
2.5V No load
mA
mA
IDD
0.8
¾
Functions disabled or
ISTB
Standby Current
2.5V
1
¾
¾
mA
CPTEN=1
f
IN=305~640Hz
5V
0
dBm
dBm
dBm
Hz
-36
-42
¾
¾
¾
¾
¾
¾
¾
GDV
Detection Level
Rejection Level
2.5V CPTENV=1
-8
GRL
fRL
fRH
tQI
All frequency, CPTENV=0
¾
¾
-50
200
¾
¾
Rejection Out-band
Frequency
V£0 dBm, CPTENV=0
800
40
Hz
Detection Pause Time
Detection Signal Time
Rejection Pause Time
ms
¾
¾
¾
V
SIN £ -50dBm, CPTENV=0
¾
In-band signal input,
CPTENV=1
tDD
tB
40
ms
ms
¾
¾
¾
20
V
SIN £ -50dBm, CPTENV=1
¾
Rev. 1.00
8
March 12, 2010
HT95R45
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
¾
tDH
tDI
Time for high output
Time for low output
VSIN=Any signal, CPTENV=0
40
40
¾
0.8
¾
2.5
10
¾
¾
¾
¾
¾
¾
25
ms
ms
ms
sec
MW
V
¾
¾
¾
¾
Envelope Output Delay Time
¾
tRD
tST
ZI
Rejection Noise Time
Oscillator Start-up Time
Input Impedance
20
2
¾
¾
¾
¾
¾
fIN=200~3.4kHz
1.0
2.4
¾
¾
¾
VREF
ZREF
VIH
VIL
IIH
Reference Voltage
No load
2.6
20
¾
¾
Output Impedance
¾
¾
¾
¾
MW
V
Logic Input High Voltage
Logic Input Low Voltage
Logic Input High Current
Logic Input Low Current
Output High Current
Output Low Current
Pull-down Current
5V
5V
5V
5V
5V
5V
5V
3.5
¾
1.5
0.1
¾
V
V
IH=0.5V
¾
mA
mA
mA
mA
mA
IIL
VIL=0V
-0.1
¾
IOH
IOL
ISO
V
OH=4.5V
OL=0.5V
-0.5
¾
V
2.0
¾
35
¾
Power-on Reset Characteristics
Test Conditions
Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
VDD Start Voltage to Ensure
Power-on Reset
VPOR
RRVDD
tPOR
0
mV
V/ms
ms
¾
¾
¾
¾
¾
¾
¾
¾
VDD raising rate to Ensure
Power-on Reset
0.05
200
¾
¾
¾
¾
Minimum Time for VDD Stays at
V
POR to Ensure Power-on Reset
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Rev. 1.00
9
March 12, 2010
HT95R45
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the
internal system architecture. The range of devices take
advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used in
practically all operations of the instruction set. It carries
out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The
internal data path is simplified by moving data through
the Accumulator and the ALU. Certain internal registers
are implemented in the Data Memory and can be directly
or indirectly addressed. The simple addressing methods
of these registers along with additional architectural
features ensure that a minimum of external components
is required to provide a functional I/O control system with
maximum reliability and flexibility. This makes these
devices suitable for low-cost, high-volume production for
phone controller applications requiring up to 8K words of
Program Memory and 2112 bytes of Data Memory
storage.
Clocking and Pipelining
The system clock is derived from an external 32768Hz
Crystal/ Resonator which then generates a 14.32MHz
system clock using internal frequency-up converter
circuitry. This internal clock is subdivided into four inter-
nally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive in-
struction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications.
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Instruction Fetching
Rev. 1.00
10
March 12, 2010
HT95R45
Program Counter
Stack
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL² that demand a jump to a
non-consecutive Program Memory address. Only the
lower 8 bits, known as the Program Counter Low Regis-
ter, are directly addressable by user.
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack has 8 levels and is neither part of the data nor part
of the program space, and can neither be read from nor
written to. The activated level is indexed by the Stack
Pointer, SP, which can also neither be read from nor
written to. At a subroutine call or interrupt acknowledge
signal, the contents of the Program Counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction, RET or RETI,
the Program Counter is restored to its previous value
from the stack. After a device reset, the Stack Pointer
will point to the top of the stack.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For condi-
tional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is dis-
carded and a dummy cycle takes its place while the cor-
rect instruction is obtained.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the ac-
knowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine in-
struction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be in-
serted.
Program Counter Bits
Mode
b13 b12 b11 b10 b9
b8
0
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
Initial Reset
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0
Overflow
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
Timer/Event Counter 1
Overflow
Peripheral Interrupt
RTC Interrupt
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
0
0
0
0
0
0
0
Multi-Function Interrupt
Skip
Program Counter + 2 (Within current bank)
PC13 PC12 PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
Loading PCL
Jump, Call Branch
Return from Subroutine
BP.5 #12 #11 #10 #9
S13 S12 S11 S10 S9
#8
S8
#7
S7
#6
S6
#5
S5
#4
S4
#3
S3
#2
S2
#1
S1
#0
S0
Program Counter
1
3
1
2
8
7
0
Note: PC13~PC8: Current Program Counter bits
@7~@0: PCL bits
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#12~#0: Instruction code address bits
S13~S0: Stack register bits
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Rev. 1.00
11
March 12, 2010
HT95R45
·
·
·
·
Location 004H
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This vector is used by the external interrupt. If the ex-
ternal interrupt pin on the device goes low, the pro-
gram will jump to this location and begin execution if
the external interrupt is enabled and the stack is not
full.
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Location 008H
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This internal vector is used by the Timer/Event Coun-
ter 0. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter 0 interrupt is enabled and the
stack is not full.
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic op-
erations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related in-
struction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or oper-
ations may result in carry, borrow or other status
changes, the status register will be correspondingly up-
dated to reflect these changes. The ALU supports the
following functions:
Location 00CH
This internal vector is used by the Timer/Event Coun-
ter 1. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter 1 interrupt is enabled and the
stack is not full.
Location 010H
This internal vector is used by the DTMF receiver.
When the DTMF receiver is enabled, if the DTMF re-
ceiver detects a valid character available, the program
will jump to this location and begin execution if the pe-
ripheral interrupt is enabled and the stack is not full.
·
Arithmetic operations ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
·
·
Location 014H
·
Logic operations AND, OR, XOR, ANDM, ORM,
This location is used by the RTC. When the RTC is en-
abled and a time-out occurs, the program will jump to
this location and begin execution if the RTC interrupt
is enabled and the stack is not full.
XORM, CPL, CPLA
·
Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
·
Increment and Decrement INCA, INC, DECA, DEC
Location 018H
·
Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,
This location is used by the Multi-function Interrupt. If
a falling edge transition is detected on PC0 or PC5, or
a rising edge transition detected on PC7 or SPI/I2C in-
terrupt, or external peripheral falling edge transition,
or timer 2 overflow, the program will jump to this loca-
tion and begin execution if the multi-function interrupt
is enabled and the stack is not full.
SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user
code or program is stored. For these devices the Pro-
gram Memory is an OTP type, which means it can be
programmed once.
0
0
0
0
0
0
0
4
8
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Structure
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The Program Memory has a capacity of 8K by 16 bits.
The Program Memory is addressed by the Program
Counter and also contains data, table information and
interrupt entries. Table data, which can be setup in any
location within the Program Memory, is addressed by a
separate table pointer register.
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Special Vectors
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Within the Program Memory, certain locations are re-
served for special usage such as reset and interrupts.
0
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·
Location 000H
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
3
F
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1
6
b
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Program Memory Structure
Rev. 1.00
12
March 12, 2010
HT95R45
Look-up Table
Table Program Example
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register, .
This register defines the lower 8-bit address of the
look-up table.
The following example shows how the table pointer and
table data is defined and retrieved from the device. This
example uses raw table data located in the last page
which is stored there using the ORG statement. The
value at this ORG statement is ²1F00H² which refers to
the start address of the last page within the 8K Program
Memory of the microcontroller. The table pointer is setup
here to have an initial value of ²06H². This will ensure
that the first data read from the data table will be at the
Program Memory address ²1F06H² or 6 locations after
the start of the last page. Note that the value for the table
pointer is referenced to the first address of the present
page if the ²TABRDC [m]² instruction is being used. The
high byte of the table data which in this case is equal to
zero will be transferred to the TBLH register automati-
cally when the ²TABRDL [m]² instruction is executed.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these in-
structions are executed, the lower order table byte from
the Program Memory will be transferred to the user de-
fined Data Memory register [m] as specified in the in-
struction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will have uncertain values.
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the inter-
rupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
The following diagram illustrates the addressing/data
flow of the look-up table:
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Look-up Table
Table Location Bits
Instruction
b13 b12 b11 b10
TABRDC [m] PC13 PC12 PC11 PC10 PC9 PC8 @7
TABRDL [m] @7
b9
b8
b7
b6
@6
@6
b5
@5
@5
b4
@4
@4
b3
@3
@3
b2
@2
@2
b1
@1
@1
b0
@0
@0
1
1
1
1
1
1
Table Location
Note: PC13~PC8: Current Program Counter bits
@7~@0: Table Pointer Lower-order bits (TBLP)
Rev. 1.00
13
March 12, 2010
HT95R45
tempreg1
tempreg2
db
db
:
?
?
; temporary register #1
; temporary register #2
:
mov
mov
a,06h
; initialise table pointer - note that this address
; is referenced
tblp,a
; to the last page or present page
:
:
tabrdl
tempreg1
; transfers value in table referenced by table pointer
; to tempregl
; data at prog. memory address ²3F06H² transferred to
; tempreg1 and TBLH
dec
tblp
; reduce value of table pointer by one
tabrdl
tempreg2
; transfers value in table referenced by table pointer
; to tempreg2
; data at prog.memory address ²3F05H² transferred to
; tempreg2 and TBLH
; in this example the data ²1AH² is transferred to
; tempreg1 and data ²0FH² to register tempreg2
; the value ²0FH² will be transferred to the high byte
; register TBLH
:
:
org
dc
3F00h
; sets initial address of HT95R35 last page
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM in-
ternal memory and is the location where temporary in-
formation is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to di-
rectly under program control, however, some remain
protected from user manipulation. The second area of
RAM Data Memory is reserved for general purpose use.
All locations within this area are read and write accessi-
ble under program control.
Structure
The Special Purpose and General Purpose Data Mem-
ory are located at consecutive locations. All are imple-
mented in RAM and are 8 bits wide. The start address of
the Data Memory is the address 00H. Registers which
are common to all microcontrollers, such as ACC, PCL,
etc., have the same Data Memory address. Note that af-
ter power-on, the contents of the Data Memory, will be in
an unknown condition, the programmer must therefore
ensure that the Data Memory is properly initialised. The
Special Purpose Data Memory is located in Bank 0
while the General Purpose Data Memory is divided into
11 individual areas or Banks known as Bank 0 to Bank
10. Switching between different banks is achieved by
setting the Bank Pointer to the correct value.
0
0
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0
Data Memory Structure
Rev. 1.00
14
March 12, 2010
HT95R45
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
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H
H
H
H
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H
H
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H
H
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H
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H
H
H
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I
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0
1
General Purpose Data Memory
M
M
P
P
0
1
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user pro-
gram for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions, individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory. As the General Purpose Data Memory is
located within 11 different banks, it is first necessary to
ensure that the Bank Pointer is properly set to the cor-
rect value before accessing the General Purpose Data
Memory. Only Bank 0 data can be read directly. Indirect
Addressing of Bank 0 is executed using Indirect Ad-
dressing Register IAR0 and Memory Pointer MP0. Data
in Banks 1~10 can only be read indirectly using Indirect
Addressing Register IAR1 and Memory Pointer MP1.
B
P
A
C
C
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2
3
4
5
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P
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P
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D
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C
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writeable but some are protected and are readable only,
the details of which are located under the relevant Spe-
cial Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H². Although the Special Pur-
pose Data Memory registers are located in Bank 0, they
will still be accessible even if the Bank Pointer has se-
lected Banks 1~10.
1
1
A
B
P
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P
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C
1
1
C
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1
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1
2
2
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
8
9
D
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Special Function Registers
S
S
I
I
M
M
C
C
T
T
L
L
0
1
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the RAM
Data Memory area. These registers ensure correct op-
eration of internal functions such as timers, interrupts,
watchdog, etc., as well as external functions such as I/O
data control. The location of these registers within the
RAM Data Memory begins at the address ²00H². Any
unused Data Memory locations between these special
function registers and the point where the General Pur-
pose Memory begins is reserved for future expansion
purposes, attempting to read data from these locations
will return a value of ²00H².
S
I
M
D
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2
2
A
B
S
I
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A
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3
3
3
3
3
3
3
3
3
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1
2
3
4
5
6
7
8
9
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Indirect Addressing Register - IAR0, IAR1
T
M
R
2
H
The Indirect Addressing Registers, IAR0 and IAR1, al-
though having their locations in normal RAM register
space, do not actually physically exist as normal regis-
ters. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory ad-
dressing, where the actual memory address is speci-
fied. Actions on the IAR0 and IAR1 registers will result in
T
M
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2
L
3
3
A
B
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2
C
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Special Purpose Data Memory Structure
Rev. 1.00
15
March 12, 2010
HT95R45
no actual read or write operation to these registers but
rather to the memory location specified by their corre-
sponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together only access data from
Bank 0, while the IAR1 and MP1 register pair can ac-
cess data from both Bank 0 and Bank 1. As the Indirect
Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indi-
rectly will result in no operation.
physically implemented in the Data Memory and can be
manipulated in the same way as normal registers pro-
viding a convenient way with which to address and track
data. When any operation to the relevant Indirect Ad-
dressing Registers is carried out, the actual address that
the microcontroller is directed to, is the address speci-
fied by the related Memory Pointer. MP0, together with
Indirect Addressing Register, IAR0, are used to access
data from Bank 0 only, while MP1 and IAR1 are used to
access data from Banks 1~10.
Memory Pointer - MP0, MP1
For all devices, two Memory Pointers, known as MP0
The following example shows how to clear a section of
four RAM locations already defined as locations adres1
to adres4.
and MP1 are provided. These Memory Pointers are
data .section ¢data¢
adres1
adres2
adres3
adres4
block
db ?
db ?
db ?
db ?
db ?
code .section at 0 ¢code¢
org 00h
start:
mov a,04h
mov block,a
mov a,offset adres1; Accumulator loaded with first RAM address
; setup size of block
mov mp0,a
; setup memory pointer with first RAM address
loop:
clr IAR0
inc mp0
sdz block
jmp loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Bank Pointer - BP
The Data Memory RAM is divided into eleven banks, known as Bank 0~Bank 10. All of the Special Purpose Registers
are contained in Bank 0. Selecting the required Data Memory area is achieved using the Bank Pointer. If data in Bank 0
is to be accessed, then the BP register must be loaded with the value ²00², while if data in Bank 1 is to be accessed,
then the BP register must be loaded with the value ²01² and so on for the other registers. Using Memory Pointer MP0
and Indirect Addressing Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank
Pointer.
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Bank Pointer
Rev. 1.00
16
March 12, 2010
HT95R45
The Data Memory is initialised to Bank 0 after a reset,
except for a WDT time-out reset in the Power Down
Mode, in which case, the Data Memory bank remains
unaffected. It should be noted that Special Function
Data Memory is not affected by the bank selection,
which means that the Special Function Registers can be
accessed from Bank 0 to Bank 10. Directly addressing
the Data Memory will always result in Bank 0 being ac-
cessed irrespective of the value of the Bank Pointer.
the location where the table data is located. Its value
must be setup before any table read commands are ex-
ecuted. Its value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user de-
fined location.
Accumulator - ACC
Watchdog Timer Register - WDTS
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
The Watchdog feature of the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows. To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ra-
tios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate divi-
sion ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set divi-
sion ratios between 1 and 128.
Status Register - STATUS
Program Counter Low Register - PCL
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system manage-
ment flags are used to record the status and operation of
the microcontroller.
To provide additional program control functions, the low
byte of the Program Counter is made accessible to pro-
grammers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily imple-
mented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory lo-
cation, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are per-
mitted. When such operations are used, note that a
dummy cycle will be inserted.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera-
tions related to the status register may give different re-
sults due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² in-
struction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Look-up Table Registers - TBLP, TBLH
These two special function registers are used to control
operation of the look-up table which is stored in the Pro-
gram Memory. TBLP is the table pointer and indicates
b
7
b
0
T
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Status Register
Rev. 1.00
17
March 12, 2010
HT95R45
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
These labeled I/O registers are mapped to specific ad-
dresses within the Data Memory as shown in the Data
Memory table, which are used to transfer the appropri-
ate output or input data on that port. With each I/O port
there is an associated control register labeled PAC,
PCC, PDC, PEC, PFC and PGC, also mapped to spe-
cific addresses with the Data Memory. Except PC2 and
PC3, the control register specifies which pins of that port
are set as inputs and which are set as outputs. PC2 or
PC3 is NMOS output, so the corresponding bit of the
control register is not implemented. To setup a pin as an
input, the corresponding bit of the control register must
be set high, for an output it must be set low. During pro-
gram initialization, it is important to first setup the control
registers to specify which pins are outputs and which
are inputs before reading data from or writing data to the
I/O ports. One flexible feature of these registers is the
ability to directly program single bits using the ²SET
[m].i² and ²CLR [m].i² instructions. The ability to change
I/O pins from output to input and vice versa by manipu-
lating specific bits of the I/O control registers during nor-
mal program operation is a useful feature of these
devices.
·
C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place dur-
ing a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
·
AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nib-
ble into the low nibble in subtraction; otherwise AC is
cleared.
·
Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
·
OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
·
PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
·
TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
DTMF Registers - DTMFC, DTMFD, DTRXC, DTRXD
The device contains fully integrated DTMF receiver and
generator circuitry for decoding and generation of DTMF
signals. The DTMF receiver requires two registers to
control its operation, a DTRXC control register to control
its overall function and a DTRXD register to store the
DTMF decoded signal data. The DTMF generator also
requires two registers for its operation, a DTMFC register
for its overall control and DTMFD register to store the dig-
ital codes that are to be generated as DMTF signals.
Interrupt Control Register - INTC0, INTC1
These two 8-bit register, known as the INTC0 and
INTC1 registers, control the operation of all interrupts.
By setting various bits within this register using standard
bit manipulation instructions, the enable/disable func-
tion of the external and timer interrupts can be inde-
pendently controlled. A master interrupt bit within this
register, the EMI bit, acts like a global enable/disable
and is used to set all of the interrupt enable bits on or off.
This bit is cleared when an interrupt routine is entered to
disable further interrupt and is set by executing the
²RETI² instruction.
Mode Register - MODE, MODE_1
The device supports two system clock and four operation
modes. The system clock could be 32768Hz or HCLK
and operation mode could be Normal, Green, Sleep or
Idle mode. These are all selected by the software.
MODE_1 register supports four high frequency clock
(HCLK) for CPU which are 3.58MHz, 7.16MHz,
10.74MHz and 14.32 MHz.
Timer/Event Counter Registers
This device contains three 16-bit Timer/Event Counters,
which have associated register pairs known as TMR0L/
TMR0H, TMR1L/TMR1H and TMR2L/TMR2H. These
are the locations where the timers 16-bit value is lo-
cated. Three associated control registers, known as
TMR0C, TMR1C and TMR2C, contain the setup infor-
mation for these three timers.
MFIC Register - MFIC0
PC0, PC5 and PC7 could be used to trigger an extra in-
terrupt. They are enabled or disabled individually by
bit0~bit2 of MFIC0. When a multi-function interrupt oc-
curs, the programmer should check bit4~bit6 of MFIC0
to determine the cause of the interrupt.
MFIC1 Register - MFIC1
Input/Output Ports and Control Registers
SPI/I2C interrupt, external peripheral interrupt, timer 2
interrupt are three additional multi-function interrupts.
They are enabled or disabled individually by bit0~2 of
MFIC1. When a multi-function interrupt occurs, the pro-
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PC, PD, PE, PF and PG.
Rev. 1.00
18
March 12, 2010
HT95R45
grammer should check bit4~bit6 of MFIC1 to determine
the cause of the interrupt.
serve power, a feature that is important for battery and
other low-power applications. Various methods exist to
wake-up the microcontroller, one of which is to change
the logic condition on one of the Port A pins from high to
PFD Registers - PFDC/PFDD
low. After
a ²HALT² instruction forces the
The device contains a Programmable Frequency Di-
vider function which can generate accurate frequencies
based on the system clock. The clock source, enable
function and output frequency is controlled using these
two registers.
microcontroller into entering the Power Down mode, the
device will remain idle or in a low-power state until the
logic condition of the selected wake-up pin on Port A
changes from high to low. This function is especially
suitable for applications that can be woken up via exter-
nal switches. Note that each pin on Port A can be se-
lected individually to have this wake-up feature.
RTCC Register
The device contains a Real Time Clock function other-
wise known as the RTC. To control this function a regis-
ter known as the RTCC register is provided which
provides the overall on/off control and time out flag.
I/O Port Control Registers
Each I/O port has its own control register PAC, PCC,
PDC, PEC, PFC and PGC, to control the input/output
configuration. with this control register, each CMOS out-
put or input with or without pull-high resistor structures
can be reconfigured dynamically under software control.
Each pin of the I/O ports is directly mapped to a bit in its
associated port control register. For the I/O pin to func-
tion as an input, the corresponding bit of the control reg-
ister must be written as a ²1². This will then allow the
logic state of the input pin to be directly read by instruc-
tions. When the corresponding bit of the control register
is written as a ²0², the I/O pin will be setup as a CMOS
output. If the pin is currently setup as an output, instruc-
tions can still be used to read the output register. How-
ever, it should be noted that the program will in fact only
read the status of the output data latch and not the ac-
tual logic status of the output pin.
DAC Register - VOICEC/VOL/DAL/DAH
These four registers are for 12-bit DAC output data and
volume control.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of ev-
ery pin fully under user program control, pull-high op-
tions for all ports and wake-up options on certain pins,
the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities. The
device provides 26 bidirectional input/output lines la-
beled with port names PA, PC, PD, PE, PF and PG.
These I/O ports are mapped to the Data Memory with
specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used
for input and output operations. For input operation,
these ports are non-latching, which means the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]², where m denotes the port address. For output
operation, all the data is latched and remains un-
changed until the output latch is rewritten.
I/O Pin Structures
The following diagrams illustrate the I/O pin internal
structures. As the exact logical construction of the I/O
pin may differ from these drawings, they are supplied as
a guide only to assist with the functional understanding
of the I/O pins.
Programming Considerations
Unlike other port lines, PC2 and PC3 are supplied as
NMOS output-only lines. They have neither pull high op-
tion nor port control bit.
Within the user program, one of the first things to con-
sider is port initialization. After a reset, all of the I/O data
and port control registers will be set high. This means
that all I/O pins will default to an input state, the level of
which depends on the other connected circuitry and
whether pull-high options have been selected. If the port
control registers, PAC, PCC, PDC, PEC, PFC and PGC,
are then programmed to setup some pins as outputs,
these output pins will have an initial high output value
unless the associated port data registers, PA, PC, PD,
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an exter-
nal resistor. To eliminate the need for these external re-
sistors, all I/O pins, when configured as an input have
the capability of being connected to an internal pull-high
resistor. These pull-high resistors are selectable via
configuration options and are implemented using a
weak PMOS transistor.
T
1
T
2
T
3
T
4
T
1
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2
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Each device has a HALT instruction enabling the
microcontroller to enter a Power Down Mode and pre-
Read/Write Timing
Rev. 1.00
19
March 12, 2010
HT95R45
V
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PC2, PC3 NMOS Output Port
Rev. 1.00
20
March 12, 2010
HT95R45
Timer Registers - TMR0L/TMR0H, TMR1L/TMR1H,
PE, PF and PG, are first programmed. Selecting which
pins are inputs and which are outputs can be achieved
byte-wide by loading the correct values into the appro-
priate port control register or by programming individual
bits in the port control register using the ²SET [m].i² and
²CLR [m].i² instructions. Note that when using these bit
control instructions, a read-modify-write operation takes
place. The microcontroller must first read in the data on
the entire port, modify it to the required new bit values
and then rewrite this data back to the output ports.
TMR2L/TMR2H
The timer registers are special function register pairs lo-
cated in the Special Purpose Data Memory and is the
place where the 16-bit actual timer value is stored.
These register pairs are known as TMR0L/TMR0H,
TMR1L/TMR1H and TMR2L/TMR2H. The value in the
timer register pair increases by one each time an inter-
nal clock pulse is received or an external transition oc-
curs on the external timer pin. The timer will count from
the initial value loaded by the preload register to the full
count of FFFFH at which point the timer overflows and
an internal interrupt signal is generated. The timer value
will then be reset with the initial preload register value
and continue counting.
Port A has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
A pins. Single or multiple pins on Port A can be setup to
have this function.
To achieve a maximum full range count of FFFFH the
preload register must first be cleared to all zeros. It
should be noted that after power-on, the preload register
will be in an unknown condition. Note that if the
Timer/Event Counter is switched off and data is written
to its preload register, this data will be immediately writ-
ten into the actual timer register. However, if the
Timer/Event Counter is enabled and counting, any new
data written into the preload data register during this pe-
riod will remain in the preload register and will only be
written into the timer register the next time an overflow
occurs.
Timer/Event Counters
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The device contains three
count-up timers of 16-bit capacity. Timer0 and Timer1
have three different operating modes, they can be con-
figured to operate as a general timer, an external event
counter or as a pulse width measurement device.
Timer2 can be configured as timer mode only.
There are two types of registers related to the
Timer/Event Counters. The first are the registers that
contains the actual value of the Timer/Event Counter
and into which an initial value can be preloaded, and are
known as TMR0L/TMR0H, TMR1L/TMR1H and
TMR2L/TMR2H. Reading these register pairs retrieves
the contents of the Timer/Event Counters. The second
type of associated register are the Timer Control Regis-
ters, which defines the timer options and determines
how the Timer/Event Counters are to be used, and have
the name TMR0C, TMR1C and TMR2C, Timer0 and
Timer1 can have the timer clock configured to come
from the internal clock source or from an external timer
pin. Timer2 can have the timer clock come from internal
system clock only.
Reading from and writing to these registers is carried
out in a specific way. It must be noted that when using in-
structions to preload data into the low byte register,
namely TMR0L, TMR1L or TMR2L, the data will only be
placed in a low byte buffer and not directly into the low
byte register. The actual transfer of the data into the low
byte register is only carried out when a write to its asso-
ciated high byte register, namely TMR0H, TMR1H or
TMR2H, is executed. Also, using instructions to preload
data into the high byte timer register will result in the
data being directly written to the high byte register. At
the same time the data in the low byte buffer will be
transferred into its associated low byte register. For this
reason, when preloading data into the 16-bit timer regis-
ters, the low byte should be written first. It must also be
noted that to read the contents of the low byte register, a
read to the high byte register must first be executed to
latch the contents of the low byte buffer from its associ-
ated low byte register. After this has been done, the low
byte register can be read in the normal way. Note that
reading the low byte timer register directly will only result
in reading the previously latched contents of the low
byte buffer and not the actual contents of the low byte
timer register.
Configuring the Timer/Event Counter Input Clock
Source
For Timer/Event Counter 0, the internal timer clock
source can originate from either the system clock/4 or
from an external clock source. For Timer/Event Counter
1, the internal timer clock source can originate from the
32768Hz or from an external clock source.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on the external timer pins TMR0 or TMR1. Depending
upon the condition of the T0E or T1E bit, each high to
low, or low to high transition on the external timer pin will
increment the counter by one.
Rev. 1.00
21
March 12, 2010
HT95R45
To choose which of the three modes the Timer/Event
Counter is to operate in, either in the timer mode, the
event counting mode or the pulse width measurement
mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair T0M1/T0M0, T1M1/T1M0 and
T2M1/T2M0, must be set to the required logic levels.
The Timer/Event Counter on/off bit, which is bit 4 of the
Timer Control Register, and known as T0ON, T1ON and
T2ON, provides the basic on/off control of the
Timer/Event Counter. Setting the bit high allows the
Timer/Event Counter to run, clearing the bit stops it run-
ning. If the Timer/Event Counter is in the event count or
pulse width measurement mode, the active transition
edge level type is selected by the logic level of bit 3 of
the Timer Control Register which is known as T0E and
T1E.
Timer Control Registers - TMR0C, TMR1C, TMR2C
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their control register, which has the
name TMR0C/TMR1C/TMR2C. It is the Timer Control
Register together with its corresponding timer register
pair that control the full operation of each Timer/Event
Counter. Before the Timer/Event Counter can be used, it
is essential that the Timer Control Register is fully pro-
grammed with the right data to ensure its correct opera-
tion, a process that is normally carried out during
program initialisation.
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16-bit Timer2 Structure
Rev. 1.00
22
March 12, 2010
HT95R45
Configuring the Event Counter Mode
Configuring the Timer Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be re-
corded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair in the Timer
Control Register must be set to the correct value as
shown.
In this mode, the Timer/Event Counters can be utilised
to measure fixed time intervals, providing an internal in-
terrupt signal each time the Timer/Event Counter over-
flows. To operate in this mode, the Operating Mode
Select bit pair in the Timer Control Register must be set
to the correct value as shown.
Bit7 Bit6
Bit7 Bit6
Control Register Operating Mode
Control Register Operating Mode
Select Bits for the Event Counter Mode
Select Bits for the Timer Mode
0
1
1
0
In this mode the external timer pin is used as the
Timer/Event Counter clock source, however it is not di-
vided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit,
which is bit 4 of the Timer Control Register, can be set
high to enable the Timer/Event Counter to run. If the Ac-
tive Edge Select bit, which is bit 3 of the Timer Control
Register, is low, the Timer/Event Counter will increment
each time the external timer pin receives a low to high
transition. If the Active Edge Select bit is high, the coun-
ter will increment each time the external timer pin re-
ceives a high to low transition. When it is full and
overflows, an interrupt signal is generated and the
In this mode the internal clock, is used as the
Timer/Event Counter clock. After the other bits in the
Timer Control Register have been setup, the enable bit,
which is bit 4 of the Timer Control Register, can be set
high to enable the Timer/Event Counter to run. Each
time an internal clock cycle occurs, the Timer/Event
Counter increments by one. When it is full and over-
flows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the Interrupt
Control Register, is reset to zero.
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Rev. 1.00
23
March 12, 2010
HT95R45
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Control Register, is reset to zero.
Control Register Operating Mode
Select Bits for the Pulse Width
Measurement Mode
Bit7 Bit6
1
1
In this mode the internal clock is used as the
Timer/Event Counter clock. After the other bits in the
Timer Control Register have been setup, the enable bit,
which is bit 4 of the Timer Control Register, can be set
high to enable the Timer/Event Counter, however it will
not actually start counting until an active edge is re-
ceived on the external timer pin.
To ensure that the timer pin is configured to operate as
an event counter input pin the Timer Control Register
must place the Timer/Event Counter in the Event
Counting Mode. It should be noted that in the event
counting mode, even if the microcontroller is in the
Power Down Mode, the Timer/Event Counter will con-
tinue to record externally changing logic events on the
timer input pin. As a result when the timer overflows it
will generate a timer interrupt and corresponding
wake-up source.
If the Active Edge Select bit, which is bit 3 of the Timer
Control Register, is low, once a high to low transition has
been received on the external timer pin, the Timer/Event
Counter will start counting until the external timer pin re-
turns to its original high level. At this point the enable bit
will be automatically reset to zero and the Timer/Event
Counter will stop counting. If the Active Edge Select bit
is high, the Timer/Event Counter will begin counting
once a low to high transition has been received on the
external timer pin and stop counting when the external
timer pin returns to its original low level. As before, the
enable bit will be automatically reset to zero and the
Configuring the Pulse Width Measurement Mode
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the ex-
ternal timer pin. To operate in this mode, the Operating
Mode Select bit pair in the Timer Control Register must
be set to the correct value as shown.
Rev. 1.00
24
March 12, 2010
HT95R45
E
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Pulse Width Measure Mode Timing Diagram
Timer/Event Counter will stop counting. It is important to
note that in the Pulse Width Measurement Mode, the
enable bit is automatically reset to zero when the exter-
nal control signal on the external timer pin returns to its
original level, whereas in the other two modes the en-
able bit can only be reset to zero under program control.
measurement mode, the internal system clock is also
used as the timer clock source but the timer will only run
when the correct logic condition appears on the external
timer input pin. As this is an external event and not syn-
chronised with the internal timer clock, the
microcontroller will only see this external event when the
next timer clock pulse arrives. As a result there may be
small differences in measured values requiring pro-
grammers to take this into account during programming.
The same applies if the timer is configured to be in the
event counting mode which again is an external event
and not synchronised with the internal system or timer
clock.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the external timer
pin. As the enable bit has now been reset, any further
transitions on the external timer pin will be ignored. Not
until the enable bit is again set high by the program can
the timer begin further pulse width measurements. In
this way, single shot pulse measurements can be easily
made.
When the Timer/Event Counter is read or if data is writ-
ten to the preload registers, the clock is inhibited to
avoid errors, however as this may result in a counting er-
ror, this should be taken into account by the program-
mer. Care must be taken to ensure that the timers are
properly initialised before using them for the first time.
The associated timer enable bits in the interrupt control
register must be properly set otherwise the internal in-
terrupt associated with the timer will remain inactive.
The edge select, timer mode control bits in timer control
register must also be correctly set to ensure the timer is
properly configured for the required application. It is also
important to ensure that an initial value is first loaded
into the timer register before the timer is switched on;
this is because after power-on the initial value of the
timer register is unknown. After the timer has been in-
itialised the timer can be turned on and off by controlling
the enable bit in the timer control register. Note that set-
ting the timer enable bit high to turn the timer on, should
only be executed after the timer mode bits have been
properly setup. Setting the timer enable bit high together
with a mode bit modification, may lead to improper timer
operation if executed as a single timer control register
byte write instruction.
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the exter-
nal timer pin and not by the logic level. When the
Timer/Event Counter is full and overflows, an interrupt
signal is generated and the Timer/Event Counter will re-
load the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the Interrupt Control Register, is reset to zero.
To ensure that the timer pin is configured to operate as a
pulse width measurement pin the Timer Control Regis-
ter must place the Timer/Event Counter in the Pulse
Width Measurement Mode.
Programming Considerations
When configured to run in the timer mode, the internal
system clock is used as the timer clock source and is
therefore synchronized with the overall operation of the
microcontroller. In this mode, when the appropriate
timer register is full, the microcontroller will generate an
internal interrupt signal directing the program flow to the
respective internal interrupt vector. For the pulse width
Rev. 1.00
25
March 12, 2010
HT95R45
Timer Program Example
When the Timer/Event counter overflows, its corre-
sponding interrupt request flag in the interrupt control
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. However irre-
spective of whether the interrupts are enabled or not, a
Timer/Event counter overflow will also generate a
wake-up signal if the device is in a Power-down condi-
tion. This situation may occur if the Timer/Event Counter
is in the Event Counting Mode and if the external signal
continues to change state. In such a case, the
Timer/Event Counter will continue to count these exter-
nal events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up from occurring, the timer interrupt re-
quest flag should first be set high before issuing the
HALT instruction to enter the Power Down Mode.
This program example shows how the Timer/Event
Counter registers are setup, along with how the inter-
rupts are enabled and managed. Note how the
Timer/Event Counter is turned on, by setting bit 4 of the
Timer Control Register. The Timer/Event Counter can
be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counter to
be in the timer mode, which uses the internal system
clock as the clock source.
Org
04h
08h
:
; external interrupt vector
reti
Org
; Timer/Event Counter 0 interrupt vector
; jump here when Timer 0 overflows
jmp tmr0nt
org 20h
; main program
;internal Timer/Event Counter interrupt routine
tmr0nt:
:
; Timer/Event Counter main program placed here
:
reti
:
:
begin:
;setup Timer registers
mov a,01fh
mov tmr01,a
; setup preload value - timer counts from this value to FFFFH
mov a,09bh
mov tmr0h,a
mov a,080h
; setup Timer control register
; timer mode
mov tmr0c,a
; setup interrupt register
mov a,005h
; enable master interrupt and timer interrupt
mov intc0,a
set tmrc0.4
; start Timer - note mode bits must be previously setup
:
:
Rev. 1.00
26
March 12, 2010
HT95R45
Serial Interface Function
The device contains a Serial Interface Function, which
includes both the four line SPI interface and the two line
I2C interface types, to allow an easy method of commu-
nication with external peripheral hardware. Having rela-
tively simple communication protocols, these serial
interface types allow the microcontroller to interface to
external SPI or I2C based hardware such as sensors,
Flash or EEPROM memory, etc. The SIM interface pins
are pin-shared with other I/O pins therefore the SIM in-
terface function must first be selected using a configura-
tion option. As both interface types share the same pins
and registers, the choice of whether the SPI or I2C type
is used is made using a bit in an internal register.
figuration option and setting the correct bits in the
SIMCTL0/SIMCTL2 register. After the SPI configura-
tion option has been configured it can also be addi-
tionally disabled or enabled using the SIMEN bit in the
SIMCTL0 register. Communication between devices
connected to the SPI interface is carried out in a
slave/master mode with all data transfer initiations be-
ing implemented by the master. The Master also con-
trols the clock signal. As the device only contains a
single SCS pin only one slave device can be utilised.
The SPI function in this device offers the following fea-
tures:
¨
Full duplex synchronous data transfer
¨
Both Master and Slave modes
SPI Interface
¨
LSB first or MSB first data transmission modes
The SPI interface is often used to communicate with ex-
ternal peripheral devices such as sensors, Flash or
EEPROM memory devices etc. Originally developed by
Motorola, the four line SPI interface is a synchronous
serial data interface that has a relatively simple commu-
nication protocol simplifying the programming require-
ments when communicating with external hardware
devices.
¨
Transmission complete flag
¨
Rising or falling active clock edge
¨
WCOL and CSEN bit enabled or disable select
The status of the SPI interface pins is determined by a
number of factors such as whether the device is in the
master or slave mode and upon the condition of cer-
tain control bits such as CSEN, SIMEN and SCS. In
the table I, Z represents an input floating condition.
There are several configuration options associated
with the SPI interface. One of these is to enable the
SIM function which selects the SIM pins rather than
normal I/O pins. Note that if the configuration option
does not select the SIM function then the SIMEN bit in
the SIMCTL0 register will have no effect. Another two
SIM configuration options determine if the CSEN and
WCOL bits are to be used.
The communication is full duplex and operates as a
slave/master type, where the MCU can be either master
or slave. Although the SPI interface specification can
control multiple slave devices from a single master,
here, as only a single select pin, SCS, is provided only
one slave device can be connected to the SPI bus.
S
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SIM Function
Function
SIM interface or I/O pins
Enable/Disable
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SPI Master/Slave Connection
SPI WCOL bit
Enable/Disable
SPI Interface Configuration Options
SPI Registers
·
SPI Interface Operation
The SPI interface is a full duplex synchronous serial
data link. It is a four line interface with pin names SDI,
SDO, SCK and SCS. Pins SDI and SDO are the Serial
Data Input and Serial Data Output lines, SCK is the
Serial Clock line and SCS is the Slave Select line. As
the SPI interface pins are pin-shared with normal I/O
pins and with the I2C function pins, the SPI interface
must first be enabled by selecting the SIM enable con-
There are three internal registers which control the over-
all operation of the SPI interface. These are the SIMDR
data register and two control registers SIMCTL0 and
SIMCTL2. Note that the SIMCTL1 register is only used
by the I2C interface.
Rev. 1.00
27
March 12, 2010
HT95R45
Master - SIMEN=1
Slave - SIMEN=1
CSEN=1
Master/Salve
SIMEN=0
Pin
CSEN=1
SCS=1
CSEN=0
CSEN=1
CSEN=0
SCS=0
SCS
SDO
SDI
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Z
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I, Z
I, Z
I, Z
Z
H: CKPOL=0
L: CKPOL=1
H: CKPOL=0
L: CKPOL=1
SCK
Z
I, Z
I, Z
Z
Note:
²Z² floating, ²H² output high, ²L² output low, ²I² Input, ²O²output level, ²I,Z² input floating (no pull-high)
SPI Interface Pin Status
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SPI/I2C Control Register - SIMCTL0
Rev. 1.00
28
March 12, 2010
HT95R45
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SPI Control Register - SIMCTL2
Rev. 1.00
29
March 12, 2010
HT95R45
the SPI Slave Mode is selected then the clock will be
supplied by an external Master device.
The SIMDR register is used to store the data being
transmitted and received. The same register is used by
both the SPI and I2C functions. Before the
microcontroller writes data to the SPI bus, the actual
data to be transmitted must be placed in the SIMDR reg-
ister. After the data is received from the SPI bus, the
microcontroller can read it from the SIMDRregister. Any
transmission or reception of data from the SPI bus must
be made via the SIMDR register.
SPI Master/Slave Clock
SIM0 SIM1 SIM2
Control and I2C Enable
0
0
0
0
0
0
1
1
0
1
0
1
SPI Master, fSYS/4
SPI Master, fSYS/16
SPI Master, fSYS/64
SPI Master, fSUB
Bit
7
6
5
4
3
2
1
0
SPI Master Timer/Event
Counter 0 output/2
1
0
0
Label SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
1
1
0
1
1
1
0
1
SPI Slave
I2C mode
Not used
POR
X
X
X
X
X
X
X
X
There are also two control registers for the SPI inter-
face, SIMCTL0 and SIMCTL2. Note that the SIMCTL2
register also has the name SIMAR which is used by the
I2C function. The SIMCTL1 register is not used by the
SPI function, only by the I2C function. Register
SIMCTL0 is used to control the enable/disable function
and to set the data transmission clock frequency. Al-
though not connected with the SPI function, the
SIMCTL0 register is also used to control the Peripheral
Clock prescaler. Register SIMCTL2 is used for other
control functions such as LSB/MSB selection, write colli-
sion flag etc.
SPI Control Register - SIMCTL2
The SIMCTL2 register is also used by the I2C interface
but has the name SIMAR.
·
TRF
The TRF bit is the Transmit/Receive Complete flag and
is set high automatically when an SPI data transmis-
sion is completed, but must be cleared by the applica-
tion program. It can be used to generate an interrupt.
·
WCOL
The WCOL bit is used to detect if a data collision has
occurred. If this bit is high it means that data has been
attempted to be written to the SIMDR register during a
data transfer operation. This writing operation will be
ignored if data is being transferred. The bit can be
cleared by the application program. Note that using
the WCOL bit can be disabled or enabled via configu-
ration option.
The following gives further explanation of each
SIMCTL1 register bit:
·
SIMIDLE
The SIMIDLE bit is used to select if the SPI interface
continues running when the device is in the IDLE
mode. Setting the bit high allows the SPI interface to
maintain operation when the device is in the Idle
mode. Clearing the bit to zero disables any SPI opera-
tions when in the Idle mode.
·
CSEN
The CSENbit is used as an on/off control for the SCS
pin. If this bit is low then the SCS pin will be disabled
and placed into a floating condition. If the bit is high
the SCS pin will be enabled and used as a select pin.
Note that using the CSEN bit can be disabled or en-
abled via configuration option.
This SPI/I2C idle mode control bit is located at
CLKMODregister bit4.
·
SIMEN
The bit is the overall on/off control for the SPI inter-
face. When the SIMEN bit is cleared to zero to disable
the SPI interface, the SDI, SDO, SCK and SCS lines
will be in a floating condition and the SPI operating
current will be reduced to a minimum value. When the
bit is high the SPI interface is enabled. The SIMconfig-
uration option must have first enabled the SIM inter-
face for this bit to be effective. Note that when the
SIMEN bit changes from low to high the contents of
the SPI control registers will be in an unknown condi-
tion and should therefore be first initialised by the ap-
plication program.
·
MLS
This is the data shift select bit and is used to select
how the data is transferred, either MSB or LSB first.
Setting the bit high will select MSB first and low for
LSB first.
·
CKEG and CKPOL
These two bits are used to setup the way that the
clock signal outputs and inputs data on the SPI bus.
These two bits must be configured before data trans-
fer is executed otherwise an erroneous clock edge
may be generated. The CKPOL bit determines the
base condition of the clock line, if the bit is high then
the SCK line will be low when the clock is inactive.
When the CKPOL bit is low then the SCK line will be
high when the clock is inactive. The CKEG bit deter-
mines active clock edge type which depends upon the
condition of CKPOL.
·
SIM0~SIM2
These bits setup the overall operating mode of the SIM
function. As well as selecting if the I2C or SPI function,
they are used to control the SPI Master/Slave selec-
tion and the SPI Master clock frequency. The SPI
clock is a function of the system clock but can also be
chosen to be sourced from the Timer/Event Counter. If
Rev. 1.00
30
March 12, 2010
HT95R45
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SPI Slave Mode Timing (CKEG=1)
Rev. 1.00
31
March 12, 2010
HT95R45
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SPI Transfer Control Flowchart
Rev. 1.00
32
March 12, 2010
HT95R45
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SCKClock Signal
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SPI Communication
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After the SPIinterface is enabled by setting the SIMEN
bit high, then in the Master Mode, when data is written to
the SIMDR register, transmission/reception will begin si-
multaneously. When the data transfer is complete, the
TRF flag will be set automatically, but must be cleared
using the application program. In the Slave Mode, when
the clock signal from the master has been received, any
data in the SIMDR register will be transmitted and any
data on the SDI pin will be shifted into the SIMDR regis-
ter. The master should output an SCS signal to enable
the slave device before a clock signal is provided and
slave data transfers should be enabled/disabled be-
fore/after an SCS signal is received.
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There are several configuration options associated
with the I2C interface. One of these is to enable the
function which selects the SIM pins rather than normal
I/O pins. Note that if the configuration option does not
select the SIM function then the SIMEN bit in the
SIMCTL0 register will have no effect. A configuration
option exists to allow a clock other than the system
clock to drive the I2C interface. Another configuration
option determines the debounce time of the I2C inter-
face. This uses the internal clock to in effect add a
debounce time to the external clock to reduce the pos-
sibility of glitches on the clock line causing erroneous
operation. The debounce time, if selected, can be
chosen to be either 1 or 2 system clocks.
The SPI will continue to function even after a HALT in-
struction has been executed.
I2C Interface
The I2C interface is used to communicate with external
peripheral devices such as sensors, EEPROM memory
etc. Originally developed by Philips, it is a two line low
speed serial interface for synchronous serial data trans-
fer. The advantage of only two lines for communication,
relatively simple communication protocol and the ability
to accommodate multiple devices on the same bus has
made it an extremely popular interface type for many
applications.
SIM
Function
SIM function
SIM interface or SEG pins
I2C runs without internal clock
Disable/Enable
I2C clock
No debounce, 1 system clock;
2 system clocks
I2C debounce
I2C Interface Configuration Options
I2C Registers
I2C Interface Operation
·
The I2C serial interface is a two line interface, a serial
data line, SDA, and serial clock line, SCL. As many
devices may be connected together on the same bus,
their outputs are both open drain types. For this rea-
son it is necessary that external pull-high resistors are
connected to these outputs. Note that no chip select
line exists, as each device on the I2C bus is identified
by a unique address which will be transmitted and re-
ceived on the I2C bus.
·
There are three control registers associated with the
I2C bus, SIMCTL0, SIMCTL1 and SIMAR and one
data register, SIMDR. The SIMDR register, which is
shown in the above SPI section, is used to store the
data being transmitted and received on the I2C bus.
Before the microcontroller writes data to the I2C bus,
the actual data to be transmitted must be placed in the
SIMDR register. After the data is received from the I2C
bus, the microcontroller can read it from the SIMDR
register. Any transmission or reception of data from
the I2C bus must be made via the SIMDR register.
Note that the SIMAR register also has the name
SIMCTL2 which is used by the SPI function. Bits
SIMIDLE , SIMEN and bits SIM0~SIM2 in register
SIMCTL0 are used by the I2C interface. The SIMCTL0
register is shown in the above SPI section.
When two devices communicate with each other on
the bidirectional I2C bus, one is known as the master
device and one as the slave device. Both master and
slave can transmit and receive data, however, it is the
master device that has overall control of the bus. For
these devices, which only operates in slave mode,
there are two methods of transferring data on the I2C
bus, the slave transmit mode and the slave receive
mode.
Rev. 1.00
33
March 12, 2010
HT95R45
D
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I2C Block Diagram
¨
¨
SIMIDLE
SRW
The SIMIDLE bit is used to select if the I2C interface
continues running when the device is in the IDLE
mode. Setting the bit high allows the I2C interface to
maintain operation when the device is in the Idle
mode. Clearing the bit to zero disables any I2C op-
erations when in the Idle mode.
The SRW bit is the Slave Read/Write bit. This bit de-
termines whether the master device wishes to
transmit or receive data from the I2C bus. When the
transmitted address and slave address match, that
is when the HAAS bit is set high, the device will
check the SRW bit to determine whether it should
be in transmit mode or receive mode. If the SRW bit
is high, the master is requesting to read data from
the bus, so the device should be in transmit mode.
When the SRW bit is zero, the master will write data
to the bus, therefore the device should be in receive
mode to read this data.
This SPI/I2C idle mode control bit is located at
CLKMOD register bit4.
¨
SIMEN
The SIMEN bit is the overall on/off control for the I2C
interface. When the SIMEN bit is cleared to zero to
disable the I2C interface, the SDA and SCLlines will
be in a floating condition and the I2C operating cur-
rent will be reduced to a minimum value. In this con-
dition the pins can be used as SEG functions. When
the bit is high the I2C interface is enabled. The SIM
configuration option must have first enabled the SIM
interface for this bit to be effective. Note that when
the SIMENbit changes from low to high the contents
of the I2C control registers will be in an unknown
condition and should therefore be first initialised by
the application program
¨
TXAK
The TXAK flag is the transmit acknowledge flag. Af-
ter the receipt of 8-bits of data, this bit will be trans-
mitted to the bus on the 9th clock. To continue
receiving more data, this bit has to be reset to zero
before further data is received.
¨
¨
HTX
The HTX flag is the transmit/receive mode bit. This
flag should be set high to set the transmit mode and
low for the receive mode.
¨
¨
SIM0~SIM2
HBB
These bits setup the overall operating mode of the
SIM function. To select the I2C function, bits SIM2~
SIM0 should be set to the value 110.
The HBB flag is the I2C busy flag. This flag will be
high when the I2C bus is busy which will occur when
a START signal is detected. The flag will be reset to
zero when the bus is free which will occur when a
STOP signal is detected.
RXAK
The RXAK flag is the receive acknowledge flag.
When the RXAKbit has been reset to zero it means
that a correct acknowledge signal has been re-
ceived at the 9th clock, after 8 bits of data have
been transmitted. When in the transmit mode, the
transmitter checks the RXAK bit to determine if the
receiver wishes to receive the next byte. The trans-
mitter will therefore continue sending out data until
the RXAK bit is set high. When this occurs, the
transmitter will release the SDA line to allow the
master to send a STOP signal to release the bus.
¨
HASS
The HASS flag is the address match flag. This flag
is used to determine if the slave device address is
the same as the master transmit address. If the ad-
dresses match then this bit will be high, if there is no
match then the flag will be low.
¨
HCF
The HCF flag is the data transfer flag. This flag will
be zero when data is being transferred. Upon com-
pletion of an 8-bit data transfer the flag will go high
and an interrupt will be generated.
Rev. 1.00
34
March 12, 2010
HT95R45
I2C Control Register - SIMAR
The SIMARregister is also used by the SPI interface but
S
t
a
r
t
has the name SIMCTL2.
W
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The SIMARregister is the location where the 7-bit slave
address of the microcontroller is stored. Bits 1~7 of the
SIMARregister define the microcontrollerslave address.
Bit 0 is not defined. When a master device, which is con-
nected to the I2C bus, sends out an address, which
matches the slave address in the SIMAR register, the
microcontroller slave device will be selected. Note that
the SIMAR register is the same register as SIMCTL2
which is used by the SPI interface.
S
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T
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2
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0
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=
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I2C Bus Communication
G
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Communication on the I2C bus requires four separate
steps, a START signal, a slave device address transmis-
sion, a data transmission and finally a STOP signal.
When a START signal is placed on the I2C bus, all de-
vices on the bus will receive this signal and be notified of
the imminent arrival of data on the bus. The first seven
bits of the data will be the slave address with the first bit
being the MSB. If the address of the microcontroller
matches that of the transmitted address, the HAAS bit in
the SIMCTL1 register will be set and an I2C interrupt will
be generated. After entering the interrupt service rou-
tine, the microcontroller slave device must first check
the condition of the HAAS bit to determine whether the
interrupt source originates from an address match or
from the completion of an 8-bit data transfer. During a
data transfer, note that after the 7-bit slave address has
been transmitted, the following bit, which is the 8th bit, is
the read/write bit whose value will be placed in the SRW
bit. This bit will be checked by the microcontroller to de-
termine whether to go into transmit or receive mode. Be-
fore any transfer of data to or from the I2C bus, the
microcontroller must initialise the bus, the following are
steps to achieve this:
I2C Bus Initialisation Flow Chart
·
Start Signal
The START signal can only be generated by the mas-
ter device connected to the I2C bus and not by the
microcontroller, which is only a slave device. This
START signal will be detected by all devices con-
nected to the I2C bus. When detected, this indicates
that the I2C bus is busy and therefore the HBB bit will
be set. A START condition occurs when a high to low
transition on the SDA line takes place when the SCL
line remains high.
·
Slave Address
The transmission of a START signal by the master will
be detected by all devices on the I2C bus. To deter-
mine which slave device the master wishes to com-
municate with, the address of the slave device will be
sent out immediately following the START signal. All
slave devices, after receiving this 7-bit address data,
will compare it with their own 7-bit slave address. If the
address sent out by the master matches the internal
address of the microcontroller slave device, then an
internal I2C bus interrupt signal will be generated. The
next bit following the address, which is the 8th bit, de-
fines the read/write status and will be saved to the
SRW bit of the SIMCTL1 register. The device will then
transmit an acknowledge bit, which is a low level, as
the 9th bit. The microcontroller slave device will also
set the status flag HAAS when the addresses match.
As an I2C bus interrupt can come from two sources,
when the program enters the interrupt subroutine, the
HAAS bit should be examined to see whether the in-
terrupt source has come from a matching slave ad-
dress or from the completion of a data byte transfer.
When a slave address is matched, the device must be
Step 1
Write the slave address of the microcontroller to the I2C
bus address register SIMAR.
Step 2
Set the SIMEN bit in the SIMCTL0 register to ²1² to en-
able the I2C bus.
Step 3
Set the EHI bit of the interrupt control register to enable
the I2C bus interrupt.
b
0
b
7
S
A
6
S
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5
S
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4
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3
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I2C Slave Address Register - SIMAR
Rev. 1.00
35
March 12, 2010
HT95R45
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S
C
L
1
0
0
1
0
1
0
0
S
D
A
S
S
S
M
D
A
P
=
A
R
S
t
S
a
r
t
(
1
b
i
t
)
=
l
a
v
e
A
d
d
r
e
s
s
(
7
b
i
t
s
)
=
S
R
W
b
i
t
(
1
b
i
t
)
=
S
l
a
v
e
d
e
v
i
c
e
s
e
n
d
a
c
k
n
o
w
l
e
d
g
e
b
i
t
(
1
b
=
D
a
t
a
(
8
b
i
t
s
)
=
=
A
S
C
t
K
(
R
X
A
K
b
i
t
f
o
r
t
r
a
n
s
m
i
t
t
e
r
,
T
X
A
K
b
i
o
p
(
1
b
i
t
)
S
S
A
M
S
R
D
A
D
A
S
S
A
M
S
R
D
A
D
A
P
I2C Communication Timing Diagram
S
t
a
r
t
N
o
Y
e
s
H
A
A
S
=
1
?
Y
e
s
N
1
o
N
o
Y
1
e
s
S
R
W
=
H
T
X
=
?
?
C
L
R
H
T
X
R
e
a
d
f
r
o
m
S
E
T
H
T
X
C
L
R
T
X
A
K
S
I
M
D
R
W
r
i
t
e
t
o
D
u
m
m
y
R
e
a
d
R
E
T
I
S
I
M
D
R
F
r
o
m
S
I
M
D
R
Y
e
s
R
X
A
K
=
1
?
R
E
T
I
R
E
T
I
N
o
C
L
R
H
T
X
W
r
i
t
e
t
o
C
L
R
T
X
A
K
S
I
M
D
R
D
u
m
m
y
R
e
a
d
R
E
T
I
f
r
o
m
S
I
M
D
R
R
E
T
I
I2C Bus ISR Flow Chart
Rev. 1.00
36
March 12, 2010
HT95R45
·
placed in either the transmit mode and then write data
to the SIMDR register, or in the receive mode where it
must implement a dummy read from the SIMDR regis-
ter to release the SCL line.
Data Byte
The transmitted data is 8-bits wide and is transmitted
after the slave device has acknowledged receipt of its
slave address. The order of serial bit transmission is
the MSB first and the LSB last. After receipt of 8-bits of
data, the receiver must transmit an acknowledge sig-
nal, level ²0², before it can receive the next data byte.
If the transmitter does not receive an acknowledge bit
signal from the receiver, then it will release the SDA
line and the master will send out a STOP signal to re-
lease control of the I2C bus. The corresponding data
will be stored in the SIMDR register. If setup as a
transmitter, the microcontroller slave device must first
write the data to be transmitted into the SIMDR regis-
ter. If setup as a receiver, the microcontroller slave de-
vice must read the transmitted data from the SIMDR
register.
·
SRW Bit
The SRW bit in the SIMCTL1 register defines whether
the microcontroller slave device wishes to read data
from the I2C bus or write data to the I2C bus. The
microcontroller should examine this bit to determine if
it is to be a transmitter or a receiver. If the SRW bit is
set to ²1² then this indicates that the master wishes to
read data from the I2 C bus, therefore the
microcontroller slave device must be setup to send
data to the I2C bus as a transmitter. If the SRW bit is
²0² then this indicates that the master wishes to send
data to the I2C bus, therefore the microcontroller slave
device must be setup to read data from the I2C bus as
a receiver.
S
S
C
L
·
Acknowledge Bit
D
A
After the master has transmitted a calling address,
any slave device on the I2C bus, whose own internal
address matches the calling address, must generate
an acknowledge signal. This acknowledge signal will
inform the master that a slave device has accepted its
calling address. If no acknowledge signal is received
by the master then a STOP signal must be transmitted
by the master to end the communication. When the
HAAS bit is high, the addresses have matched and
the microcontroller slave device must check the SRW
bit to determine if it is to be a transmitter or a receiver.
If the SRW bit is high, the microcontroller slave device
should be setup to be a transmitter so the HTX bit in
the SIMCTL1 register should be set to ²1² if the SRW
bit is low then the microcontroller slave device should
be setup as a receiver and the HTX bit in the SIMCTL1
register should be set to ²0².
S
t
a
r
t
b
i
t
D
a
t
D
a
a
t
a
S
t
o
p
b
s
t
a
b
a
l
l
e
l
o
w
c
h
a
n
g
e
Data Timing Diagram
Receive Acknowledge Bit
·
When the receiver wishes to continue to receive the
next data byte, it must generate an acknowledge bit,
known as TXAK, on the 9th clock. The microcontroller
slave device, which is setup as a transmitter will check
the RXAK bit in the SIMCTL1 register to determine if it
is to send another data byte, if not then it will release
the SDA line and await the receipt of a STOP signal
from the master.
Rev. 1.00
37
March 12, 2010
HT95R45
Interrupts
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter requires microcontroller
attention, their corresponding interrupt will enforce a
temporary suspension of the main program allowing the
microcontroller to direct attention to their respective
needs. Each device contains a single external interrupt
and single internal timer interrupt functions. The exter-
nal interrupt is controlled by the action of the external
INT pin, while the internal interrupt are controlled by
Timer/Event Counter 0 or 1 overflow, a Real Time Clock
overflow, a DTMF reciever valid character reception, a
multifunction interrupt.
Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The
Program Counter will then be loaded with a new ad-
dress which will be the value of the corresponding inter-
rupt vector. The microcontroller will then fetch its next
instruction from this interrupt vector. The instruction at
this vector will usually be a JMP statement which will
take program execution to another section of program
which is known as the interrupt service routine. Here is
located the code to control the appropriate interrupt. The
interrupt service routine must be terminated with a RETI
statement, which retrieves the original Program Counter
address from the stack and allows the microcontroller to
continue with normal execution at the point where the in-
terrupt occurred.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by two interrupt
control registers, INTC0 and INTC1, located in the Data
Memory. By controlling the appropriate enable bits in
this register each individual interrupt can be enabled or
disabled. Also when an interrupt occurs, the corre-
sponding request flag will be set by the microcontroller.
The global enable flag if cleared to zero will disable all
interrupts.
The various interrupt enable bits, together with their as-
sociated request flags, are shown in the accompanying
diagram with their order of priority.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, as the EMI bit will be cleared au-
tomatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests oc-
cur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be re-
corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the rou-
tine, to allow interrupt nesting. If the stack is full, the in-
terrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
A Timer/Event Counter 0 or 1 overflow, a Real Time
Clock overflow, a reception of a valid DTMF character, a
rising edge on PC7 or a falling edge on INT/PC0/PC5
will all generate an interrupt request by setting their cor-
responding request flag, if their appropriate interrupt en-
able bit is set. When this happens, the Program
b
7
b
0
T
1
F
E
T
I
0
F
E
F
T
E
1
I
T
0
E
I
E
E
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M
I
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N
T
C
0
R
e
g
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r
M
1
0
a
s
t
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r
I
n
t
e
r
r
u
p
t
G
l
o
b
a
l
:
:
g
g
l
l
o
o
b
b
a
l
e
n
a
b
l
e
a
l
d
i
s
a
b
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E
1
0
x
t
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a
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r
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p
t
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n
a
b
l
:
:
e
d
n
i
a
a
a
b
b
b
l
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a
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b
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T
1
0
i
i
m
m
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r
r
/
/
E
E
v
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1
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I
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n
:
:
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s
b
T
1
0
:
:
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d
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b
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1
0
x
t
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p
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R
e
q
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e
:
:
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n
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1
0
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r
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/
/
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r
r
0
1
I
I
n
n
:
:
a
i
c
t
i
c
v
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n
a
t
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v
e
T
1
0
:
:
a
i
c
t
i
c
v
e
n
a
t
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v
e
N
o
t
i
m
p
l
e
m
e
n
t
e
d
,
r
e
a
d
a
Interrupt Control 0 Register
Rev. 1.00
38
March 12, 2010
HT95R45
b
7
b
0
M
F
F
P
R
E
T
R
C
F
F
E
M
R
F
T
I
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C
P
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I
R
N
I
T
C
1
R
e
g
i
s
t
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r
P
1
0
e
r
i
p
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e
r
a
l
I
n
t
e
r
r
u
p
t
E
:
:
e
d
n
i
a
b
l
e
s
a
b
l
e
R
1
0
e
a
l
T
i
m
e
C
l
o
c
k
I
n
t
e
r
r
:
:
e
d
n
i
a
b
l
e
s
a
b
l
e
M
1
0
u
l
t
i
-
f
u
n
c
t
i
o
n
I
/
O
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n
t
:
:
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d
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a
b
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s
a
b
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N
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a
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P
1
0
e
r
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p
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r
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R
:
:
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1
0
e
a
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k
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r
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:
:
a
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1
0
u
l
t
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f
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/
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:
:
a
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N
o
t
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m
p
l
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m
e
n
t
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d
,
r
e
a
d
Interrupt Control 1 Register
b
7
b
0
P
P
C
C
P
5
7
C
F
F
0
F
E
P
C
E
P
7
I
C
E
5
P
I
C
M
0
F
I
I
C
0
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e
g
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s
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r
P
1
0
C
C
C
0
5
7
I
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(
(
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:
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a
b
b
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b
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P
1
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:
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P
1
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r
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(
R
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:
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1
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C
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0
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7
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(
(
F
F
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a
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)
g
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:
:
a
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r
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:
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1
(
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:
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a
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e
N
o
t
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m
p
l
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d
,
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e
a
d
MFIC0 Register
Rev. 1.00
39
March 12, 2010
HT95R45
b
7
b
0
T
P
2
E
F
S
R
I
M
F
E
E
T
P
2
E
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1
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2
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1
0
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:
:
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b
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1
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:
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1
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2
:
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2
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N
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r
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d
MFIC1 Register
A
u
t
o
m
a
t
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c
a
l
l
y
C
l
e
a
r
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d
b
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x
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P
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0
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A
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P
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m
5
a
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P
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D
7
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a
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5
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F
Interrupt Structure
Rev. 1.00
40
March 12, 2010
HT95R45
Peripheral Interrupt
Interrupt Priority
For a Peripheral interrupt to occur, the global interrupt
enable bit, EMI, and the corresponding peripehral inter-
rupt enable bit, EPERI, must first be set. An actual Pe-
ripheral interrupt will take place when the Peripheral
interrupt request flag, PERF, is set, a situation that will
occur when DTMF receiver detects a valid character.
When the interrupt is enabled, the stack is not full and a
Peripheral interrupt request occurs, a subroutine call to
the peripheral interrupt vector at location 10H, will take
place. When the interrupt is serviced, the peripheral in-
terrupt request flag, PERF, will be automatically reset
and the EMI bit will be automatically cleared to disable
other interrupts.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
Interrupt Source
All Devices Priority
Reset
1
2
3
4
5
6
7
External Interrupt
Timer 0 Interrupt
Timer 1 Interrupt
Peripheral Interrupt
Real Time Clock Interrupt
Multi-function Interrupt
Real Time Clock Interrupt
For a Real Time Clock interrupt to occur, the global inter-
rupt enable bit, EMI, and the corresponding real timer
clock interrupt enable bit, ERTCI, must first be set. An
actual Real Time Clock interrupt will take place when the
Real Time Clock request flag, RTCF, is set, a situation
that will occur when the RTC times out which will occur
every second. When the interrupt is enabled, the stack
is not full and a Real Time Clock interrupt request oc-
curs, a subroutine call to the real time clock interrupt
vector at location 14H, will take place. When the inter-
rupt is serviced, the timer interrupt request flag, RTCF,
will be automatically reset and the EMI bit will be auto-
matically cleared to disable other interrupts.
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt oc-
curs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the INTC reg-
ister can prevent simultaneous occurrences.
External Interrupt
For an external interrupt to occur, the global interrupt en-
able bit, EMI, and external interrupt enable bit, EEI, must
first be set. An actual external interrupt will take place
when the external interrupt request flag, EIF, is set, a situ-
ation that will occur when a high to low transition appears
on the INT line. When the interrupt is enabled, the stack is
not full and a high to low transition appears on the exter-
nal interrupt pin, a subroutine call to the external interrupt
vector at location 04H, will take place. When the interrupt
is serviced, the external interrupt request flag, EIF, will be
automatically reset and the EMI bit will be automatically
cleared to disable other interrupts.
Multi-function Interrupt
For a Multi-function interrupt to occur, the global inter-
rupt enable bit, EMI, and the corresponding
multi-function interrupt enable bit, EMFI, must first be
set. An actual Multi-function interrupt will take place
when the Multi-function interrupt request flag, MFF, is
set, a situation that will occur when PC0 or PC5 has a
falling edge, or PC7 has a rising edge, a SPI/I2C inter-
rupt, an external peripheral has a falling edge or a timer2
overflow ossurs. When the interrupt is enabled, the
stack is not full and a Multi-function interrupt request oc-
curs, a subroutine call to the multi-function interrupt vec-
tor at location 18H, will take place. When the interrupt is
serviced, the multi-function interrupt request flag, MFF,
will be automatically reset and the EMI bit will be auto-
matically cleared to disable other interrupts.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ET0I or ET1I, must first be set. An
actual Timer/Event Counter interrupt will take place
when the Timer/Event Counter request flag, T0F or T1F,
is set, a situation that will occur when the Timer/Event
Counter overflows. When the interrupt is enabled, the
stack is not full and a Timer/Event Counter overflow oc-
curs, a subroutine call to the timer interrupt vector at lo-
cation 08H or 0CH, will take place. When the interrupt is
serviced, the timer interrupt request flag, T0F or T1F, will
be automatically reset and the EMI bit will be automati-
cally cleared to disable other interrupts.
Rev. 1.00
41
March 12, 2010
HT95R45
Programming Considerations
Reset Functions
By disabling the interrupt enable bits, a requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the INTC register until the corresponding in-
terrupt is serviced or until the request flag is cleared by a
software instruction.
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and ex-
ternally:
·
Power-on Reset
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory ad-
dress, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or need
to be serviced immediately in some applications. If only
one stack is left and the interrupt is not well controlled, the
original control sequence will be damaged once a ²CALL
subroutine² is executed in the interrupt subroutine.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recom-
mended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode. Only the
Program Counter is pushed onto the stack. If the con-
tents of the register or status register are altered by the
interrupt service program, which may corrupt the de-
sired control sequence, then the contents should be
saved in advance.
Reset and Initialisation
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, af-
ter a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program com-
mences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
V
D
D
0
.
D
9
D
V
R
E
S
t
R
S
T
D
S
S
T
T
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e
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t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected be-
tween VSS and the RES pin will provide a suitable ex-
ternal reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is force-
fully pulled low. In such a case, known as a normal oper-
ation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of re-
set operations result in different register conditions be-
ing setup.
V
R
D
D
S
1
0
W
0
k
E
0
m
. F 1
V
S
S
Basic Reset Circuit
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is imple-
mented in situations where the power supply voltage
falls below a certain threshold.
Rev. 1.00
42
March 12, 2010
HT95R45
For applications that operate within an environment
where more noise is present the Enhanced Reset Cir-
cuit shown is recommended.
W
D
T
T
T
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-
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0
k
WDT Time-out Reset during Normal Operation
Timing Chart
E
S
1
0
W
k
·
Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Pro-
gram Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
0
m
. F 1
V
S
S
Enhanced Reset Circuit
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
W
D
T
T
i
m
e
-
o
u
t
t
S
S
T
·
RES Pin Reset
S
S
T
T
i
m
e
-
o
u
t
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initi-
ated from this point.
WDT Time-out Reset during Power Down
Timing Chart
Reset Initial Conditions
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
0
.
D
9
D
V
0
.
D
4
D
V
R
E
S
t
R
S
T
D
S
S
T
T
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e
-
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RES Reset Timing Chart
TO PDF
RESET Conditions
·
Low Voltage Reset - LVR
0
u
1
1
0
u
u
1
RES reset during power-on
The microcontroller contains a low voltage reset cir-
cuit in order to monitor the supply voltage of the de-
vice. The LVR function is selected via a configuration
option. If the supply voltage of the device drops to
within a range of 0.9V~VLVR such as might occur when
changing the battery, the LVR will automatically reset
the device internally. For a valid LVR signal, a low sup-
ply voltage, i.e., a voltage in the range between
0.9V~VLVR must exist for a time greater than that spec-
ified by tLVR in the A.C. characteristics. If the low sup-
ply voltage state does not exceed this value, the LVR
will ignore the low supply voltage and will not perform
a reset function. The actual VLVR value can be se-
lected via configuration options.
RES or LVR reset during normal operation
WDT time-out reset during normal operation
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
The following table indicates the way in which the vari-
ous components of the microcontroller are affected after
a power-on reset occurs.
Item
Condition After RESET
Program Counter Reset to zero
Interrupts
WDT
All interrupts will be disabled
L
V
R
Clear after reset, WDT begins
counting
t
R
S
T
D
S
S
T
T
i
m
e
-
o
u
t
Timer/Event
Counters
The Timer Counters will be
turned off
I
n
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e
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n
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e
s
e
t
Low Voltage Reset Timing Chart
Input/Output Ports I/O ports will be setup as inputs
·
Stack Pointer will point to the top
Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal opera-
tion is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
Stack Pointer
of the stack
Rev. 1.00
43
March 12, 2010
HT95R45
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable
continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller
is in after a particular reset occurs. The following table describes how each type of reset affects each of the
microcontroller internal registers.
RES or LVR Reset RES or LVR Reset WDT Time-out
WDT Time-out
(Sleep/Idle)
Register Reset (Power-on)
(Normal/Green)
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - 0 - 0 0 0 0
u u u u u u u u
0 0 0 0 H
(Sleep/Idle)
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - 0 - 0 0 0 0
u u u u u u u u
0 0 0 0 H
(Normal/Green)
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - 0 - 0 0 0 0
u u u u u u u u
0 0 0 0 H
IAR0
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
- - 0 - 0 0 0 0
x x x x x x x x
0 0 0 0 H
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - u - u u u u
u u u u u u u u
0 0 0 0 H
MP0
IAR1
MP1
BP
ACC
PCL
TBLP
TBLH
WDTS
STATUS
INTC0
TMR0H
TMR0L
TMR0C
TMR1H
TMR1L
TMR1C
TMR2H
TMR2L
TMR2C
PA
x x x x x x x x
x x x x x x x x
0 0 0 0 0 1 1 1
- - 0 0 x x x x
- 0 0 0 0 0 0 0
x x x x x x x x
x x x x x x x x
0 0 - 0 1 - - -
x x x x x x x x
x x x x x x x x
0 0 - 0 1 - - -
x x x x x x x x
x x x x x x x x
0 0 - 0 - - - -
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 - - 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - 1 1 1 1
- - - - 1 1 1 1
- 0 0 0 - 0 0 0
- - - - - 0 - 1
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
0 0 0 0 0 1 1 1
- - u u u u u u
- 0 0 0 0 0 0 0
x x x x x x x x
x x x x x x x x
0 0 - 0 1 - - -
x x x x x x x x
x x x x x x x x
0 0 - 0 1 - - -
x x x x x x x x
x x x x x x x x
0 0 - 0 - - - -
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 - - 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - 1 1 1 1
- - - - 1 1 1 1
- 0 0 0 - 0 0 0
- - - - - 0 - 1
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
0 0 0 0 0 1 1 1
- - 0 1 u u u u
- 0 0 0 0 0 0 0
x x x x x x x x
x x x x x x x x
0 0 - 0 1 - - -
x x x x x x x x
x x x x x x x x
0 0 - 0 1 - - -
x x x x x x x x
x x x x x x x x
0 0 - 0 - - - -
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 - - 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - 1 1 1 1
- - - - 1 1 1 1
- 0 0 0 - 0 0 0
- - - - - 0 - 1
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
0 0 0 0 0 1 1 1
- - 1 u u u u u
- 0 0 0 0 0 0 0
x x x x x x x x
x x x x x x x x
0 0 - 0 1 - - -
x x x x x x x x
x x x x x x x x
0 0 - 0 1 - - -
x x x x x x x x
x x x x x x x x
0 0 - 0 - - - -
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 - - 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
- - - - 1 1 1 1
- - - - 1 1 1 1
- 0 0 0 - 0 0 0
- - - - - 0 - 1
0 0 0 0 0 0 0 0
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - 1 1 u u u u
- u u u u u u u
u u u u u u u u
u u u u u u u u
u u - u u - - -
u u u u u u u u
u u u u u u u u
u u - u u - - -
u u u u u u u u
u u u u u u u u
u u - u - - - -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u - - u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
- - - - u u u u
- - - - u u u u
- u u u - u u u
- - - - - u - u
u u u u u u u u
PAC
PC
PCC
PD
PDC
PE
PEC
PF
PFC
PG
PGC
INTC1
DTMFC
DTMFD
Rev. 1.00
44
March 12, 2010
HT95R45
RES or LVR Reset RES or LVR Reset WDT Time-out
WDT Time-out
(Sleep/Idle)
Register Reset (Power-on)
(Normal/Green)
- - - - - 0 0 1
- - - - 0 0 0 0
u - u - - - - -
0 0 u - - - - -
- - - - - - 0 0
- 0 0 0 - 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 - - - -
0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
(Sleep/Idle)
(Normal/Green)
- - - - - 0 0 1
- - - - 0 0 0 0
u - u - - - - -
0 0 u - - - - -
- - - - - - 0 0
- 0 0 0 - 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 - - - -
0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
DTRXC
DTRXD
RTCC
- - - - - 0 0 1
- - - - 0 0 0 0
0 - 0 - - - - -
0 0 0 - - - - -
- - - - - - 0 0
- 0 0 0 - 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 - - - -
0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
- - - - - 0 0 1
- - - - 0 0 0 0
u - u - - - - -
0 0 u - - - - -
- - - - - - 0 0
- 0 0 0 - 0 0 0
- 0 0 0 - 0 0 0
0 0 0 0 - - - -
0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 -
1 0 0 0 0 0 0 1
x x x x x x x x
- - - - - u u u
- - - - u u u u
u - u - - - - -
0 0 u - - - - -
- - - - - - 0 0
- u u u - u u u
- u u u - u u u
u u u u - - - -
u u u u u u u u
u u u u u u u u
u u u u u u u u
u u u u u u u u
MODE
MODE_1
MFIC0
MFIC1
PFDC
PFDD
SIMCTL0
SIMCTL1
SIMDR
SIMAR/
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
u u u u u u u u
SIMCTL2
VOICEC
VOL
- - - - - - - 0
x x x - - - - -
x x x x - - - -
x x x x x x x x
- - - - - - - 0
u u u - - - - -
u u u u - - - -
u u u u u u u u
- - - - - - - 0
u u u - - - - -
u u u u - - - -
u u u u u u u u
- - - - - - - 0
u u u - - - - -
u u u u - - - -
u u u u u u u u
- - - - - - - u
u u u - - - - -
u u u u - - - -
u u u u u u u u
DAL
DAH
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Oscillator
There are two oscillator circuits within the controller.
One is for the system clock which uses an externally
connected 32768Hz crystal. The other is an internal
watchdog oscillator.
Watchdog Timer Oscillator
The WDT oscillator is a fully integrated free running RC
oscillator with a typical period of 65ms at 5V, requiring no
external components. It is selected via configuration op-
tion. If selected, when the device enters the Power Down
Mode, the system clock will stop running, however the
WDT oscillator will continue to run and keep the watch-
dog function active. However, as the WDT will consume a
certain amount of power when in the Power Down Mode,
for low power applications, it may be desirable to disable
the WDT oscillator by configuration option.
System Crystal/Ceramic Oscillator
The system clock is generated using an external
32768Hz crystal or ceramic resonator connected be-
tween pins X1 and X2. From this clock source an inter-
nal circuit generates a 14.32MHz clock source which is
also required by the system. This frequency generator
circuit requires the addition of externally connected RC
components to pin XC to form a low pass filter for the
14.32MHz output frequency stabilisation.
X
X
1
2
1
5
W
k
X
C
3
n
F
4
7
n
F
Crystal/Ceramic Oscillator
Rev. 1.00
45
March 12, 2010
HT95R45
Operation Mode, Power-down and Wake-up
There are four operational modes, known as the idle mode, sleep mode, green mode, and normal mode. The chosen
mode is selected using the MODE0, MODE1 and UPEN bits in the MODE register but also depends upon whether the
HALT instruction has been executed or not.
HALT
Operation
Mode
System
Clock
MODE1
MODE0
UPEN
32768Hz
HCLK
Instruction
Not executed
Not executed
Executed
1
0
0
0
X
X
0
1
1
0
0
0
Normal
Green
Sleep
Idle
ON
ON
ON
HCLK
OFF
OFF
OFF
32768Hz
Stopped
Stopped
ON
Executed
OFF
Note:
²X² means don¢t care
MODE0 will be cleared to 0 automatically after wake-up from Idle Mode.
HCLK is frequency from PLL, which is 3.58MHz, 7.16MHz, 10.74MHz or 14.32MHz.
b
7
b
0
M
O
D
E
1
M
O
D
E
0
U
P
E
N
M
O
D
E
R
e
g
i
s
t
e
r
N
o
t
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q
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:
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a
b
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3
1
0
2
:
:
7
6
8
H
z
o
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c
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t
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A
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T
n
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3
2
7
6
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3
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7
6
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C
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c
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t
3
2
7
6
8
H
z
a
s
C
P
U
MODE Register
b
7
b
0
F
1
F
0
M
O
D
E
_
1
R
e
g
i
s
t
e
r
H
F
C
L
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c
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0
0
0
1
1
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1
0
1
3
7
1
1
.
.
0
4
5
8
6
7
3
M
M
4
H
z
(
d
e
f
a
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l
t
)
1
H
z
.
M
H
z
2
.
M
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N
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d
,
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e
a
d
MODE_1 Register
Rev. 1.00
46
March 12, 2010
HT95R45
Idle Mode
Changing the Operational Mode
When the device enters this mode, the normal operating
current, will be reduced to an extremely low standby cur-
rent level. This occurs because when the device enters
the Power Down Mode, both the HCLK and 32768Hz
system oscillators are stopped which reduces the power
consumption to extremely low levels, however, as the
device maintains its present internal condition, it can be
woken up at a later stage and continue running, without
requiring a full reset. This feature is extremely important
in application areas where the microcontroller must
have its power supply constantly maintained to keep the
device in a known condition but where the power supply
capacity is limited such as in battery applications.
Holtek¢s telephone controllers support two system
clocks and four operational modes. The system clock
can be either 32768Hz or HCLK and the operational
mode can be either Normal, Green, Sleep or Idle mode.
The operation mode is selected using software in the
following way:
·
Normal mode to Green mode:
Clear bit MODE1 to ²0², which will change the opera-
tional mode to the Green mode.
The UPEN bit status is not changed. However, the
UPEN bit can be cleared by software.
·
Normal mode or Green mode to Sleep mode:
Step 1: Clear bit MODE0 to ²0²
Step 2: Clear bit MODE1 to ²0²
Step 3: Clear bit UPEN to ²0²
Sleep Mode
In the Sleep Mode is similar to the mode, except here
the 32768Hz oscillator continues running after after the
HALT instruction has been executed. This feature en-
ables the device to continue with instruction execution
immediately after wake-up.
Step 4: Execute the HALT instruction
After Step 4, the operational mode will be changed to
the Sleep mode.
·
Normal mode or Green mode to Idle Mode:
Step 1: Set bit MODE0 to ²1²
Step 2: Clear bit MODE1 to ²0²
Step 3: Clear bit UPEN to ²0²
Step 4: Execute the HALT instruction
After Step 4, the operational mode will be changed to
the Idle Mode.
Green Mode
In the Green Mode, the 32768Hz oscillator is used as
the system clock for instruction execution. The following
conditions will force the microcontroller enter the Green
Mode:
·
Green Mode to Normal Mode:
·
Any reset condition from any operational mode
Step 1: Set bit UPEN to ²1²
Step 2: Execute a 20ms software delay
Step 3: Set bit MODE1 to ²1²
·
Any interrupt occurring during the Sleep Mode or Idle
mode
After Step 3, the operational mode will be changed to
the Normal mode.
·
A Port A Wake-up from the Sleep Mode or Idle Mode
Normal Mode
·
Sleep mode or Idle mode to Green mode:
Method 1: The occurrence of any reset condition
Method 2: Any active interrupt
In the Normal mode the device uses the HCLK gener-
ated by the frequency-up conversion circuit as the sys-
tem clock for instruction execution.
Method 3: A Port A wake-up
Note that a Timer/Event Counter 0/1 and RTC interrupt
will not be generated when in the Idle mode as the
32768Hz crystal oscillator is stopped.
There are four high frequency HCLK system clock se-
lections which are 3.58MHz, 7.16MHz, 10.74MHz and
14.32MHz. When the system is in the Normal Mode
care must be taken when dynamically changing the
HCLK system clock, and for which the following proce-
dure is recommended:
1. Clear bit MODE1 to ²0² to select the Slow Mode
2. Clear UPEN bit to ²0²
3. Program the MODE_1 register bits to select the
required HCLK frequency
4. Set the UPEN bit to ²1²
5. Implement a 20ms software delay to allow the high
frequency clock to stabilise
6. Set the MODE1 bit to ²1² to select the HCLK system
clock
After step 6 above is executed the system clock will be
changed to that defined in the MODE_1 register.
Rev. 1.00
47
March 12, 2010
HT95R45
Standby Current Considerations
Once a Sleep mode or Idle mode Wake-up event oc-
curs, it will take an SST delay time, which is 1024 sys-
tem clock periods, to resume to the Green mode. This
means that a dummy period is inserted after a Wake-up.
If the Wake-up results from an interrupt acknowledge
signal, the actual interrupt subroutine execution will be
delayed by one or more cycles. If the Wake-up results in
the next instruction execution, this will be executed im-
mediately after the dummy period has finished.
As the main reason for entering the Power Down Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimised. Special atten-
tion must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either
a fixed high or low level as any floating input pins could
create internal oscillations and result in increased cur-
rent consumption. Care must also be taken with the
loads, which are connected to I/Os, which are setup as
outputs. These should be placed in a condition in which
minimum current is drawn or connected only to external
circuits that do not draw current, such as other CMOS
inputs. Also note that additional standby current will also
be required if the configuration options have enabled the
Watchdog Timer internal oscillator.
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Sleep Mode
or Idle Mode.
The Sleep Mode or Idle Mode is initialised by a HALT in-
struction and results in the following.
·
The system clock will be turned off.
·
The WDT function will be disabled if the WDT clock
source is the instruction clock.
·
The WDT function will be disabled if the WDT clock
source is the 32768Hz oscillator in the Idle mode.
Wake-up
·
The WDT will still function if the WDT clock source is
A reset, interrupt or port A wake-up can all wake up the
device from the Sleep Mode or the Idle Mode. A reset
can include a power-on reset, an external reset or a
WDT time-out reset. By examining the device status
flags, PDF and TO, the program can distinguish be-
tween the different reset conditions. Refer to the Reset
section for a more detailed description.
the WDT internal oscillator.
·
If the WDT function is still enabled, the WDT counter
and WDT prescaler will be cleared and resume count-
ing.
·
The contents of the on chip Data Memory and regis-
ters remain unchanged.
A port A wake-up and an interrupt can be considered as
a continuation of normal execution. Each bit in port A
can be independently selected to wake-up the device
using configuration options. When awakened by a Port
A stimulus, the program will resume execution at the
next instruction following the HALT instruction.
·
All the I/O ports maintain their original status.
·
The PDF flag is set and the TO flag is cleared by hard-
ware.
Any valid interrupt during the Sleep Mode or Idle Mode
may have one of two consequences. One is if the re-
lated interrupt is disabled or the interrupt is enabled but
the stack is full, the program will resume execution at the
next instruction. The other is if the interrupt is enabled
and the stack is not full, the regular interrupt response
takes place. It is necessary to mention that if an interrupt
request flag is set to "1" before entering the Sleep mode
or Idle mode, the Wake-up function of the related inter-
rupt will be disabled.
Rev. 1.00
48
March 12, 2010
HT95R45
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown lo-
cations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a de-
vice reset when the WDT counter overflows. The WDT
clock is supplied by one of three sources selected by a
configuration option. These can be its own
self-contained dedicated internal WDT oscillator, exter-
nal 32768Hz or the instruction clock which is the system
clock divided by 4. Note that if the WDT configuration
option has been disabled, then any instruction relating
to its operation will result in no operation.
Under Normal Mode and Green Mode operation, a WDT
time-out will initialise a device reset and set the status bit
TO. However, if the system is in the Sleep Mode or Idle
Mode, when a WDT time-out occurs, only the Program
Counter and Stack Pointer will be reset. Three methods
can be adopted to clear the contents of the WDT and the
WDT prescaler. The first is an external hardware reset,
which means a low level on the RES pin, the second is
using the watchdog software instructions and the third is
via a ²HALT² instruction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the sin-
gle ²CLR WDT² instruction while the second is to use
the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will
clear the WDT while for the second option, both ²CLR
WDT1² and ²CLR WDT2² must both be executed to
successfully clear the WDT. Note that for this second
option, if ²CLR WDT1² is used to clear the WDT, succes-
sive executions of this instruction will have no effect,
only the execution of a ²CLR WDT2² instruction will
clear the WDT. Similarly, after the ²CLR WDT2² instruc-
tion has been executed, only a successive ²CLR WDT1²
instruction can clear the Watchdog Timer.
A configuration option can select the instruction clock,
which is the system clock divided by 4, as the WDT clock
source instead of the internal WDT oscillator. If the in-
struction clock is used as the clock source, it must be
noted that when the system enters the Power Down
Mode, as the system clock is stopped, then the WDT
clock source will also be stopped. Therefore the WDT
will lose its protecting purposes. In such cases the sys-
tem cannot be restarted by the WDT and can only be re-
started using external signals. For systems that operate
in noisy environments, using the internal WDT oscillator
or 32768Hz oscillator is therefore the recommended
choice.
b
7
b
0
W
S
2
W
S
W
1
S
0
W
D
T
S
R
e
g
i
s
t
e
r
W
D
T
p
r
e
s
c
a
l
e
r
r
a
t
e
s
W
S
2
S
1
W
S
0
W
D
T
R
a
t
e
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
:
:
:
:
1
2
4
8
1
:
1
6
1
1
1
:
:
:
3
6
1
2
4
2
8
N
o
t
u
s
e
d
Watchdog Timer Register
C
L
R
W
D
T
1
F
l
a
g
r
C
l
e
a
W
D
T
T
y
p
e
C
o
n
f
i
g u
g
r
a
t
i
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n
O
p
t
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n
C
L
R
W
D
T
2
F
l
a
1
o
r
2
I
n
s
t
r
u
c
t
i
o
n
s
C
L
R
f
S
Y
S
W
D
T
C
l
o
c
k
S
o
u
r
c
e
f
S
W
D
T
O
s
c
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C
l
o
l
a
n
t
f
o
i
g
r
u
r
9
a
-
t
b
i
o
i
t
n
C
o
u
n
t
e
r
t
7
-
b
i
C
o
u
n
t
e
r
3
2
7
6
8
H
z
O
p
t
i
o
n
W
D
T
C
l
o
c
k
S
o
u
r
c
e
8
-
t
o
-
1
M
W
U
S
X
0
~
W
S
2
W
D
T
T
i
m
e
-
o
u
t
Watchdog Timer
Rev. 1.00
49
March 12, 2010
HT95R45
DTMF Generator
The device includes a fully integrated DTMF, Dual-Tone Multiple-Frequency, generator function. This functional block
can generate the necessary16 dual tones and 8 single tones for DTMF signal generation. The signal will be provided on
the DTMF pin of the device. The DTMF generator also includes a power down and a tone on/off function. The clock
source for the DTMF generator is the 3.58MHz oscillator. Before the DTMF function is used, the device must have been
placed into the Normal mode.
DTMF Generator Control
The DTMF Generator is controlled by two registers, a control register known as DTMFC and a data register known as
DTMFD. The power down mode will terminate all the DTMF generator functions and can be activated by setting the
D_PWDN bit in the DTMFC register to 1. These two registers, DTMFC and DTMFD are still accessible even if the
DTMF function is in the power down mode. The generation duration time of the DTMF output signal should be deter-
mined by the software. The DTMFD register value can be changed as desired, at which point the DTMF pin will output
the new dual-tone simultaneously.
b
7
b
0
T
O
N
E
D
_
P
W
D
D
T
N
M
F
C
R
e
g
i
s
t
e
r
D
1
0
T
M
F
G
e
n
e
r
a
t
o
r
P
o
w
e
:
:
e
d
n
i
a
b
l
e
s
a
b
l
e
N
o
t
i
m
p
l
e
m
e
n
t
e
d
,
r
e
a
T
1
0
o
n
e
O
u
t
p
u
t
E
n
a
b
l
e
:
:
e
d
n
i
a
b
l
e
s
a
b
l
e
N
o
t
i
m
p
l
e
m
e
n
t
e
d
,
r
e
a
DTMF Generator Control Register
DTMF Generator Frequency Selection
The DTMF pin output is controlled using a combination of the D_PWDN, TONE, TR~TC bits.
C
O
L
1
C
O
L
2
C
O
L
3
C
O
L
4
2
5
8
0
3
6
9
#
A
B
1
4
7
R
R
R
R
O
O
O
O
W
W
W
W
1
2
3
4
C
D
*
DTMF Dialing Matrix
b
7
b
0
T
R
4
T
R
3
T
R
2
T
R
1
T
C
D
4
T
M
T
F
C
D
3
T
C
2
T
C
1
H
i
g
h
g
r
o
u
p
(
c
o
l
u
m
n
)
t
o
L
o
w
g
r
o
u
p
(
r
o
w
)
t
o
n
e
f
DTMF Generator Data Register
Control Register Bits
DTMF Pin Output Status
D_PWDN
TONE
TR4~TR1/TC4~TC1
1
0
0
0
x
0
1
1
x
x
0
0
1/2 VDD
1/2 VDD
Any valid value
16 dual tones or 8 signal tones, bias at 1/2 VDD
Rev. 1.00
50
March 12, 2010
HT95R45
Output Frequency (Hz)
% Error
Specified
697
Actual
699
+0.29%
-0.52%
-0.59%
+0.74%
+0.50%
-0.30%
-0.34%
770
766
852
847
941
948
1209
1336
1477
1215
1332
1472
% Error does not contain the crystal frequency shift
DTMF Frequency Selection Table
Low Group
High Group
DTMF Output
Code
TR4
0
TR3
0
TR2
0
TR1
1
TC4
0
TC3
0
TC2
0
TC1
1
Low
697
697
697
697
770
770
770
770
852
852
852
852
941
941
941
941
High
1209
1336
1477
1633
1209
1336
1477
1633
1209
1336
1477
1633
1209
1336
1477
1633
1
2
3
A
4
5
6
B
7
8
9
C
*
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
#
D
1
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
Single tone for testing only
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
697
770
852
941
x
x
x
x
x
x
x
x
x
x
x
x
x
1209
1336
1477
1633
x
x
x
Writing other values to TR4~TR1, TC4~TC1 may generate an unpredictable tone.
D
_
P
D
W
N
=
1
D
_
P
D
W
N
=
0
1
/
2
V
D
D
T
A
O
N
E
=
1
T
O
N
E
=
0
T
O
N
E
=
T
O
N
E
=
0
T
O
N
E
=
1
T
O
N
E
=
1
l
l
t
h
e
t
i
m
i
n
g
o
f
t
h
e
T
O
N
E
=
1
a
n
d
T
O
N
E
=
0
a
r
e
d
e
DTMF Output
Rev. 1.00
51
March 12, 2010
HT95R45
DTMF Receiver
The device contains a fully integrated DTMF receiver which will decode the DTMF frequency content of incoming ana-
log DTMF signals. An internal operational amplifier is also supplied to adjust the input signal level as shown. There is
also a pre-filter function which is a band rejection filter tp reject frequencies between 350Hz and 400Hz. The low group
filter filters the low group frequency signal output, whereas the high group filter filters the high group frequency signal
output. Each filter output is followed by a zero-crossing detector which includes hysteresis. When the signal amplitude
at the output exceeds a specified level, it is transferred into a full swing logic signal.
(
a
)
S
t
a
n
d
a
r
d
I
n
p
u
t
C
i
r
c
(
u
b
i
)
t
D
i
f
f
e
r
e
n
t
i
a
l
I
n
p
u
t
C
C
1
R
1
V
V
P
N
V
V
P
N
V
i
i
1
2
C
R
1
V
V
i
R
2
C
2
R
3
R
4
R
5
R
F
G
V
S
G
V
S
R
E
F
R
E
F
When the input signal is recognized as an effective DTMF tone, a peripheral interrupt will be generated, and the corre-
sponding DTMF tone code will be generated.
Bit No.
Label
R/W
Function
DTMF Receiver Power Down Enable
R_PWDN= 0 ® The DTMF receiver is in normal mode;
R_PWDN= 1 ® The DTMF receiver is in power down mode
After reset, R_PWDN = 1
0
R_PWDN
RW
Inhibit the detection of tones representing characters A, B, C and D
R_INH= 0 ® detect tones representing characters A, B, C and D
R_INH= 1 ® ignore tones representing characters A, B, C and D
After reset, R_INH = 0
1
R_INH
RW
Data valid output flag
2
R_DV
RW
RO
R_DV= 0 ® There is no valid DTMF tone received
R_DV= 1 ® There is a valid DTMF tone received
7~3
¾
Unused bit, read as ²0²
Note: R_DV should be cleared manually if necessary.
DTMF Receiver Status
b
7
b
0
R
_
D
R
V
_
I
R
N
_
H
P
W
D
D
T
N
R
X
C
R
e
g
i
s
t
e
r
D
1
0
T
M
F
R
e
c
e
i
v
e
r
P
o
w
e
r
D
o
w
:
:
t
t
h
h
e
e
D
T
M
F
r
e
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DTMF Receiver Control Register
b
7
b
0
R
_
R
D
_
3
D
2
R
_
D
D
T
1
R
R
X
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D
D
0
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N
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n
t
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d
,
r
e
a
d
DTMF Receiver Data Register
Rev. 1.00
52
March 12, 2010
HT95R45
DTMF Data Output Table
Low Group (Hz)
697
High Group (Hz)
1209
Digit
1
D3, D2, D1, D0
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
697
1336
2
697
1477
3
770
1209
4
770
1336
5
770
1477
6
852
1209
7
852
1336
8
852
1477
9
941
1336
0
941
1209
*
941
1477
#
697 (Note*)
770 (Note*)
842 (Note*)
941 (Note*)
1633
A
B
C
D
1633
1633
1633
(Note*): Available only when R_INH=0
Steering Control Circuit
The steering control circuit is used to measure the effective signal duration and for protecting against a valid signal drop
out. This is achieved using an analog delay which is implemented using an external RC time-constant, controlled by the
output line EST.
The timing diagram shows more details. The EST pin is normally low and will pull the RT/GT pin low via the external RC
network. When a valid tone input is detected, the EST pin will go high, which will in turn pull the RT/GT pin high through
the RC network.
When the voltage on RT/GT rises from 0 to VTRT, which is 2.35V for a 5V power supply, the input signal is effective, and
the corresponding code will be generated by the code detector. After D0~D3 have been latched, DV will go high. When
the voltage on RT/GT falls from VDD to VTRT, i.e. when there is no input tone, the DV output will go low, and D0~D3 will
maintain their present data until a next valid tone input is produced. By selecting suitable external RC values, the mini-
mum acceptable input tone duration, tACC, and the minimum acceptable inter-tone rejection, tIR, can be set. The values
of the external RC components, can be chosen using the following formula.
t
ACC=tDP+tGTP
IR=tDA+tGTA
;
t
;
t
t
t
t
ACC: Tone duration acceptable time
DP: EST output delay time (²L² ® ²H²)
GTP: Tone present time
Where
IR: Inter-digit pause rejection time
tDA: EST outptu delay time (²H² ® ²L²)
t
GTA: Tone absent time
Rev. 1.00
53
March 12, 2010
HT95R45
Timing Diagrams
t
I
A
t
I
R
t
R
E
J
T
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T
o
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e
n
T
o
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n
+
1
t
D
P
t
D
P
t
D
A
t
D
P
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A
C
C
V
T
R
T
R
T
/
G
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t
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T
P
t
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T
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t
P
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C
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T
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n
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e
1
C
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n
T
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e
C
D
0
~
D
3
t
P
D
V
t
D
O
V
t
P
D
V
D
V
t
D
D
O
t
E
D
O
O
E
Steering Timing
T
o
n
e
T
o
n
e
P
W
D
N
E
S
T
t
P
U
Power-up Timing
Rev. 1.00
54
March 12, 2010
HT95R45
(c) tGTP > tGTA
:
(a) Fundamental circuit:
t
GTP = R1 ´ C ´ Ln (VDD / (VDD - VTRT))
t
GTP = R ´ C ´ Ln (VDD / (VDD - VTRT))
GTA = R ´ C ´ Ln (VDD / VTRT
t
GTA = (R1 // R2) ´ C ´ Ln (VDD / VTRT
)
t
)
V
D
D
V
D
D
V
D
D
V
D
D
C
C
R
T
/
G
T
R
T
/
G
T
R
1
R
E
S
T
E
S
T
D
1
R
2
(b) tGTP < tGTA
:
t
GTP = (R1 // R2) ´ C ´ Ln (VDD - VTRT))
GTA = R1 ´ C ´ Ln (VDD / VTRT
t
)
V
D
D
V
D
D
C
R
T
/
G
T
R
1
E
S
T
D
1
R
2
Steering Time Adjustment Circuits
Call Progress Tone Detector
This Device fully integrated the CPT detector, which has the advantages of low power consumption, wide CPT Band
detection range from 305Hz to 640Hz, as well as high performance, is very suitable for Auto-dialing system in Telecom
applications.
The internal call progress tone detector can be used in world wide countries. Below is an illustration of a call progress
tone frequency band, and a table of U.S.A. CPT signal is shown for user reference.
The designer can use a GPIO pin to detect the output signal, through software to distinguish correct cadence of CTP to
fit any country CPT SPEC requirement for world wide application purposes. Note that the CPT detector can be disabled
by CPTEN pin. The designer can use an external GPIO pin to enable and disable the CPT decoder in order to reduce
power consumption.
L
e
v
e
l
0
d
B
m
C
P
T
I
n
-
b
a
n
d
D
e
t
e
c
t
e
d
R
e
j
e
c
t
e
d
B
a
n
d
R
e
j
e
c
t
e
d
B
a
n
-
2
7
d
B
m
-
5
0
d
B
m
F
r
e
q
2
0
0
H
3
z
0
5
H
z
6
4
0
H
z
8
0
0
H
z
Call progress tone frequency band illustration
Rev. 1.00
55
March 12, 2010
HT95R45
U.S.A. Call Progress Tone Signal Format
Tone
Frequency
Condition
Continuous high
Continuous high
Precision Dial Tone
Old Dial Tone
350Hz+440Hz
120Hz (or 133Hz, ..) +600Hz
480Hz+620Hz
Precision Busy Tone
Old Busy Tone
0.5sec high and 0.5sec low
0.5sec high and 0.5sec low
0.3sec high and 0.2sec low
120Hz+600Hz
Precision Reorder Tone
480Hz+620Hz
0.2sec high and 0.3sec low or
0.25sec high and 0.25sec low
Old Reorder Tone
120Hz+600Hz
Precision Ring-back Tone
Old Ring-back Tone
440Hz+480Hz
2sec high and 4sec low
2sec high and 4sec low
40Hz (or the others) +420Hz
Timing Diagram
C
P
T
E
N
t
R
D
t
B
t
D
D
t
Q
I
C
P
T
S
I
N
t
D
H
t
D
L
C
P
T
E
N
V
t
S
T
C
P
T
X
1
,
C
P
T
X
2
Rev. 1.00
56
March 12, 2010
HT95R45
Programmable Frequency Divider (PFD) Generator - MUSIC
A Programmable Frequency Divider function, otherwise known as PFD, is integrated within the microcontroller, providing
a means of accurate frequency generation. It is composed of two functional blocks: a prescaler and a general counter.
P
r
e
s
c
a
l
e
r
M
U
S
I
C
P
F
D
3
2
7
6
8
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z
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t
p
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t
p
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3
.
5
8
M
H
z
/
4
B
u
z
z
e
r
P
R
E
S
1
,
P
R
E
S
0
P
F
D
E
N
PFD Control Register
The overall PFD function is controlled using the PFDC register. The prescaler is controlled by the register bits, PRES0
and PRES1. The general counter is programmed by an 8-bit register PFDD. The clock source for the PFD can be se-
lected to be either the 3.58MHz/4 or the 32768Hz oscillator. To enable the PFD output, the PFDEN bit should be set to
1. When the PFD is disabled the PFDD register is inhibited to be written to. To modify the PFDD contents, the PFD must
be enabled. When the generator is disabled, the PFDD is cleared by hardware.
b
7
b
0
F
P
F
D
P
R
E
P
S
F
1
D
P
E
R
N
E
S
0
P
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a
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1
0
1
:
:
:
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P
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c
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:
:
3
3
.
2
5
8
M
H
z
/
4
7
6
8
H
z
PFD Data Register
Bit No.
Label
R/W
Function
7~0
RW
PFD data register
PFDD (2FH) Register
¾
Prescaler_Output
PFD_Output_Frequency=
, where N = the value of the PFD Data
2x(N+1)
Rev. 1.00
57
March 12, 2010
HT95R45
RTC Function
When RTC 1000ms time-out occurs, the hardware will set the interrupt request flag RTCF and the RTCTO flag to ²1².
When the interrupt service routine is serviced, the interrupt request flag (RTCF) will be cleared to 0, but the flag RTCTO
remains in its original values. This bit (RTCTO) should be cleared only by software. However, next RTC interrupt will
still occur, even though the RTCTO flag is not cleared.
b
7
b
0
R
T
C
T
O
R
T
C
E
N
R
T
C
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:
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N
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m
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d
,
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e
a
R
1
0
T
C
T
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e
-
o
u
t
F
l
a
g
:
:
R
R
T
C
t
i
m
e
-
o
u
t
o
c
c
u
T
C
t
i
m
e
-
o
u
t
d
o
e
s
Voice Output
b
7
b
0
Voice Control
D
3
D
2
D
1
D
0
D
A
L
R
e
g
The voice control register controls the DAC circuit. If the
DAC circuit is not enabled, any DAH/DAL outputs will be
invalid. Selection the configuration option of PC1/AUD
for DAC audio output first and writing a ²1² to the
DACEN bit will enable the DAC circuit, while writing a
²0² to the DAC bit will disable the DAC circuit.
N
o
t
u
s
e
d
A
u
d
i
o
o
u
Digital to Analog Data Low Register
b
7
b
0
D
1
1
D
1
0
D
D
7
9
D
D
6
8
D
D
5
A
D
H
4
R
Audio Output and Volume Control -
DAL, DAH, VOL, VOICEC
A
u
d
i
o
The audio output is 12-bits wide whose highest 8-bits
are written into the DAH register and whose lowest four
bits are written into the highest four bits of the DAL regis-
ter. Bits 0~3 of the DAL register are always read as zero.
There are 8 levels of volume which are setup using the
VOL register. Only the highest 3-bits of this register are
used for volume control, the other bits are not used and
read as zero.
Digital to Analog Data High Register
b
7
b
0
V
O
L
2
V
O
L
1
V
O
L
0
V
O
L
R
e
g
i
N
o
t
u
s
e
d
,
D
A
v
o
l
u
m
Volume Control Register
b
7
b
0
D
A
C
V
E
O
N
I
C
E
C
R
e
g
D
1
0
A
C
E
n
a
b
l
e
:
e
n
a
b
l
e
:
d
i
s
a
b
l
e
N
o
t
i
m
p
l
e
m
e
VOICE Control Register
Rev. 1.00
58
March 12, 2010
HT95R45
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the program-
ming process. During the development process, these options are selected using the HT-IDE software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later by the application software.
All options must be defined for proper system function, the details of which are shown in the table.
Name
Options
Port A wake-up selection.
Define the activity of wake-up function.
Wake-up PA
All port A have the capability to wake-up the chip from a HALT.
This wake-up function is selected per bit.
Pull-high option.
Pull-high PA
This option determines whether the pull-high resistance is viable or not.
Port A pull-high option is selected per bit.
Port C pull-high option is selected per bit.
Port D pull-high option is selected per nibble.
Port E pull-high option is selected per nibble.
Port F pull-high option is selected per nibble.
Port G pull-high option is selected per nibble.
Pull-high PC0~PC1
Pull-high PC4~PC7
Pull-high PD
Pull-high PE
Pull-high PF
Pull-high PG
This option defines how to clear the WDT by instruction.
One clear instruction ® The ²CLR WDT² can clear the WDT.
Two clear instructions ® Only when both of the ²CLR WDT1² and ²CLR WDT2² have been ex-
ecuted, then WDT can be cleared.
CLRWDT
WDT
Watchdog enable/disable
WDT clock source selection
RC ® Select the WDT OSC to be the WDT source.
T1 ® Select the instruction clock to be the WDT source.
32kHz ® Select the external 32768Hz to be the WDT source.
WDT Clock Source
LVR
Low Voltage Reset enable or disable
LVR Voltage
SPI Options
SIM
Low Voltage Reset voltage; 2.1V, 3.15V or 4.2V
Enable/disable
SPI_WCOL
SPI_CSEN
I2C Option
Enable/disable
Enable/disable, used to enable/disable (1/0) software CSEN function
I2C debounce Time No debounce, 1 system clock debounce, 2 system clock debounce
AUD Option
DAC output
Enable/disable
Rev. 1.00
59
March 12, 2010
HT95R45
Application Circuits
DTMF Receiver Single-ended Input Application Circuits
T
e
l
e
p
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C
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c
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D
D
P
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P
0
C
5
P
C
7
P
C
1
~
P
C
4
,
P
C
6
0
.
m
F
1
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0
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k
S
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h
2
S
P
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y
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F
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k
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F
1
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0
k
V
G
N
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E
S
0
m
. F 1
0
m
. F 1
1
0
W
0
k
S
5
.
1
V
V
D
D
V
D
D
1
m
0 F 0
0
.
m
F
1
I
/
O
1
4
7
2
5
8
0
3
6
9
#
K
K
K
K
e
e
e
e
y
y
y
y
K
K
K
K
1
2
3
4
e
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y
y
y
y
K
5
6
7
8
e
y
9
K
K
K
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y
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1
1
1
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1
2
I
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1
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k
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N
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V
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F
0
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m
m
0
F
1
1
0
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W
0
k
I
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7
W
0
k
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V
-
R
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2
0
p
F
1
1
0
0
k
0
.
0
F
X
X
2
1
3
2
7
6
8
H
z
1
0
W
0
k
C
C
P
P
T
T
X
X
2
1
3
2
7
6
8
H
z
T
T
M
R
T
M
0
R
1
X
C
V
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N
1
5
W
k
3
n
F
4
7
n
F
Rev. 1.00
60
March 12, 2010
HT95R45
Instruction Set
Introduction
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to en-
sure correct handling of carry and borrow data when re-
sults exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Central to the successful operation of any
microcontroller is its instruction set, which is a set of pro-
gram instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of pro-
gramming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several func-
tional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on pro-
gram requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruc-
tion cycle. The exceptions to this are branch, call, or ta-
ble read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be im-
plemented within 1ms. Although instructions which re-
quire one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instruc-
tions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to imple-
ment. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instruc-
tions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the re-
sult of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a sub-
routine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the sub-
routine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made re-
garding the condition of a certain data memory or indi-
vidual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the pro-
gram perhaps determined by the condition of certain in-
put switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific imme-
diate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Mem-
ory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The fea-
ture removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write pro-
cess is taken care of automatically when these bit oper-
ation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² in-
struction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electro-
magnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be con-
sulted as a basic instruction reference using the follow-
ing listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using regis-
ters. However, when working with large amounts of
fixed data, the volume involved often makes it inconve-
nient to store the fixed data in the Data Memory. To over-
come this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instruc-
tions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Mnemonic
Arithmetic
Description
Cycles Flag Affected
ADD A,[m]
ADDM A,[m]
ADD A,x
Add Data Memory to ACC
1
1Note
1
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
Add ACC to Data Memory
Add immediate data to ACC
ADC A,[m]
ADCM A,[m]
SUB A,x
Add Data Memory to ACC with Carry
1
1Note
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
1
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
1
1Note
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1Note
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1Note
1Note
1
OR A,x
1
XOR A,x
1
1Note
CPL [m]
CPLA [m]
Complement Data Memory with result in ACC
1
Increment & Decrement
INCA [m]
INC [m]
Increment Data Memory with result in ACC
1
Z
Z
Z
Z
Increment Data Memory
1Note
DECA [m]
DEC [m]
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
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Mnemonic
Rotate
Description
Cycles Flag Affected
RRA [m]
RR [m]
Rotate Data Memory right with result in ACC
Rotate Data Memory right
1
1Note
1
1Note
1
1Note
None
None
C
RRCA [m]
RRC [m]
RLA [m]
RL [m]
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
C
None
None
C
RLCA [m]
RLC [m]
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
C
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Bit Operation
CLR [m].i
SET [m].i
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Branch
JMP addr
SZ [m]
Jump unconditionally
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Skip if Data Memory is zero
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
Return from subroutine
2
RET A,x
RETI
Return from subroutine and load immediate data to ACC
Return from interrupt
2
2
Table Read
TABRDC [m]
TABRDL [m]
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
Miscellaneous
NOP
No operation
1
1Note
1Note
1
None
None
CLR [m]
Clear Data Memory
SET [m]
Set Data Memory
None
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Clear Watchdog Timer
TO, PDF
TO, PDF
TO, PDF
None
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1
1Note
1
None
1
TO, PDF
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then in-
crements by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruc-
tion.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Operation
Each bit of the specified Data Memory is cleared to 0.
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is cleared to 0.
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Description
Operation
Clear Watchdog Timer
The TO, PDF flags and the WDT are all cleared.
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-
tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-
petitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-
sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-
ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Operation
Data in the specified Data Memory is decremented by 1.
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-
mulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Operation
Data in the specified Data Memory is incremented by 1.
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-
lator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Description
Operation
Move Data Memory to ACC
The contents of the specified Data Memory are copied to the Accumulator.
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
Operation
The immediate data specified is loaded into the Accumulator.
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Description
Operation
Move ACC to Data Memory
The contents of the Accumulator are copied to the specified Data Memory.
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
Operation
Affected flag(s)
No operation is performed. Execution continues with the next instruction.
No operation
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-
ation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-
ation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the re-
stored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by set-
ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed be-
fore returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-
main unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-
tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-
places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are sub-
tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-
sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Operation
Each bit of the specified Data Memory is set to 1.
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Operation
Bit i of the specified Data Memory is set to 1.
[m].i ¬ 1
Affected flag(s)
None
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SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy in-
struction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumu-
lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-
tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.00
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March 12, 2010
HT95R45
SWAP [m]
Description
Operation
Swap nibbles of Data Memory
The low-order and high-order nibbles of the specified Data Memory are interchanged.
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruc-
tion.
Operation
Skip if [m] = 0
None
Affected flag(s)
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-
tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-
quires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
None
Affected flag(s)
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.00
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March 12, 2010
HT95R45
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-
eration. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-
eration. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.00
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March 12, 2010
HT95R45
Package Information
64-pin LQFP (7mm´7mm) Outline Dimensions
C
D
H
G
4
8
3
3
I
3
2
4
9
F
A
B
E
6
4
1
7
a
K
J
1
1
6
Dimensions in inch
Symbol
Min.
0.350
0.272
0.350
0.272
¾
Nom.
¾
Max.
A
B
C
D
E
F
G
H
I
0.358
0.280
0.358
0.280
¾
¾
¾
¾
0.016
0.005
0.053
¾
0.009
0.057
0.063
0.006
0.030
0.008
7°
¾
¾
¾
¾
¾
¾
¾
0.002
0.018
0.004
0°
J
K
a
Dimensions in mm
Symbol
Min.
8.90
6.90
8.90
6.90
¾
Nom.
¾
Max.
9.10
7.10
9.10
7.10
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
0.40
0.13
1.35
¾
0.23
1.45
1.60
0.15
0.75
0.20
7°
¾
¾
¾
¾
¾
¾
¾
0.05
0.45
0.09
0°
J
K
a
Rev. 1.00
74
March 12, 2010
HT95R45
80-pin LQFP (10mm´10mm) Outline Dimensions
C
D
H
G
6
0
4
1
I
6
1
4
0
F
A
B
E
8
0
2
1
a
K
J
1
2
0
Dimensions in inch
Symbol
Min.
0.469
0.390
0.469
0.390
¾
Nom.
¾
Max.
A
B
C
D
E
F
G
H
I
0.476
0.398
0.476
0.398
¾
¾
¾
¾
0.016
0.006
¾
¾
0.053
¾
0.057
0.063
¾
¾
¾
0.004
¾
¾
J
0.018
0.004
0°
0.030
0.008
7°
K
a
¾
¾
Dimensions in mm
Symbol
Min.
11.90
9.90
11.90
9.90
¾
Nom.
¾
Max.
12.10
10.10
12.10
10.10
¾
A
B
C
D
E
F
G
H
I
¾
¾
¾
0.40
0.16
¾
¾
1.35
¾
1.45
1.60
¾
¾
¾
0.10
¾
¾
J
0.45
0.10
0°
0.75
0.20
7°
K
a
¾
¾
Rev. 1.00
75
March 12, 2010
HT95R45
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
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Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
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Tel: 86-755-8616-9908, 86-755-8616-9308
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Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2010 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
76
March 12, 2010
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