概述
数据手册HI-15530_08 概述
5V / 3.3V Manchester Encoder / Decoder 5V / 3.3V曼彻斯特编码器/解码器
HI-15530_08 数据手册
通过下载HI-15530_08数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载HI-15530
October 2008
5V / 3.3V Manchester Encoder / Decoder
GENERALDESCRIPTION
FEATURES
! MIL-STD-1553 compatible
The HI-15530 is a high performance CMOS integrated
circuit designed to meet the requirements of MIL-STD-1553
and similar Manchester II encoded, time division
multiplexed serial data protocols. The HI-15530 contains
both an Encoder and Decoder, which operate
independently.
! 5V or 3.3V operation
! Interfaces to HI-1567 Transceiver Family
! Small footprint 24-pin plastic SSOP package
option
The HI-15530 is fully compatible with either 5V or 3.3V logic
and transceivers.
! Direct replacement for:
Harris/Intersil HD15530
The device generates MIL-STD-1553 sync pulses, parity
bits as well as the Manchester II encoding of the data bits.
The decoder recognizes and identifies sync pulses,
decodes data bits, and performs parity checking.
GEC Plessey Semiconductors MAS15530
Aeroflex ACT15530
The HI-15530 supports the 1Mbit/s data rate of MIL-STD-
1553 over the full temperature and voltage range.
! 1.25 Mbit/s Maximum Data Rate
! Manchester II Encode and Decode
! Sync identification and Lock-in
For applications requiring small footprints and low cost, the
HI-15530 is available in a 24-pin plastic SSOP package.
Ceramic DIP and LCC packages are also available to
achieve the highest level of reliability and to provide drop-in
replacements for obsolete parts from other manufacturers.
PIN CONFIGURATION (Top View)
VALID WORD
ENCODER SHIFT CLK
TAKE DATA
1
2
3
4
5
6
7
8
9
24 VDD
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
APPLICATIONS
SERIAL DATA OUT
DECODER CLK
! MIL-STD-1553 Interfaces
! Smart Munitions
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15 BIPOLAR ZERO OUT
14 ¸ 6 OUT
HI-15530PSI
HI-15530PST
HI-15530PSM
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLK
! Stores Management
! Sensor Interfaces
! Instrumentation
COMMAND / DATA SYNC 10
DECODER RESET 11
GND 12
13 MASTER RESET
24 Pin SSOP package
(Additional package pin configurations shown inside data sheet)
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS15530 Rev. J)
10/08
HI-15530
PIN DESCRIPTIONS
SIGNAL
SECTION FUNCTION
DESCRIPTION
VALID WORD
DECODER
OUTPUT
OUTPUT
OUTPUT
A high output signals the receipt of a valid word
Shifts data into the encoder on a low to high transition
Output is high during receipt of data after identification of a Sync
Pulse and two valid Manchester data bits.
ENCODER SHIFT CLOCK ENCODER
TAKE DATA
DECODER
SERIAL DATA OUT
DECODER CLOCK
DECODER
DECODER
OUTPUT
INPUT
Received Data output in NRZ format
12x the data rate. Clock for the transition finder and synchronizer,
which generates the internal clock for the remainder of the decoder
A high input indicates the 1553 bus is in its negative state.
This pin must be held high when the Unipolar input is used
A high input indicates the 1553 bus is in the positive state.
This pin must be held low when the Unipolar input is used
Input for unipolar data to the transition finder. Must be held low when
Not in use
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER
DECODER
DECODER
INPUT
INPUT
INPUT
DECODER SHIFT CLOCK DECODER
OUTPUT
OUTPUT
Provides the DECODER CLOCK divided by 12, synchronized by the
recovered serial data
COMMAND / DATA SYNC
DECODER RESET
DECODER
DECODER
A high on this pin occurs during the output of decoded data which
was preceded by a Command (or Status) synchronizing character. A
low output indicates a Data synchronizing character
A high applied to this pin during a DECODER SHIFT CLOCK rising
edge resets the bit counter
INPUT
GND
BOTH
BOTH
POWER
INPUT
0V supply
MASTER RESET
A high on this pin clears the 2:1 counters in both Encoder and
Decoder and resets the divide-by-6 circuit
¸6 OUT
ENCODER
ENCODER
OUTPUT
OUTPUT
Provides ENCODER CLOCK divided by 6
BIPOLAR ZERO OUT
An active low output intended to drive the zero or negative sense of
a MIL-STD-1553 Line Driver
OUTPUT INHIBIT
ENCODER
ENCODER
INPUT
A low inhibits the BIPOLAR ZERO OUT and BIPOLAR ONE OUT by
forcing them to inactive high states
BIPOLAR ONE OUT
OUTPUT
An active low output intended to drive the one or positive sense on a
MIL-STD-1553 Line Driver
SERIAL DATA IN
ENCODER
ENCODER
INPUT
INPUT
Accepts serial data at the rate of the ENCODER SHIFT CLOCK
A high on this pin initiates the encode cycle. (Subject to the
preceeding cycle being complete)
ENCODER ENABLE
SYNC SELECT
SEND DATA
ENCODER
ENCODER
INPUT
Actuates a Command Sync for an input high and a Data Sync for a
low
OUTPUT
An active high output which enables the external source of serial
Data
SEND CLOCK IN
ENCODER CLOCK
VDD
ENCODER
ENCODER
BOTH
INPUT
INPUT
Clock input at 2 times the Data rate, usually driven by ¸6 OUT
Input to the divide by 6 circuit. Normal frequency is Data rate x12
3.0 V to 5.5 V power supply pin
POWER
HOLT INTEGRATED CIRCUITS
2
HI-15530
ENCODER OPERATION
The Encoder requires a single clock with a frequency of To abort the Encoder transmission a positive pulse must be
twice the desired data rate applied at the SEND CLOCK applied at MASTER RESET. Anytime after or during this
input. An auxiliary divide-by-six counter is provided on chip pulse, a low to high transition on SEND CLOCK clears the
which can be utilized to produce the SEND CLOCK by internal counters and initializes the Encoder for a new
dividing the ENCODER CLOCK.
word.
The Encoder's cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK (1).
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high at SYNC SELECT
input actuates a command sync or a low will produce a
data sync for that word (2). When the Encoder is ready to
accept data, the SEND DATA output will go high and
remain high for sixteen ENCODER SHIFT CLOCK periods
(3). During these sixteen periods the data should be
clocked into the SERIAL DATA IN input with every low-to-
high transition of the ENCODER SHIFT CLOCK (3) - (4).
After the sync and the Manchester II coded data are
transmitted through the BIPOLAR ONE and BIPOLAR
ZERO outputs, the Encoder adds on an additional bit which
is the parity for that word (5). If ENCODER ENABLE is held
high continuously, consecutive words will be encoded
without an interframe gap. ENCODER ENABLE must go
low by time (5) as shown to prevent a consecutive word
from being encoded. At any time a low on the OUTPUT
INHIBIT input will force both bipolar outputs to a high state
but will not affect the Encoder in any other way.
MASTER RESET
OUTPUT
INHIBIT
SEND CLK IN
BIPOLAR
ONE OUT
¸ 6 OUT
¸2
Character
Former
¸6
BIPOLAR
ZERO OUT
ENCODER CLK
Bit
Counter
SYNC
SELECT
SERIAL
DATA
IN
SEND
DATA
ENCODER
SHIFT
CLK
ENCODER
ENABLE
FIGURE 1. ENCODER
TIMING
0
1
2
3
4
5
6
7
15
16
17
18
19
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
DON’T CARE
DON’T CARE
SYNC SELECT
SEND DATA
VALID
SERIAL
DATA IN
15
14
13
12
11
10
3
2
1
0
BIPOLAR
ONE OUT
SYNC
SYNC
SYNC
15
15
14
14
13
13
12
12
11
11
3
3
2
2
1
1
0
P
P
BIPOLAR
ZERO OUT
SYNC
(3)
0
(1) (2)
(4) (5)
FIGURE 2. ENCODER OPERATION
HOLT INTEGRATED CIRCUITS
3
HI-15530
DECODER OPERATION
The Decoder requires a single clock with a frequency of 12 looking for a new sync character to start another output
times the desired data rate applied at the DECODER sequence. VALID WORD will go low approximately 20
CLOCK input. The Manchester II coded data can be DECODER SHIFT CLOCK periods after it goes high if not
presented to the Decoder in one of two ways. The reset low sooner by a valid sync and two valid Manchester
BIPOLAR ONE and BIPOLAR ZERO inputs will accept bits as shown (1). At any time in the above sequence, a
data from a comparator sensed transformer coupled bus as high input on DECODER RESET during a low-to-high
specified in MIL-STD-1553. The UNIPOLAR DATA input transition of DECODER SHIFT CLOCK will abort
can only accept non-inverted Manchester II coded data transmission and initialize the Decoder to start looking for a
(e.g. from BIPOLAR ZERO OUT of an Encoder). The new sync character.
Decoder is free running and continuously monitors its data
input lines for a valid sync character and two valid
TAKE DATA
UNIPOLAR
DATA IN
Manchester data bits to start an output cycle. When a valid
sync is recognized (1), the type of sync is indicated on
BIPOLAR
ONE IN
TRANSITION
FINDER
CHARACTER
IDENTIFIER
COMMAND/DATA SYNC output. If the sync character was
a command sync, this output will go high (2) and remain
high for sixteen DECODER SHIFT CLOCK periods (3),
otherwise it will remain low. The TAKE DATA output will go
high and remain high (2) - (3) while the Decoder is
transmitting the decoded data through SERIAL DATA OUT.
The decoded data available at SERIAL DATA OUT is in an
NRZ format. The DECODER SHIFT CLOCK is provided so
that the decoded bits can be shifted into an external register
on every low-to-high transition of this clock (2) - (3). After all
sixteen decoded bits have been transmitted (3) the data is
checked for odd parity. A high on VALID WORD output (4)
indicates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is
COMMAND/DATA
SYNC
BIPOLAR
ZERO IN
SERIAL DATA
OUT
VALID
WORD
BIT
RATE
CLK
DECODER
CLK
PARITY
CHECK
SYNCHRONIZER
DECODER
SHIFT CLK
MASTER
RESET
DECODER
RESET
BIT
COUNTER
FIGURE 3. DECODER
TIMING
0
1
2
3
4
5
6
7
8
16
17
18
19
DECODER
SHIFT CLK
BIPOLAR
ONE IN
SYNC
SYNC
SYNC
SYNC
15
15
14
14
13
13
12
12
11
11
10
10
2
2
1
1
0
0
P
P
BIPLOAR
ZERO IN
TAKE DATA
COMMAND /
DATA SYNC
SERIAL
DATA OUT
UNDEFINED
15
14
13
12
4
3
2
1
0
May be high from previous reception
VALID WORD
(1)(2)
(3)
(4)
FIGURE 4. DECODER OPERATION
HOLT INTEGRATED CIRCUITS
4
HI-15530
TIMING DIAGRAMS
SEND CLK
t
E1
ENCODER
SHIFT CLK
t
t
E3
E2
VALID
VALID
SERIAL DATA IN
SEND CLK
t
E1
ENCODER
SHIFT CLK
t
t
E6
E4
ENCODER ENABLE
SYNC SELECT
t
E5
VALID
t
E7
ENCODER
SHIFT CLK
t
E8
SEND DATA
SEND CLK
t
E9
BIPOLAR ONE OUT or
BIPOLAR ZERO OUT
ENCODER TIMING
DECODER SHIFT CLK
t
D6
t
COMMAND / DATA SYNC
D7
TAKE DATA
DECODER SHIFT CLK
SERIAL DATA OUT
t
D8
DATA BIT
DECODER SHIFT CLK
t
D9
t
COMMAND / DATA SYNC
D10
TAKE DATA
t
D11
VALID WORD
DECODER SHIFT CLK
DECODER RESET
t
DRH
t
DR
t
DRS
DECODER TIMING
HOLT INTEGRATED CIRCUITS
5
HI-15530
TIMING DIAGRAMS (cont.)
BIT PERIOD
BIT PERIOD
BIT PERIOD
BIPOLAR ONE IN
t
D1
t
D3
t
D3
t
D2
BIPOLAR ZERO IN
t
D1
t
D2
COMMAND SYNC
BIPOLAR ONE IN
BIPOLAR ZERO IN
t
D1
t
D3
t
D3
t
D1
t
t
D2
D2
DATA SYNC
BIPOLAR ONE IN
BIPOLAR ZERO IN
t
t
D1
D1
t
t
D3
D3
t
D3
t
t
D3
D3
t
t
D1
D1
t
t
t
t
D4
D4
D5
D5
ONE
ZERO
ONE
t
D2
UNIPOLAR IN
t
D2
D2
COMMAND SYNC
DATA SYNC
ZERO
t
UNIPOLAR IN
UNIPOLAR IN
t
D2
t
t
D4
D5
t
t
t
D4
D4
D5
ONE
ONE
DECODER TIMING
Bit Period
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
SYNC
TERMINAL ADDRESS R/T
SUBADDRESS
/ MODE
DATA WORD
COUNT
P
P
P
Command Word
SYNC
SYNC
DATA WORD
Data Word
SYNC
SYNC
TERMINAL ADDRESS ME
CODE FOR FAILURE MODES
TF
Status Word
SYNC
MIL-STD-1553 WORD FORMATS
HOLT INTEGRATED CIRCUITS
6
HI-15530
ABSOLUTE MAXIMUM RATINGS
Power Dissipation at 25°C
Plastic SSOP
Ceramic DIP
Supply Voltage VDD
-0.3V to +7V
1.5 W, derate10mW/°C
1.0 W, derate 7mW/°C
DC Current Drain per pin
10mA
Voltage at any pin
-0.3V to Vcc +0.3V
Storage Temperature Range:
-65°C to +150°C
Operating Temperature Range:
Industrial
Hi-Temp
-40°C to +85°C
-55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 3.0 V to 5.5 V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
SYMBOL
CONDITIONS
UNIT
MIN
TYP
MAX
Input Voltage
Input Voltage HI
Input Voltage LO
VIH
VIL
70% VDD
V
V
30% VDD
Clock Input Voltage
Input Leakage Current
Output Voltage
Input Voltage HI
Input Voltage LO
VIHC
VILC
VDD-0.5
-1.0
V
V
0.5V
1.0
Input Sink
Input Source
IIH
IIL
µA
µA
Logic “1” Output Voltage
Logic “0” Output Voltage
VOH1
VOH2
VDD=5V 10%, IOH=-3mA
VDD=3.3V 10%, IOH=-1mA
2.4
90% VDD
V
V
VOL1
VOL2
VDD=5V 10%, IOL=1.8mA
VDD=3.3V 10%, IOH=1mA
0.4
10% VDD
V
V
Standby Supply Current
Operating Supply Current
Input Capacitance
IDDSB
IDD
VIN=VDD, Outputs Open
f=1MHz, Outputs Open
2.0
10.0
7.0
mA
mA
pF
CIN
Output Capacitance
COUT
10.0
pF
HOLT INTEGRATED CIRCUITS
7
HI-15530
AC ELECTRICAL CHARACTERISTICS
VDD = 3.0V to 5.5V, GND = 0V, TA = Operating Temperature Range, CL=50pF
LIMITS
TYP
PARAMETER
SYMBOL
UNITS
MIN
MAX
Encoder Timing
Encoder Clock Frequency
Send Clock Frequency
Encoder Clock Rise Time
Encoder Clock Fall Time
Encoder Data Rate
Master Reset Pulse Width
Shift Clock Delay
fEC
fESC
tECR
tECF
fED
tMR
tE1
0
0
15
2.5
8
MHz
MHz
ns
8
ns
0
1.25
MHz
ns
150
125
ns
Serial Data Setup Time
Serial Data Hold Time
Enable Setup Time
Enable Pulse Width
Sync Setup Time
tE2
75
75
90
80
55
150
0
ns
tE3
ns
tE4
ns
tE5
ns
tE6
ns
Sync Pulse Width
tE7
ns
Send Data Delay
tE8
50
ns
Bipolar Output Delay
Enable Hold Time
tE9
130
ns
tE10
tE11
10
95
ns
Sync Hold Time
ns
Decoder Timing
Decoder Clock Frequency
Decoder Clock Rise Time
Decoder Clock Fall Time
Decoder Data Rate
fDC
tDCR
tDCF
fDD
tDR
tDRS
tDRH
tMR
tD1
0
15
8
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
0
150
75
1.25
Decoder Reset Pulse Width
Decoder Reset Setup Time
Decoder Reset Hold Time
Master Reset Pulse Width
Bipolar Data Pulse Width
Sync Transition Span
One-Zero Overlap
10
150
tDC+10
tD2
18tDC
tD3
tDC-10
Short Data Transition Span
Long Data Transition Span
Sync Delay (On)
tD4
6tDC
tD5
12tDC
tD6
-20
0
110
110
80
Take Data Delay (On)
Serial Data Out Delay
Sync Delay (Off)
tD7
tD8
tD9
0
0
0
110
110
110
Take Data Delay (Off)
Valid Word Delay
tD10
tD11
HOLT INTEGRATED CIRCUITS
8
HI-15530
ADDITIONAL PIN CONFIGURATIONS (See data sheet page 1 for 24-Pin Small Outline SSOP)
4
3
2
1 28 27 26
VALID WORD
ENCODER SHIFT CLK
TAKE DATA
1
2
3
4
5
6
7
8
9
24 VDD
DECODER CLK
N/C
5
6
7
8
9
25
24
23
22
21
20
19
SEND DATA
N/C
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
HI-15530CLI
HI-15530CLT
HI-15530CLM
N/C
N/C
SERIAL DATA OUT
DECODER CLK
BIPOLAR ZERO IN
BIPOLAR ONE IN
SYNC SELECT
ENCODER ENABLE
SERIAL DATA IN
BIPOLAR ONE OUT
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15 BIPOLAR ZERO OUT
14 ¸ 6 OUT
HI-15530CDI
HI-15530CDT
HI-15530CDM
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLK
UNIPOLAR DATA IN 10
DECODER SHIFT CLOCK 11
12 13 14 15 16 17 18
COMMAND / DATA SYNC 10
DECODER RESET 11
GND 12
13 MASTER RESET
24 - Pin Ceramic Side-Brazed DIP
28 - Pin Ceramic LCC
ORDERING INFORMATION
HI - 15530PS x x (Plastic)
LEAD
PART
NUMBER
FINISH
Tin / Lead (Sn / Pb) Solder
Blank
F
100% Matte Tin (Pb-free, RoHS compliant)
TEMPERATURE
BURN
RANGE
IN
PART
NUMBER
FLOW
I
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
I
No
No
T
T
M
M
Yes
PACKAGE
DESCRIPTION
PART
NUMBER
24 PIN PLASTIC SSOP (24HS)
15530PS
See next page for Ceramic package style Ordering Information
HOLT INTEGRATED CIRCUITS
9
HI-15530
ORDERING INFORMATION (cont.)
HI - 15530Cx x (Ceramic)
TEMPERATURE
RANGE
PART
NUMBER
BURN LEAD
IN
FLOW
FINISH
I
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
I
No
Gold (Pb-free, RoHS compliant)
T
No
T
M
Gold (Pb-free, RoHS compliant)
Tin / Lead (Sn / Pb) Solder
M
Yes
PART
NUMBER
PACKAGE
DESCRIPTION
24 PIN CERAMIC SIDE BRAZED DIP (24C)
15530CD
15530CL 28 PIN CERAMIC LEADLESS CHIP CARRIER (28S)
HOLT INTEGRATED CIRCUITS
10
HI-15530
REVISION HISTORY
Revision
Date
Description of Change
DS15530, Rev. J
10/16/08 Corrected package height in Package Dimension drawing for 24-pin ceramic side-brazed
DIP and clarified temperature ranges.
HOLT INTEGRATED CIRCUITS
11
HI-15530 PACKAGE DIMENSIONS
24-PIN PLASTIC SSOP
inches (millimeters)
Package Type: 24HS
.323 .012
(8.20 .30)
.06
typ
(0.15)
.209 .012
(5.30 .30)
.307 .016
(7.80 .40)
See Detail A
.012
(.30)
typ
.073 .0055
(1.86 .14)
0° to 8°
.005 .001
(0.13 .08)
.026
(.650)
BSC
.030 .008
(0.75 .20)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
Detail A
24-PIN CERAMIC SIDE-BRAZED DIP
inches (millimeters)
Package Type: 24C
1.220
(30.988)
max
.595 ±.010
(15.113 ±.254)
.610 ±.010
(15.494 ±.254)
.050
(1.270)
typ
.600 ±.010
(15.240 ±.254)
.085 ±.009
(2.159 ±.229)
.200
max
(5.080)
.010 +.002/-.001
(.254 +.051/-.025)
.125
min
(3.175)
.018
(.457)
.100
(2.54)
typ
BSC
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
12
HI-15530 PACKAGE DIMENSIONS
28-PIN CERAMIC LEADLESS CHIP CARRIER
inches (millimeters)
Package Type: 28S
.080 ±.020
(2.032 ±.508)
.020
(.508)
INDEX
PIN 1
PIN 1
.050 ±.005
(1.270 ±.127)
.451 ±.009
(11.455 ±.229)
SQ.
.050
(1.270)
BSC
.008R .006
(.203R ±.152)
.025 ±.003
(.635 ±.076)
.040 x 45° 3PLS
(1.016 x 45° 3PLS)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
13
HI-15530_08 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| HI-1565 | HOLTIC | 5V Monolithic Dual Transceivers | 获取价格 |
|
| HI-1565CDI | HOLTIC | 5V Monolithic Dual Transceivers | 获取价格 |
|
| HI-1565CDM | HOLTIC | 5V Monolithic Dual Transceivers | 获取价格 |
|
| HI-1565CDT | HOLTIC | 5V Monolithic Dual Transceivers | 获取价格 |
|
| HI-1565PCF | HOLTIC | MIL-STD-1553 Data Bus Transceiver, CMOS, PQCC44, 7 X 7 MM, ROHS COMPLIANT, PLASTIC, LCC-44 | 获取价格 |
|
| HI-1565PCI | HOLTIC | 5V Monolithic Dual Transceivers | 获取价格 |
|
| HI-1565PCIF | HOLTIC | 5V Monolithic Dual Transceivers | 获取价格 |
|
| HI-1565PCM | HOLTIC | 5V Monolithic Dual Transceivers | 获取价格 |
|
| HI-1565PCMF | HOLTIC | 5V Monolithic Dual Transceivers | 获取价格 |
|
| HI-1565PCT | HOLTIC | 5V Monolithic Dual Transceivers | 获取价格 |
|
HI-15530_08 相关文章
Bourns 密封通孔金属陶瓷微调电位计产品选型手册(英文版)
- 2024-09-20
- 6
Bourns 精密环境传感器产品选型手册(英文版)
- 2024-09-20
- 9
Bourns POWrTher 负温度系数(NTC)热敏电阻手册 (英文版)
- 2024-09-20
- 8
Bourns GMOV 混合过压保护组件产品选型手册(英文版)
- 2024-09-20
- 6
