HI-15530 [HOLTIC]
Manchester Encoder / Decoder; 曼彻斯特编码器/解码器
| 型号： | HI-15530 |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | Manchester Encoder / Decoder |
| 文件： | 总11页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-15530
Manchester Encoder / Decoder
July 2001
GENERALDESCRIPTION
FEATURES
! Mil-Std-1553 compatible
! Interfaces to HI-1567 Transceiver
The HI-15530 is a high performance CMOS integrated
circuit designed to meet the requirements of Mil-Std-1553
and similar Manchester II encoded, time division
multiplexed serial data protocols. The HI-15530 contains
both an Encoder and Decoder, which operate
independently.
! Small footprint 24-pin plastic SOIC package
option
The device generates Mil-Std-1553 sync pulses, parity bits
as well as the Manchester II encoding of the data bits. The
decoder recognizes and identifies sync pulses, decodes
data bits, and performs parity checking.
! Direct replacement for:
Harris HD15530
GEC Plessey Semiconductors MAS15530
Aeroflex ACT15530
The HI-15530 supports the 1Mbit/s data rate of Mil-Std-
1553 over the full temperature and voltage range.
! 1.25 Mbit/s Data Rate
For applications requiring small footprints and low cost, the
HI-15530 is available in a 24-pin plastic SOIC package.
Ceramic DIP and LCC packages are also available to
achieve the highest level of reliability and to provide drop-in
replacement for obsolete parts from other manufacturers.
! Manchester II Encode and Decode
! Sync identification and Lock-in
! Clock recovery
PIN CONFIGURATION (Top View)
VALID WORD
ENCODER SHIFT CLK
TAKE DATA
1
2
3
4
5
6
7
8
9
24 VDD
23 ENCODER CLK
22 SEND CLK IN
APPLICATIONS
HI-15530PSI
21 SEND DATA
SERIAL DATA OUT
DECODER CLK
! Mil-Std-1553 Interfaces
! ARINC 708A Interfaces
! Smart Munitions
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15 BIPOLAR ZERO OUT
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLK
! Stores management
! Sensor interfaces
! Instrumentation
COMMAND / DATA SYNC 10
DECODER RESET 11
GND 12
14 ¸ 6 OUT
13 MASTER RESET
24 Pin SOIC package
HOLT INTEGRATED CIRCUITS
(DS15530 Rev. A)
07/01
HI-15530
PIN DESCRIPTIONS
SIGNAL
FUNCTION
DESCRIPTION
VALID WORD
ENCODER SHIFT CLOCK
TAKE DATA
OUTPUT
OUTPUT
OUTPUT
A high output signals the receipt of a valid word
Shifts data into the encoder on a low to high transition
Output is high during receipt of data after identification of a Sync
Pulse and two valid Manchester data bits.
SERIAL DATA OUT
DECODER CLOCK
OUTPUT
INPUT
Received Data output in NRZ format
12x the data rate. Clock for the transition finder and synchronizer,
which generates the internal clock for the remainder of the decoder
A high input indicates the 1553 bus is in its negative state.
This pin must be held high when the Unipolar input is used
A high input indicates the 1553 bus is in the positive state.
This pin must be held low when the Unipolar input is used
Input for unipolar data to the transition finder. Must be held low when
not in use
BIPOLAR ZERO IN
INPUT
INPUT
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLOCK
COMMAND / DATA SYNC
INPUT
OUTPUT
OUTPUT
Provides the DECODER CLOCK divided by 12, synchronized by the
recovered serial data
A high on this pin occurs during the output of decoded data which
was preceded by a Command (or Status) synchronizing character. A
low output indicates a Data synchronizing character
A high applied to this pin during a DECODER SHIFT CLOCK rising
edge resets the bit counter
DECODER RESET
INPUT
GND
MASTER RESET
POWER
INPUT
0V supply
A high on this pin clears 2:1 counters in both Encoder and Decoder,
and resets the divide-by-6 circuit
¸ 6 OUT
BIPOLAR ZERO OUT
OUTPUT
OUTPUT
Provides ENCODER CLOCK divided by 6
An active low output intended to drive the zero or negative sense of a
MIL-STD-1553 Line Driver
OUTPUT INHIBIT
INPUT
A low inhibits the BIPOLAR ZERO OUT and BIPOLAR ONE OUT by
forcing them to inactive high states
BIPOLAR ONE OUT
OUTPUT
An active low output intended to drive the one or positive sense on a
MIL-STD-1553 Line Driver
SERIAL DATA IN
ENCODER ENABLE
INPUT
INPUT
Receiver serial data at the rate of the ENCODER SHIFT CLOCK
A high on this pin initiates the encode cycle. (Subject to the
preceeding cycle being complete)
SYNC SELECT
SEND DATA
INPUT
Actuates a Command Sync for an input high and a Data Sync for a
low
An active high output which enables the external source of serial
Data
OUTPUT
SEND CLOCK IN
ENCODER CLOCK
VDD
INPUT
INPUT
POWER
Clock input at 2 times the Data rate, usualy driven by ¸ 6 OUT
Input to the divide by 6 circuit. Normal frequency is Data rate x12
5V +/- 10%
HOLT INTEGRATED CIRCUITS
2
HI-15530
ENCODER OPERATION
The encoder requires a single clock with a frequency of To abort the Encoder transmission a positive pulse must be
twice the desired rate applied at the SEND CLOCK input. applied at MASTER RESET. Anytime after or during this
An auxiliary divide by six counter is provided on chip which pulse, a low to high transition on SEND CLOCK clears the
can be utilized to produce the SEND CLOCK by dividing internal counters and initializes the Encoder for a new
the ENCODER CLOCK.
word.
The Encoder's cycle begins when ENCODER ENABLE is
high during a falling edge of ENCODER SHIFT CLOCK (1).
This cycle lasts for one word length or twenty ENCODER
SHIFT CLOCK periods. At the next low-to-high transition of
the ENCODER SHIFT CLOCK, a high at SYNC SELECT
input actuates a command sync or a low will produce a
data sync for that word (2). When the Encoder is ready to
accept data, the SEND DATA output will go high and
remain high for sixteen ENCODER SHIFT CLOCK periods
(3). During these sixteen periods the data should be
clocked into the SERIAL DATA input with every low-to-high
transition of the ENCODER SHIFT CLOCK (3) - (4). After
the sync and the Manchester II coded data are transmitted
through the BIPOLAR ONE and BIPOLAR ZERO outputs,
the Encoder adds on an additional bit which is the parity for
that word (5). If ENCODER ENABLE is held high continu-
ously, consecutive words will be encoded without an
interframe gap. ENCODER ENABLE must go low by time
(5) as shown to prevent a consecutive word from being
encoded. At any time a low on the OUTPUT INHIBIT input
will force both bipolar outputs to a high state but will not
affect the Encoder in any other way.
MASTER RESET
OUTPUT
INHIBIT
SEND CLK IN
BIPOLAR
ONE OUT
¸ 6 OUT
¸ 2
Character
Former
¸ 6
BIPOLAR
ZERO OUT
ENCODER CLK
Bit
Counter
SYNC
SELECT
SERIAL
DATA
IN
SEND
DATA
ENCODER
SHIFT
CLK
ENCODER
ENABLE
TIMING
0
1
2
3
4
5
6
7
15
16
17
18
19
SEND CLK
ENCODER
SHIFT CLK
ENCODER
ENABLE
DON’T CARE
DON’T CARE
SYNC SELECT
SEND DATA
VALID
SERIAL
DATA IN
15
14
13
12
11
10
3
2
1
0
BIPOLAR
ONE OUT
SYNC
SYNC
SYNC
15
15
14
14
13
13
12
12
11
11
3
3
2
2
1
1
0
P
P
BIPLOAR
ZERO OUT
SYNC
(3)
0
(1) (2)
(4) (5)
HOLT INTEGRATED CIRCUITS
3
HI-15530
DECODER OPERATION
The Decoder requires a single clock with a frequency of 12 looking for a new sync character to start another output
times the desired data rate applied at the DECODER sequence. VALID WORD will go low approximately 20
CLOCK input. The Manchester II coded data can be DECODER SHIFT CLOCK periods after it goes high if not
presented to the Decoder in one of two ways. The reset low sooner by a valid sync and two valid Manchester
BIPOLAR ONE and BIPOLAR ZERO inputs will accept bits as shown (1). At any time in the above sequence, a
data from a comparator sensed transformer coupled bus as
high input on DECODER RESET during a low-to-high
specified in MIL-STD-1553. The UNIPOLAR DATA input transition of DECODER SHIFT CLOCK will abort
can only accept non-inverted Manchester II coded data transmission and initialize the Decoder to start looking for a
(e.g. from BIPOLAR ZERO OUT of an Encoder). The new sync character.
Decoder is free running and continuously monitors its data
input lines for a valid sync character and two valid
Manchester data bits to start an output cycle. When a valid
TAKE DATA
UNIPOLAR
DATA IN
sync is recognized (1), the type of sync is indicated on
BIPOLAR
ONE IN
TRANSITION
FINDER
CHARACTER
IDENTIFIER
COMMAND/DATA SYNC output. If the sync character was
a command sync, this output will go high (2) and remain
high for sixteen DECODER SHIFT CLOCK periods (3),
otherwise it will remain low. The TAKE DATA output will go
high and remain high (2) - (3) while the Decoder is
transmitting the decoded data through SERIAL DATA OUT.
The decoded data available at SERIAL DATA OUT is in a
NRZ format. The DECODER SHIFT CLOCK is provided so
that the decoded bits can be shifted into an external register
on every low-to-high transition of this clock (2) - (3). After all
sixteen decoded bits have been transmitted (3) the data is
checked for odd parity. A high on VALID WORD output (4)
indicates a successful reception of a word without any
Manchester or parity errors. At this time the Decoder is
COMMAND/DATA
SYNC
BIPOLAR
ZERO IN
SERIAL DATA
OUT
VALID
WORD
BIT
RATE
CLK
DECODER
CLK
PARITY
CHECK
SYNCHRONIZER
DECODER
SHIFT CLK
MASTER
RESET
DECODER
RESET
BIT
COUNTER
TIMING
0
1
2
3
4
5
6
7
8
16
17
18
19
DECODER
SHIFT CLK
BIPOLAR
ONE IN
SYNC
SYNC
SYNC
SYNC
15
15
14
14
13
13
12
12
11
11
10
10
2
2
1
1
0
0
P
P
BIPLOAR
ZERO IN
TAKE DATA
COMMAND /
DATA SYNC
SERIAL
DATA OUT
UNDEFINED
15
14
13
12
4
3
2
1
0
May be high from previous reception
VALID WORD
(1)(2)
(3)
(4)
HOLT INTEGRATED CIRCUITS
4
HI-15530
SEND CLK
t
E1
ENCODER
SHIFT CLK
t
t
E3
E2
VALID
VALID
SERIAL DATA IN
SEND CLK
t
E1
ENCODER
SHIFT CLK
t
t
E6
E4
ENCODER ENABLE
SYNC SELECT
t
E5
VALID
t
E7
ENCODER
SHIFT CLK
t
E8
SEND DATA
SEND CLK
t
E9
BIPOLAR ONE OUT or
BIPOLAR ZERO OUT
DECODER SHIFT CLK
t
D6
t
COMMAND / DATA SYNC
D7
TAKE DATA
DECODER SHIFT CLK
SERIAL DATA OUT
t
D8
DATA BIT
DECODER SHIFT CLK
t
D9
t
COMMAND / DATA SYNC
D10
TAKE DATA
t
D11
VALID WORD
DECODER SHIFT CLK
DECODER RESET
t
t
DRH
DR
t
DRS
HOLT INTEGRATED CIRCUITS
5
HI-15530
BIT PERIOD
BIT PERIOD
BIT PERIOD
BIPOLAR ONE IN
BIPOLAR ZERO IN
t
D1
t
D3
t
t
D3
t
D2
t
D1
t
D2
COMMAND SYNC
BIPOLAR ONE IN
BIPOLAR ZERO IN
t
D1
D3
t
D3
t
D1
D1
t
t
D2
D2
DATA SYNC
BIPOLAR ONE IN
BIPOLAR ZERO IN
t
t
D1
t
t
D3
D3
t
D3
t
t
D3
D3
t
t
D1
D1
t
t
t
t
D4
D4
D5
D5
ONE
ZERO
ONE
t
D2
UNIPOLAR IN
t
D2
D2
COMMAND SYNC
DATA SYNC
ZERO
t
UNIPOLAR IN
UNIPOLAR IN
t
D2
t
t
D4
D5
t
t
t
D4
D4
D5
ONE
ONE
Bit Period
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
SYNC
TERMINAL ADDRESS R/T
SUBADDRESS
/ MODE
DATA WORD
COUNT
P
P
P
Command Word
SYNC
SYNC
DATA WORD
Data Word
SYNC
SYNC
TERMINAL ADDRESS ME
CODE FOR FAILURE MODES
TF
Status Word
SYNC
HOLT INTEGRATED CIRCUITS
6
HI-15530
Power Dissipation at 25C
Plastic SOIC
Supply Voltage VDD
Voltage at any pin
-0.3V to +7V
1.5 W, derate10mW/°C
1.0 W, derate 7mW/°C
Ceramic DIP
DC Current Drain per pin
±10mA
-0.3V to Vcc +0.3V
Storage Temperature Range:
-65°C to +150°C
Operating Temperature Range:
(Industrial)
(Military)
-40°C to +85°C
-55°C to +125°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDD = 5V ±10%, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
LIMITS
PARAMETER
SYMBOL
CONDITIONS
UNIT
MIN
TYP
MAX
Input Voltage
Input Voltage HI
Input Voltage LO
VIH
VIL
70% VDD
V
V
30% VDD
Clock Input Voltage
Input Leakage Current
Output Voltage
Input Voltage HI
Input Voltage LO
VIHC
VILC
VDD-0.5
V
V
0.5V
1.0
Input Sink
Input Source
IIH
IIL
µA
µA
-1.0
2.4
Logic “1” Output Voltage
Logic “0” Output Voltage
VOH
VOL
IOH=-3mA
IOL=1.8mA
V
V
0.4
2.0
Standby Supply Current
Operating Supply Current
Input Capacitance
IDDSB
IDD
VIN=VDD, Outputs Open
f=1MHz, Outputs Open
mA
mA
pF
10.0
7.0
CIN
Output Capacitance
COUT
10.0
pF
HOLT INTEGRATED CIRCUITS
7
HI-15530
VDD = 5V±10%, GND = 0V, TA = Operating Temperature Range, CL=50pF
LIMITS
TYP
PARAMETER
SYMBOL
UNITS
MIN
MAX
Encoder Timing
Encoder Clock Frequency
Send Clock Frequency
Encoder Clock Rise Time
Encoder Clock Fall Time
Encoder Data Rate
Master Reset Pulse Width
Shift Clock Delay
fEC
fESC
tECR
tECF
fED
tMR
tE1
0
0
15
2.5
8
MHz
MHz
ns
8
ns
0
1.25
MHz
ns
150
125
ns
Serial Data Setup Time
Serial Data Hold Time
Enable Setup Time
Enable Pulse Width
Sync Setup Time
tE2
75
75
90
80
55
150
0
ns
tE3
ns
tE4
ns
tE5
ns
tE6
ns
Sync Pulse Width
tE7
ns
Send Data Delay
tE8
50
ns
Bipolar Output Delay
Enable Hold Time
tE9
130
ns
tE10
tE11
10
95
ns
Sync Hold Time
ns
Decoder Timing
Decoder Clock Frequency
Decoder Clock Rise Time
Decoder Clock Fall Time
Decoder Data Rate
fDC
tDCR
tDCF
fDD
tDR
tDRS
tDRH
tMR
tD1
0
15
8
MHz
ns
8
ns
0
150
75
1.25
MHz
ns
Decoder Reset Pulse Width
Decoder Reset Setup Time
Decoder Reset Hold Time
Master Reset Pulse Width
Bipolar Data Pulse Width
Sync Transition Span
One-Zero Overlap
ns
10
ns
150
tDC+10
ns
ns
tD2
18tDC
ns
tD3
tDC-10
ns
Short Data Transition Span
Long Data Transition Span
Sync Delay (On)
tD4
6tDC
ns
tD5
12tDC
ns
tD6
-20
0
110
110
80
ns
Take Data Delay (On)
Serial Data Out Delay
Sync Delay (Off)
tD7
ns
tD8
ns
tD9
0
0
0
110
110
110
ns
Take Data Delay (Off)
Valid Word Delay
tD10
tD11
ns
ns
HOLT INTEGRATED CIRCUITS
8
HI-15530
4
3
2
1 28 27 26
VALID WORD
ENCODER SHIFT CLK
TAKE DATA
1
2
3
4
5
6
7
8
9
24 VDD
DECODER CLK
5
6
7
8
9
25
24
23
22
21
20
19
SEND DATA
N/C
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
N/C
N/C
HI-15530CLI
N/C
SERIAL DATA OUT
DECODER CLK
HI-15530CLT
HI-15530CLM
BIPOLAR ZERO IN
BIPOLAR ONE IN
SYNC SELECT
ENCODER ENABLE
SERIAL DATA IN
BIPOLAR ONE OUT
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15 BIPOLAR ZERO OUT
14 ¸ 6 OUT
HI-15530CDI
HI-15530CDT
HI-15530CDM
BIPOLAR ZERO IN
BIPOLAR ONE IN
UNIPOLAR DATA IN
DECODER SHIFT CLK
UNIPOLAR DATA IN 10
DECODER SHIFT CLOCK 11
12 13 14 15 16 17 18
COMMAND / DATA SYNC 10
DECODER RESET 11
GND 12
13 MASTER RESET
24 - Pin Ceramic Side-Brazed DIP
28 - Pin Ceramic LCC
PART
PACKAGE
DESCRIPTION
TEMPERATURE
RANGE
BURN LEAD
FLOW
NUMBER
HI-15530CDI
HI-15530CDT
IN
FINISH
24 PIN CERAMIC SIDE BRAZED DIP
24 PIN CERAMIC SIDE BRAZED DIP
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
I
T
M
I
NO
GOLD
NO
GOLD
HI-15530CDM 24 PIN CERAMIC SIDE BRAZED DIP
YES
NO
SOLDER
SOLDER
HI-15530PSI
24 PIN PLASTIC SOIC
24 PIN PLASTIC SOIC
24 PIN CERAMIC LEADLESS CHIP CARRIER -40°C TO +85°C
24 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
24 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
HI-15530PST
HI-15530CLI
HI-15530CLT
HI-15530CLM
T
I
T
M
NO
NO
SOLDER
GOLD
NO
GOLD
YES
SOLDER
HOLT INTEGRATED CIRCUITS
9
HI-15530
24-PIN PLASTIC SSOP
Package Type:
24HS
.323 ± .012
(8.20 ± .30)
.006
TYP
(.15)
.209 ± .012
(5.30 ± .30)
.307 ± .016
(7.80 ± .40)
SEE DETAIL A
.012
(.30)
TYP
.095 ± .005
(2.413 ± .127)
0° to 8°
.005 ± .001
(.13 ± .08)
.026
(.65)
.030 ± .008
(.75 ± .20)
TYP
DETAIL A
24-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 24C
1.220 MAX
(30.988 MAX)
.595 ± .010
.610 ± .010
(15.113 ± .254)
(15.494 ± .254)
.050 TYP
(1.270 TYP)
.600 ± .010
.225 MAX
(5.715 MAX)
.085 ± .009
(2.159 ± .229)
(15.240 ± .254)
.125 MIN
(3.175 MIN)
.100 BSC
(2.540 BSC)
.010 + .002/- .001
(.254 + .051/- .025)
.018 TYP
(.457 TYP)
HOLT INTEGRATED CIRCUITS
10
HI-15530
28-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 28S
.080 ± .020
(2.032 ± .508)
.020 INDEX
(.508 INDEX)
PIN 1
PIN 1
.050 ± .005
(1.270 ± .127)
.451 ± .009
(11.455 ± .229)
SQ.
.050 BSC
(1.270 BSC)
.008R ± .006
(.203R ± .152)
.025 ± .003
(.635 ± .076)
.040 x 45° 3PLS
(1.016 x 45° 3PLS)
HOLT INTEGRATED CIRCUITS
11
相关型号：
©2020 ICPDF网 联系我们和版权申明