HI-3000HPSF [HOLTIC]
Network Interface,;型号: | HI-3000HPSF |
厂家: | HOLT INTEGRATED CIRCUITS |
描述: | Network Interface, |
文件: | 总12页 (文件大小:529K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HI-3000H, HI-3001H
1Mbps Avionics CAN Transceiver
with High Operating Temperature
March 2020
PIN CONFIGURATIONS (Top Views)
GENERALDESCRIPTION
TXD - 1
GND - 2
VDD - 3
RXD - 4
8 - STB
The HI-3000H is a 1 Mbps Controller Area Network
(CAN) transceiver optimized for use in high temperature
avionics applications. The device is capable of operating
at extended temperature ranges of -55°C to 175°C for
plastic packages and -55°C to 200°C for the ceramic
CERDIP-8 package. It interfaces between a CAN proto-
col controller and the physical wires of the bus in a CAN
network. Differential output amplitude and current drive
capability are specifically enhanced to meet the needs of
long cable runs typical ofavionics applications.
7 - CANH
6 - CANL
5 - SPLIT
HI-3000PSHF
HI-3000CRH
TXD - 1
GND - 2
VDD - 3
RXD - 4
8 - STB
7 - CANH
6 - CANL
5 - VIO
HI-3001PSHF
HI-3001CRH
The HI-3000H supports two modes of operation: Normal
Mode and Standby Mode. The Standby Mode is a very
low-current mode which continues to monitor bus activity
and allows an external controller tomanage wake-up.
8-Pin Plastic SOIC package (Narrow Body)
& 8-Pin Ceramic CERDIP
FEATURES
Superior common-mode receiver performance makes
the device especially suitable for applications where
ground reference voltages may vary from point to point
over long distances along the CAN bus. In addition, the
HI-3000H provides a SPLIT pin to give an output refer-
ence voltage of VDD/2 which can be used for stabilizing
the recessive bus level when the split termination tech-
nique isused toterminate the bus.
· Extended Temperature Ranges -55°C to 175°C (plastic
SOIC-8 package) and -55°C to 200°C (ceramic CERDIP-
8 package)
· Fully compliant with ARINC 825 and ISO 11898-5
standards.
· Signaling rates up to 1Mbit/s.
· Internal VDD/2 voltage source available to stabilize the
recessive bus level if split termination is used (HI-3000H
SPLIT pin).
A TXD dominant time-out feature protects the bus from
being driven into a permanent dominant state (so-called
“babbling idiot”) ifpinTXDbecomes permanently low due
toapplication failure.
· VIO input on HI-3001H allows for direct interfacing with
3.3V controllers.
· Detection of permanent dominant on TXD pin (babbling
idiot protection).
The device also has short circuit protection to +/-58V on
CANH, CANL and SPLIT pins and ESD protection to
+/-6kVon all pins.
· High impedance allows connection of up to 120 nodes.
· Input levels compatible with 3.3V or 5V controllers.
· CANH, CANL and SPLIT pins short-circuit proof to +/-
58V.
The HI-3001H is identical to the HI-3000H except the
SPLIT pin is substituted with a VIO supply voltage pin.
This allows the HI-3001H to interface directly with con-
trollers with 3.3V supply voltages.
· Will not disturb the bus if unpowered.
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS3000H Rev. A)
03/20
HI-3000H, HI-3001H
PIN DESCRIPTIONS
SIGNAL
TXD
FUNCTION
INPUT
DESCRIPTION
100kOhm internal pull-up. Transmit Data Input.
Chip 0V supply
GND
VDD
RXD
CANL
CANH
STB
POWER
POWER
OUTPUT
BUS I/O
BUS I/O
INPUT
Positive supply, 5V +/-5%. Bypass with 0.1uF ceramic capacitor.
Receive Data Output.
CAN Bus Line Low.
CAN Bus Line High.
100kOhm internal pull-up. Standby Mode selection input. Drive STB low or connect to GND
for Normal operation. Drive STB high to select low-current Standby Mode.
Supplies a VDD/2 output to provide recessive bus level stabilization when a split termination
is used to terminate the bus.
Connect to a 3.3V supply to allow compatibility of all digital I/O (RXD, TXD, STB) with a
3.3V controller input.
SPLIT
(HI-3000H)
VIO
INPUT
INPUT
(HI-3001H)
BLOCK DIAGRAM
VDD
SPLIT
V Split
(HI-3000H)
CANH
TXD
Dominant
Detect
CANL
TXD
STB
Driver
Standby
Control
VIO
(HI-3001H)
Main
Receiver
RXD
GND
MUX
Low power
Standby Rx
Figure 1. HI-3000H Functional Block Diagram
HOLT INTEGRATED CIRCUITS
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HI-3000H, HI-3001H
FUNCTIONAL DESCRIPTION
due to an unpowered node with high leakage from the bus
lines to ground), the split circuit will force the recessive
voltage to VDD/2.
OPERATING MODES
The HI-3000H provides two modes of operation which are
selectable via the STB pin. Table 1 summarizes the modes.
INTERNAL PROTECTION FEATURES
Table 1 - Operating Modes
Short-circuit protection
MODE
STB pin
Short-circuit protection is provided on the CANH, CANL and
SPLIT pins. These pins are protected from ESD to over 6KV
(HBM) and from shorts between -58V and +58V continuous,
as specified in ISO 11898-5. The short circuit current is limited
toless than 200mAtypical.
Normal
Standby
LOW
HIGH
TXDpermanent dominanttime-out
Normal Mode
A timer circuit prevents the bus lines being driven into a
permanent dominant state, which would result in a situation
blocking all bus traffic. This could happen in the case of the
TXD pin becoming permanently low due to a hardware or
application failure. The timer is triggered by a negative edge
on the TXD pin (start of dominant state). If the TXD pin is not
set high (recessive state) after a typical time of 2ms, the
transmitter outputs will be disabled, driving the bus lines into
the recessive state. The timer is reset by a positive edge on
the TXD pin. Note that the minimum TXD dominant time-out
time, tdom = 300µs, defines the minimum possible bit rate of
40kbit/s (the CAN protocol specifies a maximum of 11
successive dominant bits − 5 successive dominant bits
immediately followed by an error frame).
Normal mode is selected by setting the STB pin to a LOW
logic level (GND). In this mode, the transceiver transmits and
receives data in the usual way from the CANH and CANLbus
lines. The differential receiver converts the analog bus data
to digital data which is output on the RXD pin (Note: the RXD
output on HI-3001H is compatible with 3.3V controllers if the
VIOpin is connected toa 3.3V supply).
StandbyMode
Standby Mode is selected by setting the STB pin to a HIGH
logic level. In this mode, the transmitter is switched off and a
low power differential receiver monitors the bus lines for
activity. A dominant signal of more than 3ms will be reflected
on the RXD pin as a logic LOW, where it may be detected by
the host as a wake-up request. The device will not leave
standby mode until the host forces the STBpin toa logic low.
Fail-safe features
Pin TXD has a pull up in order to force a recessive level if pin
TXDis leftopen.
Pins TXD and STB will become floating if power is lost. This
will prevent reverse currents via these pins.
SPLITCircuit
The SPLIT pin provides a stable VDD/2 DC voltage. This
pin can be used to stabilize the recessive common mode
voltage by connecting the SPLIT pin to the center tap of the
split termination (see figure 7). In the case of a recessive
bus voltage dropping below the ideal value of VDD/2 (e.g.
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HI-3000H, HI-3001H
TIMING DIAGRAMS
Timing Delays
HIGH
LOW
TXD
CANH
CANL
Dominant
Recessive
0.9V
VDIFF(BUS) =
VCANH - VCANL
0.5V
HIGH
LOW
RXD
50%
50%
tdr(TXD)
tdf(TXD)
tdr(RXD)
tdf(RXD)
tProp1
tProp2
TXD dominant time-out feature
transmitter
enabled
tRdom
tdom(TXD)
recessive
HIGH
LOW
TXD
dominant
transmitter disabled
CANH
CANL
HOLT INTEGRATED CIRCUITS
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HI-3000H, HI-3001H
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND = 0V)
Supply Voltage, VDD, VIO :.....................................................................7V Operating Temperature Range:(Plastic)...........................-55°C to +175°C
Current at Input pins ......................................................-100mA to +100mA
DC Voltages at TXD, RXD and STB ..............................-0.5V to VDD +0.5V
DC Voltages at CANH, CANL and SPLIT: ...............................-58V to +58V
Internal Power Dissipation: ..............................................................900mW
(Ceramic)........................-55°C to +200°C
Storage Temperature Range: -65°C to +150°C
Soldering Temperature:
(Ceramic)......................60 sec. at +300°C
(Plastic - leads).............10 sec. at +280°C
(Plastic - body) .....................+260°C Max.
Electrostatic Discharge (ESD)1, All pins ..........................................+/- 6kV
NOTES:
1. Human Body Model (HBM).
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5V±5%, Operating temperature range (unless otherwise noted). Positive currents flow into the IC.
LIMITS
TYP
PARAMETER
SUPPLY CURRENT
SYMBOL
CONDITIONS
UNIT
MIN
MAX
VDD Supply Current
IDD
IIO
Recessive: VTXD = VDD
Dominant: VTXD = 0 V
6
10
70
mA
mA
µA
50
15
Standby Mode: VTXD = VDD
50
VIO Supply Current
100
µA
DIGITAL INPUTS (Pins TXD, STB)
HIGH-level input voltage (see Note 1)
LOW-level input voltage (TXD pin)
VIH
VIL
80%VDD
− 0.5
VDD + 0.5
20%VDD
V
V
HIGH-level input current
LOW-level input current
IIH
IIL
VTXD = VDD or VIO
VTXD = 0 V
− 5
0
+ 5
µA
µA
− 50
− 150
DIGITAL OUTPUTS
HIGH-level output voltage (RXD Pin) (see Note 1)
LOW-level output voltage (RXD Pin)
VOH
VOL
IOH = 1mA
IOL = 1mA
90%VDD
0
V
V
0.1
10%VDD
Output voltage (SPLIT Pin)
VSPLIT
ISTB
− 100 µA < ISPLIT < 100 µA
0.45VDD 0.5VDD 0.55VDD
V
Standby leakage current (SPLIT Pin)
-5
+5
µA
DRIVER
CANH dominant output voltage
CANL dominant output voltage
VO(CANH)
VO(CANL)
VTXD = 0 V
3
3.6
1.4
4.25
1.75
V
V
VTXD = 0 V (See Fig. 2)
0.5
Recessive output voltage
VCANH(r),
VCANL(r)
VTXD = VDD, RL = 0 (See Fig. 2)
VTXD = VDD, RL = 0 (See Fig. 2)
2
0.5VDD
3
V
V
Bus output voltage in standby
VSTB
-0.1
0.1
Dominant differential output voltage
Recessive differential output voltage
VDIFF(d)(o)
VDIFF(r)(o)
VTXD = 0 V, 45 Ω < RL < 65 Ω
1.5
1.8
0
3
V
VTXD = VDD, no load (See Fig. 2)
− 50
50
mV
Matching of dominant output voltage,
VDD − VO(CANH) − VO(CANL)
VOM
(See Fig. 4)
− 100
2
-40
150
3
mV
V
Steady state common mode output voltage
VOC(ss)
VSTB = 0V, RL = 60 Ω (See Fig. 5)
0.5VDD
NOTE:
1. When VIO is connected (HI-3001H), limits are referenced wrt VIO rather than VDD.
HOLT INTEGRATED CIRCUITS
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HI-3000H, HI-3001H
DC ELECTRICAL CHARACTERISTICS (cont.)
VDD = 5V±5%, Operating temperature range. Positive currents flow into the IC.
LIMITS
TYP
PARAMETER
SYMBOL
CONDITIONS
UNIT
MIN
MAX
Short-circuit steady-state output current
IOS(ss)
VCANH = +58V, VCANL open
VCANH = -58V, VCANL openV
-20
-200
100
-20
20
100
200
20
mA
mA
mA
mA
VCANL = +58V, VCANH open
VCANL = -58V, VCANH open (See Fig. 6)
RECEIVER
Differential receiver threshold voltage
Differential hysteresis voltage
VTh(Rx)(diff)
VHys(Rx)(diff)
VHys(Stb)(diff)
− 12 V < VCANH, VCANL < + 12 V
− 12 V < VCANH, VCANL < + 12 V
− 12 V < VCANH, VCANL < + 12 V
500
50
700
120
900
200
mV
mV
mV
Differential hysteresis voltage in Standby mode
500
1150
Input leakage current, unpowered node
ICANH, ICANL
VDD = VIO 0 V
VCANH = VCANL = 5V
− 200
25
+ 200
100
µA
kΩ
Differential input resistance
RIN(DIFF)
VTXD = VDD
− 12 V < VCANH, VCANL < + 12 V
50
30
Common mode input resistance
RIN(CM)
VTXD = VDD
− 12 V < VCANH, VCANL < + 12 V
15
45
kΩ
%
Deviation between common mode input resistance
between CANH and CANL
RIN(CM)(m)
VCANH = VCANL
− 3
+ 3
AC ELECTRICAL CHARACTERISTICS
VDD = 5V±5%, Operating temperature range. Positive currents flow into the IC.
LIMITS
TYP
PARAMETER
SYMBOL
CONDITIONS
UNIT
MIN
MAX
Bit time
Bit rate
tBit
fBit
1
25
µs
40
1000
kHz
Common mode input capacitance3
CIN(CM)
VTXD = VDD, 1Mbit/s data rate
VTXD = VDD, 1Mbit/s data rate
20
10
pF
pF
Differential input capacitance3
CDIFF(CM)
Delay TXD to bus active
Delay TXD to bus inactive
Delay bus active to RXD
Delay bus inactive to RXD
tdr(TXD)
tdf(TXD)
tdf(RXD)
tdr(RXD)
40
40
30
70
90
90
ns
ns
ns
ns
See Timing Diagrans
70
150
Propagation delay TXD to RXD (recessive to dominant)
Propagation delay TXD to RXD (dominant to recessive)
tProp1
tProp2
70
160
240
ns
ns
110
TXD permanent dominant time-out
tdom
VTXD = 0 V
0.3
0.5
2
6
1
ms
µs
TXD permanent dominant timer reset time
tRdom
Rising edge on TXD while in
permanent dominant state
Dominant time required on bus for wake up from standby
twake
3
5
µs
NOTES:
1. All currents into the device pins are positive; all currents out of the device pins are negative.
2. All typicals are given for VDD = 5V, TA = 25°C.
3. Guaranteed by design but not tested.
HOLT INTEGRATED CIRCUITS
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HI-3000H, HI-3001H
Application and Test Information
Transceiver
TXD
VDIFF(d)(o)
RL
VO(CANH)
VO(CANL)
STB
Dominant
~3.5V: VO(CANH)
~2.5V
Recessive
~1.5V: VO(CANL)
Figure 2. CAN Bus Driver Circuit
300 W +/- 1%
Transceiver
TXD
CANH
0V
VDIFF(d)(o)
RL
+
-12V <= VTEST <= +12V
_
CANL
300 W +/- 1%
STB
Figure 3. CAN Bus Driver (Dominant) Test Circuit
Transceiver
TXD
VDIFF(d)(o)
RL
VO(CANH)
V1
VO(CANL)
VOM = VDD - VO(CANH) + VO(CANL)
STB
Figure 4. Driver Output Symmetry Test.
HOLT INTEGRATED CIRCUITS
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HI-3000H, HI-3001H
Application and Test Information
Transceiver
TXD
VDIFF(d)(o)
RL
V1
VO(CANH)
VO(CANL)
VOC(ss) = VO(CANH) + VO(CANL)
2
STB
Figure 5. Common Mode Output Voltage Test.
Transceiver
CANH
TXD
+
-58V or +58V
_
CANL
V1
Figure 6. CAN Bus Driver Short-Circuit Test. (Note: V1 is a pulse from 0V to VDD with duty cycle
of 99% such that permanent dominant time-out is avoided).
HOLT INTEGRATED CIRCUITS
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HI-3000H, HI-3001H
Application and Test Information
VBAT
5V
Regulator
VDD
3
TXD
RXD
CANH
SPLIT
VDD
1
4
TXD
RXD
7
5
RL/2
RL/2
HI-3000H
Controller
GND
(optional)
STB
CANL
8
6
2
GND
5V
VBAT
3.3V
Regulator
VDD
7
VIO
1
TXD
RXD
3
5
CANH
CANL
VDD
TXD
RXD
4
RL
HI-3001H
Controller
STB
8
6
GND
2
GND
Figure 7. Typical Application Connections
HOLT INTEGRATED CIRCUITS
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HI-3000H, HI-3001H
ORDERING INFORMATION
HI - 300x PS H x
LEAD
FINISH
PART
NUMBER
100% Matte Tin (Pb-free, RoHS compliant)
F
PART
PACKAGE
NUMBER
DESCRIPTION
8 PIN PLASTIC NARROW BODY SOIC (8HN): -55oC to +175oC.
PS
PART
DESCRIPTION
NUMBER
SPLIT pin option
VIO pin option
3000
3001
HI - 300x CR H
PART
PACKAGE
NUMBER
DESCRIPTION
8 PIN CERDIP (8D) not available Pb-free: -55oC to +200oC.
CR
PART
DESCRIPTION
NUMBER
SPLIT pin option
VIO pin option
3000
3001
HOLT INTEGRATED CIRCUITS
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HI-3000H, HI-3001H
REVISION HISTORY
P/N
Rev
Date
Description of Change
DS3000H
New
G
12/05/12
03/04/20
Initial Release
Change “Compatible with ARINC 825 and ISO 11898-5 standards” to “Fully
compliant with ARINC 825 and ISO 11898-5 standards” in Features.
HOLT INTEGRATED CIRCUITS
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PACKAGE DIMENSIONS
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
inches (millimeters)
Package Type: 8HN
(Narrow Body)
.193
BSC
(4.90)
.007 ± .003
(.175 ± .075)
.236
(6.00)
.154 ± .004
(3.90 ± .09)
BSC
PIN 1
See Detail A
1.25 min.
.016 ± .004
(.410 ± .10)
0° to 8°
.007 ± .003
(.175 ± .075)
.050
(1.27)
.033 ± .017
(.835 ± .435)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
BSC
Detail A
inches (millimeters)
Package Type: 8D
8-PIN CERDIP
.380 ±.004
(9.652 ±.102)
.005 min
(.127 min)
.248 ±.003
(6.299 ±.076)
.039 ±.006
(.991 ±.154)
.100
(2.54)
BSC
.314 ±.003
(7.976 ±.076)
.015 min
(.381min)
.200 max
(5.080 max)
Base Plane
.010 ±.006
(.254 ±.152)
Seating Plane
.163 ±.037
(4.140 ±.940)
.018 ±.006
(.457 ±.152)
.350 ±.030
(8.890 ±.762)
.056 ±.006
(1.422 ±.152)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
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