HI-8020CLI-61 [HOLTIC]
Liquid Crystal Driver, 38-Segment, CMOS, CQCC48, ROHS COMPLIANT, CERAMIC, LCC-48;
| 型号： | HI-8020CLI-61 |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | Liquid Crystal Driver, 38-Segment, CMOS, CQCC48, ROHS COMPLIANT, CERAMIC, LCC-48 |
| 文件： | 总7页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-8020, HI-8120
CMOS High Voltage
Display Driver
November 2007
PIN CONFIGURATION (Top View)
GENERAL DESCRIPTION
The HI-8020 & HI-8120 high voltage display drivers
are functional replacements for the AMI S5420 and
Micrel MIC8013/8014 series. These CMOS prod-
ucts are designed to drive liquid crystal displays by
converting 5 volt serial data to parallel segment and
backplane waveforms with amplitudes up to 30 volts.
The HI-8020 & HI-8120 differ from the HI-8010 by
only the shift register clock and chip select gating
logic. The HI-8020 has TTL logic inputs whereas the
HI-8120 has CMOS logic inputs.
6
5
4
3
2
1 44 43 42 41 40
7
39
38
37
36
35
34
33
32
31
30
29
S27
S28
S29
S30
S31
S32
N/C
VSS
CS
S17
S16
S15
VEE
S14
S13
S12
S11
S10
S9
8
9
HI-8020J-85
&
HI-8120J-85
10
11
12
13
14
15
16
17
44 - PIN
PLASTIC
PLCC
Both devices can drive up to 38 segments and have 3
possible shift register data taps to provide options to
cascade devices for larger displays. Data is clocked
into a 38 stage shift register and parallel latched
before the output translators by a Load input.
CL
LD
S8
18 19 20 21
22 23 24 25 26 27 28
The HI-8020 & HI-8120 are available in ceramic
leadless chip carriers and plastic PLCC packages.
FEATURES
! 5 volt input translated to 30 volts or less
(See page 4 for additional package pin configurations)
! Pin-out adaptable to drive 30, 32 or 38
LCD segments
! RC oscillator or high voltage (BP) clock input
! TTL compatible inputs (HI-8020 only)
! CMOS compatible inputs (HI-8120 only)
! Low power consumption
FUNCTIONAL BLOCK DIAGRAM
DATA IN
DIN Þ
DOUT 38
DOUT 32
DOUT 30
Þ
Þ
Þ
38 Stage
Shift Register
CL Þ
CS Þ
LD Þ
! Industrial (-40°C to +85°C) & Military (-55°C
to +125°C) temperature ranges
CLK
LE
! Pin for pin compatible with the Micrel
MIC8010/8011 series and the AMI S4520
series drivers
38 Bit Latch
LCDØ Þ
Oscillator
Divider
! Cascadable
Voltage
Translators
LCDØ OPT Þ
! Military level processing available
Voltage
Translator
High Voltage
Drivers
APPLICATIONS
High Voltage
Buffer
!
!
!
!
Dichroic Liquid Crystal Displays
Standard Liquid Crystal Displays
Vacuum Fluorescent Displays
MEMS Drivers
SEGMENTS
Þ BP
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8020 Rev. G)
11/07
HI-8020/HI-8120 Series
FUNCTIONAL DESCRIPTION
on the rising edge of the Clock (CL). Clock (CL), Load (LD)
and Chip Select (CS) should be tied in common with each
other, respectively, between all cascaded display drivers.
Whenever a Logic "0" is applied to the Chip Select (CS)
input, one bit of data is clocked into the shift register from the
serial data input (DIN) with each negative transition of the
Clock (CL) input. A Logic "1" present at the Load (LD) input
will cause a parallel transfer of data from the shift register to
the data latch. If the Load (LD) input is held high while data
is clocked into the shift register, the latch will be transparent.
All four logic inputs are TTL compatible on the HI-8020 and
CMOS compatible on the HI-8120.
INTERNAL OSCILLATOR CIRCUIT
To display segments, a Logic "1" is stored in the appropriate
shift register bit position, and the segment output is out-of-
phase with the backplane.
R
C
The backplane output functions in 1 of 2 modes; externally
driven or self-oscillating. When the LCDØ input is externally
driven with the LCDØOPT input open circuit (Figure 2), the
backplane output will be in-phase with LCDØ. Utilizing the
self-oscillating mode, inputs LCDØ and LCDØOPT are tied
together and connected to an RC circuit (Figure 3).
A 150KW resistor with a 470pF capacitor generates an
approximate backplane frequency of 100Hz. The
LCDØ/LCDØOPT oscillator frequency is divided by 256 to
determine the backplane output frequency. The resistor
value (R) must be at least 30KW for proper self-oscillator
operation.
÷ 256
Q
LCDØ
LCDØ
OPT
For displays having a number of segments greater than 38,
two or more of the display drivers may be cascaded together
by connecting the serial data output (DOUT) from the first
driver, to the serial data input (DIN) of the following driver,
etc.(See Figures 2 & 3). Data out (DOUT) will change state
TO BACKPLANE
TRANSLATOR
AND DRIVER
Figure 1.
TIMING DIAGRAM
CL
INPUT
tCL
DIN
INPUT
VALID
VALID
tDS
tDH
CS
INPUT
tCSS
tLCS
tCSL
tCSH
LD
INPUT
tLS
tLW
tCDO
DOUT
OUTPUT
VALID
VALID
VALID
HOLT INTEGRATED CIRCUITS
2
HI-8020/HI-8120 Series
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to VSS = 0V
Supply Voltage VDD........................ 0V to 7V
VEE................VDD-35V to 0V
Voltage at any input, except LCDØ..-0.3 to VDD+0.3V
Power Dissipation......................................................300 mW
Operating Temperature Range - Industrial........-40° to +85°C
Operating Temperature Range - Hi-Temp/Mil..-55° to +125°C
Storage Temperature Range...........................-65° to +150°C
Voltage at LCDØ input...............VDD-35 to VDD+0.3V
DC Current any input pin...................................10 mA
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage
SYMBOL
CONDITION
MIN
TYP
MAX UNITS
VDD
3.0
7.0
225
300
150
0.8
V
µA
µA
µA
V
Supply Current (Static, No Load)
@+85°C, fBP=0Hz
@ +125°C, fBP=0Hz
@ +125°C, fBP=100Hz
IDD
IEE
Input Low Voltage, HI-8020 (except LCDØ)
Input High Voltage, HI-8020 (except LCDØ)
Input Low Voltage, HI-8120 (except LCDØ)
VILTTL
VIHTTL
VILCMOS
0
2
VDD
0.3 VDD
VDD
3
V
0
V
Input High Voltage, HI-8120 (except LCDØ) VIHCMOS
0.7 VDD
VEE
3.5
V
Input Low Voltage (LCDØ)
Input High Voltage (LCDØ)
Input Current
VILX
VIHX
IIN
V
VDD
1
V
VIN = 0 to 5V
µA
pF
KW
W
Input Capacitance (not tested)
Segment Output Impedance
Backplane Output Impedance
Data Out Current:
CI
5
RSEG
RBP
IDOH
IDOL
IL = 10µA
IL = 10µA
10
15
450
600
-0.6
Source Current, VOH = 4.5V
Sink Current, VOL = 0.5V
mA
mA
0.6
AC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
tCL
VDD
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
MIN
1200
520
50
TYP
MAX
UNITS
ns
Clock Period
Clock Pulse Width
tCW
ns
Data In - Setup
tDS
ns
Data In - Hold
tDH
400
200
450
500
300
500
300
ns
Chip Select - Setup to Clock
Chip Select - Hold to Clock
Load - Setup to Clock
Chip Select - Setup to Load
Load Pulse Width
tCSS
tCSH
tLS
ns
ns
ns
tCSL
tLW
ns
ns
Chip Select - Hold to Load
Data Out Valid, from Clock
tLCS
tCDO
ns
800
ns
HOLT INTEGRATED CIRCUITS
3
HI-8020/HI-8120 Series
CASCADING - EXT. OSCILLATOR
LD
CL
CS
CASCADING - RC OSCILLATOR
LD
CL
CS
LD
LD
LD
LD
LD
CS CL
DIN
CS CL
DIN
CS CL
DIN
CS CL
DIN
LD
CS CL
DIN
CS CL
DIN
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
150KW
HI-8120J-85
HI-8120J-85
HI-8120J-85
HI-8020J-85
HI-8020J-85
HI-8020J-85
LCDØ
BP
LCDØ
BP
LCDØ
BP
LCDØ
BP
LCDØ
BP
LCDØ
BP
LCDØ OPT
LCDØ OPT
LCDØ OPT
470pf
SEGMENTS
1 - 33
SEGMENTS BACK
33 - 64
SEGMENTS
65 - 96
SEGMENTS
1 - 32
SEGMENTS BACK
33 - 64
SEGMENTS
65 - 96
PLANE
PLANE
Figure 2
Figure 3
PIN DESCRIPTIONS
SYMBOL
VSS
FUNCTION
POWER
INPUT
DESCRIPTION
0 Volts
CS
Logic input
Logic input
Logic input
Logic input
Chip select
CL
INPUT
Clocks shift register on negative edge and DOUT pins on positive edge
Segment outputs equal shift register data if Load is high
Shift register data input
LD
INPUT
DIN
INPUT
LCD0
LCD0OPT
VDD
INPUT
Analog input
Display clock input and is always bonded out. Can swing from VEE to VDD
Bonded out only if an RC oscillator is required
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
OUTPUT
Analog output
5 Volts
VEE
0 Volts to -30 Volts
Logic output
DOUT
BP
Selected pinout can provide shift register taps at positions 30, 32, 34, or 38
Low resistance drive for the backplane and swings from VDD to VEE
High resistance drive for each segment and swings from VDD to VEE
Display drive output
Display drive output
Segments
ADDITIONAL HI-8020/HI-8120 PIN CONFIGURATIONS
(See page 1 for the 44-Pin Plastic PLCC)
6
5
4
3
2
1
48 47 46 45 44 43
42
6
5
4
3
2
1
48 47 46 45 44 43
42
7
7
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
VSS
CS
S16
S15
VEE
S14
S13
S12
S11
S10
S9
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
VSS
CS
S16
S15
VEE
S14
S13
S12
S11
S10
S9
8
41
40
39
38
37
36
35
34
33
32
31
8
41
40
39
38
37
36
35
34
33
32
31
HI-8020CLI-61
HI-8120CLI-61
HI-8020CLM-62
&
HI-8020CLI-63
HI-8120CLI-63
HI-8020CLM-64
&
9
9
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
HI-8120CLM-62
HI-8120CLM-64
48 - PIN
CERAMIC
LCC
48 - PIN
CERAMIC
LCC
S8
S8
S7
S7
S6
S6
19 20 21 22 23 24 25 26 27 28 29 30
19 20 21 22 23 24 25 26 27 28 29 30
LCDØ /
LCDØOPT
HOLT INTEGRATED CIRCUITS
4
HI-8020/HI-8120 Series
ORDERING INFORMATION
HI - 8XXX J X - 85 (44-pin Plastic J-Lead PLCC) (44J)
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
Blank
F
100% Matte Tin (Pb-free, RoHS compliant)
PART
NUMBER
INPUT
LOGIC
NUMBER OF MASTER/
TEMPERATURE
RANGE
FLOW
BURN
IN
SEGMENTS
SLAVE
BOTH
BOTH
8020
8120
TTL
32
32
-40°C TO +85°C
-40°C TO +85°C
I
I
NO
NO
CMOS
HI - 8XXX XXX-XX (48-pin Ceramic Leadless Chip Carrier) (48S)
PART
NUMBER
MASTER/ TEMPERATURE
RANGE
FLOW
BURN
IN
LEAD
FINISH
SLAVE
Gold (Pb-free, RoHS compliant)
Tin / Lead (Sn / Pb) Solder
Gold (Pb-free, RoHS compliant)
Tin / Lead (Sn / Pb) Solder
CLI - 61
CLM - 62
CLI - 63
CLM - 64
MASTER
MASTER
SLAVE
-40°C TO +85°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
I
NO
YES
NO
M
I
SLAVE
M
YES
PART
NUMBER
INPUT
LOGIC
NUMBER OF
SEGMENTS
8020
8120
TTL
38
38
CMOS
HOLT INTEGRATED CIRCUITS
5
HI-8020/HI-8120 Series
SEMI-CUSTOM PACKAGING
The above part numbers represent the standard configurations of the HI-8020 & HI-8120 products. They can also be provided with a
varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide variety of packages. Listed
below are currently available packages. Please contact the Holt Sales Department for your specific requirements.
PACKAGE
DESCRIPTION
#
LEADS
PLASTIC DUAL-IN-LINE (PDIP)
40
48
52
44
40
48
40
48
44
48
40
48
PLASTIC QUAD FLAT PACK (PQFP)
PLASTIC J-LEAD CHIP CARRIER (PLCC)
CERAMIC DUAL-IN-LINE (CDIP)
CERAMIC LEADLESS CHIP CARRIER (LCC)
CERAMIC J-LEAD CHIP CARRIER
CERAMIC LEADED CHIP CARRIER
HOLT INTEGRATED CIRCUITS
6
HI-8020/HI-8120 PACKAGE DIMENSIONS
44-PIN PLASTIC PLCC
inches (millimeters)
Package Type: 44J
PIN NO. 1
PIN NO. 1 IDENT
.045 x 45°
.045 x 45°
.050
BSC
(1.27)
.690 ±.005
(17.526 ±.127)
SQ.
.653 ±.004
.031±.005
(16.586 ±.102)
SQ.
(.787 ±.127)
.017 ±.004
(.432 ±.102)
See Detail A
.010 .001
(.254 .03)
.173 ±.008
(4.394 ±.203)
.020
(.508)
min
.610 ±.020
(15.494±.508)
DETAILA
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
.035±.010
(.889 ±.254)
R
48-PIN CERAMIC LEADLESS CHIP CARRIER
inches (millimeters)
Package Type: 48S
.040 ±.007
(1.016 ±.178)
PIN 1 IDENT.
.090
(2.286)
max
PIN 1 IDENT.
.020
typ
(.508)
.563 ±.009
(14.300 ±.228)
SQ.
.020
(.508)
typ
.040
(1.016)
BSC
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
7
相关型号：
HI-8020CLI-63
Liquid Crystal Driver, 38-Segment, CMOS, CQCC48, ROHS COMPLIANT, CERAMIC, LCC-48
HOLTIC
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