HI-8040 [HOLTIC]
CMOS HIGH VOLTAGE DISPLAY DRIVER; CMOS高电压显示驱动器
| 型号： | HI-8040 |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | CMOS HIGH VOLTAGE DISPLAY DRIVER |
| 文件： | 总6页 (文件大小：704K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-8040
September 1999
GENERAL DESCRIPTION
APPLICATIONS
The HI-8040 is a CMOS integrated circuit designed for high
voltage LCD display drive applications. It can drive 85
segments at voltages between +5 and -30 volts. An optional
negative converter can generate the negative display drive
voltage. Test inputs facilitate opens and shorts testing. The
backplane frequency is checked and, as long as power is
available, the segments are shut "Off" if the frequency
becomes too low.
! Dichroic Liquid Crystal Displays
! Standard Liquid Crystal Displays
PIN CONFIGURATION (Top View)
The HI-8040 is part of a family of display drivers which
control segment information in the same way. Data is
serially clocked into the device and the data for all segment
outputs are latched in parallel when the Load input
transitions from high to low. With the Data Out from the shift
register available, devices may be cascaded to obtain more
segment outputs. The shift register is 85 bits long.
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
S29
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S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
100 PIN QUAD CERPACK
The die is metal mask programmable to provide for various
package and/or cascade tap options. Consult your Holt
Sales representative to explore the possibilities.
See page 3-19 for magnified view
FEATURES
FUNCTIONAL BLOCK DIAGRAM
! 4 MHz serial input data rate
! 85 segment outputs
DIN ⇒
DATA IN
85 Stage
Shift Register
DOUT
85
CL ⇒
CLK
! Cascadable
CS ⇒
! 5 Volt inputs translated to 35 Volts
LE
85 Bit Latch
! T est pins allow hardware all "ON", all "OFF" or
alternating
LD ⇒
Oscillator
Divider
BPOSC ⇒
Voltage
! Monitors backplane oscillation and forces all
segments to "OFF" condition if below 10Hz
BPIN ⇒
Translators
Voltage
Translator
High Voltage
Drivers
! Negative voltage converter available on-chip
! CMOS low power
High Voltage
Buffer
! Military processing available
⇒ BP
85 SEGMENTS
HOLT INTEGRATED CIRCUITS
3-15
(DS8040 Rev. NEW)
9/99
HI-8040
FUNCTIONAL DESCRIPTION
DOUT
INPUT LOGIC
The DOUT pin is available from segment 85 for cascading
devices to drive more segments and for verifying the data
integrity. This output can drive 2 TTL loads. It changes on the
positive edge of CL .
CS must be held low to enter data into the shift register.
The data is clocked on the negative edge of CL . LD is nor-
mally held low and only pulsed high when new data is ready
for display. When LD is high the latch is transparent. All four
logic inputs are TTL compatible. A logic "1" at DIN that is
eventually latched to the segment drivers will cause the seg-
ment to be at the opposite voltage level of the BP pin (out of
phase).
AUTOMATIC SEGMENTS OFF
The internal backplane signal is tested continuously to be at
least 10Hz. If the detector senses f<10Hz, then the segments
are forced to the same voltage as the backplane (all segments
in "OFF" state). However, the detector is only functional while
VDD is above the minimum operating voltage specification.
BPOSC and BPIN
The user can either make an oscillator to create the
backplane frequency or drive a signal into BPIN leaving
BPOSC open. To make an oscillator, pins BPOSC and
BPIN must be connected togeth er and the appropriate R
and C combination applied (See Figure 1). If the oscillator is
used, the backplane frequency is approximately
1
TEST INPUTS
The test functions available are:
T2
0
T1
0
Display
Normal
fBP =
.
(for R = 180KΩ & C = 220pF, fBP ≈ 100Hz).
0
1
All Off
256 RC
1
0
All On
1
1
Alternating On/Off Segments
VEE & NEGATIVE VOLTAGE CONVERTER
Th e test inputs must be tied to the appropriate logic level for
correct circuit operation.
VEE may be externally driven to a maximum -30V. Alterna-
tively, there is a voltage converter that will provide -21.4 volts
(See Figure 2). If the converter pins are left open circuit, an
on-chip sense resistor will cause shut down of all current
consumption associated with the converter. The converter
will survive a shorted segment condition and continue to
maintain VEE at -20 volts.
VDD
R 330KΩ
OSC
R SENSE
Control
IN5818, IN5819
VDD
330µh
VSS
10µF
VSS
HOLT INTEGRATED CIRCUITS
3-16
HI-8040
LD
CL
CS
1M W
1mF
1M W
BP
DIN
CS CL LD
CS CL LD
CS CL LD
1500pF
1mF
DIN
DO
DIN
DO
DIN
DO
R
C
V
os
BPIN
BP
BPIN
BP
BPIN
BP
BPOSC
BPOSC
BPOSC
1M W
1mF
1M W
SEG
n
BACK
PLANE
SEGMENTS
SEGMENTS
SEGMENTS
1mF
360pF
VALID
HOLT INTEGRATED CIRCUITS
3-17
Voltages referenced to VSS = 0V
Supply Voltage VDD........................ 0V to 7V
VEE................VDD-35V to 0V
Voltage at any input, except BPIN....-0.3 to VDD+0.3V
Power Dissipation......................................................300 mW
Operating Temperature Range - Industrial...... -40° to +85°C
Operating Temperature Range - Hi-Temp/Mil...-55° to +125°C
Storage Temperature Range............................-65° to +150°C
Voltage at BPIN input.................VDD-35 to VDD+0.3V
DC Current any input pin...................................10 mA
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These a re stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational section s of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDD = 5V ±5%, VEE = -21.5V, VSS = 0V, TA = operating temperature range (unless otherwise specified).
PARAMETER
SYMBOL
VDD
IDD
CONDITION
MIN
TYP
MAX
7.0
UNITS
V
Operating Voltage
3.0
Supply Current:
(Converter Off, fBP = 100Hz)
Static, No Load
Static, No Load
300
120
µA
µA
V
V
V
IEE
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Current
(excluding BPIN)
(excluding BPIN)
(BPIN)
VIL
VIH
VILX
VIHX
IIN
0
2
0.8
VDD
0.6 VDD
VDD
100
VEE
0.8 VDD
(BPIN)
V
VIN = 0 to 5V
nA
pF
Ω
Input Capacitance
(Guaranteed, not tested)
CI
5
Segment Output Impedance
Backplane Output Impedance
Data Out Current:
RSEG
RBP
IDOH
IDOL
VEEC
IDD
IL = 10µA
IL = 10µA
VOH = 4.5
VOL = 0.4
See Fig. 2
See Fig. 2
See Fig. 2
See Fig. 4
15,000
600
-3.0
Ω
Source Current
Sink Current
@ No Load
@ 0.1mA Load
@ 10KΩ Load
mA
mA
V
mA
V
3.2
-22
Voltage Converter:
(VDD - VSS = 5V, TA = 25°C)
-21.5
-21
1.8
VEEC
VOS
-20
Offset Voltage
(Guaranteed, not tested)
25
mV
VDD = 5V , VEE = -21.5V, VSS = 0V, TA = operating temperature range (unless otherwise specified).
PARAMETER
SYMBOL
tCL
VDD
5V
5V
5V
5V
5V
5V
5V
MIN
250
500
125
250
80
TYP
MAX
UNITS
ns
Clock Period
non-cascaded
cascaded
tCL
ns
Clock Pulse Width
non-cascaded
cascaded
tCW
tCW
tDS
ns
ns
Data In - Setup
ns
Data In - Hold
tDH
80
ns
Chip Select - Setup to Clock
tCSS
100
ns
Chip Select - Hold to Clock
Load - Setup to Clock
tCSH
tLS
5V
5V
120
120
ns
ns
Chip Select - Setup to Load
Load Pulse Width
Chip Select - Hold to Load
Data Out Valid, from Clock
tCSL
tLW
tLCS
tCDO
5V
5V
5V
5V
0
ns
ns
ns
ns
130
120
170
HOLT INTEGRATED CIRCUITS
3-18
HI-8040
ORDERING INFORMATION
PART
NUMBER
PACKAGE
DESCRIPTION
TEMPERATURE
RANGE
BURN
IN
LEAD
FINISH
FLOW
HI-8040Q
100-PIN CERAMIC QUAD FLAT PACK (CQFP)
100-PIN CERAMIC QUAD FLAT PACK (CQFP)
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
I
NO
NO
SOLDER
SOLDER
HI-8040QT
T
M
HI-8040QM-01 100-PIN CERAMIC QUAD FLAT PACK (CQFP)
YES SOLDER
MAGNIFIED VIEW OF PIN ASSIGNMENTS
S60
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S65
S66
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S68
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S71
S72
S73
S74
S75
S76
S77
S78
S79
S29
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
100 PIN QUAD CERPACK
Pin 1
HOLT INTEGRATED CIRCUITS
3-19
HI-8040 PACKAGE DIMENSIONS
inches (millimeters)
100-PIN CERAMIC QUAD FLAT PACK
Package Type: 100 CQR
.014 ± .002 TYP
(.356 ± .051 TYP)
.0256 ± .002 TYP
(.6502 ± .051 TYP)
.654 ± .012
(16.612 ± .305)
.718 ± .014
(18.237 ± .356)
.551 ± .006
(13.995 ± .152)
Pin 1
.890 ± .012
.170 MAX
(22.606 ± .305)
(4.318 MAX)
.032 ± .008
(.813 ± .203)
.787 ± .007
(19.99 ± .178)
Detail A
.0065 ± .0015
(.165 ± .038)
.008 TYP
(.203 TYP)
0° TO 7°
.954 ± .014
(24.23 ± .356)
Detail A
HOLT INTEGRATED CIRCUITS
1
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