HI-8120J-85 [HOLTIC]
CMOS HIGH VOLTAGE DISPLAY DRIVER; CMOS高电压显示驱动器
| 型号： | HI-8120J-85 |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | CMOS HIGH VOLTAGE DISPLAY DRIVER |
| 文件： | 总6页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-8020/HI-8120
January 2001
PIN CONFIGURATION (Top View)
GENERAL DESCRIPTION
The HI-8020 & HI-8120 high voltage display drivers
are functional replacements for the AMI S5420 and
Micrel MIC8013/8014 series. These CMOS prod-
ucts are designed to drive liquid crystal displays by
converting 5 volt serial data to parallel segment and
backplane waveforms with amplitudes up to 30 volts.
The HI-8020 & HI-8120 differ from the HI-8010 by
only the shift register clock and chip select gating
logic. The HI-8020 has TTL logic inputs whereas the
HI-8120 has CMOS logicinputs.
7
39
38
37
36
35
34
33
32
31
30
29
S27
S28
S29
S30
S31
S32
N/C
VSS
CS
S17
S16
S15
VEE
S14
S13
S12
S11
S10
S9
8
9
HI-8020J-85
&
HI-8120J-85
10
11
12
13
14
15
16
17
44 - PIN
PLASTIC
PLCC
Both devicescan drive up to 38 segments and have 3
possible shift register data taps to provide options to
cascade devices for larger displays. Data is clocked
into a 38 stage shift register and parallel latched
before the output translators by a Load input.
CL
LD
S8
The HI-8020 & HI-8120 are available in a variety of
ceramic and plastic packaging including DIP; leaded
and leadless chip carriers; and J-lead and gull-wing
quad flat packs.
(See page 3-6 for additional package pin configurations)
FEATURES
! 5 volt input translated to 30 volts or less
FUNCTIONAL BLOCK DIAGRAM
! Pin-out adaptable to drive 30, 32 or 38
LCD segments
! RC oscillator or high voltage (BP) clock input
! TTL compatible inputs (HI-8020 only)
! CMOS compatible inputs (HI-8120 only)
! Low power consumption
DATA IN
DIN ⇒
DOUT 38
DOUT 32
DOUT 30
⇒
⇒
⇒
38 Stage
CL ⇒
CS ⇒
LD ⇒
Shift Register
CLK
! Industrial (-40°C to +85°C) & Military (-55°C
to +125°C) temperature ranges
38 Bit Latch
! Pin for pin compatible with the Micrel
MIC8010/8011 series and the AMI S4520
series drivers
LCDØ ⇒
LCDØ OPT ⇒
Oscillator
Divider
Voltage
Translators
Voltage
Translator
! Cascadable
High Voltage
Drivers
! Military level processing available
High Voltage
Buffer
SEGMENTS
⇒ BP
! Dichroic Liquid Crystal Displays
! Standard Liquid Crystal Displays
! Vacuum Fluorescent Displays
HOLT INTEGRATED CIRCUITS
3-9
(DS8020 Rev. B)
01/01
HI-8020/HI-8120 Series
FUNCTIONAL DESCRIPTION
Whenever a Logic "0" is applied to the Chip Select (CS)
input, one bit of data is clocked into the shift register from the
serial data input (DIN) with each negative transition of the
Clock (CL) input. CS is internally tied to VSS on some
versions. A Logic "1" present at the Load (LD) input will
cause a parallel transfer of data from the shift register to the
data latch. If the Load (LD) input is held high while data is
clocked into the shift register, the latch will be transparent.
All four logic inputs are TTL compatible on the HI-8020 and
CMOS compatible ontheHI-8120.
on the rising edge of the Clock (CL). Clock (CL ), Load (LD)
and Chip Select (CS) should be tied in common with each
other, respectively, betweenall cascaded displaydrivers.
INTERNAL OSCILLATOR CIRCUIT
To display segments, a Logic "1" is stor ed in the appropriate
shift register bit position, and the segment output is out-of-
phase with thebackplane.
R
C
The backplane output functions in 1 of 2 modes; externally
driven or self-oscillating. When the LCDØ input is externally
driven with the LCDØOPT input open circuit (Figure 2), the
backplane output will be in-phase with LCDØ. Utilizing the
self-oscillating mode, inputs LCDØ and LCDØOPT are tied
together and connected to an RC circuit (Figure 3).
A 150KΩ resistor with a 470pF capacitor generates an
approximate backplane frequency of 100Hz. The
LCDØ/LCDØOPT oscillator frequency i s divided by 256 to
determine the backplane output frequency. The resistor
value (R) must be at least 30KΩ for proper self-oscillator
operation.
÷ 256
Q
LCDØ
LCDØ
OPT
TO BACKPLANE
TRANSLATOR
AND DRIVER
For displays having a number of segments greater than 38,
two or more of the display drivers may be cascaded together
by connecting the serial data output (DOUT) from the first
driver, to the serial data input (DIN) of the following driver,
etc.(See Figures 2 & 3). Data out (DOUT) will change state
Figure 1.
TIMING DIAGRAM
CL
INPUT
tCL
DIN
INPUT
VALID
tDS
tDH
CS
INPUT
tCSS
tLCS
tCSL
tCSH
LD
INPUT
tCDO
tLS
tLW
DOUT
OUTPUT
VALID
VALID
HOLT INTEGRATED CIRCUITS
3-10
HI-8020/HI-8120 Series
Voltages referenced to VSS = 0V
Supply Voltage VDD........................ 0V to 7V
VEE................VDD-35V to 0V
Voltage at any input, except LCDØ..-0.3 to VDD+0.3V
Power Dissipation......................................................300 mW
Operating Temperature Range - Industrial........-40° to +85°C
Operating Temperature Range - Hi-Temp/Mil..-55° to +125°C
Storage Temperature Range...........................-65° to +150°C
Voltage at LCDØ input...............VDD-35 to VDD+0.3V
DC Current any input pin...................................10 mA
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These a re stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational section s of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
Operating Voltage
SYMBOL
VDD
CONDITION
MIN
TYP
MAX UNITS
3.0
7.0
200
150
0.8
V
µA
µA
V
Supply Current
IDD
Static, No Load
IEE
Static, No Load fBP=100Hz
Input Low Voltage, HI-8020 (except LCDØ)
Input High Voltage, HI-8020 (except LCDØ)
Input Low Voltage, HI-8120 (except LCDØ)
VILTTL
VIHTTL
VILCMOS
0
2
VDD
0.3 VDD
VDD
3
V
0
V
Input High Voltage, HI-8120 (except LCD Ø) VIHCMOS
0.7 VDD
VEE
3.5
V
Input Low Voltage (LCDØ)
Input High Voltage (LCDØ)
Input Current
VILX
VIHX
IIN
V
VDD
1
V
VIN = 0 to 5V
µA
pF
Ω
Input Capacitance (not tested)
Segment Output Impedance
Backplane Output Impedance
Data Out Current:
CI
5
RSEG
RBP
IDOH
IDOL
IL = 10µA
IL = 10µA
10,000
450
-0.6
Ω
Source Current, VOH = 4.5V
Sink Current, VOL = 0.5V
mA
mA
0.6
AC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
tCL
VDD
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
MIN
1200
520
50
TYP
MAX
UNITS
ns
Clock Period
Clock Pulse Width
tCW
ns
Data In - Setup
tDS
ns
Data In - Hold
tDH
400
200
450
500
300
500
300
ns
Chip Select - Setup to Clock
Chip Select - Hold to Clock
Load - Setup to Clock
Chip Select - Setup to Load
Load Pulse Width
tCSS
tCSH
tLS
ns
ns
ns
tCSL
tLW
ns
ns
Chip Select - Hold to Load
Data Out Valid, from Clock
tLCS
tCDO
ns
800
ns
HOLT INTEGRATED CIRCUITS
3-11
HI-8020/HI-8120 Series
CASCADING - EXT. OSCILLATOR
LD
CL
CS
CASCADING - RC OSCILLATOR
LD
CL
CS
LD
DOUT
LD
DOUT
LD
DOUT
LD
DOUT
LD
CS CL
DIN
CS CL
DIN
CS CL
DIN
CS CL
DIN
LD
DOUT
CS CL
DIN
CS CL
DIN
DOUT
150KΩ
HI-8120J-85
HI-8120J-85
HI-8120J-85
HI-8020J-85
HI-8020J-85
HI-8020J-85
LCDØ
BP
LCDØ
BP
LCDØ
BP
LCDØ
BP
LCDØ
BP
LCDØ
BP
LCDØ OPT
LCDØ OPT
LCDØ OPT
470pf
SEGMENTS
1 - 33
SEGMENTS BACK
SEGMENTS
65 - 96
SEGMENTS
1 - 32
SEGMENTS BACK
SEGMENTS
65 - 96
33 - 64
PLANE
33 - 64
PLANE
Figure 2
Figure 3
PIN DESCRIPTIONS
POWER
INPUT
VSS
0 Volts
CS
Logic input
Logic input
Logic input
Logic input
Chip select
CL
INPUT
Clocks shift register on negative edge and DOUT pins on positive edge
Segment outputs equal shift register data if Load is high
Shift register data input
LD
INPUT
DIN
INPUT
LCD0
LCD0OPT
VDD
INPUT
Analog input
Display clock input and is always bonded out. Can swing from VEE to VDD
Bonded out only if an RC oscillator is required
OUTPUT
POWER
POWER
OUTPUT
OUTPUT
OUTPUT
Analog output
5 Volts
VEE
O Volts to -30 Volts
Logic output
DOUT
BP
Selected pinout can provide shift register taps at positions 30, 32, 34, or 38
Low resistance drive for the backplane and swings from VDD to VEE
High resistance drive for each segment and swings from VDD to VEE
Display dr ive output
Display drive output
Segments
ADDITIONAL HI-8020/HI-8120 PIN CONFIGURATIONS
(See page 3-9 for 44-Pin Plastic PLCC)
7
42
41
40
39
38
37
36
35
34
33
32
7
42
41
40
39
38
37
36
35
34
33
32
S17
S18
S19
S5
S4
S3
S2
S1
S38
S37
VDD
S17
S18
S19
S5
S4
S3
S2
8
8
HI-8020S-61
HI-8120S-61
HI-8020SM-62
&
HI-8020S-63
HI-8120S-63
HI-8020SM-64
&
9
9
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
BP
DOUT 38
S20
BP
DOUT 38
S20
S1
S38
S37
VDD
LCDØ
DIN
LD
HI-8120SM-62
HI-8120SM-64
S21
S22
S23
S24
S25
S26
S21
S22
S23
S24
S25
S26
48 - PIN
CERAMIC
LCC
LCDØ/LCDØOPT
DIN
LD
48 - PIN
CERAMIC
LCC
CL
CL
HOLT INTEGRATED CIRCUITS
3-12
HI-8020/HI-8120 Series
ORDERING INFORMATION
PART
NUMBER
NUMBER OF MASTER PACKAGE
SEGMENTS /SLAVE DESCRIPTION
TEMPERATURE
RANGE
BURN
IN
LEAD
FINISH
FLOW
TTL Input Logic
HI-8020J-85
HI-8020S-61
32
38
BOTH
44 PIN PLASTIC J LEAD
-40°C TO +85°C
I
I
NO SOLDER
NO GOLD
YES SOLDER
NO GOLD
MASTER 48 PIN CERAMIC LEADLESS CHIP CARRIER -40°C TO +85°C
MASTER 48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
HI-8020SM-62
38
M
HI-8020S-63
HI-8020SM-64
38
38
SLAVE 48 PIN CERAMIC LEADLESS CHIP CARRIER -40°C TO +85°C
SLAVE 48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
I
M
YES SOLDER
CMOS Input Logic
HI-8120J-85
HI-8120S-61
HI-8120SM-62
HI-8120S-63
HI-8120SM-64
32
38
38
38
38
BOTH
44 PIN PLASTIC J LEAD
-40°C TO +85°C
I
I
NO SOLDER
MASTER 48 PIN CERAMIC LEADLESS CHIP CARRIER -40°C TO +85°C
MASTER 48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
SLAVE 48 PIN CERAMIC LEADLESS CHIP CARRIER -40°C TO +85°C
SLAVE 48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
NO
YES SOLDER
NO GOLD
YES SOLDER
GOLD
M
I
M
SEMI-CUSTOM PACKAGING
The above part numbers represent some of the typical configurations of the HI-8020 & HI-8120 products. They can also b e provided
with a varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide vari ety of packages.
Listed below are currently available packages. Please contact the Holt Sales Department for your specific requirem ents.
PACKAGE
NO.
DESCRIPTION
LEADS
PLASTIC DUAL-IN-LINE (PDIP)
40
48
52
44
40
48
40
48
44
48
40
48
PLASTIC QUAD FLAT PACK (PQFP)
PLASTIC J-LEAD CHIP CARRIER (PLCC)
CERAMIC DUAL-IN-LINE (CDIP)
CERAMIC LEADLESS CHIP CARRIER (LCC)
CERAMIC J-LEAD CHIP CARRIER
CERAMIC LEADED CHIP CARRIER
HOLT INTEGRATED CIRCUITS
3-13
HI-8020/HI-8120 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC PLCC
Package Type:
44J
PIN NO. 1
PIN NO. 1 IDENT
.045 x 45°
.045 x 45°
.050 ± .005
(1.27 ± .127)
.690 ± .005
(17.526 ± .127)
SQ.
.653 ± .004
(16.586 ± .102)
.031± .005
(.787 ± .127)
SQ.
.017 ± .004
(.432 ± .102)
SEE DETAIL
A
.009
.011
.015 ± .002
(.381 ± .051)
.172 ± .008
(4.369 ± .203)
.020 MIN
(.508 MIN )
.025
R
.045
DETAIL A
.610 ± .020
(15.494± .508)
48-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 48S
.040 ± .007
(1.016 ± .178)
PIN 1 IDENT.
.090 MAX.
(2.286 MAX.)
PIN 1 IDENT.
.563 ± .009
(14.300 ± .228)
SQ.
.020 TYP.
(.508 TYP.)
.040 TYP.
(1.016 TYP.)
HOLT INTEGRATED CIRCUITS
1
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