HI-8504PSM [HOLTIC]
Line Driver,;
| 型号： | HI-8504PSM |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | Line Driver, 驱动 接口集成电路 |
| 文件： | 总15页 (文件大小：485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-8500
ARINC 429 Line Driver Family
with Tri-State Option
July 2017
FEATURES
DESCRIPTION
?
0, 10 and 37.5 Ohmoutputs
The HI-8500 family is a full-featuredARINC 429 Line Driver
providing three choices of output resistance and a tri-state
option, which allows the outputs to be put in a high-
impedance stateeven when the device ispowered off.
?Tri-stateoutputs are Hi-Zwith no power applied
?Wide power-supply range
Like Holt’s industry-standard HI-8585 and HI-8586 ARINC
429 line drivers, the HI-8500 includes digital slew-rate
selection to support high-speed (100kb/s) and low-speed
(12.5kb/s) data rates.
?
8kV ESD tolerance
?Digital slew-rate control
?
Drop-in alternative toDEI1070A-DEI1075A,
The part is offered in a variety of small footprint packages
including 5mm x 5mm 20-lead plastic QFN package and
traditional 8-pin SOIC package. Ceramic DIPs are also
available.
DEI1170A, DEI1171A
?DO-254 certifiable
Inputs are compatible with either 5V or 3.3V logic. Internal
pull-up/down resistors are available on HI-8507 for each
digital input. The resistors are brought out to pins, which
may be externally grounded to hold the ARINC bus in the
null-sate during system power-up, or connected to logic
power to hold the outputs tri-state. This feature is of benefit
when interfacing to field-programmable logic as it defines a
known-state during FPGA initialization, avoiding transient
bus noise atpower-on.
PIN CONFIGURATIONS
SLP1.5 - 1
TXIN0 - 2
TXIN1 - 3
GND - 4
8 - V+
7 - TXBn
6 - TXAn
5 - V-
The HI-8500 family offers a pin-for-pin drop-in replacement
for the DEI1070A-DEI1075A, DEI1170A and DEI1171A.
See table 1 forexactpart number crossreferences.
HI-8500PSx, HI-8501PSx, HI-8502PSx
HI-8503PSx, HI-8504PSx & HI-8505PSx
8 - PIN Plastic Narrow Body ESOIC
TSEN -
1
2
3
4
15 - SLP1.5
14 - RSLP (*)
13 -
-
-
V- -
12 - V+
TXA37 - 5
11 - TXB37
HI-8506PCx, HI-8507PCx
20-pin 5mm x 5mm Chip-Scale Package
(*) Not connected on HI-8506
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8500 Rev. B)
07/17
HI-8500
BLOCK DIAGRAM
SLP1.5
50K?
RSLP
(HI-8507 only)
+5V
TXA37
27.5?
TXA10
TSEN
10?
+
TXA0
INPUT
LOGIC
SLOPE
LINE
TXIN1
DRIVER
CONTROL
TXB0
-
50K?
10?
RIN1
(HI-8507 only)
TXB10
TRI-STATE
27.5?
TXIN0
TXB37
50K?
RIN0
(HI-8507 only)
V+
+5V
POWER
GND
REGULATION
-5V
V-
Figure 1
TRUTH TABLES
HI-8500, HI-8501, HI-8502
TXIN1
TXIN0
TXA
TXB
State
0
1
0
1
0
0
1
1
0V
5V
0V
-5V
+5v
0V
NULL State
ONE State
ZERO State
NULL State
-5V
0V
HI-8503, HI-8504, HI-8505
TXIN1
TXIN0
TXA
TXB
State
0
1
0
1
0
0
1
1
0V
5V
0V
-5V
+5v
Hi-Z
NULL State
ONE State
ZERO State
Tri-State
-5V
Hi-Z
HI-8506, HI-8507
TXIN1
TXIN0
TSEN
TXA
TXB
State
0
1
0
1
1
0
0
1
1
1
X
X
X
1
0V
5V
0V
-5V
+5v
0V
NULL State
ONE State
ZERO State
NULL State
Tri-State
-5V
0V
0
Hi-Z
Hi-Z
HOLT INTEGRATED CIRCUITS
2
HI-8500
CROSS-REFERENCE TABLE
DEI P/N
Holt P/N
Package
Output
Tri-State
Outputs
Burn-In
Temperature
Range
Resistance
DEI1070A-SES-G
DEI1070A-SMS-G
DEI1070A-SMB-G
DEI1070A-DMS
DEI1070A-DMB
DEI1071A-SES-G
DEI1071A-SMS-G
DEI1071A-SMB-G
DEI1071A-DMS
DEI1071A-DMB
DEI1072A-SES-G
DEI1072A-SMS-G
DEI1072A-SMB-G
DEI1072A-DMS
DEI1072A-DMB
DEI1073A-SES-G
DEI1073A-SMS-G
DEI1073A-SMB-G
DEI1073A-DMS
DEI1073A-DMB
DEI1074A-SES-G
DEI1074A-SMS-G
DEI1074A-SMB-G
DEI1074A-DMS
DEI1074A-DMB
DEI1075A-SES-G
DEI1075A-SMS-G
DEI1075A-SMB-G
DEI1075A-DMS
DEI1075A-DMB
DEI1170A-MESG
DEI1170A-MMSG
DEI1171A-MESG
DEI1171A-MMSG
HI-8500PSTF
HI-8500PSTF
HI-8500PSMF
HI-8500CRT
HI-8500CRM
HI-8501PSTF
HI-8501PSTF
HI-8501PSMF
HI-8501CRT
HI-8501CRM
HI-8502PSTF
HI-8502PSTF
HI-8502PSMF
HI-8502CRT
HI-8502CRM
HI-8503PSTF
HI-8503PSTF
HI-8503PSMF
HI-8503CRT
HI-8503CRM
HI-8504PSTF
HI-8504PSTF
HI-8504PSMF
HI-8504CRT
HI-8504CRM
HI-8505PSTF
HI-8505PSTF
HI-8505PSMF
HI-8505CRT
HI-8505CRM
HI-8506PCTF
HI-8506PCTF
HI-8506PCTF
HI-8506PCTF
8-pin ESOIC
8-pin ESOIC
8-pin ESOIC
8-pin CDIP
8-pin CDIP
8-pin ESOIC
8-pin ESOIC
8-pin ESOIC
8-pin CDIP
8-pin CDIP
8-pin ESOIC
8-pin ESOIC
8-pin ESOIC
8-pin CDIP
8-pin CDIP
8-pin ESOIC
8-pin ESOIC
8-pin ESOIC
8-pin CDIP
8-pin CDIP
8-pin ESOIC
8-pin ESOIC
8-pin ESOIC
8-pin CDIP
8-pin CDIP
8-pin ESOIC
8-pin ESOIC
8-pin ESOIC
8-pin CDIP
8-pin CDIP
20-lead QFN
20-lead QFN
20-lead QFN
20-lead QFN
37.5?
37.5?
37.5?
37.5?
37.5?
10?
No
No
No
No
-55 / +85°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +85°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +85°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +85°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +85°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +85°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +125°C
-55 / +85°C
-55 / +125°C
-55 / +85°C
-55 / +125°C
No
Yes
No
No
No
Yes
No
No
10?
No
No
10?
No
Yes
No
10?
No
10?
No
Yes
No
0?
No
0?
No
No
0?
No
Yes
No
0?
No
0?
No
Yes
No
37.5?
37.5?
37.5?
37.5?
37.5?
10?
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Yes
No
Yes
10?
Yes
No
10?
Yes
Yes
No
10?
Yes
10?
Yes
Yes
No
0?
Yes
0?
Yes
No
0?
Yes
Yes
No
0?
Yes
0?
Yes
Yes
No
0/10/37.5?
0/10/37.5?
0/10/37.5?
0/10/37.5?
Selectable
Selectable
Selectable
Selectable
No
No
No
Table 1
HOLT INTEGRATED CIRCUITS
3
HI-8500
PIN DESCRIPTIONS
HI-8500, HI-8501, HI-8502, HI-8503, HI-8504, HI-8505
PIN SYMBOL
FUNCTION
DESCRIPTION
1
2
3
4
5
6
7
8
SLP1.5
TXIN0
TXIN1
GND
V-
Digital Input
Digital Input
Slope Control. Set high for 1.5us output rise/fall time. Set low for 10us rise/fall time.
Negative data input. See truth table, figure 2.
Positive data input. See truth table, figure 2.
Ground
Digital Input
Power supply
Power supply
Analog output
Analog output
Power supply
Negative supply pin. -9.5V to -16.5V
TXAn
TXBn
V+
ARINC 429 bus positive output with n? internal resistor
ARINC 429 bus negative output with n? internal resistor
Positive supply pin. +9.5V to +16.5V
HI-8506, HI-8507
PIN SYMBOL
FUNCTION
DESCRIPTION
1
2
TSEN
-
Digital Input
-
Enables tri-state option. See truth table, figure 2. Internal 250k pull-up to 5V.
Not connected
3
-
-
Not connected
4
V-
Power supply
Analog output
Analog output
Analog output
-
Negative supply pin. -9.5V to -16.5V
5
TXA37
TXA10
TXA0
-
ARINC 429 bus positive output with 37.5? internal resistor
ARINC 429 bus positive output with 10? internal resistor
ARINC 429 bus positive output with 0? internal resistor
Not connected
6
7
8
9
TXB0
TXB10
TXB37
V+
Analog output
Analog output
Analog output
Power supply
Pull-up/down
Pull-up/down
Digital Input
Pull-up/down
Digital Input
Digital Input
Power supply
-
ARINC 429 bus negative output with 0? internal resistor
ARINC 429 bus negative output with 10? internal resistor
ARINC 429 bus negative output with 37.5? internal resistor
Positive supply pin. +9.5V to +16.5V
10
11
12
13
14
15
16
17
18
19
20
RIN1
RSLP
SLP1.5
RIN0
TXIN0
TXIN1
GND
-
50K? internal connection to TXIN1. May be connected to GND, VDD or left floating.
50K? internal connection to SLP1.5. May be connected to GND, VDD or left floating.
Slope Control. Set high for 1.5us output rise/fall time. Set low for 10us rise/fall time.
50K? internal connection to TXIN0. May be connected to GND, VDD or left floating.
Negative data input. See truth table, figure 2.
Positive data input. See truth table, figure 2.
Ground
Not connected
Note: Pins 13, 14 and 16 are not connected for HI-8506.
HOLT INTEGRATED CIRCUITS
4
HI-8500
FUNCTIONAL DESCRIPTION
Figure 2 is a block diagram of the line driver. The +5V and
-5V levels are generated from the supply voltages. Output
slope control is set by on-chip precision current sources
and capacitors.
A unity gain buffer receives the internally generated slopes
and differentially drives the ARINC line. Current is limited
by the series output resistors at each pin. There are no
fuses at the outputs of the HI-8500.
The TXIN0 and TXIN1 inputs receive logic signals from a
control transmitter chip such as the HI-3210 or FPGA.
TXAn and TXBn hold each side of the ARINC bus at
Ground until one of the inputs becomes a One. If for ex-
ample TXIN1 goes high, a charging path is enabled to 5V
on an “A” side internal capacitor while the “B” side is en-
abled to -5V. The charging current is selected by the
SLP1.5 pin. If the SLP1.5 pin is high, the capacitor is
nominally charged from 10% to 90% in 1.5µs. If SLP1.5 is
low, the rise and fall times are 10µs.
ARINC 429 requires that each line has a source imped-
ance of 37.5 Ohms. The TXA37 and TXB37 have the re-
quired resistance to directly drive the bus. Alternatively,
TXA/B10 or TXA/B0 outputs have 10 ohms or zero ohms
internally. The reduced resistance allows for external light-
ning protection circuitry to be added, while maintaining the
total output resistance at 37.5 Ohms. See Holt Applica-
tions Notes AN-300 and AN-301 for suitable, proven light-
ning protection schemes.
The HI-8500 is built using high-speed CMOS technology.
Care should be taken to ensure the V+ and V- supplies are
locally decoupled.
5V
“A” SIDE
ONE
TXAOUT
CURRENT
CONTROL
NULL
ZERO
-5V
CONTROL
LOGIC
TX0IN
ESD
PROTECTION
AND
SLP1.5
VOLTAGE
TRANSLATION
5V
“B” SIDE
TX1IN
ZERO
NULL
ONE
TXBOUT
CURRENT
CONTROL
-5V
CONTROL
LOGIC
FIGURE 2 - LINE DRIVER BLOCK DIAGRAM
5V
1
VCC
2
6
7
HARDWIRED
TESTA
ROUTA
ARX0P
ARX0N
OR
8
{
TESTB
DRIVEN FROM LOGIC
ROUTB
HI-8450
4
3
RINA
ARINC
HI-3200
APPLICATION INFORMATION
Channel
RINB
Figure 3 shows a possible application
of the HI-8500 interfacing an ARINC 429
transmit channel from the HI-3200.
5
HOST SPI
12V
8
V+
TXIN1
6
7
3
TXA37
ATX0P
ARINC
HI-8500
Channel
2
1
TXB37
ATX0N
TXIN0
SLP1.5
V-
ATXSLP0
GND
4
5
-12V
FIGURE 3 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
5
HI-8500
ABSOLUTE MAXIMUM RATINGS
PARAMETER
MIN
-0.3
-20
MAX
UNITS
V+ Supply Voltage
V- Supply Voltage
Storage Temperature
+20
V
+0.3
V
-65
+150
°C
Input voltage (TXIN0, TXIN1, SLP1.5, TSEN, RIN0, RIN1, RSLP)
-0.5
V+ +0.5
V
Output Voltage (200 µs surge)
TXA0, TXB0
V- -1.0
V- -5.0
V- - 20
V+ +1.0
V+ +5.0
V+ +20
V
V
V
TXA10, TXB10
TXA37, TXB37
Output Current (200 µs surge)
TXAn, TXBn
-800
+800
mA
Power Dissipation @ 125°C
8-lead ESOIC heat-sink soldered
8-pin ceramic DIP
1.2
1.0
1.0
W
W
W
20-lead QFN heat-sink soldered
Junction Temperature
Electrostatic Discharge
Peak Reflow Temperature
TJMAX
175
°C
kV
°C
JEDEC A114-A HBM
8
260
Notes:
1. Stressesabove absolute maximum ratings or outside recommended operating conditions
may cause permanent damage tothe device. These are stressratings only. Operation atthe
limits is not recommended.
2. The device is tolerant ofone or both outputs shorted toGND or toeach other.
3. Voltages referenced toGND
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
MAX
+16.5
-9.5
UNITS
V+ Supply Voltage
V- Supply Voltage
Operating Temperature
9.5
V
-16.5
V
“I” grade
“T” or “M” grade
-40
-55
+85
°C
°C
+125
HOLT INTEGRATED CIRCUITS
6
HI-8500
DC ELECTRICAL CHARACTERISTICS
V+/V- = +/- 9.5V to +/- 16.5V, T = Operating Temperature Range (unless otherwise stated)
A
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Input voltage (Logic Inputs)
high
low
VIH
VIL
2.0
-
-
V+
V
V
-0.3
0.8
Input current (TX1IN, TX0IN, SLP1.5)
source
sink
IIH
IIL
VIN = 5V
VIN = 0V
0
-
-
1.0
0
µA
µA
-1.0
Input current (TSEN)
source
sink
IIH
IIL
VIN = 5V
VIN = 0V
0
-
-
1.0
0
µA
µA
-100
ARINC output voltage (Differential)
one
zero
null
VDIFF1
VDIFF0
VDIFFN
no load; TXAn - TXBn
no load; TXAn - TXBn
no load; TXAn - TXBn
9.00
10.00 11.00
V
V
V
-11.00 -10.00 -9.00
-0.50
0
0.50
ARINC output voltage (Ref. to GND)
one or zero
null
VDOUT
VNOUT
no load & magnitude at pin
no load
4.50
5.00
0
5.50
0.25
V
V
-0.25
Output Tristate Leakage Current
IOZ
VOUT = -10V to +10V
-100
+100
µA
ARINC Output Short Circuit Current
(TXA0 or TXB0 pin)
Output Low
External 37.5? to GND
ISCLO
ISCHI
100
133
146
mA
mA
Output High
-146
-133
-100
Output Resistance
TXA37, TXB37
TXA10, TXB10
TXA0, TXB0
ROUT37
ROUT10
ROUT0
See Figure 5.
35
7.5
0
37.5
10
40
12.5
2.0
?
?
?
0.2
Operating supply current
SLP1.5 = V+
IV+
IV-
IDD
IEE
TX1IN & TX0IN = 0V: no load
-
3.0
6.0
-
mA
mA
TX0IN & TX1IN = 0V: no load -6.0
-2.5
HOLT INTEGRATED CIRCUITS
7
HI-8500
AC ELECTRICAL CHARACTERISTICS
V+/V- = +/-9.5V to +/-16.5V, T = Operating Temperature Range (unless otherwise
A
SYMBOL TEST CONDITIONS
PARAMETERS
MIN
TYP
MAX
UNITS
Line Driver propagation delay
defined in Figure 4, no load
ns
ns
Output high to low
Output low to high
t
-
-
500
500
-
-
phlx
t
plhx
Line Driver transition times
High Speed
SLP 1.5 = V+
Output high to low
Output low to high
t
1.0
1.0
1.5
1.5
2.0
2.0
µs
µs
fx
rx
t
Low Speed
SLP1.5 =GND
Output high to low
Output low to high
t
t
5.0
5.0
10.0
10.0
15.0
15.0
µs
µs
fx
rx
Input capacitance (1)
logic
C
-
-
10
pF
IN
Notes:
1. Guaranteed but not tested
5V
0V
TXIN1
t
phlx
t
t
plhx
plhx
5V
0V
TXIN0
t
phlx
t
rx
t
rx
10V
0V
90%
V
10%
10%
DIFF
90%
TXA - TXB
10%
-10V
t
fx
t
fx
FIGURE 4 - LINE DRIVER TIMING
HOLT INTEGRATED CIRCUITS
8
HI-8500
ARINC 429 SPECIFICATON COMPLIANCE CHARTS
11V
10.5V
10V
9.5V
9V
ARINC 429 Upper Limit
TA = -55°C
TA = 25°C
8.5V
TA = 125°C
8V
7.5V
ARINC 429 Lower Limit
7V
0
5
10
15
(533? )
20
(Open)
(1.6k? )
(800? )
(400? )
# ARINC 429 Loads
(RDIFF)
ARINC 429 bus Amplitude as a function of load
(Measured using TXA/B0 with 37.5? external resistors)
Figure 5
ARINC 429 Upper Limit
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
TA = -55°C
TA = 25°C
TA = 125°C
ARINC 429 Lower Limit
0
5
10
Capacitance (nF)
15
20
Hi-Speed ARINC 429 bus rise / fall time versus total bus capacitance
(Measured using TXA/B0 with 37.5? external resistors)
Figure 6
HOLT INTEGRATED CIRCUITS
9
HI-8500
ARINC 429 SPECIFICATON COMPLIANCE CHARTS
18
17
16
15
14
13
12
11
10
9
ARINC 429 Upper Limit
TA = -55°C
TA = 25°C
TA = 125°C
8
7
ARINC 429 Lower Limit
6
5
0
10
20
Capacitance (nF)
30
40
Lo-Speed ARINC 429 bus rise / fall time versus total bus
capacitance
Figure 7
2000
-55C
-40C
25C
1500
1000
500
0
+85C
+125C
-500
1000
-1500
-2000
-11.00-9.00 -7.00 -5.00 -3.00 -1.00 1.00 3.00 5.00 7.00 9.00 11.00
Bus Voltage (V)
Tri-state leakage current
(V+ = +12V, V- = -12V)
Figure 8
HOLT INTEGRATED CIRCUITS
10
HI-8500
THERMAL CHARACTERISTICS
Maximum ARINC Load
1
2
PACKAGE STYLE
ARINC 429
SUPPLY CURRENT (mA)
JUNCTION TEMP, Tj °C
DATA RATE Ta = 25°C
Ta = 85°C
Ta = 125°C
Ta = 25°C
Ta = 85°C
Ta = 125°C
3
Low Speed
20.98
26.40
20.96
26.16
20.96
25.96
38.24
44.78
98.34
138.92
144.59
5
8 Lead Plastic ESOIC
4
High Speed
104.66
6,7,8
TXAOUT and TXBOUT Shorted to Ground
1
2
PACKAGE STYLE
ARINC 429
SUPPLY CURRENT (mA)
JUNCTION TEMP, Tj °C
DATA RATE Ta = 25°C
Ta = 85°C
Ta = 125°C
Ta = 25°C
Ta = 85°C
Ta = 125°C
3
Low Speed
30.26
30.44
29.22
29.42
28.46
28.68
53.75
53.92
112.76
112.95
152.04
152.25
5
8 Lead Plastic ESOIC
4
High Speed
Notes:
1. All data taken in still air.
2. At 100% duty cycle, +/-15V power supplies.
3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF.
4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF.
5. 8 Lead Plastic ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink not soldered.
6. Similar results would be obtained with TXAOUT shorted to TXBOUT.
7. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.
8. Data will vary depending on air flow and the method of heat sinking employed.
HEAT SINK - ESOIC PACKAGES
HEAT SINK - QFN PACKAGES
An 8-pin thermally enhanced SOIC package is used for the
HI-8500 through HI-8505 products. The ESOIC package
includes a metal heat sink located on the bottom surface of
the device. This heat sink should be soldered down to the
printed circuit board for optimum thermal dissipation. The
heat sink is electrically isolated from the chip and can be
soldered to any ground or power plane.
A 20-pin thermally enhanced QFN package is used for the
HI-8506 and HI-8507 products. The QFN package
includes a metal heat sink located on the bottom surface of
the device. This heat sink should be soldered down to the
printed circuit board for optimum thermal dissipation. The
heat sink is electrically isolated from the chip and can be
soldered to any ground or power plane.
HOLT INTEGRATED CIRCUITS
11
HI-8500
ORDERING INFORMATION
HI-8500, HI-8501, HI-8502, HI-8503, HI-8504, HI-8505
HI - 850x xx x F
PART
LEAD
NUMBER
FINISH
100% Matte Tin (Pb-free, RoHS compliant)
Pb/Sn
F
Blank
PART
TEMPERATURE
FLOW
BURN
IN
NUMBER
RANGE
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
I
I
NO
NO
T
T
M
M
YES
PART
PACKAGE
NUMBER
DESCRIPTION
PS
CR
8-Pin Thermally enhanced SOIC (ESOIC) (8HNE)
8-pin Ceramic Dual-In-Line (CDIP) (8D) (Not available Pb-free)
PART
OUTPUT
TRI-STATE
OUTPUTS
NUMBER
RESISTANCE
8500
8501
8502
8503
8504
8505
37.5?
10?
0?
NO
NO
NO
37.5?
10?
0?
YES
YES
YES
HI-8506, HI-8507
HI - 850x PC x F
PART
LEAD
NUMBER
FINISH
NiPdAu (Pb-free, RoHS compliant)
F
PART
TEMPERATURE
FLOW
BURN
NUMBER
RANGE
IN
I
-40°C TO +85°C
I
NO
NO
T
-55°C TO +125°C
T
PART
PACKAGE
NUMBER
DESCRIPTION
PC
20-Lead 5mm x 5mm Plastic QFN (20PCS)
PART
RIN1, RIN0, RSLP Pins
NUMBER
8506
8507
Not connected (Pin is open-circuit)
Pins connected
HOLT INTEGRATED CIRCUITS
12
HI-8500
REVISION HISTORY
P/N
Rev
Date
Description of Change
DS8500
New
A
07/28/16
06/26/16
Initial Release.
Correct typo in HI-8507 pin definition. Clarify that tri-state outputs are Hi-Z even
when the device is powered down.
B
7/12/17
Updated Tri-state leakage current Figure 8
HOLT INTEGRATED CIRCUITS
13
PACKAGE DIMENSIONS
8-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB
millimeters (inches)
(Narrow Body, Thermally Enhanced)
Package Type: 8HNE
Top View
0.175 ± 0.075
4.90
Bottom View
(0.007 ± 0.003)
BSC
(0.193)
3.048 ± 0.305
(0.120 ± 0.012)
3.90
6.00
2.235 ± 0.305
BSC
BSC
PIN 1
(0.154)
(0.236)
(0.088 ± 0.012)
Electrically isolated heat
sink pad on bottom of
package
SEE DETAIL A
0.410 ± 0.100
(0.016 ± 0.004)
1.25
Connect to any ground or
power plane for optimum
thermal dissipation
min
(0.049)
0°to 8°
0.075 ± 0.075
(0.003 ± 0.003)
1.27
BSC
0.835 ± 0.435
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
(0.50)
(0.033 ± 0.017)
DETAIL A
20-PIN PLASTIC CHIP-SCALE PACKAGE
millimeters (inches)
Package Type: 20PCS
Electrically isolated heat sink
pad on bottom of package.
Connect to any ground or
3.075 ± 0.075
power plane for optimum
5.00
(0.121 ± 0.003)
BSC
thermal dissipation.
(0.197)
0.65
BSC
(0.026)
5.00
3.075 ± 0.075
(0.121 ± 0.003)
Bottom
View
BSC
Top View
(0.197)
0.30 ± 0.050
(0.012 ± 0.002)
0.550 ± 0.100
(0.0217 ± 0.004)
1.00
.200
max.
typ.
(0.039)
(0.008)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
14
PACKAGE DIMENSIONS
inches (millimeters)
8-PIN CERDIP
Package Type: 8D
.380 ±.004
(9.652 ±.102)
.005 min
(.127 min)
.248 ±.003
(6.299 ±.076)
.039 ±.006
.100
BSC
(.991 ±.154)
(2.54)
.314 ±.003
(7.976 ±.076)
.015 min
(.381min)
.200 max
(5.080 max)
Base Plane
.010 ±.006
(.254 ±.152)
Seating Plane
.163 ±.037
.018 ±.006
.350 ±.030
(4.140 ±.940)
(.457 ±.152)
.056 ±.006
(8.890 ±.762)
(1.422 ±.152)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
15
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