HI-8588PDMF [HOLTIC]
ARINC 429 LINE RECEIVER; ARINC 429线路接收器
| 型号： | HI-8588PDMF |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | ARINC 429 LINE RECEIVER |
| 文件： | 总6页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-8588
ARINC 429 LINE RECEIVER
August 2006
DESCRIPTION
PIN CONFIGURATION
The HI-8588 is an ARINC 429 bus interface receiver and is
available in a SO 8 pin package. The technology is
analog/digital CMOS. The circuitry requires only a 5 volt
supply.
VCC - 1
TESTA - 2
RINB - 3
RINA - 4
8 - TESTB
7 - ROUTB
6 - ROUTA
5 - GND
8588PS
The ARINC bus can be connected directly to the chip. The
typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are
just below the standard 6.5 volt minimum ARINC data
threshold and just above the standard 2.5 volt maximum
ARINC null threshold.
8 - PIN PLASTIC NARROW BODY SOIC
SUPPLY VOLTAGES
The TESTA and TESTB inputs bypass the analog for
testing purposes. Also if TESTAand TESTB are both taken
high, the analog powers down and the digital outputs tri-
state allowing wire-or possibilities.
vcc = 5.0V 5%
Please refer to the HI-8588-10 for applications where an
external resistance in series with the ARINC inputs is
required for lightning protection or when the digital outputs
need to be a logic zero rather than open circuit when
TESTAandTESTB are both high.
FUNCTION TABLE
RECEIVER
RINA
RINB
TESTA TESTB ROUTA ROUTB
See Holt Application Note AN-300 for more information on
lightning protection.
-1.25V to 1.25V
-1.25V to 1.25V
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
1
-3.25V to -6.5V
3.25V to 6.5V
3.25V to 6.5V
-3.25V to -6.5V
1
0
FEATURES
X
X
X
X
X
X
0
1
! Direct ARINC 429 line receiver interface
in a small outline package
1
0
HI-Z
HI-Z
! Receiver input hystersis at least 2 volts
PIN DESCRIPTION TABLE
! Test inputs that bypass analog input and
can power down and tri-state outputs
PIN
1
SYMBOL
VCC
FUNCTION
SUPPLY
DESCRIPTION
5 VOLT SUPPLY
CMOS
! Plastic and ceramic package options -
2
TESTA
RINB
LOGIC INPUT
ARINC INPUT
ARINC INPUT
POWER
surface mount and DIP
3
RECEIVER B INPUT
RECEIVER A INPUT
GROUND
4
RINA
5
GND
! Mil processing available
6
ROUTA
ROUTB
TESTB
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC INPUT
RECEIVER CMOS OUTPUT A
RECEIVER CMOS OUTPUT B
CMOS
7
8
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8588 Rev. C)
08/06
HI-8588
FUNCTIONAL DESCRIPTION
RECEIVER
The status of the ARINC receiver input is latched. A
Null input resets the latches and a One or Zero input
sets the latches.
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINAand RINB each have series resistors, typi-
cally 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, then
the receiver is powered down and the output pins float.
The powerdown does not disconnect the internal resis-
tors at the ARINC input.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider be-
tween VCC and Ground. The nominal settings correspond
to a One/Zero amplitude of 6.0V and a Null amplitude of
3.3V.
TEST
ONE
S
Q
ROUTA
LATCH
R
TEST
'
TESTA TESTB
TESTA
RINA
ESD
NULL
PROTECTION
AND
TEST
TRANSLATION
ZERO
RINB
S
Q
ROUTB
LATCH
R
TEST
'
TESTA TESTB
TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
5V
1
VCC
2
6
7
HARDWIRE
OR
DRIVE FROM LOGIC
TESTA
TESTB
ROUTA
ROUTB
RXD1
RXD0
8
{
HI-8588
4
RINA
ARINC
Channel
HI-6010
3
APPLICATION INFORMATION
RINB
5
Figure 2 shows a possible application
of the HI-8588 interfacing anARINC re-
ceive channel to the HI-6010 which in
turn interfaces to an 8-bit bus.
8 BIT BUS
15V
1
SLP1.5 V+
8
6
7
3
2
TXD1
TXD0
TXAOUT TX1IN
ARINC
Channel
HI-8586
TXBOUT
TX0IN
GND
V-
5
4
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-8588
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Voltages referenced to Ground
Supply Voltages
VCC...........................................5V 5%
Supply voltages
VCC...................................................7V
Temperature Range
ARINC input - pins 3 & 4
Voltage at either pin......+29V to -29V
Industrial Screening........-40°C to +85°C
Hi-Temp Screening.......-55°C to +125°C
Military Screening.........-55°C to +125°C
DC current per input pin................ 10mA
Power dissipation at 25°C
plastic DIP............0.7W
ceramic DIP..........0.5W
NOTE: Stresses above absolute maximum
ratings or outside recommended operating con-
ditions may cause permanent damage to the
device. These are stress ratings only. Opera-
tion at the limits is not recommended.
Solder Temperature ........275°C for 10 sec
Storage Temperature........-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V UNLESS OTHERWISE STATED
OPERATING TEMPERATURE RANGE,
SYMBOL TEST CONDITIONS
MIN
TYP
MAX UNITS
PARAMETERS
ARINC input voltage
one or zero
V
V
differential voltage, pins 3 & 4
6.5
10
-
13
2.5
5.0
volts
volts
volts
DIN
null
"
"
"
-
-
NIN
common mode
V
with respect to Ground
-
COM
logic input voltage
high
low
V
3.5
-
-
-
-
volts
volts
IH
IL
V
1.5
ARINC input resistance
RINA to RINB
supplies floating
Kohm
Kohm
R
R
30
19
75
40
-
-
DIFF
SUP
"
"
RINA or RINB to Gnd or VCC
logic input current
source
I
-
-
-
-
0.1
0.1
µA
µA
V
V
= 0 V
= 5 V
IH
IN
IN
sink
I
IL
logic output drive current
V
= 4.6V
= 0.4V
mA
mA
one
I
I
-
-1.6
5.6
-0.8
-
OH
OL
OH
V
zero
3.6
OL
Current drain
operating
I
I
pins 2, 8 = 0V; pins 3, 4 open
pins 2, 8 = 5V; pins 3, 4 open
mA
mA
-
-
2.3
6.3
0.6
CC1
CC2
powerdown
0.36
HOLT INTEGRATED CIRCUITS
3
HI-8588
AC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE,
VCC = 5.0V UNLESS OTHERWISE STATED
PARAMETERS
SYMBOL TEST CONDITIONS
MIN
TYP
MAX UNITS
Receiver propagation delay
Output high to low
defined in Figure 3, C = 50pF
L
t
-
-
600
600
-
-
ns
ns
phlr
Output low to high
t
plhr
Receiver output transition times
Output high to low
t
fr
-
-
50
50
80
80
ns
ns
t
Output low to high
rr
Input capacitance (1)
ARINC differential
ARINC single ended to Ground
Logic
C
-
-
-
5
-
10
10
10
pF
pF
pF
AD
C
AS
C
-
IN
Notes: 1. Guaranteed but not tested
10V
V
DIFF
pin 4 - pin 3
0V
-10V
t
t
plhr
t
t
rr
rr
t
t
phlr
5V
0V
90%
10%
pin 6
pin 7
t
t
t
t
fr
plhr
t
t
phlr
5V
0V
FIGURE 3 - RECEIVER TIMING
ORDERING INFORMATION
HI - 8588 xx x x
PART
NUMBER
LEAD
FINISH
Tin / Lead (Sn / Pb) Solder
100% Matte Tin (Pb-free, RoHS compliant)
Blank
F
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
I
NO
NO
T
M
T
M
YES
PART
NUMBER
PACKAGE
DESCRIPTION
PD
PS
CR
8 PIN PLASTIC DIP (not available with “M” flow)
8 PIN PLASTIC NARROW BODY SOIC
8 PIN CERDIP (not available Pb-free)
HOLT INTEGRATED CIRCUITS
4
HI-8588 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN PLASTIC DIP
Package Type: 8P
.385 .015
(4.699 .381)
.250 .010
(6.350 .254)
.100 .010
(3.540 .254)
.300 .010
(7.620 .254)
7° TYP.
.025 .010
(.635 .254)
.135 .015
(3.429 .381)
.0115 .0035
(.292 .089)
.1375 .0125
(3.493 .318)
.055 .010
(1.397 .254)
.335 .035
(8.509 .889)
.019 .002
(.483 .102)
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
(Narrow Body)
Package Type:
8HN
.1935 .0035
(4.915 .085)
.0086 .0012
(.2184 .0305)
.236 .008
(5.994 .203)
.1535 .0035
(3.90 .09)
PIN 1
.0165 .0035
(.4191 .0889)
Detail A
.055 .005
(1.397 .127)
0° to 8°
.0069 .0029
(.1753 .0737)
.050 .010
(1.27 .254)
.033 .017
(.8382 .4318)
Detail A
HOLT INTEGRATED CIRCUITS
5
HI-8588 PACKAGE DIMENSIONS
inches (millimeters)
8-PIN CERDIP
8D
Package Type:
.380 .004
(9.652 .102)
.005 MIN.
(.127 MIN.)
.248 .003
(6.299 .076)
.039 .006
(.991 .154)
.100 .008
(2.540 .203)
.015 MIN.
.314 .003
(7.976 .076)
(.381 MIN.)
.200 MAX.
(5.080 MAX.)
Base Plane
.010 .006
(.254 .152`)
Seating Plane
.163 .037
(4.140 .940)
.018 .006
(.457 .152)
.350 .030
(8.890 .762)
.056 .006
(1.422 .152)
HOLT INTEGRATED CIRCUITS
6
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