HI-8591PDF-40 [HOLTIC]
Line Receiver, 1 Func, 1 Rcvr, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8;
| 型号： | HI-8591PDF-40 |
| 厂家： | 
HOLT INTEGRATED CIRCUITS |
| 描述： | Line Receiver, 1 Func, 1 Rcvr, PDIP8, ROHS COMPLIANT, PLASTIC, DIP-8 光电二极管 |
| 文件： | 总7页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-8591
ARINC 429
Line Receiver
March 2007
DESCRIPTION
PIN CONFIGURATIONS
The HI-8591 is an ARINC 429 bus interface receiver
designed to operate from a single 3.3 V or 5 V supply. The
part is designed with high-impedance inputs to minimize
bus loading, and has an exceptional input common-mode
performance in excess of +/- 30V, making it immune to
ground offsets around the aircraft. The RINA and RINB
inputs of the standard HI-8591 may be connected directly
to the ARINC 429 bus. To enable external lightning protec-
tion circuitry to be added, the HI-8591-40 variant is avail-
able. The HI-8591-40 requires only the addition of external
40 KW, ¼ watt resistors in series with RINA and RINB to
allow the part to meet the lightning protection requirements
of DO-160D level 3.
VCC - 1
TESTA - 2
RINB - 3
RINA - 4
8 - TESTB
7 - ROUTB
6 - ROUTA
5 - GND
HI-8591PSI, HI-8591PST & HI-8591PSM
HI-8591PSI-40, HI-8591PST-40 & HI-8591PSM-40
8 - PIN PLASTIC NARROW BODY SOIC
TESTA
RINB
1
2
12 ROUTB
11 NC
The typical 10 volt differential ARINC 429 signal is trans-
lated and input to a window comparator and latch. The
comparator levels are set just below the standard 6.5 volt
minimum ARINC data threshold and just above the stan-
dard 2.5 volt maximumARINC null threshold.
10 ROUTA
RINA
NC
3
4
9
NC
The TESTAand TESTB inputs bypass the analog inputs for
testing purposes. Also if TESTAand TESTB are both taken
high, the digital outputs are forced to zero.
HI-8591PCI, HI-8591PCT, HI-8591PCI-40 & HI-8591PCT-40
16- pin 4mm x 4mm Chip-scale package
See Holt Application Note AN-300 for more information on
lightning protection.
SUPPLY VOLTAGES
vcc = 3.3V 10%, 5.0V 10%
FEATURES
FUNCTION TABLE
! ARINC 429 line receiver interface in a
small outline package
RINA
RINB
TESTA TESTB ROUTA ROUTB
-1.25V to 1.25V
-1.25V to 1.25V
0
0
0
0
1
1
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
0
-3.25V to -6.5V
3.25V to 6.5V
! 3.3V single rail supply voltage
! +/-30 V common-mode performance
! >140 KOhm input impedance
3.25V to 6.5V
-3.25V to -6.5V
X
X
X
X
X
X
! Lightning protection simplified with the
ability to add 40 KOhm external series
resistors
PIN DESCRIPTION TABLE
SYMBOL
VCC
FUNCTION
DESCRIPTION
SUPPLY
3.3V or 5V SUPPLY
CMOS
TESTA
RINB
LOGIC INPUT
ARINC INPUT
ARINC INPUT
POWER
RECEIVER B INPUT
RECEIVER A INPUT
GROUND
! Receiver input hysteresis at least 2 volt
RINA
GND
! Test inputs bypass analog inputs and
force digital outputs to a one, zero or
null state
ROUTA
ROUTB
TESTB
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC INPUT
RECEIVER CMOS OUTPUT A
RECEIVER CMOS OUTPUT B
CMOS
HOLT INTEGRATED CIRCUITS
www.holtic.com
(DS8591, Rev. E)
03/07
HI-8591
FUNCTIONAL DESCRIPTION
RECEIVER
spond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 140KW of resis-
tance between the ARINC bus and comparator. This resis-
tance is completely on-chip for the HI-8591. In contrast,
the HI-8591-40 has 100 KW on-chip and requires an exter-
nal 40KW, ¼ watt resistor on each of the ARINC 429 input
pins. The HI-8591-40 device is typically chosen for appli-
cations where lightning protection is a requirement.
The status of theARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, the HI-
8591 outputs are pulled low. This allows the digital out-
puts of a transmitter to be connected to the test inputs
through control logic for system self-test purposes.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider
between V.C. and Ground. The nominal settings corre-
TEST
ONE
S
Q
ROUTA
LATCH
R
TESTA
TESTB
RINA
ESD
NULL
PROTECTION
AND
TEST
TRANSLATION
RINB
ZERO
S
Q
ROUTB
LATCH
R
TESTA
TESTB
NULL
FIGURE 1 - RECEIVER BLOCK DIAGRAM
3.3V
1
VCC
2
6
7
HARDWIRE
OR
DRIVE FROM LOGIC
TESTA
TESTB
ROUTA
ROUTB
RXD1
RXD0
8
{
HI-8591
4
3
RINA
ARINC
Channel
FPGA
APPLICATION INFORMATION
RINB
GND
Figure 2 shows a possible application of the
HI-8591 interfacing an ARINC 429 bus input
to a 3.3V ASIC or FPGA. In this example a
HI-8586 ARINC 429 line driver is used to
take 3.3V logic outputs and generate the nec-
essary 10V differential signal for driving an
ARINC 429 bus.
5
15V
1
SLP1.5
8
V+
6
7
3
TXAOUT
TXD1
TXD0
TX1IN
ARINC
Channel
HI-8586
TXBOUT
2
TX0IN
GND
V-
5
4
-15V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-8591
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Voltages referenced to Ground
Supply Voltages
VCC..............................3.3V to 5V 10%
Supply voltages
VCC......................................-0.3V to +7V
Temperature Range
ARINC input - pins 3 & 4
Voltage at either pin.........+120V to -120V
Industrial Screening........-40°C to +85°C
Hi-Temp Screening.......-55°C to +125°C
Military Screening.........-55°C to +125°C
DC current per input pin.................... 10mA
Power dissipation at 25°C
plastic DIP............0.7W
ceramic DIP..........0.5W
NOTE: Stresses above absolute maximum
ratings or outside recommended operating con-
ditions may cause permanent damage to the
device. These are stress ratings only. Opera-
tion at the limits is not recommended.
Solder Temperature .........275°C for 10 sec
Storage Temperature........-65°C to +150°C
DC ELECTRICAL CHARACTERISTICS
VCC = 3.3V 10% or 5.0V 10% UNLESS OTHERWISE STATED
OPERATING TEMPERATURE RANGE,
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PARAMETERS
ARINC input voltage
one or zero
V
V
Differential volt., pins 3 & 4
6.5
-
10
-
13
2.5
volts
volts
volts
DIN
NIN
null
"
"
with respect to ground
"
common mode
V
-30.0
-
+30.0
COM
logic input voltage
-
-
-
70% VCC
-
volts
high
low
V
IH
V
30% VCC volts
IL
ARINC input resistance
RINA to RINB
KW
Supplies floating
-
-
-
R
R
R
140
140
100
-
DIFF
GND
VCC
KW
RINA or RINB to GND
RINA or RINB to VCC
-
"
"
"
"
KW
-
logic input current
source
I
V
V
= 2.0V
-
-
-
-
20.0
20.0
µA
µA
IH
IN
IN
sink
I
= 0.8V
IL
logic output drive voltage
one
2.4
2.4
V
V
-
-
-
-
V
V
VCC = 5V 10% I
= 5mA
OH1
OH
VCC= 3.3V 10% I
VCC = 5V 10% I
= 1.5mA
OH2
OH
zero
V
V
= 5mA
OH
-
-
-
-
0.5
0.4
V
V
OL1
VCC = 3.3V 10% I
OH
= 1.5mA
OL2
Current drain
operating
-
I
pins 2, 8 = 0V; pins 3, 4 open
1.5
5.0
mA
CC1
HOLT INTEGRATED CIRCUITS
3
HI-8591
AC ELECTRICAL CHARACTERISTICS
OPERATING TEMPERATURE RANGE,
VCC = 3.3V 10% or 5.0V 10% UNLESS OTHERWISE STATED
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Receiver propagation delay
Output high to low
defined in Figure 3, C = 50pF
L
t
VCC = 3.3V 10%
VCC = 5.0V 10%
VCC = 3.3V 10%
VCC = 5.0V 10%
-
-
-
-
600
600
600
600
1000
900
ns
ns
ns
ns
phlr
Output low to high
t
1000
900
plhr
TEST pin propagation delay
Output high to low
defined in Figure 4, C = 50pF
L
t
VCC = 3.3V 10%
VCC = 5.0V 10%
VCC = 3.3V 10%
VCC = 5.0V 10%
-
-
-
-
-
-
-
-
100
60
ns
ns
pth
Output low to high
t
100
60
ns
ns
ptl
Receiver output transition times
Output high to low
VCC = 3.3V or 5.0V 10%
t
fr
-
-
15
15
50
50
ns
ns
t
Output low to high
rr
Input capacitance (1)
ARINC differential
ARINC single ended to Ground
Logic
C
-
-
-
5
-
10
10
10
pF
pF
pF
AD
C
AS
C
-
IN
Notes: 1. Guaranteed but not tested
10V
0V
-10V
V
DIFF
pin 4 - pin 3
t
plhr
t
rr
t
phlr
VCC
90%
pin 6
pin 7
10%
0V
t
t
fr
plhr
t
phlr
VCC
0V
FIGURE 3 - RECEIVER TIMING
VCC
0V
TESTA or B
pin 2 or pin 8
t
pth
t
ptl
VCC
0V
pin 6 or pin 7
FIGURE 4 - TEST PIN TIMING
HOLT INTEGRATED CIRCUITS
4
HI-8591
HEAT SINK - CHIP-SCALE PACKAGE ONLY
The HI-8591PCI and HI-8591PCT use a 16-pin plastic
chip-scale package. This package has a metal heat sink
pad on its bottom surface. This heat sink is electrically
connected to the die. To enhance thermal dissipation, the
heat sink can be soldered to matching circuit board pad.
The heat sink may be connected to VDD or left floating.
Do not connect heat sink pad to GND.
ORDERING INFORMATION
HI - 8591 xx x x - xx
INPUT SERIES RESISTANCE
PART
NUMBER
BUILT-IN
140 Kohm
100 Kohm
REQUIRED EXTERNALLY
0
No dash number
-40
40 Kohm
LEAD
PART
NUMBER
FINISH
Tin / Lead (Sn / Pb) Solder
Blank
F
100% Matte Tin (Pb-free, RoHS compliant)
PART
NUMBER
TEMPERATURE
RANGE
FLOW
BURN
IN
I
-40°C TO +85°C
-55°C TO +125°C
I
NO
NO
T
T
M
-55°C TO +125°C
M
YES
PART
NUMBER
PACKAGE
DESCRIPTION
16 PIN PLASTIC 4 x 4 mm CHIP SCALE (16PCS) not available with “M” flow
8 PIN PLASTIC DIP (8P) not available with “M” flow
8 PIN PLASTIC NARROW BODY SOIC (8HN)
PC
PD
PS
CR
8 PIN CERDIP (8D) not available Pb-free
HOLT INTEGRATED CIRCUITS
5
HI-8591 PACKAGE DIMENSIONS
8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB
(Narrow Body)
inches (millimeters)
Package Type: 8HN
.194 .004
(4.92 .09)
.0085 .0015
(.216 .038)
.236 .008
(5.99 .21)
.154 .004
(3.90 .09)
PIN 1
See Detail A
.0165 .003
(.419 .089)
.055 .005
(1.397 .127)
0° to 8°
.0069 .003
(.1753 .074)
.050
(1.27)
.033 .017
(.838 .432)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
BSC
Detail A
inches (millimeters)
8-PIN CERDIP
Package Type: 8D
.380 ±.004
(9.652 ±.102)
.005 min
(.127 min)
.248 ±.003
(6.299 ±.076)
.039 ±.006
(.991 ±.154)
.100
(2.54)
BSC
.314 ±.003
(7.976 ±.076)
.015 min
(.381min)
.200 max
(5.080 max)
Base Plane
.010 ±.006
(.254 ±.152)
Seating Plane
.163 ±.037
(4.140 ±.940)
.018 ±.006
(.457 ±.152)
.350 ±.030
(8.890 ±.762)
.056 ±.006
(1.422 ±.152)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
6
HI-8591 PACKAGE DIMENSIONS
8-PIN PLASTIC DIP
inches (millimeters)
Package Type: 8P
.385 ±.015
(9.799 ±.381)
.250 .010
(6.350 ±.254)
.100
(2.54)
BSC
.300 ±.010
(7.620 ±.254)
.025 ±.010
(.635 .254)
.135 ±.015
(3.429 ±.381)
.0115 ±.0035
(.292 ±.089)
.1375 ±.0125
(3.493 ±.318)
.055 ±.010
(1.397 ±.254)
.335 ±.035
(8.509 ±.889)
.019 ±.002
(.483 ±.102)
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
16-PIN PLASTIC CHIP-SCALE PACKAGE
millimeters
Package Type: 16PCS
Heat sink pad on bottom of
package. Heat sink can float
or can be connected to VDD.
DO NOT connect heat sink to
GND
2.15 .15
4.00 BSC
0.65 BSC
Bottom
View
Top View
4.00 BSC
2.15 .15
0.30 .05
0.55 .1
1.00 max
0.20 typ
BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)
HOLT INTEGRATED CIRCUITS
7
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