HT46R01A3_技术文档

HT46R01A

Small Package A/D Type 8-Bit OTP MCU

Technical Document

·

Tools Information

FAQs

Application Note

-

HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM

HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series

HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series

HA0049E Read and Write Control of the HT1380

HA0075E MCU Reset and Oscillator Circuits Application Note

Features

·

Operating voltage:

Power down and wake-up functions to reduce power

consumption

f

_SYS= 4MHz: 2.2V~5.5V

_SYS= 8MHz: 3.3V~5.5V

_SYS= 12MHz: 4.5V~5.5V

Up to 0.33ms instruction cycle with 12MHz system

clock at V_DD= 5V

·

7 bidirectional I/O lines and 1 input line

·

4-level subroutine nesting

External interrupt input shared with an I/O line

4-channel 8-bit resolution A/D converter

8-bit PWM output shared with I/O line

Bit manipulation instruction

Table read instructions

Single 8-bit programmable Timer/Event Counters

with overflow interrupt and 7-stage prescaler

·

External crystal system oscillator

Fully integrated internal RC oscillator available with

three frequencies: 4MHz, 8MHz or 12MHz

63 powerful instructions

All instructions executed in one or two machine cy-

cles

·

Watchdog Timer function

PFD for audio frequency generation

·

Low voltage reset function

10-pin ultra-small MSOP package

General Description

The HT46R01A is 8-bit high performance, RISC archi-

tecture microcontroller devices specifically designed for

a wide range of applications. In addition to providing the

usual microcontroller I/O control functions, the fully inte-

grated A/D converter allows the interfacing and pro-

cessing of external analog signals such as those from

sensors. The PWM function also allows the driving of

external analog signals for applications such as motor

driving while the PFD function provides a means of gen-

erating a fixed frequency reference. The usual Holtek

microcontroller features of low power consumption, I/O

flexibility, timer functions, oscillator options, power

down and wake-up functions, watchdog timer and low

voltage reset, combine to provide devices with a huge

range of functional options while still maintaining cost

effectiveness. Their fully integrated system oscillator,

with three frequency selections, and being supplied in

an extremely small outline MSOP 10-pin package

opens up a huge range of new application possibilities

for these devices, some of which may include industrial

control, consumer products, household appliances sub-

system controllers, etc.

Rev. 1.10

1

August 13, 2008

HT46R01A

Device Markings

A suffix with the number 1, 2 or 3 will be added to each of the part numbers and printed on the package. The suffix num-

ber denotes the fixed oscillation frequency of the internal RC oscillator as shown.

Part No.

Device Marking

Internal RC Oscillator Frequency

46R01A1

46R01A2

46R01A3

4MHz

8MHz

HT46R01A

12MHz

Block Diagram

The following block diagram illustrates the main functional blocks.

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Pin Assignment

1

0

9

8

7

6

P

A

3

/

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3

1

2

3

4

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Rev. 1.10

2

August 13, 2008

HT46R01A

Pin Description

Configuration

Options

Pin Name

I/O

Description

Bidirectional single line I/O. The pin can be setup as a wake-up input using

the wake-up register. Software instructions determine if the pin is a CMOS

output or a Schmitt Trigger input. A pull-high resistor can be connected using

the pull-high register. PA0 is pin-shared with the AN0 input pin. The A/D input

function is selected via software instructions. If selected as an A/D input, the

I/O function and pull-high resistor functions are disabled automatically.

PA0/AN0

I/O

¾

Bidirectional single line I/O. The pin can be setup as a wake-up input using

the wake-up register. Software instructions determine if the pin is a CMOS

output or a Schmitt Trigger input. A pull-high resistor can be connected using

the pull-high register. PA1 is pin-shared with the PFD output and the AN1 in-

put pin. The A/D input function is selected via software instructions. If selected

as an A/D input, the I/O function, PFD output and pull-high resistor functions

are disabled automatically. If the A/D function is not selected the PFD output

or I/O function selection is chosen via a bit in the CRTL0 register.

PA1/PFD/AN1

I/O

Bidirectional single line I/O. The pin can be setup as a wake-up input using

the wake-up register. Software instructions determine if the pin is a CMOS

output or a Schmitt Trigger input. A pull-high resistor can be connected us-

ing the pull-high register. PA2 is pin-shared with the TMR0 input and the

AN2 input pin. The A/D input function is selected via software instructions. If

selected as an A/D input, the I/O function, timer input and pull-high resistor

functions are disabled automatically.

PA2/TMR0/AN2 I/O

¾

Bidirectional single line I/O. The pin can be setup as a wake-up input using

the wake-up register. Software instructions determine if the pin is a CMOS

output or a Schmitt Trigger input. A pull-high resistor can be connected us-

ing the pull-high register. PA3 is pin-shared with the INT input and the AN3

input pin. The A/D input function is selected via software instructions. If se-

lected as an A/D input, the I/O function, external interrupt input and pull-high

resistor functions are disabled automatically.

PA3/INT/AN3

I/O

¾

Bidirectional single line I/O. The pin can be setup as a wake-up input using

the wake-up register. Software instructions determine if the pin is a CMOS

output or a Schmitt Trigger input. A pull-high resistor can be connected us-

ing the pull-high register. PA4 is pin-shared with the PWM output pin. The

PWM output or I/O function selection is chosen via a bit in CTRL0 register.

PA4/PWM

Bidirectional 2-line I/O. The pins can be setup as wake-up inputs using the

wake-up register. Software instructions determine if the pins are CMOS out-

puts or Schmitt Trigger inputs. Pull-high resistors can be connected using

the pull-high register. Configuration options determine if the pins are to be

used as oscillator pins or I/O pins. Configuration options also determine

which oscillator mode is selected. The four oscillator modes are:

1. Internal RC OSC: both pins configured as I/Os.

PA6/OSC1

PA5/OSC2

RC, Crystal,

RTC or I/O

I/O

2. External crystal OSC: both pins configured as OSC1/OSC2.

3. Internal RC + RTC OSC: both pins configured as OSC2, OSC1.

4. External RC OSC+PA5: PA6 configured as OSC1 pin, PA5 configured

as I/O.

If the internal RC OSC is selected, the frequency will be fixed at either

4MHz, 8MHz or 12MHz, dependent upon which device is chosen.

Active low Schmitt trigger reset input or PA7 input. A configuration option

PA7/RES

I

PA7 or RES determines which function is selected. PA7 has a wake-up function but does

not have a pull-high function.

VDD

VSS

Positive power supply

¾

Negative power supply, ground

Note: Each pin on PA except PA7 can be selected to have a pull-high resistor.

Rev. 1.10

3

August 13, 2008

HT46R01A

Absolute Maximum Ratings

Supply Voltage...........................V_SS-0.3V to V_SS+6.0V

Input Voltage..............................V_SS-0.3V to V_DD+0.3V

I_OLTotal ..............................................................150mA

Total Power Dissipation .....................................500mW

Storage Temperature............................-50°C to 125°C

Operating Temperature...........................-40°C to 85°C

I_OHTotal............................................................-100mA

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed

in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

D.C. Characteristics

Ta=25°C

Test Conditions

Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

¾

f

_SYS=4MHz

2.2

3.3

4.5

¾

5.5

2

V

¾

1

V_DD

f_SYS=8MHz

_SYS=12MHz

Operating Voltage

V

¾

f

V

¾

3V

5V

3V

5V

mA

Operating Current

I_DD1

No load, f_SYS=4MHz

(Crystal OSC, RC OSC)

2.5

2

5

¾

4

¾

Operating Current

I_DD2

I_DD3

I_DD4

No load, f_SYS=8MHz

No load, f_SYS=12MHz

No load, f_SYS=4MHz

(Crystal OSC, RC OSC)

4

8

¾

Operating Current

5V

6

12

mA

¾

(Crystal OSC, RC OSC)

3V

5V

3V

5V

1

2.5

2

5

4

8

mA

¾

Operating Current (Internal

RC+RTC OSC, Normal Mode)

Operating Current (Internal

I_DD5

I_DD6

I_DD7

No load, f_SYS=8MHz

No load, f_SYS=12MHz

No load, f_SYS=32768Hz

RC+RTC OSC, Normal Mode)

4

Operating Current (Internal

5V

6

12

mA

¾

RC+RTC OSC, Normal Mode)

3V

5V

3V

5V

3V

5V

3V

5V

20

40

¾

30

60

5

¾

mA

Operating Current (Internal

RC+RTC OSC, Slow Mode)

Standby Current

I_STB1

I_STB2

I_STB3

No load, system HALT

(WDT Enabled, RTC Off)

10

1

Standby Current

(WDT Disabled, RTC Off)

2

5

Standby Current

No load, system HALT

QOSC=1

(WDT Disabled, RTC On)

10

Input Low Voltage for PA0~PA7,

TMR0 and INT

V_IL1

0.3V_DD

V_DD

0

V

¾

Input High Voltage forPA0~PA7,

TMR0 and INT

V_IH1

0.7V_DD

V_IL2

0.4V_DD

V_DD

Input Low Voltage (RES)

Input High Voltage (RES)

Low Voltage Reset 1

Low Voltage Reset 2

Low Voltage Reset 3

0

V

¾

V_IH2

0.9V_DD

3.98

¾

V_LVR1

V_LVR2

V_LVR3

Configuration option: 4.2V

Configuration option: 3.15V

Configuration option: 2.1V

4.2

3.15

2.1

4.42

2.98

3.32

1.98

2.22

Rev. 1.10

4

August 13, 2008

HT46R01A

Test Conditions

Conditions

Symbol

Parameter

I/O Port Sink Current

I/O Port Source Current

Pull-high Resistance

Min.

Typ.

Max.

Unit

V_DD

3V

5V

3V

5V

3V

5V

¾

4

8

20

mA

kW

¾

I_OL

V

_OL=0.1V_DD

_OH=0.9V_DD

¾

10

-2

-5

20

10

0

-4

¾

I_OH

-10

60

¾

100

50

R_PH

30

kW

V_AD

E_AD

V_DD

A/D Input Voltage

V

¾

ADC Conversion Error

LSB

mA

¾

±0.5

0.5

1.5

±1

1

3V

5V

I_ADC

No load, t_AD=1ms

ADC Power Consumption

3

A.C. Characteristics

Ta=25°C

Test Conditions

Conditions

2.2V~5.5V

Symbol

Parameter

Min.

Typ.

Max.

Unit

V_DD

¾

400

4000

8000

kHz

¾

System Clock

f_SYS1

3.3V~5.5V

¾

(Crystal OSC, RC OSC)

4.5V~5.5V

12000 kHz

¾

4.5V~

5.5V

11400 12000 12600 kHz

12MHz, Ta=25°C

8MHz, Ta=25°C

4MHz, Ta=25°C

System Clock

(Internal RC OSC)

(±5%)

3.3V~

5.5V

f_SYS2

7600 8000 8400

3800 4000 4200

kHz

2.7V~

5.5V

f_SYS3

System Clock (32768 Crystal)

Timer I/P Frequency (TMR)

32768

¾

Hz

¾

3V

5V

¾

0

¾

2.2V~5.5V

4000

8000

kHz

f_TIMER

3.3V~5.5V

0

¾

4.5V~5.5V

0

12000 kHz

¾

45

32

1

90

180

130

¾

ms

t_WDTOSC

Watchdog Oscillator Period

65

¾

t_RES

t_SST

t_INT

External Reset Low Pulse Width

System Start-up Timer Period

Interrupt Pulse Width

¾

ms

t_SYS

Wake-up from Power Down

1024

¾

1

¾

ms

t_LVR

Low Voltage Width to Reset

0.25

1

2

ms

VDD Start Voltage to Ensure

Power-on Reset

V_POR

100

mV

¾

VDD Rise Time to Ensure

Power-on Reset

R_POR

0.035

V/ms

¾

t_AD

ADC Clock Period

1

¾

64

32

¾

ms

t_AD

t_ADC

t_ADS

ADC Conversion Time

ADC Sampling Time

¾

Note: t_SYS=1/f_SYS1, 1/f_SYS2or 1/f_SYS3

Rev. 1.10

5

August 13, 2008

HT46R01A

System Architecture

A key factor in the high-performance features of the

Holtek range of microcontrollers is attributed to the inter-

nal system architecture. The range of devices take ad-

vantage of the usual features found within RISC

microcontrollers providing increased speed of operation

and enhanced performance. The pipelining scheme is

implemented in such a way that instruction fetching and

instruction execution are overlapped, hence instructions

are effectively executed in one cycle, with the exception

of branch or call instructions. An 8-bit wide ALU is used

in practically all operations of the instruction set. It car-

ries out arithmetic operations, logic operations, rotation,

increment, decrement, branch decisions, etc. The inter-

nal data path is simplified by moving data through the

Accumulator and the ALU. Certain internal registers are

implemented in the Data Memory and can be directly or

indirectly addressed. The simple addressing methods of

these registers along with additional architectural fea-

tures ensure that a minimum of external components is

required to provide a functional I/O and A/D control sys-

tem with maximum reliability and flexibility.

Clocking and Pipelining

The main system clock, derived from either a Crys-

tal/Resonator or RC oscillator is subdivided into four in-

ternally generated non-overlapping clocks, T1~T4. The

Program Counter is incremented at the beginning of the

T1 clock during which time a new instruction is fetched.

The remaining T2~T4 clocks carry out the decoding and

execution functions. In this way, one T1~T4 clock cycle

forms one instruction cycle. Although the fetching and

execution of instructions takes place in consecutive in-

struction cycles, the pipelining structure of the

microcontroller ensures that instructions are effectively

executed in one instruction cycle. The exception to this

are instructions where the contents of the Program

Counter are changed, such as subroutine calls or

jumps, in which case the instruction will take one more

instruction cycle to execute.

For instructions involving branches, such as jump or call

instructions, two machine cycles are required to com-

plete instruction execution. An extra cycle is required as

the program takes one cycle to first obtain the actual

jump or call address and then another cycle to actually

execute the branch. The requirement for this extra cycle

should be taken into account by programmers in timing

sensitive applications

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Instruction Fetching

Rev. 1.10

6

August 13, 2008

HT46R01A

Program Counter

to pre-fetch. Further information on the PCL register can

be found in the Special Function Register section.

During program execution, the Program Counter is used

to keep track of the address of the next instruction to be

executed. It is automatically incremented by one each

time an instruction is executed except for instructions,

such as ²JMP² or ²CALL² that demand a jump to a

non-consecutive Program Memory address. Note that

the Program Counter width varies with the Program

Memory capacity depending upon which device is se-

lected. However, it must be noted that only the lower 8

bits, known as the Program Counter Low Register, are

directly addressable by user.

Stack

This is a special part of the memory which is used to

save the contents of the Program Counter only. The

stack has 4 levels and is neither part of the data nor part

of the program space, and is neither readable nor

writable. The activated level is indexed by the Stack

Pointer, SP, and is neither readable nor writeable. At a

subroutine call or interrupt acknowledge signal, the con-

tents of the Program Counter are pushed onto the stack.

At the end of a subroutine or an interrupt routine, sig-

naled by a return instruction, RET or RETI, the Program

Counter is restored to its previous value from the stack.

After a device reset, the Stack Pointer will point to the

top of the stack.

When executing instructions requiring jumps to

non-consecutive addresses such as a jump instruction,

a subroutine call, interrupt or reset, etc., the

microcontroller manages program control by loading the

required address into the Program Counter. For condi-

tional skip instructions, once the condition has been

met, the next instruction, which has already been

fetched during the present instruction execution, is dis-

carded and a dummy cycle takes its place while the cor-

rect instruction is obtained.

If the stack is full and an enabled interrupt takes place,

the interrupt request flag will be recorded but the ac-

knowledge signal will be inhibited. When the Stack

Pointer is decremented, by RET or RETI, the interrupt

will be serviced. This feature prevents stack overflow al-

lowing the programmer to use the structure more easily.

However, when the stack is full, a CALL subroutine in-

struction can still be executed which will result in a stack

overflow. Precautions should be taken to avoid such

cases which might cause unpredictable program

branching.

The lower byte of the Program Counter, known as the

Program Counter Low register or PCL, is available for

program control and is a readable and writeable regis-

ter. By transferring data directly into this register, a short

program jump can be executed directly, however, as

only this low byte is available for manipulation, the

jumps are limited to the present page of memory, that is

256 locations. When such program jumps are executed

it should also be noted that a dummy cycle will be in-

serted.

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The lower byte of the Program Counter is fully accessi-

ble under program control. Manipulating the PCL might

cause program branching, so an extra cycle is needed

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Program Counter Bits

Mode

b9

0

b8

0

b7

0

b6

0

b5

0

b4

0

b3

0

b2

0

b1

0

b0

0

Initial Reset

External Interrupt

Timer/Event Counter Overflow

A/D Converter Interrupt

Skip

0

1

0

1

0

1

0

Program Counter + 2

Loading PCL

PC9

#9

PC8

#8

@7

#7

@6

#6

@5

#5

@4

#4

@3

#3

@2

#2

@1

#1

@0

#0

Jump, Call Branch

Return from Subroutine

S9

S8

S7

S6

S5

S4

S3

S2

S1

S0

Program Counter

Note: PC9~PC8: Current Program Counter bits

@7~@0: PCL bits

#9~#0: Instruction code address bits

S9~S0: Stack register bits

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HT46R01A

begin execution if the external interrupt is enabled and

the stack is not full. The external interrupt active edge

transition type, whether high to low, low to high or both

is specified in the CTRL1 register.

Arithmetic and Logic Unit - ALU

The arithmetic-logic unit or ALU is a critical area of the

microcontroller that carries out arithmetic and logic op-

erations of the instruction set. Connected to the main

microcontroller data bus, the ALU receives related in-

struction codes and performs the required arithmetic or

logical operations after which the result will be placed in

the specified register. As these ALU calculation or oper-

ations may result in carry, borrow or other status

changes, the status register will be correspondingly up-

dated to reflect these changes. The ALU supports the

following functions:

·

Location 008H

This internal vector is used by the Timer/Event Coun-

ter. If a counter overflow occurs, the program will jump

to this location and begin execution if the timer/event

counter interrupt is enabled and the stack is not full.

Location 00CH

This internal vector is used by the A/D converter.

When an A/D conversion cycle is complete, the pro-

gram will jump to this location and begin execution if

the A/D interrupt is enabled and the stack is not full.

·

Arithmetic operations: ADD, ADDM, ADC, ADCM,

SUB, SUBM, SBC, SBCM, DAA

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Logic operations: AND, OR, XOR, ANDM, ORM,

XORM, CPL, CPLA

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Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,

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Increment and Decrement INCA, INC, DECA, DEC

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Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,

SIZA, SDZA, CALL, RET, RETI

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Program Memory

The Program Memory is the location where the user

code or program is stored. These devices are supplied

with One-Time Programmable, OTP, memory where us-

ers can program their application code into the device.

By using the appropriate programming tools, OTP de-

vices offer users the flexibility to freely develop their ap-

plications which may be useful during debug or for

products requiring frequent upgrades or program

changes. OTP devices are also applicable for use in ap-

plications that require low or medium volume production

runs.

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Program Memory Structure

Look-up Table

Any location within the Program Memory can be defined

as a look-up table where programmers can store fixed

data. To use the look-up table, the table pointer must

first be setup by placing the lower order address of the

look up data to be retrieved in the table pointer register,

TBLP. This register defines the lower 8-bit address of

the look-up table.

Structure

The Program Memory has a capacity of 1K by 14. The

Program Memory is addressed by the Program Counter

and also contains data, table information and interrupt

entries. Table data, which can be setup in any location

within the Program Memory, is addressed by separate

table pointer registers.

After setting up the table pointer, the table data can be

retrieved from the current Program Memory page or last

Program Memory page using the ²TABRDC[m]² or

²TABRDL [m]² instructions, respectively. When these in-

structions are executed, the lower order table byte from

the Program Memory will be transferred to the user de-

fined Data Memory register [m] as specified in the in-

struction. The higher order table data byte from the

Program Memory will be transferred to the TBLH special

register. Any unused bits in this transferred higher order

byte will be read as ²0².

Special Vectors

Within the Program Memory, certain locations are re-

served for special usage such as reset and interrupts.

·

Location 000H

This vector is reserved for use by the device reset for

program initialisation. After a device reset is initiated, the

program will jump to this location and begin execution.

·

Location 004H

This vector is used by the external interrupt. If the ex-

ternal interrupt pin on the device receives an edge

transition, the program will jump to this location and

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HT46R01A

Table Location Bits

Instruction

b9

PC9

1

b8

PC8

1

b7

@7

b6

@6

b5

@5

b4

@4

b3

@3

b2

@2

b1

@1

b0

@0

TABRDC [m]

TABRDL [m]

Table Location

Note: PC9~PC8: Current Program Counter bits

@7~@0: Table Pointer TBLP bits

The following diagram illustrates the addressing/data

flow of the look-up table:

which is stored there using the ORG statement. The

value at this ORG statement is ²300H² which refers to

the start address of the last page within the 1K Program

Memory. The table pointer is setup here to have an ini-

tial value of ²06H². This will ensure that the first data

read from the data table will be at the Program Memory

address ²306H² or 6 locations after the start of the last

page. Note that the value for the table pointer is refer-

enced to the first address of the present page if the

²TABRDC [m]² instruction is being used. The high byte

of the table data which in this case is equal to zero will

be transferred to the TBLH register automatically when

the ²TABRDL [m]² instruction is executed.

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Table Program Example

The following example shows how the table pointer and

table data is defined and retrieved from the device. This

example uses raw table data located in the last page

tempreg1

tempreg2

db

:

?

; temporary register #1

; temporary register #2

:

mov

a,06h

; initialise table pointer - note that this address

; is referenced

tblp,a

:

; to the last page or present page

tabrdl

tempreg1

; transfers value in table referenced by table pointer

; to tempregl

; data at prog. memory address ²306H² transferred to

; tempreg1 and TBLH

dec

tblp

; reduce value of table pointer by one

tabrdl

tempreg2

; transfers value in table referenced by table pointer

; to tempreg2

; data at prog.memory address ²305H² transferred to

; tempreg2 and TBLH

; in this example the data ²1AH² is transferred to

; tempreg1 and data ²0FH² to register tempreg2

; the value ²00H² will be transferred to the high byte

; register TBLH

:

org

dc

300h

; sets initial address of last page

00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh

:

Rev. 1.10

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HT46R01A

General Purpose Data Memory

Because the TBLH register is a read-only register and

cannot be restored, care should be taken to ensure its

protection if both the main routine and Interrupt Service

Routine use the table read instructions. If using the table

read instructions, the Interrupt Service Routines may

change the value of TBLH and subsequently cause er-

rors if used again by the main routine. As a rule it is rec-

ommended that simultaneous use of the table read

instructions should be avoided. However, in situations

where simultaneous use cannot be avoided, the inter-

rupts should be disabled prior to the execution of any

main routine table-read instructions. Note that all table

related instructions require two instruction cycles to

complete their operation.

All microcontroller programs require an area of

read/write memory where temporary data can be stored

and retrieved for use later. It is this area of RAM memory

that is known as General Purpose Data Memory. This

area of Data Memory is fully accessible by the user pro-

gram for both read and write operations. By using the

²SET [m].i² and ²CLR [m].i² instructions individual bits

can be set or reset under program control giving the

user a large range of flexibility for bit manipulation in the

Data Memory.

Special Purpose Data Memory

This area of Data Memory is where registers, necessary

for the correct operation of the microcontroller, are

stored. Most of the registers are both readable and

writable but some are protected and are readable only,

the details of which are located under the relevant Spe-

cial Function Register section. Note that for locations

that are unused, any read instruction to these addresses

will return the value ²00H².

Data Memory

The Data Memory is a volatile area of 8-bit wide RAM

internal memory and is the location where temporary in-

formation is stored. Divided into two sections, the first of

these is an area of RAM where special function registers

are located. These registers have fixed locations and

are necessary for correct operation of the device. Many

of these registers can be read from and written to di-

rectly under program control, however, some remain

protected from user manipulation. The second area of

Data Memory is reserved for general purpose use. All

locations within this area are read and write accessible

under program control.

Special Function Registers

To ensure successful operation of the microcontroller,

certain internal registers are implemented in the Data

Memory area. These registers ensure correct operation

of internal functions such as timers, interrupts, etc., as

well as external functions such as I/O data control and

A/D converter operation. The location of these registers

within the Data Memory begins at the address 00H. Any

unused Data Memory locations between these special

function registers and the point where the General Pur-

pose Memory begins is reserved and attempting to read

data from these locations will return a value of 00H.

Structure

The two sections of Data Memory, the Special Purpose

and General Purpose Data Memory are located at con-

secutive locations. All are implemented in RAM and are

8 bits wide but the length of each memory section is dic-

tated by the type of microcontroller chosen. The start

address of the Data Memory for all devices is the ad-

dress ²00H². Registers which are common to all

microcontrollers, such as ACC, PCL, etc., have the

same Data Memory address.

Indirect Addressing Registers - IAR0, IAR1

The Indirect Addressing Registers, IAR0 and IAR1, al-

though having their locations in normal RAM register

space, do not actually physically exist as normal regis-

ters. The method of indirect addressing for RAM data

manipulation uses these Indirect Addressing Registers

and Memory Pointers, in contrast to direct memory ad-

dressing, where the actual memory address is speci-

fied. Actions on the IAR0 and IAR1 registers will result in

no actual read or write operation to these registers but

rather to the memory location specified by their corre-

sponding Memory Pointer, MP0 or MP1. Acting as a

pair, IAR0 with MP0 and IAR1 with MP1 can together ac-

cess data from the Data Memory. As the Indirect Ad-

dressing Registers are not physically implemented,

reading the Indirect Addressing Registers indirectly will

return a result of ²00H² and writing to the registers indi-

rectly will result in no operation.

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Data Memory Structure

Note: Most of the Data Memory bits can be directly

manipulated using the ²SET [m].i² and ²CLR

[m].i² with the exception of a few dedicated bits.

The Data Memory can also be accessed

through the memory pointer registers.

Rev. 1.10

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HT46R01A

Memory Pointers - MP0, MP1

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Two Memory Pointers, known as MP0 and MP1 are pro-

vided. These Memory Pointers are physically imple-

mented in the Data Memory and can be manipulated in

the same way as normal registers providing a conve-

nient way with which to address and track data. When

any operation to the relevant Indirect Addressing Regis-

ters is carried out, the actual address that the

microcontroller is directed to, is the address specified by

the related Memory Pointer, bit 7 of the Memory

Pointers is not required to address the full memory

space. It must be noted that when bit 7 of the Memory

Pointers for these devices is read, a value of ²1² will be

returned. The following example shows how to clear a

section of four Data Memory locations already defined as

locations adres1 to adres4.

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Special Purpose Data Memory

data .section ¢data¢

adres1

adres2

adres3

adres4

block

db ?

code .section at 0 ¢code¢

org 00h

start:

mov a,04h

mov block,a

mov a,offset adres1; Accumulator loaded with first RAM address

; setup size of block

mov mp0,a

; setup memory pointer with first RAM address

loop:

clr IAR0

inc mp0

sdz block

jmp loop

; clear the data at address defined by MP0

; increment memory pointer

; check if last memory location has been cleared

continue:

The important point to note here is that in the example shown above, no reference is made to specific Data Memory ad-

dresses.

Rev. 1.10

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August 13, 2008

HT46R01A

Accumulator - ACC

Status Register - STATUS

The Accumulator is central to the operation of any

microcontroller and is closely related with operations

carried out by the ALU. The Accumulator is the place

where all intermediate results from the ALU are stored.

Without the Accumulator it would be necessary to write

the result of each calculation or logical operation such

as addition, subtraction, shift, etc., to the Data Memory

resulting in higher programming and timing overheads.

Data transfer operations usually involve the temporary

storage function of the Accumulator; for example, when

transferring data between one user defined register and

another, it is necessary to do this by passing the data

through the Accumulator as no direct transfer between

two registers is permitted.

This 8-bit register contains the zero flag (Z), carry flag

(C), auxiliary carry flag (AC), overflow flag (OV), power

down flag (PDF), and watchdog time-out flag (TO).

These arithmetic/logical operation and system manage-

ment flags are used to record the status and operation of

the microcontroller.

With the exception of the TO and PDF flags, bits in the

status register can be altered by instructions like most

other registers. Any data written into the status register

will not change the TO or PDF flag. In addition, opera-

tions related to the status register may give different re-

sults due to the different instruction operations. The TO

flag can be affected only by a system power-up, a WDT

time-out or by executing the ²CLR WDT² or ²HALT² in-

struction. The PDF flag is affected only by executing the

²HALT² or ²CLR WDT² instruction or during a system

power-up.

Program Counter Low Register - PCL

To provide additional program control functions, the low

byte of the Program Counter is made accessible to pro-

grammers by locating it within the Special Purpose area

of the Data Memory. By manipulating this register, direct

jumps to other program locations are easily imple-

mented. Loading a value directly into this PCL register

will cause a jump to the specified Program Memory lo-

cation, however, as the register is only 8-bit wide, only

jumps within the current Program Memory page are per-

mitted. When such operations are used, note that a

dummy cycle will be inserted.

The Z, OV, AC and C flags generally reflect the status of

the latest operations.

·

C is set if an operation results in a carry during an ad-

dition operation or if a borrow does not take place dur-

ing a subtraction operation; otherwise C is cleared. C

is also affected by a rotate through carry instruction.

·

AC is set if an operation results in a carry out of the

low nibbles in addition, or no borrow from the high nib-

ble into the low nibble in subtraction; otherwise AC is

cleared.

Look-up Table Registers - TBLP, TBLH

·

Z is set if the result of an arithmetic or logical operation

These two special function registers are used to control

operation of the look-up table which is stored in the Pro-

gram Memory. TBLP is the table pointer and indicates

the location where the table data is located. Its value

must be setup before any table read commands are ex-

ecuted. Its value can be changed, for example using the

²INC² or ²DEC² instructions, allowing for easy table data

pointing and reading. TBLH is the location where the

high order byte of the table data is stored after a table

read data instruction has been executed. Note that the

lower order table data byte is transferred to a user de-

fined location.

is zero; otherwise Z is cleared.

OV is set if an operation results in a carry into the high-

est-order bit but not a carry out of the highest-order bit,

or vice versa; otherwise OV is cleared.

·

PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by executing the

²HALT² instruction.

TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is set by a

WDT time-out.

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Rev. 1.10

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August 13, 2008

HT46R01A

In addition, on entering an interrupt sequence or execut-

ing a subroutine call, the status register will not be

pushed onto the stack automatically. If the contents of

the status registers are important and if the interrupt rou-

tine can change the status register, precautions must be

taken to correctly save it.

Pulse Width Modulation Register - PWM

Each device contains a Pulse Width Modulator which

has a corresponding control register, known as PWM.

The 8-bit contents of this register defines the duty cycle

value for the modulation cycle of the Pulse Width Modu-

lator.

Interrupt Control Registers - INTC0

A/D Converter Register - ADR, ADCR, ACSR

The 8-bit register, known as INTC0, control the opera-

tion of both external, and internal timer and A/D inter-

rupts. By setting various bits within this register using

standard bit manipulation instructions, the enable/dis-

able function of each interrupt can be independently

controlled. A master interrupt bit within this register, the

EMI bit, acts like a global enable/disable and is used to

set all of the interrupt enable bits on or off. This bit is

cleared when an interrupt routine is entered to disable

further interrupt and is set by executing the ²RETI² in-

struction.

The device contains a 4-channel 8-bit A/D converter,

which has a single data register, known as ADR. This is

the register where the digital value is placed after the

completion of an analog to digital conversion cycle. The

channel selection and configuration of the A/D converter

is setup via the control register ADCR while the A/D

clock frequency is defined by the clock source register,

ACSR.

System Control Register - CTRL0

This register is used to provide control over certain inter-

nal functions including certain system clock options, the

PFD clock source and on/off control, the PWM mode

and on/off control and an RTC Oscillator quick start up

function.

Timer/Event Counter Registers

Depending upon which device is selected, all devices

contain one or two integrated 8-bit Timer/Event Coun-

ters. For the device, which have a single 8-bit Timer/

Event Counter, an associated register known as TMR0

is the location where the timer¢s 8-bit value is located.

An associated control register, known as TMR0C, con-

tains the setup information for this timer.

System Control Register - CTRL1

This register is used to provide control over certain inter-

nal functions including the External Interrupt edge trig-

ger type and the Watchdog Timer control function.

Input/Output Ports and Control Registers

Wake-up Function Register - PAWK

Within the area of Special Function Registers, the port

PA data I/O register and its associated control register

PAC play a prominent role. These registers are mapped

to specific addresses within the Data Memory as shown

in the Data Memory table. The PA data I/O register, is

used to transfer the appropriate output or input data on

the PA port. The PAC control register specifies which

pins of PA are set as inputs and which are set as out-

puts. To setup a pin as an input, the corresponding bit of

the control register must be set high, for an output it

must be set low. During program initialisation, it is impor-

tant to first setup the control registers to specify which

pins are outputs and which are inputs before reading

data from or writing data to the I/O ports. One flexible

feature of these registers is the ability to directly pro-

gram single bits using the ²SET [m].i² and ²CLR [m].i²

instructions. The ability to change I/O pins from output to

input and vice versa by manipulating specific bits of the

I/O control registers during normal program operation is

a useful feature of these devices.

When the microcontroller enters the Power Down Mode,

various methods exist to wake the device up and con-

tinue with normal operation. One method is to allow a

low going edge on the I/O pins to have a wake-up func-

tion. This register is used to select which I/O pins are

used to have this wake-up function.

Pull-high Register - PAPU

The I/O pins, if configured as inputs, can have internal

pull-high resistors connected, which eliminates the need

for external pull-high resistors. This register selects which

I/O pins are connected to internal pull-high resistors.

Rev. 1.10

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HT46R01A

b

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Input/Output Ports

Holtek microcontrollers offer considerable flexibility on

their I/O ports. There are seven I/O pins whose input or

output designation is under user program control and an

additional input pin. Additionally, as there are pull-high

resistor and wake-up software configurations for each

pin, the user is provided with an I/O structure to meet the

needs of a wide range of application possibilities.

Pull-high Resistors

Many product applications require pull-high resistors for

their switch inputs usually requiring the use of an exter-

nal resistor. To eliminate the need for these external re-

sistors, I/O pins PA0~PA6, when configured as an input

have the capability of being connected to an internal

pull-high resistor. These pull-high resistors are

selectable via a register known as PAPU, located in the

Data Memory. The pull-high resistors are implemented

using weak PMOS transistors.

Each device has a single I/O port known as Port A,

which has a corresponding data register known as PA.

This register is mapped to the Data Memory with an ad-

dresses as shown in the Special Purpose Data Memory

table. Seven of these I/O lines can be used for input and

output operations and one line as an input only. For in-

put operation, these ports are non-latching, which

means the inputs must be ready at the T2 rising edge of

instruction ²MOV A,[m]², where m denotes the port ad-

dress. For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

Rev. 1.10

14

August 13, 2008

HT46R01A

Port A Wake-up

the pin is setup as an external interrupt input the I/O

function still remains.

If the HALT instruction is executed, the device will enter

the Power Down Mode, where the system clock will stop

resulting in power being conserved, a feature that is im-

portant for battery and other low-power applications.

Various methods exist to wake-up the microcontroller,

one of which is to change the logic condition on one of

the PA0~PA7 pins from high to low. After a HALT instruc-

tion forces the microcontroller into entering the Power

Down Mode, the processor will remain idle or in a

low-power state until the logic condition of the selected

wake-up pin on Port A changes from high to low. This

function is especially suitable for applications that can

be woken up via external switches. Note that pins PA0 to

PA7 can be selected individually to have this wake-up

feature using an internal register known as PAWK, lo-

cated in the Data Memory.

·

External Timer/Event Counter Input

The device contains a single Timer/Event Counter.

The Timer/Event Counter has an external input pin,

known as TMR0 which is pin-shared with the I/O pin

PA2. For the shared pin to be used as a Timer/Event

Counter input, the Timer/Event Counter must be con-

figured to be in the Event Counter or Pulse Width

Measurement Mode. This is achieved by setting the

appropriate bits in the Timer/Event Counter Control

Register. The pin must also be setup as an input by

setting the appropriate bit in the Port Control Register.

Pull-high resistor options can also be selected via the

port pull-high resistor register. Note that even if the pin

is setup as an external timer input the I/O function still

remains.

·

PFD Output

The device contains a PFD function whose single out-

put is pin-shared with PA1. The PFD output function of

this pin along with the timer source is chosen via bits

in the CTRL0 register. Note that the corresponding bit

of the port control register, PAC.1, must setup the pin

as an output to enable the PFD output. If the PAC port

control register has setup the pin as an input, then the

pin will function as a normal logic input with the usual

pull-high option, even if the PFD has been selected.

I/O Port Control Registers

Port A has its own control register, known as PAC, which

controls the input/output configuration. With this control

register, each PA0~PA6 I/O pin with or without pull-high

resistors can be reconfigured dynamically under soft-

ware control. Pins PA0 to PA6 port are directly mapped

to a bit in its associated port control register. For the I/O

pin to function as an input, the corresponding bit of the

control register must be written as a ²1². This will then

allow the logic state of the input pin to be directly read by

instructions. When the corresponding bit of the control

register is written as a ²0², the I/O pin will be setup as a

CMOS output. If the pin is currently setup as an output,

instructions can still be used to read the output register.

However, it should be noted that the program will in fact

only read the status of the output data latch and not the

actual logic status of the output pin.

·

PWM Output

The device contains a single PWM output pin shared

with pins PA4. The PWM output function of this pin

along with the mode type is chosen via bits in the

CTRL0 register. Note that the corresponding bit or bits

of the port control register, PAC.4, must setup the pin

as an output to enable the PWM output. If the PAC

port control register has setup the pin as an input, then

the pin will function as a normal logic input with the

usual pull-high resistor option, even if the PWM has

been selected.

Pin-shared Functions

·

A/D Inputs

The device has four A/D converter inputs. All of these

analog inputs are pin-shared with PA0 to PA3. If these

pins are to be used as A/D inputs and not as normal

I/O pins then the corresponding bits in the A/D Con-

verter Control Register, ADCR, must be properly set.

There are no configuration options associated with

the A/D function. If used as I/O pins, then full pull-high

resistor selections remain, however if used as A/D in-

puts then any pull-high resistor selections associated

with these pins will be automatically disconnected.

The flexibility of the microcontroller range is greatly en-

hanced by the use of pins that have more than one func-

tion. Limited numbers of pins can force serious design

constraints on designers but by supplying pins with

multi-functions, many of these difficulties can be over-

come. For some pins, the chosen function of the

multi-function I/O pins is set by configuration options

while for others the function is set by application pro-

gram control.

·

External Interrupt Input

I/O Pin Structures

The external interrupt pin, INT, is pin-shared with the

I/O pin PA3. To use the pin as an external interrupt in-

put the correct bits in the INTCO register must be pro-

grammed. The pin must also be setup as an input by

setting the appropriate bit in the Port Control Register.

A pull-high resistor can also be selected via the appro-

priate port pull-high resistor register. Note that even if

The diagrams illustrate the I/O pin internal structures. As

the exact logical construction of the I/O pin may differ

from these drawings, they are supplied as a guide only

to assist with the functional understanding of the I/O

pins.

Rev. 1.10

15

August 13, 2008

HT46R01A

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Rev. 1.10

16

August 13, 2008

HT46R01A

Programming Considerations

count-up timer of 8-bit capacity. As the timer has three

different operating modes, it can be configured to oper-

ate as a general timer, an external event counter or as a

pulse width measurement device. The provision of an

internal prescaler to the clock circuitry gives added

range to the timer.

Within the user program, one of the first things to con-

sider is port initialisation. After a reset, the PA data regis-

ter and PAC port control register will be set high. This

means that all I/O pins will default to an input state, the

level of which depends on the other connected circuitry

and whether pull-high options have been selected. If the

PAC port control register, is then programmed to setup

some pins as outputs, these output pins will have an ini-

tial high output value unless the associated PA port data

register is first programmed. Selecting which pins are in-

puts and which are outputs can be achieved byte-wide

by loading the correct value into the port control register

or by programming individual bits in the port control reg-

ister using the ²SET [m].i² and ²CLR [m].i² instructions.

Note that when using these bit control instructions, a

read-modify-write operation takes place. The

microcontroller must first read in the data on the entire

port, modify it to the required new bit values and then re-

write this data back to the output ports.

There are two types of registers related to the

Timer/Event Counter. The first is the register that con-

tains the actual value of the Timer/Event Counter and

into which an initial value can be preloaded. Reading

from this register retrieves the contents of the

Timer/Event Counter. The second type of associated

register is the Timer Control Register which defines the

timer options and determines how the timer is to be

used. The device can have the timer clock configured to

come from the internal clock source. In addition, the

timer clock source can also be configured to come from

an external timer pin.

An external clock source is used when the timer is in the

event counting mode, the clock source being provided

on the external timer pin, known as TMR0. These exter-

nal timer pins are pin-shared with other I/O pins. De-

pending upon the condition of the T0E bit in the

corresponding Timer Control Register, each high to low,

or low to high transition on the external timer input pin

will increment the counter by one.

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Read/Write Timing

Configuring the Timer/Event Counter Input Clock

Source

Pins PA0 to PA7 each have a wake-up functions, se-

lected via the PAWK register. When the device is in the

Power Down Mode, various methods are available to

wake the device up. One of these is a high to low transi-

tion of any of the these pins. Single or multiple pins on

Port A can be setup to have this function.

The internal timer¢s clock can originate from various

sources, depending upon which device and which timer

is chosen. The system clock input timer source is used

when the timer is in the timer mode or in the pulse width

measurement mode. This system clock timer source is

first divided by a prescaler, the division ratio of which is

conditioned by the Timer Control Register bits

T0PSC0~T0PSC2.

Timer/Event Counter

The provision of timers form an important part of any

microcontroller, giving the designer a means of carrying

out time related functions. This device contains one

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Rev. 1.10

17

August 13, 2008

HT46R01A

Timer Control Registers - TMR0C

The flexible features of the Holtek microcontroller

Timer/Event Counters enable them to operate in three

different modes, the options of which are determined by

the contents of their respective control register.

An external clock source is used when the timer is in the

event counting mode, the clock source being provided

on an external timer pin TMR0, depending upon which

device and which timer is used. Depending upon the

condition of the T0E bit, each high to low, or low to high

transition on the external timer pin will increment the

counter by one.

The Timer Control Register is known as TMR0C. It is the

Timer Control Register together with its corresponding

timer registers that control the full operation of the

Timer/Event Counters. Before the timers can be used, it

is essential that the appropriate Timer Control Register

is fully programmed with the right data to ensure its cor-

rect operation, a process that is normally carried out

during program initialisation.

Timer Registers - TMR0

The timer registers are special function registers located

in the Special Purpose Data Memory and is the place

where the actual timer value is stored. This register is

known as TMR0. The value in the timer registers in-

creases by one each time an internal clock pulse is re-

ceived or an external transition occurs on the external

timer pin. The timer will count from the initial value loaded

by the preload register to the full count of FFH at which

point the timer overflows and an internal interrupt signal is

generated. The timer value will then be reset with the ini-

tial preload register value and continue counting.

To choose which of the three modes the timer is to oper-

ate in, either in the timer mode, the event counting mode

or the pulse width measurement mode, bits 7 and 6 of

the Timer Control Register, which are known as the bit

pair T0M1/T0M0, must be set to the required logic lev-

els. The timer-on bit, which is bit 4 of the Timer Control

Register and known as T0ON, provides the basic on/off

control of the respective timer. Setting the bit high allows

the counter to run, clearing the bit stops the counter. Bits

0~2 of the Timer Control Register determine the division

ratio of the input clock prescaler. The prescaler bit set-

tings have no effect if an external clock source is used. If

the timer is in the event count or pulse width measure-

ment mode, the active transition edge level type is se-

lected by the logic level of bit 3 of the Timer Control

Register which is known as T0E.

Note that to achieve a maximum full range count of FFH,

the preload register must first be cleared to all zeros. It

should be noted that after power-on, the preload regis-

ters will be in an unknown condition. Note that if the

Timer/Event Counters are in an OFF condition and data

is written to their preload registers, this data will be im-

mediately written into the actual counter. However, if the

counter is enabled and counting, any new data written

into the preload data registers during this period will re-

main in the preload registers and will only be written into

the actual counter the next time an overflow occurs.

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Rev. 1.10

18

August 13, 2008

HT46R01A

Configuring the Timer Mode

will increment each time the external timer pin receives

a high to low transition. As in the case of the other two

modes, when the counter is full, the timer will overflow

and generate an internal interrupt signal. The counter

will then preload the value already loaded into the

preload register. As the external timer pins are

pin-shared with other I/O pins, to ensure that the pin is

configured to operate as an event counter input pin, two

things have to happen. The first is to ensure that the

T0M1/T0M0 bits place the Timer/Event Counter in the

event counting mode, the second is to ensure that the

port control register configures the pin as an input. It

should be noted that a timer overflow is one of the inter-

rupt and wake-up sources. Note that the timer interrupts

can be disabled by ensuring that the ET0I bits in the

INTC0 register are reset to zero.

In this mode, the timer can be utilized to measure fixed

time intervals, providing an internal interrupt signal each

time the counter overflows. To operate in this mode, the

bit pair, T0M1/T0M0, must be set to 1 and 0 respectively.

In this mode the internal clock is used as the timer clock.

The timer input clock source is either f_SYSor the RTC os-

cillator. However, this timer clock source is further di-

vided by a prescaler, the value of which is determined by

the bits T0PSC2~T0PSC0 in the Timer Control Regis-

ter. The timer-on bit, T0ON must be set high to enable

the timer to run. Each time an internal clock high to low

transition occurs, the timer increments by one; when the

timer is full and overflows, an interrupt signal is gener-

ated and the timer will preload the value already loaded

into the preload register and continue counting. A timer

overflow condition and corresponding internal interrupt

is one of the wake-up sources, however, the internal in-

terrupts can be disabled by ensuring that the ET0I bits of

the INTC0 register are reset to zero.

Configuring the Pulse Width Measurement Mode

In this mode, the width of external pulses applied to the

external timer pin can be measured. In the Pulse Width

Measurement Mode the timer clock source is supplied

by the internal clock. For the timer to operate in this

mode, the bit pair, T0M1/T0M0 must both be set high. If

the T0E bit is low, once a high to low transition has been

received on the external timer pin, the timer will start

counting until the external timer pin returns to its original

high level. At this point the T0ON bit will be automatically

reset to zero and the timer will stop counting. If the T0E

bit is high, the timer will begin counting once a low to

high transition has been received on the external timer

pin and stop counting when the external timer pin re-

Configuring the Event Counter Mode

In this mode, a number of externally changing logic

events, occurring on the external timer pin, can be re-

corded by the internal timer. For the timer to operate in

the event counting mode, the bit pair, T0M1/T0M0 must

be set to 0 and 1 respectively. The timer-on bit T0ON or

T1ON, depending upon which timer is used, must be set

high to enable the timer to count. If T0E is low, the coun-

ter will increment each time the external timer pin re-

ceives a low to high transition. If T0E is high, the counter

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Pulse Width Measure Mode Timing Chart

Rev. 1.10

19

August 13, 2008

HT46R01A

turns to its original low level. As before, the T0ON bit will

be automatically reset to zero and the timer will stop

counting. It is important to note that in the Pulse Width

Measurement Mode, the T0ON bit is automatically reset

to zero when the external control signal on the external

timer pin returns to its original level, whereas in the other

two modes the T0ON bit can only be reset to zero under

program control. The residual value in the timer, which

can now be read by the program, therefore represents

the length of the pulse received on the external timer

pin. As the T0ON bit has now been reset, any further

transitions on the external timer pin, will be ignored. Not

until the T0ON bit is again set high by the program can

the timer begin further pulse width measurements. In

this way, single shot pulse measurements can be easily

made. It should be noted that in this mode the counter is

controlled by logical transitions on the external timer pin

and not by the logic level. As in the case of the other two

modes, when the counter is full, the timer will overflow

and generate an internal interrupt signal. The counter

will also be reset to the value already loaded into the

preload register. If the external timer pin is pin-shared

with other I/O pins, to ensure that the pin is configured to

operate as a pulse width measuring input pin, two things

have to happen. The first is to ensure that the

T0M1/T0M0 bits place the Timer/Event Counter in the

pulse width measuring mode, the second is to ensure

that the port control register configures the pin as an in-

put. It should be noted that a timer overflow and corre-

sponding timer interrupt is one of the wake-up sources.

Note that the timer interrupts can be disabled by ensur-

ing that the ET0I bits in the INTC0 register are reset to

zero.

counter, driven by the system clock and if applicable, di-

vided by the prescaler value, will begin to count-up from

this preloaded register value until full, at which point an

overflow signal will be generated, causing the PFD out-

put to change state. The counter will then be automati-

cally reloaded with the preload register value and once

again continue counting-up.

For the PFD output to function, it is essential that the

corresponding bit of the Port A control register PAC bit 1

is setup as an output. If setup as an input the PFD output

will not function, however, the pin can still be used as a

normal input pin. The PFD output will only be activated if

bit PA1 is set to ²1². This output data bit is used as the

on/off control bit for the PFD output. Note that the PFD

output will be low if the PA1 output data bit is cleared to

²0².

Using this method of frequency generation, and if a

crystal oscillator is used for the system clock, very pre-

cise values of frequency can be generated.

Prescaler

Bits T0PSC0~T0PSC2 of the TMR0C register can be

used to define a division ratio for the internal clock

source of the Timer/Event Counter enabling longer time

out periods to be setup.

I/O Interfacing

The Timer/Event Counter, when configured to run in the

event counter or pulse width measurement mode, re-

quires the use of the external timer pin for its operation.

As this pin is a shared pin it must be configured correctly

to ensure that it is setup for use as a Timer/Event Coun-

ter input pin. This is achieved by ensuring that the mode

select bits in the Timer/Event Counter control register,

select either the event counter or pulse width measure-

ment mode. Additionally the corresponding PAC Port

Control Register bit must be set high to ensure that the

pin is setup as an input. Any pull-high resistor connected

to this pin will remain valid even if the pin is used as a

Timer/Event Counter input.

Programmable Frequency Divider - PFD

The PFD output is pin-shared with the I/O pin PA1. The

PFD on/off function and its timer source are selected via

bits in the CTRL0 register, however, if not selected, the

pin can operate as a normal I/O pin. The timer overflow

signal is the clock source for the PFD circuit. The output

frequency is controlled by loading the required values

into the timer register and if available the timer prescaler

registers to give the required frequency. The timer/event

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PFD Output Control

Rev. 1.10

20

August 13, 2008

HT46R01A

Programming Considerations

the timer registers before the timer is switched on; this is

because after power-on the initial values of the timer reg-

isters are unknown. After the timer has been initialised

the timer can be turned on and off by controlling the en-

able bit in the timer control register.

When configured to run in the timer mode, the internal

system clock is used as the timer clock source and is

therefore synchronised with the overall operation of the

microcontroller. In this mode when the appropriate timer

register is full, the microcontroller will generate an internal

interrupt signal directing the program flow to the respec-

tive internal interrupt vector. For the pulse width mea-

surement mode, the internal system clock is also used as

the timer clock source but the timer will only run when the

correct logic condition appears on the external timer input

pin. As this is an external event and not synchronised

with the internal timer clock, the microcontroller will only

see this external event when the next timer clock pulse

arrives. As a result, there may be small differences in

measured values requiring programmers to take this into

account during programming. The same applies if the

timer is configured to be in the event counting mode,

which again is an external event and not synchronised

with the internal system or timer clock.

When the Timer/Event Counter overflows, its corre-

sponding interrupt request flag in the interrupt control

register will be set. If the timer interrupt is enabled this

will in turn generate an interrupt signal. However irre-

spective of whether the interrupts are enabled or not, a

Timer/Event counter overflow will also generate a

wake-up signal if the device is in a Power-down condi-

tion. This situation may occur if the Timer/Event Counter

is in the Event Counting Mode and if the external signal

continues to change state. In such a case, the

Timer/Event Counter will continue to count these exter-

nal events and if an overflow occurs the device will be

woken up from its Power-down condition. To prevent

such a wake-up from occurring, the timer interrupt re-

quest flag should first be set high before issuing the

²HALT² instruction to enter the Power Down Mode.

When the Timer/Event Counter is read, or if data is writ-

ten to the preload register, the clock is inhibited to avoid

errors, however as this may result in a counting error, this

should be taken into account by the programmer. Care

must be taken to ensure that the timers are properly in-

itialised before using them for the first time. The associ-

ated timer enable bits in the interrupt control register must

be properly set otherwise the internal interrupt associated

with the timer will remain inactive. The edge select, timer

mode and clock source control bits in timer control regis-

ter must also be correctly set to ensure the timer is prop-

erly configured for the required application. It is also

important to ensure that an initial value is first loaded into

Timer Program Example

The program shows how the Timer/Event Counter regis-

ters are setup along with how the interrupts are enabled

and managed. Note how the Timer/Event Counter is

turned on, by setting bit 4 of the Timer Control Register.

The Timer/Event Counter can be turned off in a similar

way by clearing the same bit. This example program

sets the Timer/Event Counters to be in the timer mode,

which uses the internal system clock as their clock

source.

:

org 04h

:

; external interrupt vector

org 08h

jmp tmr0int

; Timer Counter 0 interrupt vector

; jump here when Timer 0 overflows

:

org 20h

:

; main program

:

;internal Timer 0 interrupt routine

tmr0int:

:

; Timer 0 main program placed here

:

begin:

;setup Timer 0 registers

mov a,09bh

tmr0,a

; setup Timer 0 preload value

mov a,081h ; setup Timer 0 control register

mov tmr0c,a ; timer mode and prescaler set to /2

;setup interrupt register

mov a,00dh

; interrupts

intc0,a

:

; enable master interrupt and both timer

:

set tmr0c.4

:

; start Timer 0

:

Rev. 1.10

21

August 13, 2008

HT46R01A

Pulse Width Modulator

Each microcontroller is provided with a single Pulse

Width Modulation, PWM, output. Useful for such appli-

cations such as motor speed control, the PWM function

provides outputs with a fixed frequency but with a duty

cycle that can be varied by setting particular values into

the corresponding PWM register.

frequency for the 6+2 mode of operation will be f_SYS/64.

PWM

PWM Cycle PWM Cycle

Modulation

Frequency

Duty

f_SYS/64 for (6+2) bits mode

f

_SYS/256

[PWM]/256

f

_SYS/128for (7+1) bits mode

Asingle register, known as PWM and located in the Data

Memory is assigned to the Pulse Width Modulator. It is

here that the 8-bit value, which represents the overall

duty cycle of one modulation cycle of the output wave-

form, should be placed. To increase the PWM modula-

tion frequency, each modulation cycle is subdivided into

two or four individual modulation subsections, known as

the 7+1 mode or 6+2 mode respectively. The required

mode and the on/off control for the PWM is selected us-

ing the CTRL0 register. Note that when using the PWM,

it is only necessary to write the required value into the

PWM register and select the required mode setup and

on/off control using the CTRL0 register, the subdivision

of the waveform into its sub-modulation cycles is imple-

mented automatically within the microcontroller hard-

ware. For all devices, the PWM clock source is the

6+2 PWM Mode

Each full PWM cycle, as it is controlled by an 8-bit PWM

register, has 256 clock periods. However, in the 6+2

PWM mode, each PWM cycle is subdivided into four in-

dividual sub-cycles known as modulation cycle 0 ~ mod-

ulation cycle 3, denoted as i in the table. Each one of

these four sub-cycles contains 64 clock cycles. In this

mode, a modulation frequency increase of four is

achieved. The 8-bit PWM register value, which repre-

sents the overall duty cycle of the PWM waveform, is di-

vided into two groups. The first group which consists of

bit2~bit7 is denoted here as the DC value. The second

group which consists of bit0~bit1 is known as the AC

value. In the 6+2 PWM mode, the duty cycle value of

each of the four modulation sub-cycles is shown in the

following table.

system clock f_SYS

.

This method of dividing the original modulation cycle

into a further 2 or 4 sub-cycles enable the generation of

higher PWM frequencies which allow a wider range of

applications to be served. As long as the periods of the

generated PWM pulses are less than the time constants

of the load, the PWM output will be suitable as such long

time constant loads will average out the pulses of the

PWM output. The difference between what is known as

the PWM cycle frequency and the PWM modulation fre-

quency should be understood. As the PWM clock is the

system clock, f_SYS, and as the PWM value is 8-bits wide,

the overall PWM cycle frequency is f_SYS/256. However,

when in the 7+1 mode of operation the PWM modulation

frequency will be f_SYS/128, while the PWM modulation

DC

Parameter

AC (0~3)

i<AC

(Duty Cycle)

DC+1

64

Modulation cycle i

(i=0~3)

DC

64

i³AC

6+2 Mode Modulation Cycle Values

The following diagram illustrates the waveforms associ-

ated with the 6+2 mode of PWM operation. It is impor-

tant to note how the single PWM cycle is subdivided into

4 individual modulation cycles, numbered from 0~3 and

how the AC value is related to the PWM value.

S

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6+2 PWM Mode

Rev. 1.10

22

August 13, 2008

HT46R01A

b

7

b

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PWM Register for 6+2 Mode

7+1 PWM Mode

DC

Parameter

AC (0~1)

i<AC

(Duty Cycle)

Each full PWM cycle, as it is controlled by an 8-bit PWM

register, has 256 clock periods. However, in the 7+1

PWM mode, each PWM cycle is subdivided into two indi-

vidual sub-cycles known as modulation cycle 0 ~ modula-

tion cycle 1, denoted as i in the table. Each one of these

two sub-cycles contains 128 clock cycles. In this mode, a

modulation frequency increase of two is achieved. The

8-bit PWM register value, which represents the overall

duty cycle of the PWM waveform, is divided into two

groups. The first group which consists of bit1~bit7 is de-

noted here as the DC value. The second group which

consists of bit0 is known as the AC value. In the 7+1

PWM mode, the duty cycle value of each of the two mod-

ulation sub-cycles is shown in the following table.

DC+1

128

Modulation cycle i

(i=0~1)

DC

i³AC

128

7+1 Mode Modulation Cycle Values

The following diagram illustrates the waveforms associ-

ated with the 7+1 mode PWM operation. It is important

to note how the single PWM cycle is subdivided into 2 in-

dividual modulation cycles, numbered 0 and 1 and how

the AC value is related to the PWM value.

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PWM Register for 7+1 Mode

Rev. 1.10

23

August 13, 2008

HT46R01A

PWM Output Control

Analog to Digital Converter

The PWM output is pin-shared with the I/O pin PA4. To

operate as a PWM output and not as an I/O pin, the cor-

rect bits must be set in the CTRL0 register. A zero value

must also be written to the corresponding bit in the I/O

port control register PAC.4 to ensure that the PWM out-

put pin is setup as an output. After these two initial steps

have been carried out, and of course after the required

PWM value has been written into the PWM register, writ-

ing a high value to the corresponding bit in the output

data register PA.4 will enable the PWM data to appear

on the pin. Writing a zero value will disable the PWM

output function and force the output low. In this way, the

Port A data output register can be used as an on/off con-

trol for the PWM function. Note that if the CTRL0 register

has selected the PWM function, but a high value has

been written to its corresponding bit in the PAC control

register to configure the pin as an input, then the pin can

still function as a normal input line, with pull-high resistor

options.

The need to interface to real world analog signals is a

common requirement for many electronic systems.

However, to properly process these signals by a

microcontroller, they must first be converted into digital

signals by A/D converters. By integrating the A/D con-

version electronic circuitry into the microcontroller, the

need for external components is reduced significantly

with the corresponding follow-on benefits of lower costs

and reduced component space requirements.

A/D Overview

The device contains a 4-channel analog to digital con-

verter which can directly interface to external analog sig-

nals, such as that from sensors or other control signals

and convert these signals directly into an 8-bit digital

value.

The following diagram shows the overall internal struc-

ture of the A/D converter, together with its associated

registers.

PWM Programming Example

The following sample program shows how the PWM

output is setup and controlled.

mov a,64h

; setup PWM value of 100

; decimal which is 64H

mov pwm,a

set ctrl.5 ; select the 7+1 PWM mode

set ctrl.3 ; select pin PA4 to have a PWM

; function

clr pac.4

set pa.4

; setup pin PA4 as an output

; PD.0=1; enable the PWM

; output

:

clr pa.4

; disable the PWM output - pin

; PD4 forced low

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A/D Converter Structure

Rev. 1.10

24

August 13, 2008

HT46R01A

The START bit in the ADCR register is used to start and

reset the A/D converter. When the microcontroller sets

this bit from low to high and then low again, an analog to

digital conversion cycle will be initiated. When the

START bit is brought from low to high but not low again,

the EOCB bit in the ADCR register will be set high and

the analog to digital converter will be reset. It is the

START bit that is used to control the overall on/off opera-

tion of the internal analog to digital converter.

A/D Converter Data Registers - ADR

As the device has an 8-bit A/D converter, a single regis-

ter, known as ADR, is used to store the 8-bit analog to

digital conversion value. After the conversion process

takes place, this register can be directly read by the

microcontroller to obtain the digitised conversion value.

In the following tables, D0~D7 are the A/D conversion

data result bits.

The EOCB bit in the ADCR register is used to indicate

when the analog to digital conversion process is com-

plete. This bit will be automatically cleared to zero by the

microcontroller after a conversion cycle has ended. In

addition, the corresponding A/D interrupt request flag

will be set in the interrupt control register, and if the inter-

rupts are enabled, an appropriate internal interrupt sig-

nal will be generated. This A/D internal interrupt signal

will direct the program flow to the associated A/D inter-

nal interrupt address for processing. If the A/D internal

interrupt is disabled, the microcontroller can be used to

poll the EOCB bit in the ADCR register to check whether

it has been cleared as an alternative method of detect-

ing the end of an A/D conversion cycle.

Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

ADR

D7

D6

D5

D4

D3

D2

D1

D0

A/D Data Register

A/D Converter Control Register - ADCR

To control the function and operation of the A/D con-

verter, a control register known as ADCR is provided.

This 8-bit register defines functions such as the selec-

tion of which analog channel is connected to the internal

A/D converter, which pins are used as analog inputs and

which are used as normal I/Os as well as controlling the

start function and monitoring the A/D converter end of

conversion status.

One section of this register contains the bits

ACS2~ACS0 which define the channel number. As each

of the devices contains only one actual analog to digital

converter circuit, each of the individual 4 analog inputs

must be routed to the converter. It is the function of the

ACS2~ACS0 bits in the ADCR register to determine

which analog channel is actually connected to the inter-

nal A/D converter. Note that the ACS2 bit must always

be assigned a zero value. The ADCR control register

also contains the PCR2~PCR0 bits which determine

which pins on Port A are used as analog inputs for the

A/D converter and which pins are to be used as normal

I/O pins. If the 3-bit address on PCR2~PCR0 has a

value of ²100² or higher, then all four pins, namely AN0,

AN1, AN2 and AN3 will all be set as analog inputs. Note

that if the PCR2~PCR0 bits are all set to zero, then all

the Port B pins will be setup as normal I/Os and the inter-

nal A/D converter circuitry will be powered off to reduce

the power consumption.

A/D Converter Clock Source Register - ACSR

The clock source for the A/D converter, which originates

from the system clock f_SYS, is first divided by a division

ratio, the value of which is determined by the bits

ADCS0 to ADCS2 in the ACSR register.

Although the A/D clock source is determined by the sys-

tem clock f_SYS, and by bits ADCS0 to ADCS2, there are

some limitations on the maximum A/D clock source

speed that can be selected. As the minimum value of

permissible A/D clock period, t_AD, is 1us for all devices,

care must be taken for system clock speeds in excess of

1MHz. For system clock speeds in excess of 1MHz, the

ADCS0 to ADCS2 bits should not be set to give an A/D

clock period less than the specified minimum A/D clock

period which may result in inaccurate A/D conversion

values. Refer to the table for examples, where values

marked with an asterisk * show where special care must

be taken, as the values are less than the specified mini-

mum A/D Clock Period.

Rev. 1.10

25

August 13, 2008

HT46R01A

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A/D Clock Period (t_AD)/ADCS0~ADCS2

f_SYS

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f_SYS/2

000

f_SYS/4

101

f_SYS/8

001

f_SYS/16

110

f_SYS/32

010

1MHz

2MHz

4MHz

8MHz

1ms

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666.7ns*

1.33ms

2.67ms

A/D Clock Period Examples

Rev. 1.10

26

August 13, 2008

HT46R01A

·

A/D Input Pins

Step 1

Select the required A/D conversion clock by correctly

programming bits ADCS0 to ADCS20 in the ACSR

register.

All of the A/D analog input pins are pin-shared with the

I/O pins on Port A. Bits PCR0~PCR2 in the ADCR regis-

ter, not configuration options, determine whether the in-

put pins are setup as normal Port A input/output pins or

whether they are setup as analog inputs. In this way,

pins can be changed under program control to change

their function from normal I/O operation to analog inputs

and vice versa. Pull-high resistors, which are setup via

the PAPU register, apply to the input pins only when they

are used as normal I/O pins, if setup as A/D inputs the

pull-high resistors will be automatically disconnected.

Note that it is not necessary to first setup the A/D pin as

an input in the PAC port control register to enable the

A/D input, when the PCR2~PCR0 bits enable an A/D in-

put, the status of the port control register will be overrid-

den. The VDD power supply pin is used as the A/D

converter reference voltage, and as such analog inputs

must not be allowed to exceed this value. Appropriate

measures should also be taken to ensure that the VDD

pin remains as stable and noise free as possible.

Step 2

Select which pins on Port A are to be used as A/D in-

puts and configure them as A/D input pins by correctly

programming the PCR0~PCR2 bits in the ADCR reg-

ister.

·

Step 3

Select which channel is to be connected to the internal

A/D converter by correctly programming the

ACS0~ACS2 bits which are also contained in the

ADCR register. Note that this step can be combined

with Step 2 into a single ADCR register programming

operation.

·

Step 4

If the interrupts are to be used, the interrupt control

registers must be correctly configured to ensure the

A/D converter interrupt function is active. The master

interrupt control bit, EMI, in the interrupt control regis-

ter must be set high and the A/D converter interrupt

bit, EADI, in the interrupt control register must also be

set high.

Initialising the A/D Converter

The internal A/D converter must be initialised in a spe-

cial way. Each time the A/D channel selection bits are

modified by the program, the A/D converter must be

re-initialised. If the A/D converter is not initialised after

the channel selection bits are changed, the EOCB flag

may have an undefined value, which may produce a

false end of conversion signal. To initialise the A/D con-

verter after the channel selection bits have changed,

then, within a time frame of one to ten instruction cycles,

the START bit in the ADCR register must first be set high

and then immediately cleared to zero. This will ensure

that the EOCB flag is correctly set to a high condition.

·

Step 5

The analog to digital conversion process can now be

initialised by setting the START bit in the ADCR regis-

ter from low to high and then low again. Note that this

bit should have been originally set to a zero value.

Step 6

To check when the analog to digital conversion pro-

cess is complete, the EOCB bit in the ADCR register

can be polled. The conversion process is complete

when this bit goes low. When this occurs the A/D data

registers be read to obtain the conversion value. As

an alternative method if the interrupts are enabled and

the stack is not full, the program can wait for an A/D in-

terrupt to occur.

Summary of A/D Conversion Steps

Note: When checking for the end of the conversion

process, if the method of polling the EOCB bit in

the ADCR register is used, the interrupt enable

step above can be omitted.

The following summarises the individual steps that

should be executed in order to implement an A/D con-

version process.

Rev. 1.10

27

August 13, 2008

HT46R01A

The following timing diagram shows graphically the various stages involved in an analog to digital conversion process

and its associated timing.

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A/D Conversion Timing

The setting up and operation of the A/D converter func-

tion is fully under the control of the application program

as there are no configuration options associated with

the A/D converter. After an A/D conversion process has

been initiated by the application program, the

microcontroller internal hardware will begin to carry out

the conversion, during which time the program can con-

tinue with other functions. The time taken for the A/D

conversion is dependent upon the device chosen and is

a function of the A/D clock period t_ADas shown in the ta-

ble.

supplied to the internal A/D circuitry will be reduced re-

sulting in a reduction of supply current. This ability to re-

duce power by turning off the internal A/D function by

clearing the A/D channel selection bits may be an impor-

tant consideration in battery powered applications.

Another important programming consideration is that

when the A/D channel selection bits change value the

A/D converter must be re-initialised. This is achieved by

pulsing the START bit in the ADCR register immediately

after the channel selection bits have changed state. The

exception to this is where the channel selection bits are

all cleared, in which case the A/D converter is not re-

quired to be re-initialised.

Device

A/D Conversion Time

HT46R01A

64t_AD

A/D Programming Example

A/D Conversion Time

The following two programming examples illustrate how

to setup and implement an A/D conversion. In the first

example, the method of polling the EOCB bit in the

ADCR register is used to detect when the conversion

cycle is complete, whereas in the second example, the

A/D interrupt is used to determine when the conversion

is complete.

Programming Considerations

When programming, special attention must be given to

the A/D channel selection bits in the ADCR register. If

these bits are all cleared to zero no external pins will be

selected for use as A/D input pins allowing the pins to be

used as normal I/O pins. When this happens the power

Example: using an EOCB polling method to detect the end of conversion.

clr

mov

EADI

a,00000001B

ACSR,a

; disable ADC interrupt

; setup the ACSR register to select f_SYS/8 as

; the A/D clock

mov

a,00100000B

; setup ADCR register to configure Port PA0~PA3

; as A/D inputs

; and select AN0 to be connected to the A/D

; converter

ADCR,a

:

Rev. 1.10

28

August 13, 2008

HT46R01A

:

; As the Port A channel bits have changed the

; following START

; signal (0-1-0) must be issued within 10

; instruction cycles

Start_conversion:

clr

set

clr

Polling_EOC:

sz

START

; reset A/D

; start A/D

EOCB

; poll the ADCR register EOCB bit to detect end

; of A/D conversion

; continue polling

; read conversion result value from the ADR

; register

; save result to user defined memory

jmp

mov

polling_EOC

a,ADR

mov

jmp

adr_buffer,a

:

start_conversion

; start next A/D conversion

Example: using an interrupt method to detect the end of conversion

clr

mov

EADI

a,00000001B

ACSR,a

; disable ADC interrupt

; setup the ACSR register to select f_SYS/8 as

; the A/D clock

mov

a,00100000B

; setup ADCR register to configure Port PA0~PA3

; as A/D inputs

; and select AN0 to be connected to the A/D

; converter

ADCR,a

:

; As the Port A channel bits have changed the

; following START

; signal (0-1-0) must be issued within 10

; instruction cycles

:

Start_conversion:

clr

set

clr

set

START

ADF

EADI

EMI

:

; reset A/D

; start A/D

; clear ADC interrupt request flag

; enable ADC interrupt

; enable global interrupt

:

; ADC interrupt service routine

ADC_ISR:

mov

acc_stack,a

a,STATUS

status_stack,a

:

; save ACC to user defined memory

; save STATUS to user defined memory

:

a,ADR

mov

; read conversion result value from the ADR

; register

; save result to user defined register

adr_buffer,a

:

EXIT_INT_ISR:

mov

reti

a,status_stack

STATUS,a

a,acc_stack

; restore STATUS from user defined memory

; restore ACC from user defined memory

Rev. 1.10

29

August 13, 2008

HT46R01A

A/D Transfer Function

Interrupts

As the device contain an 8-bit A/D converter, its

full-scale converted digitised value is equal to 0FFH.

Since the full-scale analog input value is equal to the

Interrupts are an important part of any microcontroller

system. When an external event or an internal function

such as a Timer/Event Counter or an A/D converter re-

quires microcontroller attention, their corresponding in-

terrupt will enforce a temporary suspension of the main

program allowing the microcontroller to direct attention

to their respective needs. The device contains a single

external interrupt and several internal interrupts func-

tions. The external interrupt is controlled by the action of

the external INT pin, while the internal interrupts are

controlled by the Timer/Event Counter overflows and

the A/D converter interrupt.

V

_DDvoltage, this gives a single bit analog input value of

_DD/256. The following graphs show the ideal transfer

function between the analog input value and the digit-

ised output value for the A/D converters.

Note that to reduce the quantisation error, a 0.5 LSB off-

set is added to the A/D Converter input. Except for the

digitised zero value, the subsequent digitised values will

change at a point 0.5 LSB below where they would

change without the offset, and the last full scale digitised

value will change at a point 1.5 LSB below the V_DDlevel.

1

.

5

L

S

B

F

H

F

E

H

F

D

H

A

/

D

C

o

n

v

e

r

s

i

o

n

R

e

s

u

l

t

0

.

5

L

S

B

0

3

2

1

H

V

D

(

)

2

5

6

0

1

2

3

2

5

3

2

5

4

2

5

2

5

6

A

n

a

l

o

g

I

n

p

u

t

V

o

l

t

a

g

e

Ideal A/D Transfer Function

b

7

b

0

A

D

F

T

0

F

E

I

F

E

A

D

I

E

T

0

I

E

I

E

M

I

N

T

C

0

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g

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r

M

a

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p

t

G

l

o

b

a

l

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n

a

b

l

e

1

0

:

g

l

o

b

a

l

e

n

a

b

l

e

a

d

i

s

a

b

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x

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1

0

:

e

d

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s

a

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1

0

:

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a

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1

0

/

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t

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a

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:

e

d

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i

a

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s

a

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1

0

x

t

e

r

n

a

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r

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p

t

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t

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l

a

g

:

a

i

c

t

i

c

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t

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i

m

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r

/

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v

e

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t

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o

u

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r

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n

t

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p

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q

u

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t

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l

a

g

1

0

:

a

i

t

i

c

v

e

n

a

t

i

n

v

e

A

/

D

C

o

v

e

r

t

e

r

R

e

q

u

e

s

t

F

l

a

g

1

0

:

a

i

c

t

i

c

e

n

a

t

i

v

l

e

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o

t

i

m

p

e

m

e

n

t

e

d

,

r

e

a

d

a

s

"

0

"

INTC0 Register

Rev. 1.10

30

August 13, 2008

HT46R01A

Interrupt Register

tine, to allow interrupt nesting. If the stack is full, the in-

terrupt request will not be acknowledged, even if the

related interrupt is enabled, until the Stack Pointer is

decremented. If immediate service is desired, the stack

must be prevented from becoming full.

Overall interrupt control, which means interrupt enabling

and request flag setting, is controlled by a single INTC0

register, which is located in the Data Memory. By con-

trolling the appropriate enable bits in these registers

each individual interrupt can be enabled or disabled.

Also when an interrupt occurs, the corresponding re-

quest flag will be set by the microcontroller. The global

enable flag if cleared to zero will disable all interrupts.

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests, the

following table shows the priority that is applied. These

can be masked by resetting the EMI bit.

Interrupt Operation

A Timer/Event Counter overflow, an end of A/D conver-

sion or an active edge on the external interrupt pin will all

generate an interrupt request by setting their corre-

sponding request flag, if their appropriate interrupt en-

able bit is set. When this happens, the Program

Counter, which stores the address of the next instruction

to be executed, will be transferred onto the stack. The

Program Counter will then be loaded with a new ad-

dress which will be the value of the corresponding inter-

rupt vector. The microcontroller will then fetch its next

instruction from this interrupt vector. The instruction at

this vector will usually be a JMP statement which will

jump to another section of program which is known as

the interrupt service routine. Here is located the code to

control the appropriate interrupt. The interrupt service

routine must be terminated with a RETI statement,

which retrieves the original Program Counter address

from the stack and allows the microcontroller to continue

with normal execution at the point where the interrupt

occurred.

Interrupt Source

External Interrupt

HT46R01A

1

2

3

Timer/Event Counter 0 Overflow

A/D Converter Interrupt

In cases where both external and internal interrupts are

enabled and where an external and internal interrupt oc-

curs simultaneously, the external interrupt will always

have priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the interrupt

registers can prevent simultaneous occurrences.

External Interrupt

For an external interrupt to occur, the global interrupt en-

able bit, EEI, and external interrupt enable bit, EEI, must

first be set. An actual external interrupt will take place

when the external interrupt request flag, EIF, is set, a sit-

uation that will occur when an edge transition appears

on the external INTline. The type of transition that will

trigger an external interrupt, whether high to low, low to

high or both is determined by the INTES0 and INTES1

bits, which are bits 6 and 7 respectively, in the CTRL1

control register. These two bits can also disable the ex-

ternal interrupt function.

The various interrupt enable bits, together with their as-

sociated request flags, are shown in the following dia-

gram with their order of priority.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked, as the EMI bit will be cleared au-

tomatically. This will prevent any further interrupt nesting

from occurring. However, if other interrupt requests oc-

cur during this interval, although the interrupt will not be

immediately serviced, the request flag will still be re-

corded. If an interrupt requires immediate servicing

while the program is already in another interrupt service

routine, the EMI bit should be set after entering the rou-

INTES1

INTES0

Edge Trigger Type

Disable

0

1

0

1

0

1

Rising Edge Trigger

Falling Edge Trigger

Dual Edge Trigger

A

u

t

o

m

a

t

i

c

a

l

y

C

l

e

a

r

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d

b

y

I

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R

A

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t

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m

a

t

i

c

a

l

y

D

i

s

a

b

l

e

d

b

y

I

S

R

M

a

n

u

a

l

y

S

e

t

o

r

C

l

e

a

r

e

d

b

y

S

o

f

t

w

a

r

e

C

a

n

b

e

E

n

a

b

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M

a

n

u

a

l

y

P

r

i

o

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i

t

y

E

x

t

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n

a

l

I

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p

t

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T

I

E

M

I

H

i

g

h

R

e

q

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t

F

l

a

g

E

I

F

T

i

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r

/

E

v

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r

0

I

n

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r

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p

t

0

I

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l

a

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0

F

P

o

l

i

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g

A

/

D

C

o

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v

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A

D

I

n

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p

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t

F

l

a

g

A

D

F

L

o

w

Interrupt Scheme

Rev. 1.10

31

August 13, 2008

HT46R01A

The external interrupt pin is pin-shared with the I/O pin

PA3 and can only be configured as an external interrupt

pin if the corresponding external interrupt enable bit in

the INTC0 register has been set and the edge trigger

type has been selected using the CTRL1 register. The

pin must also be setup as an input by setting the corre-

sponding PAC.3 bit in the port control register. When the

interrupt is enabled, the stack is not full and a transition

appears on the external interrupt pin, a subroutine call to

the external interrupt vector at location 04H, will take

place. When the interrupt is serviced, the external inter-

rupt request flag, EIF, will be automatically reset and the

EMI bit will be automatically cleared to disable other in-

terrupts. Note that any pull-high resistor connections on

this pin will remain valid even if the pin is used as an ex-

ternal interrupt input.

It is recommended that programs do not use the ²CALL

subroutine² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a ²CALL subroutine² is executed in the interrupt

subroutine.

All of these interrupts have the capability of waking up

the processor when in the Power Down Mode.

Only the Program Counter is pushed onto the stack. If

the contents of the register or status register are altered

by the interrupt service program, which may corrupt the

desired control sequence, then the contents should be

saved in advance.

Timer/Event Counter Interrupt

Reset and Initialisation

For a Timer/Event Counter interrupt to occur, the global

interrupt enable bit, EMI, and the corresponding timer

interrupt enable bit, ET0I, must first be set. An actual

Timer/Event Counter interrupt will take place when the

Timer/Event Counter request flag, T0F, is set, a situation

that will occur when the Timer/Event Counter overflows.

When the interrupt is enabled, the stack is not full and a

Timer/Event Counter overflow occurs, a subroutine call

to the timer interrupt vector at location 08H, will take

place. When the interrupt is serviced, the timer interrupt

request flag, T0F, will be automatically reset and the

EMI bit will be automatically cleared to disable other in-

terrupts.

A reset function is a fundamental part of any

microcontroller ensuring that the device can be set to

some predetermined condition irrespective of outside

parameters. The most important reset condition is after

power is first applied to the microcontroller. In this case,

internal circuitry will ensure that the microcontroller, af-

ter a short delay, will be in a well defined state and ready

to execute the first program instruction. After this

power-on reset, certain important internal registers will

be set to defined states before the program com-

mences. One of these registers is the Program Counter,

which will be reset to zero forcing the microcontroller to

begin program execution from the lowest Program

Memory address.

A/D Interrupt

In addition to the power-on reset, situations may arise

where it is necessary to forcefully apply a reset condition

when the microcontroller is running. One example of this

is where after power has been applied and the

microcontroller is already running, the RES line is force-

fully pulled low. In such a case, known as a normal oper-

ation reset, some of the microcontroller registers remain

unchanged allowing the microcontroller to proceed with

normal operation after the reset line is allowed to return

high. Another type of reset is when the Watchdog Timer

overflows and resets the microcontroller. All types of re-

set operations result in different register conditions be-

ing setup.

For an A/D interrupt to occur, the global interrupt enable

bit, EMI, and the corresponding interrupt enable bit,

EADI, must be first set. An actual A/D interrupt will take

place when the A/D converter request flag, ADF, is set, a

situation that will occur when an A/D conversion process

has completed. When the interrupt is enabled, the stack

is not full and an A/D conversion process finishes exe-

cution, a subroutine call to the A/D interrupt vector at lo-

cation 0CH, will take place. When the interrupt is

serviced, the A/D interrupt request flag, ADF, will be au-

tomatically reset and the EMI bit will be automatically

cleared to disable other interrupts.

Programming Considerations

Another reset exists in the form of a Low Voltage Reset,

LVR, where a full reset, similar to the RES reset is imple-

mented in situations where the power supply voltage

falls below a certain threshold.

By disabling the interrupt enable bits, a requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the interrupt register until the corresponding

interrupt is serviced or until the request flag is cleared by

a software instruction.

Rev. 1.10

32

August 13, 2008

HT46R01A

Reset Functions

For applications that operate within an environment

where more noise is present the Enhanced Reset Cir-

cuit shown is recommended.

There are five ways in which a microcontroller reset can

occur, through events occurring both internally and ex-

ternally:

m

0 . 0 1 F

V

D

1

0

k

·

Power-on Reset

The most fundamental and unavoidable reset is the

one that occurs after power is first applied to the

microcontroller. As well as ensuring that the Program

Memory begins execution from the first memory ad-

dress, a power-on reset also ensures that certain

other registers are preset to known conditions. All the

I/O port and port control registers will power up in a

high condition ensuring that all pins will be first set to

inputs.

R

E

S

1

0

k

m

0 . 1 F

V

S

Enhanced Reset Circuit

More information regarding external reset circuits is

located in Application Note HA0075E on the Holtek

website.

Although the microcontroller has an internal RC reset

function, if the VDD power supply rise time is not fast

enough or does not stabilise quickly at power-on, the

internal reset function may be incapable of providing

proper reset operation. For this reason it is recom-

mended that an external RC network is connected to

the RES pin, whose additional time delay will ensure

that the RES pin remains low for an extended period

to allow the power supply to stabilise. During this time

delay, normal operation of the microcontroller will be

inhibited. After the RES line reaches a certain voltage

value, the reset delay time t_RSTDis invoked to provide

an extra delay time after which the microcontroller will

begin normal operation. The abbreviation SST in the

figures stands for System Start-up Timer.

·

RES Pin Reset

This type of reset occurs when the microcontroller is

already running and the RES pin is forcefully pulled

low by external hardware such as an external switch.

In this case as in the case of other reset, the Program

Counter will reset to zero and program execution initi-

ated from this point.

0

.

9

V

0

.

4

V

R

E

S

t

R S T D

S

T

i

m

e

-

o

u

t

I

n

t

e

r

n

a

l

R

e

s

e

t

V

D

RES Reset Timing Chart

0

.

9

V

R

E

S

t

R S T D

·

Low Voltage Reset - LVR

S

T

i

m

e

-

o

u

t

The microcontroller contains a low voltage reset cir-

cuit in order to monitor the supply voltage of the de-

vice. The LVR function is selected via a configuration

option. If the supply voltage of the device drops to

within a range of 0.9V~V_LVRsuch as might occur when

changing the battery, the LVR will automatically reset

the device internally. For a valid LVR signal, a low sup-

ply voltage, i.e., a voltage in the range between

0.9V~V_LVRmust exist for a time greater than that spec-

ified by t_LVRin the A.C. characteristics. If the low sup-

ply voltage state does not exceed this value, the LVR

will ignore the low supply voltage and will not perform

a reset function. The actual V_LVRvalue can be se-

lected via configuration options.

I

n

t

e

r

n

a

l

R

e

s

e

t

Power-On Reset Timing Chart

For most applications a resistor connected between

VDD and the RES pin and a capacitor connected be-

tween VSS and the RES pin will provide a suitable ex-

ternal reset circuit. Any wiring connected to the RES

pin should be kept as short as possible to minimise

any stray noise interference.

V

D

1

0

k

R

E

S

L

V

R

m

0 . 1 F

t

R S T D

V

S

T

i

m

e

-

o

u

t

Basic Reset Circuit

I

n

t

e

r

n

a

l

R

e

s

e

t

Low Voltage Reset Timing Chart

Rev. 1.10

33

August 13, 2008

HT46R01A

·

Watchdog Time-out Reset during Normal Operation

The Watchdog time-out Reset during normal opera-

tion is the same as a hardware RES pin reset except

that the Watchdog time-out flag TO will be set to ²1².

TO are located in the status register and are controlled

by various microcontroller operations, such as the

Power Down function or Watchdog Timer. The reset

flags are shown in the table:

W

D

T

i

m

e

-

o

u

t

TO PDF

RESET Conditions

t

R S T D

0

u

1

0

u

1

RES reset during power-on

S

T

i

m

e

-

o

u

t

RES or LVR reset during normal operation

WDT time-out reset during normal operation

WDT time-out reset during Power Down

I

n

t

e

r

n

a

l

R

e

s

e

t

WDT Time-out Reset during Normal Operation

Timing Chart

Note: ²u² stands for unchanged

·

Watchdog Time-out Reset during Power Down

The Watchdog time-out Reset during Power Down is

a little different from other kinds of reset. Most of the

conditions remain unchanged except that the Pro-

gram Counter and the Stack Pointer will be cleared to

²0² and the TO flag will be set to ²1². Refer to the A.C.

Characteristics for t_SSTdetails.

The following table indicates the way in which the vari-

ous components of the microcontroller are affected after

a power-on reset occurs.

Item

Condition After RESET

Program Counter Reset to zero

Interrupts

WDT

All interrupts will be disabled

W

D

T

i

m

e

-

o

u

t

S

T

Clear after reset, WDT begins

counting

S

T

i

m

e

-

o

u

t

WDT Time-out Reset during Power Down

Timing Chart

Timer/Event

Counter

Timer Counter will be turned off

The Timer Counter Prescaler will

be cleared

Note:

The SST can be chosen to be either 1024 or 2

clock cycles via configuration option if the sys-

tem clock source is not provided by an external

crystal

Prescaler

Input/Output Ports I/O ports will be setup as inputs

Stack Pointer will point to the top

Stack Pointer

of the stack

Reset Initial Conditions

The different types of reset described affect the reset

flags in different ways. These flags, known as PDF and

Rev. 1.10

34

August 13, 2008

HT46R01A

The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable

continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller

is in after a particular reset occurs. The following table describes how each type of reset affects each of the

microcontroller internal registers.

Reset

RES or LVR

Reset

WDT Time-out

(HALT)

Register

(Power-on)

(Normal Operation)

MP0

MP1

1 x x x x x x x

x x x x x x x x

- - x x x x x x

- - - - - 1 1 1

- - 0 0 x x x x

- 0 0 0 0 0 0 0

x x x x x x x x

0 0 0 0 1 0 0 0

1 1 1 1 1 1 1 1

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

- 0 0 - 0 0 0 0

1 0 - - 1 0 1 0

x x x x x x x x

0 1 0 0 0 0 0 0

1 - - - - 0 0 0

u u u u u u u u

- - u u u u u u

- - - - - 1 1 1

- - u u u u u u

- 0 0 0 0 0 0 0

x x x x x x x x

0 0 0 0 1 0 0 0

1 1 1 1 1 1 1 1

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

- 0 0 - 0 0 0 0

1 0 - - 1 0 1 0

x x x x x x x x

0 1 0 0 0 0 0 0

1 - - - - 0 0 0

1 u u u u u u u

u u u u u u u u

- - u u u u u u

- - - - - 1 1 1

- - 1 u u u u u

- 0 0 0 0 0 0 0

x x x x x x x x

0 0 0 0 1 0 0 0

1 1 1 1 1 1 1 1

- 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

- 0 0 - 0 0 0 0

1 0 - - 1 0 1 0

x x x x x x x x

0 1 0 0 0 0 0 0

1 - - - - 0 0 0

1 u u u u u u u

u u u u u u u u

- - u u u u u u

- - - - - u u u

- - 1 1 u u u u

- u u u u u u u

u u u u u u u u

- u u u u u u u

u u u u u u u u

- u u - u u u u

u u - - u u u u

u u u u u u u u

u - - - - u u u

ACC

TBLP

TBLH

WDTS

STATUS

INTC0

TMR0

TMR0C

PA

PAC

PAPU

PAWK

CTRL0

CTRL1

PWM

ADR

ADCR

ACSR

Note:

²*² means ²warm reset²

²-² not implemented

²u² means ²unchanged²

²x² means ²unknown²

Rev. 1.10

35

August 13, 2008

HT46R01A

Oscillator

Various oscillator options offer the user a wide range of

functions according to their various application require-

ments. Four types of system clocks can be selected

while various clock source options for the Watchdog

Timer are provided for maximum flexibility. All oscillator

options are selected through the configuration options.

Crystal Oscillator C1 and C2 Values

Crystal Frequency

12MHz

C1

C2

CL

TBD

8MHz

The four methods of generating the system clock are:

4MHz

·

External crystal/resonator oscillator

External RC oscillator

1MHz

Note: 1. C1 and C2 values are for guidance only.

2. CL is the crystal manufacturer specified

load capacitor value.

Internal RC oscillator

Combined Internal RC oscillator and Real Time Clock

One of these four methods must be selected using the

configuration options.

Crystal Recommended Capacitor Values

More information regarding the oscillator is located in

Application Note HA0075E on the Holtek website.

Resonator C1 and C2 Values

Resonator Frequency

3.58MHz

C1

C2

External Crystal/Resonator Oscillator

TBD

The simple connection of a crystal across OSC1 and

OSC2 will create the necessary phase shift and feed-

back for oscillation, and will normally not require exter-

nal capacitors. However, for some crystals and most

resonator types, to ensure oscillation and accurate fre-

quency generation, it may be necessary to add two

1MHz

455kHz

Note: C1 and C2 values are for guidance only.

Resonator Recommended Capacitor Values

External RC Oscillator

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1

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1

Using the external system RC oscillator requires that a

resistor, with a value between 24kW and 1.5MW, is con-

nected between OSC1 and VDD, and a capacitor is con-

nected to ground. Although this is a cost effective

oscillator configuration, the oscillation frequency can

vary with VDD, temperature and process variations and

is therefore not suitable for applications where timing is

critical or where accurate oscillator frequencies are re-

quired.For the value of the external resistor ROSC refer

to the Holtek website for typical RC Oscillator vs. Tem-

perature and VDD characteristics graphics Here only

the OSC1 pin is used, which is shared with I/O pin PA6,

leaving pin PA5 free for use as a normal I/O pin. Note

that it is the only microcontroller internal circuitry to-

gether with the external resistor, that determine the fre-

quency of the oscillator. The external capacitor shown

on the diagram does not influence the frequency of os-

cillation.

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Crystal/Resonator Oscillator

small value external capacitors, C1 and C2. The exact

values of C1 and C2 should be selected in consultation

with the crystal or resonator manufacturer¢s specifica-

tion. The external parallel feedback resistor, Rp, is nor-

mally not required but in some cases may be needed to

assist with oscillation start up.

V

D

Internal Ca, Cb, Rf Typical Values @ 5V, 25°C

R

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Ca

Cb

Rf

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1

11~13pF

13~15pF

270kW

4

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Oscillator Internal Component Values

P

A

5

External RC Oscillator

Rev. 1.10

36

August 13, 2008

HT46R01A

Internal RC Oscillator

Internal Ca, Cb, Rf Typical Values @ 5V, 25°C

The internal RC oscillator is a fully integrated system os-

cillator requiring no external components. The internal

RC oscillator has three fixed frequencies of either

4MHz, 8MHz or 12MHz, the choice of which is indicated

by the suffix marking next to the part number of the de-

vice used. Note that if this internal system clock option is

selected, as it requires no external pins for its operation,

I/O pins PA5 and PA6 are free for use as normal I/O

pins. Refer to the Appendix section for more information

on the actual internal oscillator frequency vs. Tempera-

ture and VDD characteristics graphics.

Ca

Cb

Rf

11~13pF

13~15pF

270kW

RTC Oscillator Internal Component Values

RTC Oscillator C1 and C2 Values

Crystal Frequency

C1

C2

CL

32768Hz

TBD

Note: 1. C1 and C2 values are for guidance only.

2. CL is the crystal manufacturer specified

load capacitor value.

P

A

5

6

32768 Hz Crystal Recommended Capacitor Values

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For applications using the RTC oscillator, the system

clock can be chosen to be either the Internal System RC

Oscillator or the RTC oscillator itself. This selection is

made using the CLKMOD bit in the CTRL0 register. If

this bit is set high then the 32768Hz external crystal will

also provide the system clock source. If the bit is low

then the system clock source will be the Internal RC Os-

cillator. When the system enters the Power Down Mode,

the system clock, irrespective of whether the CLKMOD

bit has selected the RTC or Internal RC Oscillator as its

source, will always stop running. The accompanying ta-

ble shows the relationship between the CLKMOD bit

and the various oscillators.

N

o

t

e

:

Internal RC Oscillator

Internal RC Oscillator + External RTC Oscillator

When the microcontroller enters the Power Down Mode,

the system clock is switched off to stop microcontroller

activity and to conserve power. However, in many

microcontroller applications it may be necessary to keep

the internal timers operational even when the

microcontroller is in the Power Down Mode. To do this,

Operating CLKMOD Internal

System

Clock

I

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RTC

C

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Mode

Bit

RC Osc.

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32768Hz

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During power up there is a time delay associated with

the RTC oscillator waiting for it to start up. Bit 1 of the

CTRL0 register, known as the QOSC bit, is provided to

give a quick start-up function and can be used to mini-

mize this delay. During a power up condition, this bit will

be cleared to 0 which will initiate the RTC oscillator quick

start-up function. However, as there is additional power

consumption associated with this quick start-up func-

tion, to reduce power consumption after start up takes

place, it is recommended that the application program

should set the QOSC bit high about 2 seconds after

power on. It should be noted that, no matter what condi-

tion the QOSC bit is set to, the RTC oscillator will always

function normally, only there is more power consump-

tion associated with the quick start-up function.

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Internal RC Oscillator + External RTC Oscillator

another clock, independent of the system clock, must be

provided. To do this a configuration option exists to allow

the Internal System RC Oscillator to be used in conjunc-

tion with a Real Time Clock - RTC oscillator. Here the

OSC1 and OSC2 pins, which are shared with I/O pins

PA6 and PA5 should be connected to a 32768Hz crystal

to implement this internal RTC oscillator. However, for

some crystals, to ensure oscillation and accurate fre-

quency generation, it may be necessary to add two

small value external capacitors, C1 and C2. The exact

values of C1 and C2 should be selected in consultation

with the crystal or resonator manufacturer¢s specifica-

tion. The external parallel feedback resistor, Rp, is nor-

mally not required but in some cases may be needed to

assist with oscillation start up.

Rev. 1.10

37

August 13, 2008

HT46R01A

Watchdog Timer Oscillator

Special attention must be made to the I/O pins on the

device. All high-impedance input pins must be con-

nected to either a fixed high or low level as any floating

input pins could create internal oscillations and result in

increased current consumption. Care must also be

taken with the loads, which are connected to I/O pins,

which are setup as outputs. These should be placed in a

condition in which minimum current is drawn or con-

nected only to external circuits that do not draw current,

such as other CMOS inputs.

The WDT oscillator is a fully self-contained free running

on-chip RC oscillator with a typical period of 65ms at 5V

requiring no external components. When the device en-

ters the Power Down Mode, the system clock will stop

running but the WDT oscillator continues to free-run and

to keep the watchdog active. However, to preserve

power in certain applications the WDT oscillator can be

disabled via a configuration option.

If the configuration options have enabled the Watchdog

Timer internal oscillator then this will continue to run

when in the Power Down Mode and will thus consume

some power. For power sensitive applications it may be

therefore preferable to use the system clock source for

the Watchdog Timer. The RTC, if configured for use, will

also consume a limited amount of power, as it continues

to run when the device enters the Power Down Mode. To

keep the RTC power consumption to a minimum level

the QOSC bit in the CTRL0 register, which controls the

quick start up function, should be set high. If any I/O pins

are configured as A/D analog inputs using the channel

configuration bits in the ADCR register, then the A/D

converter will be turned on and a certain amount of

power will be consumed. It may be therefore desirable

before entering the Power Down Mode to ensure that

the A/D converter is powered down by ensuring that any

A/D input pins are setup as normal logic inputs with

pull-high resistors.

Power Down Mode and Wake-up

Power Down Mode

All of the Holtek microcontrollers have the ability to enter

a Power Down Mode. When the device enters this

mode, the normal operating current, will be reduced to

an extremely low standby current level. This occurs be-

cause when the device enters the Power Down Mode,

the system oscillator is stopped which reduces the

power consumption to extremely low levels, however,

as the device maintains its present internal condition, it

can be woken up at a later stage and continue running,

without requiring a full reset. This feature is extremely

important in application areas where the MCU must

have its power supply constantly maintained to keep the

device in a known condition but where the power supply

capacity is limited such as in battery applications.

Entering the Power Down Mode

There is only one way for the device to enter the Power

Down Mode and that is to execute the ²HALT² instruc-

tion in the application program. When this instruction is

executed, the following will occur:

Wake-up

After the system enters the Power Down Mode, it can be

woken up from one of various sources listed as follows:

·

An external reset

The system oscillator will stop running and the appli-

cation program will stop at the ²HALT² instruction.

An external falling edge on PA0 to PA7

A system interrupt

If the RTC oscillator configuration option is enabled

then the RTC clock will keep running.

A WDT overflow

The Data Memory contents and registers will maintain

their present condition.

If the system is woken up by an external reset, the de-

vice will experience a full system reset, however, if the

device is woken up by a WDT overflow, a Watchdog

Timer reset will be initiated. Although both of these

wake-up methods will initiate a reset operation, the ac-

tual source of the wake-up can be determined by exam-

ining the TO and PDF flags. The PDF flag is cleared by a

system power-up or executing the clear Watchdog

Timer instructions and is set when executing the ²HALT²

instruction. The TO flag is set if a WDT time-out occurs,

and causes a wake-up that only resets the Program

Counter and Stack Pointer, the other flags remain in

their original status.

The WDT will be cleared and resume counting if the

WDT clock source is selected to come from the WDT

or RTC oscillator. The WDT will stop if its clock source

originates from the system clock.

·

The I/O ports will maintain their present condition.

In the status register, the Power Down flag, PDF, will

be set and the Watchdog time-out flag, TO, will be

cleared.

Standby Current Considerations

As the main reason for entering the Power Down Mode

is to keep the current consumption of the MCU to as low

a value as possible, perhaps only in the order of several

micro-amps, there are other considerations which must

also be taken into account by the circuit designer if the

power consumption is to be minimised.

Pins PA0 to PA7 can be setup via the PAWK register to

permit a negative transition on the pin to wake-up the

system. When a PA0 to PA7 pin wake-up occurs, the

program will resume execution at the instruction follow-

ing the ²HALT² instruction.

Rev. 1.10

38

August 13, 2008

HT46R01A

If the system is woken up by an interrupt, then two possi-

ble situations may occur. The first is where the related

interrupt is disabled or the interrupt is enabled but the

stack is full, in which case the program will resume exe-

cution at the instruction following the ²HALT² instruction.

In this situation, the interrupt which woke-up the device

will not be immediately serviced, but will rather be ser-

viced later when the related interrupt is finally enabled or

when a stack level becomes free. The other situation is

where the related interrupt is enabled and the stack is

not full, in which case the regular interrupt response

takes place. If an interrupt request flag is set to ²1² be-

fore entering the Power Down Mode, the wake-up func-

tion of the related interrupt will be disabled.

Configuration

Option

CTRL1

WDT

Register

Function

Disable

Enable

Disable

Enable

Disable

Enable

OFF

ON

Watchdog Timer On/Off Control

The Watchdog Timer will be disabled if bits

WDTEN3~WDTEN0 in the CTRL1 register are written

with the binary value 1010B and WDT configuration op-

tion is disable. This will be the condition when the device

is powered up. Although any other data written to

WDTEN3~WDTEN0 will ensure that the Watchdog

Timer is enabled, for maximum protection it is recom-

mended that the value 0101B is written to these bits.

No matter what the source of the wake-up event is, once

a wake-up situation occurs, a time period equal to 1024

system clock periods will be required before normal sys-

tem operation resumes. However, if the wake-up has

originated due to an interrupt, the actual interrupt sub-

routine execution will be delayed by an additional one or

more cycles. If the wake-up results in the execution of

the next instruction following the ²HALT² instruction, this

will be executed immediately after the 1024 system

clock period delay has ended.

The Watchdog Timer clock can emanate from three dif-

ferent sources, selected by configuration option. These

are its own fully integrated dedicated internal oscillator,

the RTC or f_SYS/4. The Watchdog Timer dedicated inter-

nal clock source is an internal oscillator which has an

approximate period of 65ms at a supply voltage of 5V.

However, it should be noted that this specified internal

clock period can vary with VDD, temperature and pro-

cess variations. The other Watchdog Timer clock source

options are the f_SYS/4 clock and the RTC. It is important

to note that when the system enters the Power Down

Mode the instruction clock is stopped, therefore if the

configuration options have selected f_SYS/4 as the

Watchdog Timer clock source, the Watchdog Timer will

cease to function. For systems that operate in noisy en-

vironments, using the internal Watchdog Timer internal

oscillator or the RTC as the clock source is therefore the

recommended choice. No matter which clock source is

selected, it is further divided by 256 via an internal 8-bit

counter and then by a 7-bit prescaler to give longer

time-out periods. The division ratio of the prescaler is

determined by bits 0, 1 and 2 of the WDTS register,

known as WS0, WS1 and WS2. If the Watchdog Timer

internal clock source is selected and with the WS0, WS1

and WS2 bits of the WDTS register all set high, the

prescaler division ratio will be 1:128, which will give a

maximum time-out period of about 2.1s.

Watchdog Timer

The Watchdog Timer, also known as the WDT, is pro-

vided to inhibit program malfunctions caused by the pro-

gram jumping to unknown locations due to certain

uncontrollable external events such as electrical noise.

It operates by providing a device reset when the Watch-

dog Timer counter overflows. Note that if the Watchdog

Timer function is not enabled, then any instructions re-

lated to the Watchdog Timer will result in no operation.

Setting up the various Watchdog Timer options are con-

trolled via the configuration options and two internal reg-

isters WDTS and CTRL1. Enabling the Watchdog Timer

can be controlled by both a configuration option and the

WDTEN bits in the CTRL1 internal register in the Data

Memory.

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Watchdog Timer

Rev. 1.10

39

August 13, 2008

HT46R01A

Under normal program operation, a Watchdog Timer

time-out will initialise a device reset and set the status bit

TO. However, if the system is in the Power Down Mode,

when a Watchdog Timer time-out occurs, the device will

be woken up, the TO bit in the status register will be set

and only the Program Counter and Stack Pointer will be

reset. Three methods can be adopted to clear the con-

tents of the Watchdog Timer. The first is an external

hardware reset, which means a low level on the external

reset pin, the second is using the Clear Watchdog Timer

software instructions and the third is when a HALT in-

struction is executed. There are two methods of using

software instructions to clear the Watchdog Timer, one

of which must be chosen by configuration option. The

first option is to use the single ²CLR WDT² instruction

while the second is to use the two commands ²CLR

WDT1² and ²CLR WDT2². For the first option, a simple

execution of ²CLR WDT² will clear the Watchdog Timer

while for the second option, both ²CLR WDT1² and

²CLR WDT2² must both be executed to successfully

clear the Watchdog Timer. Note that for this second op-

tion, if ²CLR WDT1² is used to clear the Watchdog

Timer, successive executions of this instruction will

have no effect, only the execution of a ²CLR WDT2² in-

struction will clear the Watchdog Timer. Similarly after

the ²CLR WDT2² instruction has been executed, only a

successive ²CLR WDT1² instruction can clear the

Watchdog Timer.

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Configuration Options

Configuration options refer to certain options within the MCU that are programmed into the OTP Program Memory de-

vice during the programming process. During the development process, these options are selected using the HT-IDE

software development tools. As these options are programmed into the device using the hardware programming tools,

once they are selected they cannot be changed later by the application software. All options must be defined for proper

system function, the details of which are shown in the table.

No.

1

Options

Watchdog Timer: enable or disable

2

Watchdog Timer clock source: WDT internal oscillator, f_SYS/4 or RTC

CLRWDT instructions: 1 or 2 instructions

3

4

System oscillator: Internal RC, Internal RC with external RTC, External Crystal, External RC

LVR function: enable or disable

5

6

LVR voltage: 2.1V, 3.15V or 4.2V

7

RES or PA7

8

SST: enable (1024 clocks) or disable (2 clocks)

Rev. 1.10

40

August 13, 2008

HT46R01A

Application Circuits

V

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Rev. 1.10

41

August 13, 2008

HT46R01A

Instruction Set

Introduction

subtract instruction mnemonics to enable the necessary

arithmetic to be carried out. Care must be taken to en-

sure correct handling of carry and borrow data when re-

sults exceed 255 for addition and less than 0 for

subtraction. The increment and decrement instructions

INC, INCA, DEC and DECA provide a simple means of

increasing or decreasing by a value of one of the values

in the destination specified.

Central to the successful operation of any

microcontroller is its instruction set, which is a set of pro-

gram instruction codes that directs the microcontroller to

perform certain operations. In the case of Holtek

microcontrollers, a comprehensive and flexible set of

over 60 instructions is provided to enable programmers

to implement their application with the minimum of pro-

gramming overheads.

Logical and Rotate Operations

For easier understanding of the various instruction

codes, they have been subdivided into several func-

tional groupings.

The standard logical operations such as AND, OR, XOR

and CPL all have their own instruction within the Holtek

microcontroller instruction set. As with the case of most

instructions involving data manipulation, data must pass

through the Accumulator which may involve additional

programming steps. In all logical data operations, the

zero flag may be set if the result of the operation is zero.

Another form of logical data manipulation comes from

the rotate instructions such as RR, RL, RRC and RLC

which provide a simple means of rotating one bit right or

left. Different rotate instructions exist depending on pro-

gram requirements. Rotate instructions are useful for

serial port programming applications where data can be

rotated from an internal register into the Carry bit from

where it can be examined and the necessary serial bit

set high or low. Another application where rotate data

operations are used is to implement multiplication and

division calculations.

Instruction Timing

Most instructions are implemented within one instruc-

tion cycle. The exceptions to this are branch, call, or ta-

ble read instructions where two instruction cycles are

required. One instruction cycle is equal to 4 system

clock cycles, therefore in the case of an 8MHz system

oscillator, most instructions would be implemented

within 0.5ms and branch or call instructions would be im-

plemented within 1ms. Although instructions which re-

quire one more cycle to implement are generally limited

to the JMP, CALL, RET, RETI and table read instruc-

tions, it is important to realize that any other instructions

which involve manipulation of the Program Counter Low

register or PCL will also take one more cycle to imple-

ment. As instructions which change the contents of the

PCL will imply a direct jump to that new address, one

more cycle will be required. Examples of such instruc-

tions would be ²CLR PCL² or ²MOV PCL, A². For the

case of skip instructions, it must be noted that if the re-

sult of the comparison involves a skip operation then

this will also take one more cycle, if no skip is involved

then only one cycle is required.

Branches and Control Transfer

Program branching takes the form of either jumps to

specified locations using the JMP instruction or to a sub-

routine using the CALL instruction. They differ in the

sense that in the case of a subroutine call, the program

must return to the instruction immediately when the sub-

routine has been carried out. This is done by placing a

return instruction RET in the subroutine which will cause

the program to jump back to the address right after the

CALL instruction. In the case of a JMP instruction, the

program simply jumps to the desired location. There is

no requirement to jump back to the original jumping off

point as in the case of the CALL instruction. One special

and extremely useful set of branch instructions are the

conditional branches. Here a decision is first made re-

garding the condition of a certain data memory or indi-

vidual bits. Depending upon the conditions, the program

will continue with the next instruction or skip over it and

jump to the following instruction. These instructions are

the key to decision making and branching within the pro-

gram perhaps determined by the condition of certain in-

put switches or by the condition of internal data bits.

Moving and Transferring Data

The transfer of data within the microcontroller program

is one of the most frequently used operations. Making

use of three kinds of MOV instructions, data can be

transferred from registers to the Accumulator and

vice-versa as well as being able to move specific imme-

diate data directly into the Accumulator. One of the most

important data transfer applications is to receive data

from the input ports and transfer data to the output ports.

Arithmetic Operations

The ability to perform certain arithmetic operations and

data manipulation is a necessary feature of most

microcontroller applications. Within the Holtek

microcontroller instruction set are a range of add and

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Bit Operations

Other Operations

The ability to provide single bit operations on Data Mem-

ory is an extremely flexible feature of all Holtek

microcontrollers. This feature is especially useful for

output port bit programming where individual bits or port

pins can be directly set high or low using either the ²SET

[m].i² or ²CLR [m].i² instructions respectively. The fea-

ture removes the need for programmers to first read the

8-bit output port, manipulate the input data to ensure

that other bits are not changed and then output the port

with the correct new data. This read-modify-write pro-

cess is taken care of automatically when these bit oper-

ation instructions are used.

In addition to the above functional instructions, a range

of other instructions also exist such as the ²HALT² in-

struction for Power-down operations and instructions to

control the operation of the Watchdog Timer for reliable

program operations under extreme electric or electro-

magnetic environments. For their relevant operations,

refer to the functional related sections.

Instruction Set Summary

The following table depicts a summary of the instruction

set categorised according to function and can be con-

sulted as a basic instruction reference using the follow-

ing listed conventions.

Table Read Operations

Table conventions:

Data storage is normally implemented by using regis-

ters. However, when working with large amounts of

fixed data, the volume involved often makes it inconve-

nient to store the fixed data in the Data Memory. To over-

come this problem, Holtek microcontrollers allow an

area of Program Memory to be setup as a table where

data can be directly stored. A set of easy to use instruc-

tions provides the means by which this fixed data can be

referenced and retrieved from the Program Memory.

x: Bits immediate data

m: Data Memory address

A: Accumulator

i: 0~7 number of bits

addr: Program memory address

Mnemonic

Arithmetic

Description

Cycles Flag Affected

ADD A,[m]

ADDM A,[m]

ADD A,x

Add Data Memory to ACC

1

1^Note

1

Z, C, AC, OV

C

Add ACC to Data Memory

Add immediate data to ACC

ADC A,[m]

ADCM A,[m]

SUB A,x

Add Data Memory to ACC with Carry

1

1^Note

Add ACC to Data memory with Carry

Subtract immediate data from the ACC

Subtract Data Memory from ACC

1

SUB A,[m]

SUBM A,[m]

SBC A,[m]

SBCM A,[m]

DAA [m]

1

1^Note

Subtract Data Memory from ACC with result in Data Memory

Subtract Data Memory from ACC with Carry

Subtract Data Memory from ACC with Carry, result in Data Memory

Decimal adjust ACC for Addition with result in Data Memory

1

1^Note

Logic Operation

AND A,[m]

OR A,[m]

XOR A,[m]

ANDM A,[m]

ORM A,[m]

XORM A,[m]

AND A,x

Logical AND Data Memory to ACC

Logical OR Data Memory to ACC

Logical XOR Data Memory to ACC

Logical AND ACC to Data Memory

Logical OR ACC to Data Memory

Logical XOR ACC to Data Memory

Logical AND immediate Data to ACC

Logical OR immediate Data to ACC

Logical XOR immediate Data to ACC

Complement Data Memory

1

Z

1

1^Note

1

OR A,x

1

XOR A,x

1

1^Note

CPL [m]

CPLA [m]

Complement Data Memory with result in ACC

1

Increment & Decrement

INCA [m]

INC [m]

Increment Data Memory with result in ACC

1

Z

Increment Data Memory

1^Note

DECA [m]

DEC [m]

Decrement Data Memory with result in ACC

Decrement Data Memory

1

1^Note

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Mnemonic

Rotate

Description

Cycles Flag Affected

RRA [m]

RR [m]

Rotate Data Memory right with result in ACC

Rotate Data Memory right

1

1^Note

1

1^Note

1

1^Note

None

C

RRCA [m]

RRC [m]

RLA [m]

RL [m]

Rotate Data Memory right through Carry with result in ACC

Rotate Data Memory right through Carry

Rotate Data Memory left with result in ACC

Rotate Data Memory left

C

None

C

RLCA [m]

RLC [m]

Rotate Data Memory left through Carry with result in ACC

Rotate Data Memory left through Carry

1

1^Note

C

Data Move

MOV A,[m]

MOV [m],A

MOV A,x

Move Data Memory to ACC

Move ACC to Data Memory

Move immediate data to ACC

1

1^Note

1

None

Bit Operation

CLR [m].i

SET [m].i

Clear bit of Data Memory

Set bit of Data Memory

1^Note

None

Branch

JMP addr

SZ [m]

Jump unconditionally

2

None

Skip if Data Memory is zero

1^Note

1^note

1^Note

2

SZA [m]

SZ [m].i

SNZ [m].i

SIZ [m]

Skip if Data Memory is zero with data movement to ACC

Skip if bit i of Data Memory is zero

Skip if bit i of Data Memory is not zero

Skip if increment Data Memory is zero

Skip if decrement Data Memory is zero

Skip if increment Data Memory is zero with result in ACC

Skip if decrement Data Memory is zero with result in ACC

Subroutine call

SDZ [m]

SIZA [m]

SDZA [m]

CALL addr

RET

Return from subroutine

2

RET A,x

RETI

Return from subroutine and load immediate data to ACC

Return from interrupt

2

Table Read

TABRDC [m]

TABRDL [m]

Read table (current page) to TBLH and Data Memory

Read table (last page) to TBLH and Data Memory

2^Note

None

Miscellaneous

NOP

No operation

1

1^Note

1

None

CLR [m]

Clear Data Memory

SET [m]

Set Data Memory

None

CLR WDT

CLR WDT1

CLR WDT2

SWAP [m]

SWAPA [m]

HALT

Clear Watchdog Timer

TO, PDF

None

Pre-clear Watchdog Timer

Swap nibbles of Data Memory

Swap nibbles of Data Memory with result in ACC

Enter power down mode

1

1^Note

1

None

1

TO, PDF

Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,

if no skip takes place only one cycle is required.

2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.

3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by

the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and

²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags

remain unchanged.

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Instruction Definition

ADC A,[m]

Add Data Memory to ACC with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the Accumulator.

Operation

ACC ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADCM A,[m]

Add ACC to Data Memory with Carry

Description

The contents of the specified Data Memory, Accumulator and the carry flag are added. The

result is stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m] + C

Affected flag(s)

OV, Z, AC, C

ADD A,[m]

Add Data Memory to ACC

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

ADD A,x

Add immediate data to ACC

Description

The contents of the Accumulator and the specified immediate data are added. The result is

stored in the Accumulator.

Operation

ACC ¬ ACC + x

Affected flag(s)

OV, Z, AC, C

ADDM A,[m]

Add ACC to Data Memory

Description

The contents of the specified Data Memory and the Accumulator are added. The result is

stored in the specified Data Memory.

Operation

[m] ¬ ACC + [m]

Affected flag(s)

OV, Z, AC, C

AND A,[m]

Logical AND Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² [m]

Affected flag(s)

Z

AND A,x

Logical AND immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical AND

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²AND² x

Affected flag(s)

Z

ANDM A,[m]

Logical AND ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²AND² [m]

Affected flag(s)

Z

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CALL addr

Subroutine call

Description

Unconditionally calls a subroutine at the specified address. The Program Counter then in-

crements by 1 to obtain the address of the next instruction which is then pushed onto the

stack. The specified address is then loaded and the program continues execution from this

new address. As this instruction requires an additional operation, it is a two cycle instruc-

tion.

Operation

Stack ¬ Program Counter + 1

Program Counter ¬ addr

Affected flag(s)

None

CLR [m]

Clear Data Memory

Description

Operation

Each bit of the specified Data Memory is cleared to 0.

[m] ¬ 00H

Affected flag(s)

None

CLR [m].i

Clear bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is cleared to 0.

[m].i ¬ 0

Affected flag(s)

None

CLR WDT

Description

Operation

Clear Watchdog Timer

The TO, PDF flags and the WDT are all cleared.

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT1

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT2 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

CLR WDT2

Pre-clear Watchdog Timer

Description

The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc-

tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re-

petitively executing this instruction without alternately executing CLR WDT1 will have no

effect.

Operation

WDT cleared

TO ¬ 0

PDF ¬ 0

Affected flag(s)

TO, PDF

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CPL [m]

Complement Data Memory

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa.

Operation

[m] ¬ [m]

Affected flag(s)

Z

CPLA [m]

Complement Data Memory with result in ACC

Description

Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits

which previously contained a 1 are changed to 0 and vice versa. The complemented result

is stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m]

Affected flag(s)

Z

DAA [m]

Decimal-Adjust ACC for addition with result in Data Memory

Description

Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re-

sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or

if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble

remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of

6 will be added to the high nibble. Essentially, the decimal conversion is performed by add-

ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C

flag may be affected by this instruction which indicates that if the original BCD sum is

greater than 100, it allows multiple precision decimal addition.

Operation

[m] ¬ ACC + 00H or

[m] ¬ ACC + 06H or

[m] ¬ ACC + 60H or

[m] ¬ ACC + 66H

Affected flag(s)

C

DEC [m]

Decrement Data Memory

Description

Operation

Data in the specified Data Memory is decremented by 1.

[m] ¬ [m] - 1

Affected flag(s)

Z

DECA [m]

Decrement Data Memory with result in ACC

Description

Data in the specified Data Memory is decremented by 1. The result is stored in the Accu-

mulator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] - 1

Affected flag(s)

Z

HALT

Enter power down mode

Description

This instruction stops the program execution and turns off the system clock. The contents

of the Data Memory and registers are retained. The WDT and prescaler are cleared. The

power down flag PDF is set and the WDT time-out flag TO is cleared.

Operation

TO ¬ 0

PDF ¬ 1

Affected flag(s)

TO, PDF

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INC [m]

Increment Data Memory

Description

Operation

Data in the specified Data Memory is incremented by 1.

[m] ¬ [m] + 1

Affected flag(s)

Z

INCA [m]

Increment Data Memory with result in ACC

Description

Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu-

lator. The contents of the Data Memory remain unchanged.

Operation

ACC ¬ [m] + 1

Affected flag(s)

Z

JMP addr

Jump unconditionally

Description

The contents of the Program Counter are replaced with the specified address. Program

execution then continues from this new address. As this requires the insertion of a dummy

instruction while the new address is loaded, it is a two cycle instruction.

Operation

Program Counter ¬ addr

Affected flag(s)

None

MOV A,[m]

Description

Operation

Move Data Memory to ACC

The contents of the specified Data Memory are copied to the Accumulator.

ACC ¬ [m]

Affected flag(s)

None

MOV A,x

Move immediate data to ACC

Description

Operation

The immediate data specified is loaded into the Accumulator.

ACC ¬ x

Affected flag(s)

None

MOV [m],A

Description

Operation

Move ACC to Data Memory

The contents of the Accumulator are copied to the specified Data Memory.

[m] ¬ ACC

Affected flag(s)

None

NOP

No operation

Description

Operation

Affected flag(s)

No operation is performed. Execution continues with the next instruction.

No operation

None

OR A,[m]

Logical OR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper-

ation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² [m]

Affected flag(s)

Z

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OR A,x

Logical OR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical OR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²OR² x

Affected flag(s)

Z

ORM A,[m]

Logical OR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper-

ation. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²OR² [m]

Affected flag(s)

Z

RET

Return from subroutine

Description

The Program Counter is restored from the stack. Program execution continues at the re-

stored address.

Operation

Program Counter ¬ Stack

Affected flag(s)

None

RET A,x

Return from subroutine and load immediate data to ACC

Description

The Program Counter is restored from the stack and the Accumulator loaded with the

specified immediate data. Program execution continues at the restored address.

Operation

Program Counter ¬ Stack

ACC ¬ x

Affected flag(s)

None

RETI

Return from interrupt

Description

The Program Counter is restored from the stack and the interrupts are re-enabled by set-

ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending

when the RETI instruction is executed, the pending Interrupt routine will be processed be-

fore returning to the main program.

Operation

Program Counter ¬ Stack

EMI ¬ 1

Affected flag(s)

None

RL [m]

Rotate Data Memory left

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ [m].7

Affected flag(s)

None

RLA [m]

Rotate Data Memory left with result in ACC

Description

The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit

0. The rotated result is stored in the Accumulator and the contents of the Data Memory re-

main unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ [m].7

Affected flag(s)

None

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RLC [m]

Rotate Data Memory left through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7

replaces the Carry bit and the original carry flag is rotated into bit 0.

Operation

[m].(i+1) ¬ [m].i; (i = 0~6)

[m].0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RLCA [m]

Rotate Data Memory left through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces

the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in

the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.(i+1) ¬ [m].i; (i = 0~6)

ACC.0 ¬ C

C ¬ [m].7

Affected flag(s)

C

RR [m]

Rotate Data Memory right

Description

The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into

bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ [m].0

Affected flag(s)

None

RRA [m]

Rotate Data Memory right with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro-

tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data

Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ [m].0

Affected flag(s)

None

RRC [m]

Rotate Data Memory right through Carry

Description

The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0

replaces the Carry bit and the original carry flag is rotated into bit 7.

Operation

[m].i ¬ [m].(i+1); (i = 0~6)

[m].7 ¬ C

C ¬ [m].0

Affected flag(s)

C

RRCA [m]

Rotate Data Memory right through Carry with result in ACC

Description

Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re-

places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is

stored in the Accumulator and the contents of the Data Memory remain unchanged.

Operation

ACC.i ¬ [m].(i+1); (i = 0~6)

ACC.7 ¬ C

C ¬ [m].0

Affected flag(s)

C

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SBC A,[m]

Subtract Data Memory from ACC with Carry

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result

of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or

zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SBCM A,[m]

Subtract Data Memory from ACC with Carry and result in Data Memory

Description

The contents of the specified Data Memory and the complement of the carry flag are sub-

tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re-

sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is

positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m] - C

Affected flag(s)

OV, Z, AC, C

SDZ [m]

Skip if decrement Data Memory is 0

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0 the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] - 1

Skip if [m] = 0

Affected flag(s)

None

SDZA [m]

Skip if decrement Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first decremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0, the program proceeds with the following instruction.

Operation

ACC ¬ [m] - 1

Skip if ACC = 0

Affected flag(s)

None

SET [m]

Set Data Memory

Description

Operation

Each bit of the specified Data Memory is set to 1.

[m] ¬ FFH

Affected flag(s)

None

SET [m].i

Set bit of Data Memory

Description

Operation

Bit i of the specified Data Memory is set to 1.

[m].i ¬ 1

Affected flag(s)

None

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SIZ [m]

Skip if increment Data Memory is 0

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. As this requires the insertion of a dummy instruction while

the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program

proceeds with the following instruction.

Operation

[m] ¬ [m] + 1

Skip if [m] = 0

Affected flag(s)

None

SIZA [m]

Skip if increment Data Memory is zero with result in ACC

Description

The contents of the specified Data Memory are first incremented by 1. If the result is 0, the

following instruction is skipped. The result is stored in the Accumulator but the specified

Data Memory contents remain unchanged. As this requires the insertion of a dummy in-

struction while the next instruction is fetched, it is a two cycle instruction. If the result is not

0 the program proceeds with the following instruction.

Operation

ACC ¬ [m] + 1

Skip if ACC = 0

Affected flag(s)

None

SNZ [m].i

Skip if bit i of Data Memory is not 0

Description

If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is 0 the program proceeds with the following instruction.

Operation

Skip if [m].i ¹ 0

Affected flag(s)

None

SUB A,[m]

Subtract Data Memory from ACC

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

ACC ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUBM A,[m]

Subtract Data Memory from ACC with result in Data Memory

Description

The specified Data Memory is subtracted from the contents of the Accumulator. The result

is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will

be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.

Operation

[m] ¬ ACC - [m]

Affected flag(s)

OV, Z, AC, C

SUB A,x

Subtract immediate data from ACC

Description

The immediate data specified by the code is subtracted from the contents of the Accumu-

lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega-

tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will

be set to 1.

Operation

ACC ¬ ACC - x

Affected flag(s)

OV, Z, AC, C

Rev. 1.10

52

August 13, 2008

HT46R01A

SWAP [m]

Description

Operation

Swap nibbles of Data Memory

The low-order and high-order nibbles of the specified Data Memory are interchanged.

[m].3~[m].0 « [m].7 ~ [m].4

Affected flag(s)

None

SWAPA [m]

Swap nibbles of Data Memory with result in ACC

Description

The low-order and high-order nibbles of the specified Data Memory are interchanged. The

result is stored in the Accumulator. The contents of the Data Memory remain unchanged.

Operation

ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4

ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0

Affected flag(s)

None

SZ [m]

Skip if Data Memory is 0

Description

If the contents of the specified Data Memory is 0, the following instruction is skipped. As

this requires the insertion of a dummy instruction while the next instruction is fetched, it is a

two cycle instruction. If the result is not 0 the program proceeds with the following instruc-

tion.

Operation

Skip if [m] = 0

None

Affected flag(s)

SZA [m]

Skip if Data Memory is 0 with data movement to ACC

Description

The contents of the specified Data Memory are copied to the Accumulator. If the value is

zero, the following instruction is skipped. As this requires the insertion of a dummy instruc-

tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the

program proceeds with the following instruction.

Operation

ACC ¬ [m]

Skip if [m] = 0

Affected flag(s)

None

SZ [m].i

Skip if bit i of Data Memory is 0

Description

If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re-

quires the insertion of a dummy instruction while the next instruction is fetched, it is a two

cycle instruction. If the result is not 0, the program proceeds with the following instruction.

Operation

Skip if [m].i = 0

None

Affected flag(s)

TABRDC [m]

Read table (current page) to TBLH and Data Memory

Description

The low byte of the program code (current page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

TABRDL [m]

Read table (last page) to TBLH and Data Memory

Description

The low byte of the program code (last page) addressed by the table pointer (TBLP) is

moved to the specified Data Memory and the high byte moved to TBLH.

Operation

[m] ¬ program code (low byte)

TBLH ¬ program code (high byte)

Affected flag(s)

None

Rev. 1.10

53

August 13, 2008

HT46R01A

XOR A,[m]

Logical XOR Data Memory to ACC

Description

Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op-

eration. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XORM A,[m]

Logical XOR ACC to Data Memory

Description

Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op-

eration. The result is stored in the Data Memory.

Operation

[m] ¬ ACC ²XOR² [m]

Affected flag(s)

Z

XOR A,x

Logical XOR immediate data to ACC

Description

Data in the Accumulator and the specified immediate data perform a bitwise logical XOR

operation. The result is stored in the Accumulator.

Operation

ACC ¬ ACC ²XOR² x

Affected flag(s)

Z

Rev. 1.10

54

August 13, 2008

HT46R01A

Device Characteristic Graphics

The following characteristic graphics depicts typical device behavior. The data presented here is a statistical summary

of data gathered from different units. This is for information only and the figures were not tested during manufacturing.

In some of the graphs, the data exceeding the specified operating range are shown for information purposes only. The

device will operate properly only within the specified range.

Noramlized frequency is the ratio of actual frequency(F) to reference frequency(Fr) at V_DD=5V, Ta=25°C

4MHZ IRC Frequency vs. VDD

1

.

6

0

1

.

5

0

-

4

5

1

.

4

0

1

.

3

0

1

.

2

0

1

.

1

0

1

.

0

°

2 5 C

0

.

9

0

.

8

0

9

°

0 C

0

.

7

6

0

2

.

5

3

.

5

4

.

5

.

5

V

D

8MHZ IRC Frequency vs. VDD

1

.

6

0

1

.

5

0

-

4

5

1

.

4

0

1

.

3

0

1

.

2

0

1

.

1

0

1

.

0

°

2 5 C

0

.

9

0

.

8

0

9

°

0 C

0

.

7

6

0

2

.

5

3

.

5

4

.

5

.

5

V

D

Rev. 1.10

55

August 13, 2008

HT46R01A

12MHZ IRC Frequency vs. VDD

1

.

6

0

1

.

5

0

-

4

5

1

.

4

0

1

.

3

0

1

.

2

0

1

.

1

0

1

.

0

°

2 5 C

0

.

9

0

.

8

0

9

°

0 C

0

.

7

6

0

2

.

5

3

.

5

4

.

5

.

5

V

D

Rev. 1.10

56

August 13, 2008

HT46R01A

Package Information

10-pin MSOP Outline Dimensions

1

0

6

E

1

5

E

D

L

A

2

C

q

e

B

A

1

L

1

R

0

.

1

0

(

4

C

O

R

N

E

R

S

)

Dimensions in mm

Symbol

Min.

¾

Nom.

¾

Max.

1.1

0.15

0.95

0.27

0.25

¾

A

A1

A2

B

0

¾

0.75

0.17

¾

C

¾

D

3

¾

E

4.9

3

¾

E1

e

¾

0.5

¾

L

0.4

¾

0.8

¾

0.95

¾

L1

q

0°

8°

Rev. 1.10

57

August 13, 2008

HT46R01A

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan

Tel: 886-3-563-1999

Fax: 886-3-563-1189

http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan

Tel: 886-2-2655-7070

Fax: 886-2-2655-7373

Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103

Tel: 86-21-5422-4590

Fax: 86-21-5422-4705

http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057

Tel: 86-755-8616-9908, 86-755-8616-9308

Fax: 86-755-8616-9722

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031

Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752

Fax: 86-10-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016

Tel: 86-28-6653-6590

Fax: 86-28-6653-6591

Holtek Semiconductor (USA), Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538

Tel: 1-510-252-9880

Fax: 1-510-252-9885

http://www.holtek.com

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-

sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used

solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable

without further modification, nor recommends the use of its products for application that may present a risk to human life

due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices

or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,

please visit our web site at http://www.holtek.com.tw.

Rev. 1.10

58

August 13, 2008


型号：	HT46R01A3
厂家：	HOLT INTEGRATED CIRCUITS
描述：	RISC Microcontroller, 8-Bit, OTPROM, 12MHz, CMOS, PDSO10, ULTRA SMALL, MSOP-10 可编程只读存储器时钟微控制器光电二极管外围集成电路
文件：	总58页 (文件大小：442K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HT46R01A3 [HOLTIC]

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