HC6856XSFCC40 [HONEYWELL]
32K x 8 STATIC RAM; 32K x 8静态RAM
| 型号： | HC6856XSFCC40 |
| 厂家： | 
Honeywell |
| 描述： | 32K x 8 STATIC RAM |
| 文件： | 总12页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Military & Space Products
32K x 8 STATIC RAM
HC6856
FEATURES
RADIATION
OTHER
• Fabricated with RICMOS™ IV Bulk
• Listed on SMD #5962-92153. Available as
MIL-PRF-38535 QML Class Q and Class V
0.8 µm Process (Leff = 0.65 µm)
• Read/Write Cycle Times
• Total Dose Hardness through 1x106 rad(SiO2)
• Neutron Hardness through 1x1014 cm-2
≤ 30 ns (Typical)
≤ 40 ns (-55 to 125°C)
• Standby Current of 20 µA (typical)
• Asynchronous Operation
• Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
• Soft Error Rate of <1x10-10 upsets/bit-day
• Dose Rate Survivability through 1x1012 rad(Si)/s
• Latchup Free
• CMOS or TTL Compatible I/O
• Single 5 V 10% Power Supply
• Packaging Options
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
- 28-Lead Flat Pack (0.530 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 x 8-bit static random access memory
with industry-standard functionality. It is fabricated with
Honeywell’s radiation hardened technology, and is de-
signed for use in systems operating in radiation environ-
ments. The RAM operates over the full military temperature
range and requires only a single 5 V 10% power supply.
The RAM is available with either TTL or CMOS compatible
I/O. Power consumption is typically less than 50 mW/MHz
in operation, and less than 5 mW/MHz in the low power
disabled mode. The RAM read operation is fully asynchro-
nous, with an associated typical access time of 20 ns.
Honeywell’s enhanced RICMOS™ IV (Radiation Insensitive
CMOS)technologyisradiationhardenedthroughtheuseof
advancedandproprietarydesign,layout,andprocesshard-
ening techniques. The RICMOS™ IV process is a 5-volt,
twin-well CMOS technology with a 170 Å gate oxide and a
minimum drawn feature size of 0.8 µm (0.65 µm effective
gate length—Leff). Additional features include a three layer
interconnect metalization and a lightly doped drain (LDD)
structure for improved short channel reliability. High resis-
tivitycross-coupledpolysiliconresistorshavebeenincorpo-
rated for single event upset hardening.
HC6856
FUNCTIONAL DIAGRAM
•
•
•
32,768 x 8
Memory
Array
A:0-8,12-13
CE
Row
Decoder
11
•
•
•
8
Column Decoder
Data Input/Output
NCS
DQ:0-7
8
NWE
WE • CS • CE
1 = enabled
Signal
NWE • CS • CE • OE
(0 = high Z)
NOE
Signal
#
CS • CE
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
A:9-11,14
4
SIGNAL DEFINITIONS
A: 0-14
DQ: 0-7
Address input pins (A) which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level it forces
the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all
the input buffers. If this signal is not used it must be connected to VSS.
NWE
NOE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level it allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level it forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers.
If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE
NWE
NOE
MODE
DQ
L
L
H
H
X
L
H
L
L
Read
Write
Data Out
Data In
High Z
Notes:
X: VI=VIH or VIL
X
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
H
X
XX
XX
XX
XX
Deselected
Disabled
High Z
2
HC6856
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The RAM will meet any functional or electrical specification
after exposure to a radiation pulse of ≤ 50 ns duration up to
1x1012 rad(Si)/s, when applied under recommended oper-
atingconditions.Notethatthecurrentconductedduringthe
pulse by the RAM inputs, outputs, and power supply may
significantly exceed the normal operating levels. The appli-
cation design must accommodate these effects.
The RAM will meet all stated functional and electrical speci-
fications over the entire operating temperature range after
the specified total ionizing radiation dose. All electrical and
timing performance parameters will remain within specifica-
tions after rebound at VDD = 5.5 V and T =125°C extrapo-
lated to ten years of operation. Total dose hardness is
assured by wafer level testing of process monitor transistors
and RAM product using 10 keV X-ray radiation. Transistor
gate threshold shift correlations have been made between
10 keV X-rays applied at a dose rate of 1x105 rad(SiO2)/min
at T = 25°C and gamma rays (Cobalt 60 source) to ensure
that wafer level X-ray testing is consistent with standard
military radiation test environments.
Neutron Radiation
The RAM will meet any functional or timing specification
after a total neutron fluence of up to 1x1014 cm-2 applied
under recommended operating or storage conditions. This
assumes an equivalent neutron energy of 1 MeV.
Transient Pulse Ionizing Radiation
Soft Error Rate
The RAM is capable of writing, reading, and retaining
storeddataduringandafterexposuretoatransientionizing
radiationpulseof≤1µsdurationupto1x109 rad(Si)/s,when
applied under recommended operating conditions. To en-
sure validity of all specified performance parameters be-
fore, during, and after radiation (timing degradation during
transient pulse radiation is ≤10%), it is suggested that a
minimum of 0.8 µF per part of stiffening capacitance be
placed between the package (chip) VDD and VSS, with a
maximum inductance between the package (chip) and
stiffening capacitance of 0.7 nH per part. If there are no
operate-through or valid stored data requirements, the
capacitance specification can be reduced to a minimum of
0.1 µF per part.
The RAM is capable of soft error rate (SER) performance
of <1x10-10 upsets/bit-day, under recommended operating
conditions. This hardness level is defined by the Adams
10% worst case cosmic ray environment.
Latchup
The RAM will not latch up due to any of the above radiation
exposure conditions when applied under recommended
operating conditions. Fabrication with the RICMOS™ p-epi
on p+ substrate process and use of proven design tech-
niques, such as double guardbanding, ensure latchup
immunity.
RADIATION HARDNESS RATINGS (1)
Limits (2)
Units
Test Conditions
Parameter
Total Dose
≥1x106
≥1x109
≥1x1012
rad(SiO2)
rad(Si)/s
rad(Si)/s
TA=25°C
Pulse width≤1 µs
Transient Dose Rate Upset (3)
Transient Dose Rate Survivability
Soft Error Rate: Level A
Level Z
Pulse width≤50 ns, X-ray,
VDD=6.6 V, TA=25°C
<1x10-9 (4)
Adams 10%
worst case environment
upsets/bit-day
<1x10-10
1 MeV equivalent energy,
Unbiased, TA=25°C
Neutron Fluence
≥1x1014
N/cm2
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C.
(3) Suggested stiffening capacitance specifications for optimum expected dose rate upset performance is stated above in the text.
(4) SER <1x10-10 u/b-d from -55 to 80°C.
3
HC6856
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Symbol
Parameter
Units
Min
-0.5
-0.5
-65
Max
7.0
VDD
Positive Supply Voltage (2)
Voltage on Any Pin (2)
V
V
VPIN
VDD+0.5
150
TSTORE
TSOLDER
PD
Storage Temperature (Zero Bias)
Soldering Temperature • Time
Total Package Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case) 28 FP/36 FP
28 DIP
°C
270•5
2.5
°C•s
W
IOUT
25
mA
V
VPROT
ΘJC
2000
2
°C/W
°C/W
°C
10
TJ
Junction Temperature
175
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Parameter
Symbol
Units
Typ
5.0
25
Max
5.5
Min
4.5
VDD
TA
Supply Voltage (referenced to VSS)
Ambient Temperature
V
°C
V
-55
-0.3
125
VPIN
Voltage on Any Pin (referenced to VSS)
VDD+0.3
CAPACITANCE (1)
Worst Case
Symbol
Parameter
Test Conditions
Typical
Units
Max
6
CI
Input Capacitance
Output Capacitance
4
pF
pF
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
CO
6.5
8
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Worst Case
Typical
(1)
Symbol
Parameter (2)
Units
Test Conditions
Max
Min
NCS=VDR
VDR
IDR
Data Retention Voltage (3)
2.0
2.5
V
VI=VDR or VSS
NCS=VDD=VDR
VI=VDR or VSS
Data Retention Current
150
400
µA
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.
(3) To maintain valid data storage during transient radiation, VDD must be held within the recommended operating range.
4
HC6856
DC ELECTRICAL CHARACTERISTICS
Typical Worst Case (2)
Symbol
Parameter
Units
Test Conditions (3)
(1)
0.02
0.02
5.5
Min
Max
VIH=VDD IO=0
VIL=VSS Inputs Stable
IDDSB1
IDDSB2
Static Supply Current
1.2
mA
mA
mA
mA
µA
CE=VSS or NCS=VDD
IO=0, VSS≤ VI≤VDD (4)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (5)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (5)
Static Supply Current with Chip Disabled
1.2
7.5
6.5
+5
IDDOPW Dynamic Supply Current, Selected (Write)
IDDOPR
II
Dynamic Supply Current, Selected (Read)
Input Leakage Current
4.5
VSS≤VI≤VDD
0.05
0.1
-5
VSS≤VIO≤VDD
IOZ
Output Leakage Current
-10
10
µA
Output=high Z
VIL
Low-Level InputVoltage
High-Level Input Voltage
CMOS
TTL
1.9
1.3
0.3xVDD
V
V
VDD=4.5V
VDD=4.5V
0.8
VIH
CMOS
TTL
3.0 0.7xVDD
1.7
V
V
VDD=5.5V
VDD=5.5V
2.2
0.2
0.4
0.05
V
V
VDD=4.5V, IOL=10 mA
VOL
VOH
Low-Level Output Voltage
High-Level Output Voltage
VDD=4.5V, IOL=200 µA
4.8
4.2
VDD-0.05
V
V
VDD=4.5V, IOH=-5 mA
VDD=4.5V, IOH=-200 µA
(1) Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55°C to +125°C, post total dose at 25°C.
(3) Input high = VIH ≥ VDD-0.3V, input low =VIL ≤ 0.3V
(4) Guaranteed but not tested.
(5) All inputs switching. DC average current.
2.9 V
Valid high
output
+
-
Vref1
Vref2
249Ω
+
-
Valid low
output
DUT
output
C >50 pF*
L
*C = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
L
Tester Equivalent Load Circuit
5
HC6856
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical
(2)
-55 to 125°C
Units
Min
Max
TAVAVR Address Read Cycle Time
18
18
15
20
20
6
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TEHQV
TEHQX
TELQZ
TGLQV
TGLQX
TGHQZ
Address Access Time
40
40
Address Change to Output Invalid Time
Chip Select Access Time
5
Chip Select Output Enable Time
Chip Select Output Disable Time
Chip Enable Access Time
16
10
40
20
20
6
Chip Enable Output Enable Time
Chip Enable Output Disable Time
Output Enable Access Time
16
0
10
10
4
Output Enable Output Enable Time
Output Enable Output Disable Time
3
4
10
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent capacitive
output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, post total dose at 25°C.
T
AVAVR
ADDRESS
NCS
T
AVQV
TAXQX
T
SLQV
T
SLQX
TSHQZ
HIGH
IMPEDANCE
DATA OUT
DATA VALID
T
EHQX
EHQV
T
TELQZ
CE
T
GLQX
GLQV
T
TGHQZ
NOE
(NWE = high)
6
HC6856
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Typical (2) SER <1E-9 (4) SER <1E-10
Symbol
Parameter
Min
Max
Min
Max
Units
TAVAVW Write Cycle Time (5)
30
25
25
20
25
0
40
35
35
30
35
0
60
55
55
50
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TWLWH Write Enable Write Pulse Width
TSLWH
TDVWH
TAVWH
TWHDX
TAVWL
TWHAX
TWLQZ
Chip Select to End of Write Time
Data Valid to End of Write Time
Address Valid to End of Write Time
Data Hold Time after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Write Enable to Output Disable Time
0
0
0
0
0
0
5
0
10
0
10
TWHQX Write Disable to Output Enable Time
15
4
5
5
TWHWL Write Disable to Write Enable Pulse Width
5
5
TEHWH
Chip Enable to End of Write Time
25
35
55
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading0 pF, or equivalent capacitive
load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4) SER ≤1E-10 u/b-d from -55 to 80°.
(5) TAVAVW= TWLWH + TWHWL
TAVAVW
ADDRESS
TAVWH
TWHAX
TAVWL
TWHWL
TWLWH
NWE
TWLQZ
TWHQX
TWHDX
DATA OUT
DATA IN
HIGH
IMPEDANCE
TDVWH
DATA VALID
TSLWH
NCS
CE
TEHWH
7
HC6856
DYNAMIC ELECTRICAL CHARACTERISTICS
Write Cycle
Read Cycle
The RAM is asynchronous in operation, allowing the read
cycletobecontrolledbyaddress,chipselect(NCS),orchip
enable (CE) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and chip enable and write
enable (NWE) must be high. The output drivers can be
controlled independently by the NOE signal. Consecutive
read cycles can be executed with NCS held continuously
low, and with CE held continuously high.
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To per-
form a write operation, both NWE and NCS must be low,
and CE must be high. Consecutive write cycles can be
performed with NWE or NCS held continuously low, or CE
held continuously high. At least one of the control signals
must transition to the opposite state between consecutive
write operations.
For an address activated read cycle, NCS and CE must be
valid prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between
address edge transitions is permissible; however, data
outputs will become valid TAVQV time following the latest
occurring address edge transition. The minimum address
activated read cycle time is TAVAV. When the RAM is
operated at the minimum address activated read cycle
time, the data outputs will remain valid on the RAM I/O until
TAXQX time following the next sequential address transi-
tion.
The write mode can be controlled via three different control
signals: NWE, NCS, and CE. All three modes of control are
similar except the NCS and CE controlled modes actually
disable the RAM during the write recovery pulse. Only the
NWE controlled mode is shown in the table and diagram on
the previous page for simplicity; however, each mode of
control provides the same write cycle timing characteris-
tics. Thus, someoftheparameternamesreferencedbelow
are not shown in the write cycle table or diagram, but
indicate which control pin is in control as it switches high or
low.
To control a read cycle with NCS, all addresses and CE
must be valid prior to or coincident with the enabling NCS
edge transition. Address or CE edge transitions can occur
later than the specified setup times to NCS; however, the
valid data access time will be delayed. Any address edge
transition, which occurs during the time when NCS is low,
will initiate a new read access, and data outputs will not
becomevaliduntilTAVQVtimefollowingtheaddressedge
transition. Data outputs will enter a high impedance state
TSHQZ time following a disabling NCS edge transition.
TowritedataintotheRAM,NWEandNCSmustbeheldlow
and CE must be held high for at least TWLWH/TSLSH/
TEHEL time. Any amount of edge skew between the
signals can be tolerated, and any one of the control signals
can initiate or terminate the write operation. For consecu-
tivewriteoperations, writepulsesmustbeseparatedbythe
minimumspecifiedTWHWL/TSHSL/TELEHtime.Address
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
must remain valid during the entire write time. A valid data
overlapofwritepulsewidthtimeofTDVWH/TDVSH/TDVEL,
and an address valid to end of write time of TAVWH/
TAVSH/TAVEL also must be provided for during the write
operation. Hold times for address inputs and data inputs
with respect to the disabling NWE/NCS/CE edge transition
must be a minimum of TWHAX/TSHAX/TELAX time and
TWHDX/TSHDX/TELDX time, respectively. The minimum
write cycle time is TAVAV.
To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edge transition. Address or NCS edge transitions can
occur later than the specified setup times to CE; however,
the valid data access time will be delayed. Any address
edge transition which occurs during the time when CE is
high will initiate a new read access, and data outputs will
not become valid until TAVQV time following the address
edge transition. Data outputs will enter a high impedance
state TELQZ time following a disabling CE edge transition.
8
HC6856
TESTER AC TIMING CHARACTERISTICS
TTL I/O Configuration
CMOS I/O Configuration
3 V
0 V
VDD-0.5 V
Input
Levels*
1.5 V
VDD/2
0.5 V
1.5 V
VDD/2
Output
Sense
Levels
VDD-0.4V
0.4 V
VDD-0.4V
High Z
High Z
0.4 V
3.4 V
2.4 V
3.4 V
2.4 V
High Z
High Z
High Z = 2.9V
High Z = 2.9V
* Input rise and fall times <1 ns/V
QUALITY AND RADIATION HARDNESS
ASSURANCE
QML devices offer ease of procurement by eliminating the
need to create detailed specifications and offer benefits of
improved quality and cost savings through standardization.
Honeywellmaintainsahighlevelofproductintegritythrough
process control, utilizing statistical process control, a com-
plete “Total Quality Assurance System,” a computer data
base process performance tracking system, and a radia-
tion hardness assurance strategy.
RELIABILITY
Honeywell understands the stringent reliability require-
ments that space and defense systems require and has
extensive experience in reliability testing on programs of
this nature. This experience is derived from comprehen-
sive testing of VLSI processes. Reliability attributes of the
RICMOS™ process were characterized by testing specially
designed irradiated and non-irradiated test structures from
which specific failure mechanisms were evaluated. These
specific mechanisms included, but were not limited to, hot
carriers, electromigration and time dependent dielectric
breakdown. This data was then used to make changes to
the design models and process to ensure more reliable
products.
The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiationhardnessisassuredoneverywaferbyirradiating
test structures as well as SRAM product, and then monitor-
ing key parameters which are sensitive to ionizing radia-
tion. ConventionalMIL-STD-883TM5005GroupEtesting,
which includes total dose exposure with Cobalt 60, may
alsobeperformedasrequired. ThisTotalQualityapproach
ensures our customers of a reliable product by engineering
in reliability, starting with process development and con-
tinuing through product qualification and screening.
SCREENING LEVELS
In addition, the reliability of the RICMOS™ process and
product in a military environment was monitored by testing
irradiated and non-irradiated circuits in accelerated dy-
namic life test conditions. Packages are qualified for prod-
uct use after undergoing Groups B & D testing as outlined
in MIL-STD-883, TM 5005, Class S. The product is quali-
fied by following a screening and testing flow to meet the
customer’s requirements. Quality conformance testing is
performed as an option on all production lots to ensure the
ongoing reliability of the product.
Honeywell offers several levels of device screening to meet
your system needs. “Engineering Devices” are available
with limited performance and screening for breadboarding
and/or evaluation testing. Hi-Rel Level B and S devices
undergo additional screening per the requirements of MIL-
STD-883. As a QML supplier, Honeywell also offers QML
Class Q and V devices per MIL-PRF-38535 and are avail-
able per the applicable Standard Military Drawing (SMD).
9
HC6856
PACKAGING
insertion. Ceramic chip capacitors can be mounted to the
package by the user to maximize supply noise decoupling
and increase board packing density. These capacitors
attach directly to the internal package power and ground
planes. This design minimizes resistance and inductance
of the bond wire and package, both of which are critical in
a transient radiation environment. All NC (no connect) pins
must be connected to either VDD, VSS or an active driver
to prevent charge build up in the radiation environment.
The 32K x 8 SRAM is offered in a custom 36-lead flat pack
(FP), 28-Lead FP, or standard 28-lead DIP. Each package
is constructed of multilayer ceramic (Al2O3) and features
internal power and ground planes. The 36-lead FP also
features a non-conductive ceramic tie bar on the lead
frame.Thepurposeofthetiebaristoallowelectricaltesting
of the device, while preserving the lead integrity during
shipping and handling, up to the point of lead forming and
28-LEAD DIP & FP PINOUT
36-LEAD FLAT PACK PINOUT
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
NWE
A13
A8
VSS
VDD
A14
A12
A7
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VSS
VDD
NWE
CE
2
2
3
3
4
4
5
A13
A8
A6
6
5
A9
A5
7
A9
6
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
A4
8
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
Top
View
Top
View
A3
9
7
A2
10
11
12
13
14
15
16
17
18
8
A1
A0
9
DQ0
DQ1
DQ2
NC
A0
10
11
12
13
14
DQ0
DQ1
DQ2
VSS
VDD
VSS
36-LEAD FLAT PACK (22017194-001)
E
1
b
Top
(width)
Side
e
(pitch)
H
L
L
Non-
Conductive
Tie-Bar
Ceramic
Body
Optional
Standoff
Kovar
Lid [3]
A
J
0.004
C
M
S
N
I
X
Optional
Capacitors
All dimensions are in inches [1]
VDD
VSS
VSS
VDD
A
b
C
D
E
e
F
G
H
I
0.095 ± 0.010
0.008 ± 0.002
0.005 to 0.0075
0.650 ± 0.010
0.630 ± 0.007
0.025 ± 0.002 [2]
0.425 ± 0.005 [2]
0.525 ± 0.005
0.135 ± 0.005
0.030 ± 0.005
0.080 typ.
M
N
O
P
R
S
T
U
V
W
X
Y
0.008 ± 0.003
0.050 ± 0.010
0.090 ref
0.015 ref
0.075 ref
0.113 ± 0.010
0.050 ref
0.030 ref
0.080 ref
0.005 ref
Y
J
L
0.450 ref
0.400 ref
0.285 ± 0.015
1
[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS
1
O
T
V
W
P
U
R
10
HC6856
28-LEAD FLAT PACK (22017362-001)
Optional capacitors
in cutout
All dimensions in inches
VDD
VSS
VDD
E
A
b
C
D
e
0.135 ± 0.015
1
1
0.015 ± 0.002
0.004 to 0.009
0.720 ± 0.008
0.050 ± 0.005 [1]
0.530 ± 0.008
b
(width)
E
TOP
VIEW
BOTTOM
VIEW
E2 0.420 ± 0.008
E3 0.055 ref
F
G
L
Q
S
U
V
W
X
Y
Z
e
(pitch)
0.650 ± 0.005 [2]
0.050 ± 0.005
0.295 min [3]
0.026 to 0.045
0.035 ± 0.010
0.065 ref
0.300 ref
0.050 ref
0.030 ref
0.100 ref
S
Z
U
L
Y
X
W
V
Kovar
Lid [4]
Cutout Ceramic
Area Body
A
Lead
Alloy 42
C
Q
G
0.080 ref
[1] BSC - Basic lead spacing between centers
[2] Where lead is brazed to package
[3] Parts delivered with leads unformed
[4] Lid connected to VSS
E2
E3
28-LEAD DIP (22017502-001)
For 28-Lead DIP description, see MIL-STD-1835, Type CDIP2-T28, Config. C, Dimensions D-10
DYNAMIC BURN-IN DIAGRAM
STATIC BURN-IN DIAGRAM
VDD
VDD
1
2
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
VSS
VSS
VDD
A14
A12
A7
VSS
VDD
NWE*
CE*
VSS
VSS
VDD
NWE*
CE*
VSS
VDD
A14
A12
A7
3
3
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
F0
F16
R
R
4
4
F17
F7
F6
5
5
A13*
A8
F15
F12
F11
F10
F17
F9
R
R
R
R
R
A13*
A8
6
6
A6
F5
A6
7
7
A5
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
F4
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
A5
8
8
A4
F3
A4
9
9
A3
F2
A3
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
A2
F8
R
R
A2
R
R
F17
F1
R
R
A1
F13
F14
F1
A1
A0
R
R
R
R
R
R
R
R
A0
R
R
R
R
DQO
DQ1
DQ2
F1
DQO
DQ1
DQ2
F1
F1
R
R
R
F1
F1
R
F1
NC
NC
VDD
VSS
VDD
VSS
VSS
VSS
VDD = 6.5V, R ≤ 10 KΩ, VIH = VDD, VIL = VSS
Ambient Temperature ≥ 125 °C, F0 ≥ 100 KHz Sq Wave
Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
VDD = 5.5V, R ≤ 10 KΩ
Ambient Temperature ≥ 125 °C
NOTE — *Denotes package pinout option dependent (28-Lead DIP/FP diagrams not shown but have similar connections)
11
HC6856
ORDERING INFORMATION (1)
40
H
Q
H
6856/1
X
Z
C
C
PART NUMBER
Pinout options (2)
SCREEN LEVEL (1)
V=QML Class V
Q=QML Class Q
S=Level S
B=Level B
E=Engr Device (4)
SOFT ERROR
RATE
SPEED (5)
60 ns
Z=<1x10-10 upsets/bit-day
PROCESS
C=CMOS
A=<1x10-9 upsets/bit-day (3)
C=<1x10-7 upsets/bit-day
- =No SER Guaranteed
40 ns
35 ns
SOURCE
H=HONEYWELL
PACKAGE DESIGNATION
W=36-Lead FP
X=36-Lead FP, with standoff
Y=36-Lead FP, with standoff & caps
N=28-Lead FP
TOTAL DOSE
HARDNESS
INPUT BUFFER TYPE
C=CMOS Level
T=TTL Level
R=1x105rad(SiO2)
F=3x105 rad(SiO2)
H=1x106 rad(SiO2)
N=No Level Guaranteed
R=28-Lead DIP
- = Bare Die (No Package)
(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information.
(2) Pinout options:
36-Lead FP
28-Lead FP & DIP
pin 32 pin 33
pin 34
HC6856/1
HC6856/2
A13
CE
CE
NWE
A13
JEDEC Pinout
N/A
NWE
(3) SER <1E-10 u/b-d from -55 to 80°C.
(4) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.
(5) Only specified for Engineering Devices. Number defines worst case maximum Write Cycle time in nano-seconds (ns).
Contact Factory with other needs.
To lea r n m or e a bou t Hon eyw ell Solid Sta te Electr on ics Cen ter ,
visit ou r w eb site a t h ttp ://w w w .ssec.h on eyw ell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
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