HRT0100AVN [HONEYWELL]
Standard SRAM;
| 型号： | HRT0100AVN |
| 厂家： | 
Honeywell |
| 描述： | Standard SRAM 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：1364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HRT6408
HRT6408 512k x 8 Static RAM
Radiation Tolerant
Features
■
Fabricated on S150 Silicon On
Insulator (SOI) CMOS
■
■
150 nm Process (Leff = 110 nm)
Read/Write Cycle Times
Typical Write = 7 ns
Typical Read = 12ns
■
■
■
■
Asynchronous Operation
CMOS Compatible I/O
5
Total Dose ≥3X10 rad(Si)
Soft Error Rate
-12
Heavy Ion ≤1x10
-12
Proton ≤ 2x10
Upsets/bit-day
■
■
■
■
Upsets/bit-day
14
2
Neutron ≥1x10 N/cm
No Latchup
Core Operating Voltage
1.8 V ± 0.15 V
■
I/O Voltages
3.3 V ± 0.3 V
2.5 V ± 0.2 V
■
■
Operating Range is
-55°C to +125°C
36-Lead Flat Pack Package
The monolithic 512k x 8 Radiation Tolerant Static RAM is a high performance
524,288 word x 8-bit static random access memory, fabricated with Honeywell’s
150nm silicon-on-insulator CMOS (S150) technology.
It is designed for use in low voltage
systems operating in radiation sensitive
environments. The RAM operates over
the full military temperature range and
can operate on power supplies of 1.8V,
2.5V or 3.3V. The SRAM supports I/O
voltages of 3.3V and 2.5V.
process hardening techniques. There
is no internal EDAC implemented.
It is a low power process with a minimum
drawn feature size of 150 nm. This
delivers high speed with typical READ
access time of 12ns, WRITE time of 7ns
and a low power consumption of 35
mW at 40 MHz. A seven transistor (7T)
memory cell is used for superior single
event upset hardening.
Honeywell’s S150 technology is radiation
hardened through the use of advanced
and proprietary design, layout and
Block Diagram
A(0-8)
Row
Drive
524,288 x 8
Memory Array
A(9-18)
NWE
Column
Decoder
NOE
NCS
Voltage
Regulator
NVREN
D(0-7)
VDD2
VDD
Signal Description
Signal
A(0-18)
D(0 – 7)
NCS
Definition
Address input pins (A) which select a particular eight bit word within the memory array.
Bi-directional data pins which serve as data outputs during a read operation and as data inputs during a write operation.
Negative chip select, when at a low level, allows normal read or write operation. When at a high level it defaults the SRAM to a pre-charge
condition and holds the data output drivers in a high impedance state. If the NCS signal is not used, it must be connected to VSS.
Negative write enable, when at a low level, activates a write operation and holds the data output drivers in a high impedance state. When at
a high level, it allows normal read operation.
NWE
NOE
Negative output enable, when at a high level, holds the data output drivers in a high impedance state. When at a low level, the data output
driver state is defined by NCS and NWE. If the NOE signal is not used, it must be connected to VSS
.
NVREN
Negative voltage regulator enable, when at a high level, the SRAM operates directly from the 1.8V supply on the VDD pin. The regulator is off.
When at a low level the voltage regulator is enabled and is powered by the VDD2 source. The VDD pin should be a no connect. NVREN has
an internal pull-down.
VDD
Power Input, supply power for SRAM core when supplying 1.8V direct.
VDD2
Power Input, supply power for I/O and SRAM core.
36 Lead Flat Pack Pinout
A0
A1
1
2
3
4
5
6
7
8
9
36 NVREN
35 A18
34 A17
33 A16
32 A15
31 NOE
30 D4
A2
A3
A4
NCS
D0
D1
29 D5
VDD2
28 VSS
27 VDD2
26 D6
HRT6408
VSS 10
D2 11
D3 12
NWE 13
A5 14
A6 15
A7 16
A8 17
A9 18
Top View
25 D7
24 A14
23 A13
22 A12
21 A11
20 A10
19 VDD
Truth Table
NCS
NVREN
NWE
NOE
Mode
DQ
L
L
L
L
H
L
L
X
X
L
X
X
Regulator, Read
Regulator, Write
Data Out
Data In
High Z
H
L
L
X
H
L
Regulator, Deselected
No regulator, Read
H
H
H
Data Out
Data In
High Z
L
No regulator, Write
H
X
No regulator, Deselected
X: VI = VIH or VIL,
NOE=H: High Z output state maintained for NCS=X, NWE=X
Absolute Maximum Ratings (1)
Ratings
Max
Symbol
VDD2
VDD
Parameter
Min
Units
Volts
Volts
Volts
mA
Positive Supply Voltage (I/O) (2)
Positive Supply Voltage (core) (2)
Voltage on Any Pin (2) (3)
Average Output Current
Storage Temperature
-0.5
-0.5
-0.5
4.4
2.4
VPIN
VDD2+ 0.5
15
IOUT
o
TSTORE
TSOLDER
PD
-65
150
C
o
Soldering Temperature
Package Power Dissipation (4)
270
C (6)
2.5
W
o
PJC
Package Thermal Resistance (Junction to Case)
Electrostatic Discharge Protection Voltage (5)
Junction Temperature
2.0
C /W
V
VPROT
TJ
2000
o
150
C
(1) Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only, and operation at these levels is not implied.
Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS
(3) Pin 19 (VDD) is required to have no connection when NVREN is low or left undriven (internal pull-down)
(4) RAM power dissipation (IDDS + IDDOP), plus RAM output driver power dissipation due to external loading must
not exceed this specification
(5) Class 2 electrostatic discharge (ESD) input protection voltage per MIL-STD-883, Method 3015
(6) Maximum soldering temp of 270°C can be maintained for no more than 5 seconds.
Recommended Operating Conditions (1)
Limits
Typical
Symbol
Parameter
Min
3.0
Max
3.6
Units
VDD2
Positive Supply Voltage (I/O)
3.3
2.5
1.80
25
Volts
2.3
2.7
VDD
Positive Supply Voltage (2) (core)
External Package Temperature
Voltage On Any Pin (3)
1.65
-55
-0.3
1.95
Volts
o
TC
125
C
VPIN
VDD2+0.3
1
Volts
µs
VDD2/ VDD Ramp Time
TREG
Supply Voltages Ramp Rate
Regulator Settling Time (4)
100
(1) Voltages referenced to VSS
(2) The VDD supply is generated internally by the voltage regulator when NVREN=low or can be driven externally in the range shown in this table.
(3) Pin 19 (VDD) is required to have no connection when NVREN is low or left undriven (internal pull-down).
(4) The internal voltage regulator has a 100µs start up settling time following VDD2 power up.
Power Supply Functional Configurations
Power Source
The SRAM can be powered by two methods. The power can
be supplied directly through the VDD pin at 1.8V or the on-chip
voltage regulator can be used. If the user selects to operate with
a 2.5V or 3.3V power supply only, the regulator will use the VDD2
power supply to generate the 1.8V.
Two external capacitors are mounted on the package for
additional power supply energy storage and support the
need for high speed supply current demands.
Power Supply Regulator
The voltage regulator is not intended to power other devices in
addition to the SRAM. The SRAM is qualified to operate in either
voltage regulator enabled or voltage regulator disabled mode but
not switch between modes through the life of the part.
The internal regulator has a start up settling time of 100us.
C = 0µF ± 10%
The user selects the method to provide power to the SRAM. The
mode of operation is controlled by the NVREN signal.
VDD2 Power Source (2.5V or 3.3V)
NVREN = 0 (Low)
VDD Power Source (1.8V)
NVREN = 1 (high)
VDD = 1.8V
VDD = No Connect
Regulator: On
Regulator: Off
When the NVREN is low, the SRAM will be powered by VDD2. The
VDD pin (pin 19) should be left open (no connect) and the power
for the chip is supplied by VDD2 (pins 9 and 27). When this mode is
used, the part is a pin for pin replacement for the HX6408 SRAM.
When the NVREN is a high, 1.8V must be supplied to the VDD pin
(Pin 19). VDD2 (pin 9 and 27) is still required for the I/O and may be
3.3V or 2.5V.
A(0-8)
A(0-8)
524,288 x 8
Memory Array
524,288 x 8
Memory Array
Row
Drive
Row
Drive
A(9-18)
NWE
NOE
A(9-18)
NWE
NOE
Column
Decoder
Column
Decoder
NCS
NCS
Voltage
Regulator
Voltage
Regulator
NVREN
NVREN
D(0-7)
D(0-7)
(Low)
(High)
VDD2
VDD
VDD2
VDD
(No Connect)
(1.8V)
Radiation-Hardness Ratings (1)
Parameter
Total Dose:
F-Level
Limits
Units
Rads(Si)
Test Conditions
= 25°C, VDD2 = 3.6 Volts,
T
A
> 3 x 105
Rads(Si) Co60
Upsets/bit-day
N/cm2
VDD = 1.95 Volts
Soft Error Rate:
Heavy Ion
VDD2 = 3.0 Volts, VDD = 1.95 Volts
< 1 x 10-12
< 2 x 10-12
≥ 1 x 1012
Proton
TC = -55 to 125°C
Neutron Fluence
1 MeV equivalent energy, Unbiased, TA = 25°C
(1) Device will not latch up due to any of the specified radiation exposure conditions.
Radiation
Soft Error Rate
Total Ionizing Dose Radiation
The SRAM is capable of meeting the specified Soft Error Rate
(SER), under recommended operating conditions. This hardness
level is defined by the Adams 90% worst case cosmic ray
environment for geosynchronous orbits.
The SRAM will meet all stated functional and electrical
specifications after the specified total ionizing radiation dose.
All electrical and timing performance parameters will remain within
specifications, post rebound (based on extrapolation), after an
operational period of 15 years. Total dose hardness is assured
by wafer level testing of process monitor transistors and RAM
product using 10 KeV X-ray. Parameter correlations have been
made between 10 KeV X-rays applied at dose rates of 1x105 to
Latchup
The SRAM will not latch up due to any of the above radiation
exposure conditions when applied under recommended operating
conditions. Fabrication with the SOI substrate material provides
oxide isolation between adjacent PMOS and NMOS transistors
and eliminates any potential SCR latchup structures. Sufficient
transistor body tie connections to the p- and n-channel substrates
are made to ensure no source/drain snapback occurs.
5x105 rad(SiO )/min at T= 25°C and gamma rays (Cobalt 60
2
source) to ensure that wafer level X-ray testing is consistent
with standard military radiation test environments.
Neutron Radiation
The SRAM will meet any functional or timing specification after
exposure to the specified neutron fluence under recommended
operating or storage conditions. This assumes an equivalent
neutron energy of 1 MeV.
DC Electrical Characteristics (1)
Min
Max
Symbol
Parameter
VDD
VDD2
Units
Test Conditions
VREG disabled VREG enabled VREG disabled VREG enabled
IDDSB (4)
Static Supply Current
TA = 25°C
2 (5)
12
NA
NA
0.2
0.2
2.5 (5)
12
mA
mA
VDD=max, Iout=0mA,
Inputs Stable
TA = 125°C
IDDOPW
IDDOPR
IDR
Dynamic Supply
Current, Selected
(Write)
1 MHz
2 MHz
1.25
2.5
10
NA
NA
NA
NA
NA
NA
0.15
0.3
1.5
3.8
6.0
7.5
1.25
2.5
10
mA
mA
mA
mA
mA
mA
VDD2 and VDD=max,
NCS=VIL (1) (2) (3)
10 MHz
25 MHz
40 MHz
50 MHz
25
25
40
40
50
50
Dynamic Supply
Current, Selected
(Read)
1 MHz
2 MHz
0.75
1.5
6
NA
NA
NA
NA
NA
NA
0.13
0.25
1.25
3.2
0.75
1.5
6
mA
mA
mA
mA
mA
mA
mA
VDD2 and VDD=max
NCS=VIL (1) (3)
10 MHz
25 MHz
40 MHz
50 MHz
15
15
24
30
5.0
24
30
6.25
Data Retention Current
TA = 25°C (6)
VDD=1V, VDD2=2V
1
NA
1
1
NA
TA = 125°C
10
Symbol
II
Parameter
Min
Max
Units
Test Conditions
Input Leakage Current
-5
5
10
µA
µA
V
IOZ
Output Leakage Current
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
-10
Output = high Z
VIL
0.3xVDD2
VDD2=3.0V or 2.5V
VDD2=3.6V or 2.4V
VDD2=3.0V, IOL = 10mA
VDD2=3.0V, IOH = 5mA
VIH
0.7xVDD2
2.7
V
VOL
VOH
0.4
V
V
(1) Worst case operating conditions: VDD2=2.3V to 3.6V, VDD=1.65V to 1.95V, -55°C to +125°C. Post-radiation performance guaranteed at 25°C per MIL-STD-883 method 1019 up to
300KRad(Si) total dose.
(2) All inputs switching. DC average current.
(3) All dynamic operating mode current measurements (IDDOPx) exclude standby mode current (IDDSB)
(4) See graph below for typical static current values.
(5) For applications with maximum dose rates <1 Rad(Si)/s this value applies post total dose.
(6) This is an estimated maximum for reference and is not a pass/fail criteria.
i/O Capacitance (1)
Symbol
CA
Parameter
Max
5
Units
pF
Test Conditions
Address Input Capacitance (2)
NCS, NOE, NWE Input Capacitance (2)
Data I/O Capacitance (2)
VIN = VDD2 or VSS, F = 1MHz
VIN = VDD2 or VSS, F = 1MHz
VIN = VDD2 or VSS, F = 1MHz
CC
15
7
pF
CD
pF
(1) This parameter is evaluated as part of initial qualification only.
(2) Bare die input pads are 2.5pf and data I/O pads are 3.5pf. NCS, NOE, NWE each have two pads.
Typical IDD Standby Current
10
9
8
7
6
5
4
3
2
1
0
0
20
40
60
80
100
120
140
Temperature (Degrees C)
Read Cycle AC Timing Characteristics (1)(2)
Vdd2 = 3.3V / 2.5V
Symbol
TAVAVR
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TGLQV
TGLQX
TGLQZ
Parameter
Min
Max
Units
ns
Read Cycle Time (4)
15 / 16.5
Address Access Time (4)
15 / 16.5
15 / 16.5
ns
Address Change to Output Invalid Time (3)
Chip Select Access Time (4)
Chip Select Output Enable Time (3)
Chip Select Output Disable Time (3)
Output Enable Access Time (4)
Output Enable Output Enable Time (3)
Output Enable Output Disable Time (3)
5
0
ns
ns
ns
2
ns
4/5
ns
0.5
ns
3
ns
(1) Test conditions: VIL/VIH=0V/Vdd. Reference Tester Equivalent Load Circuit and Tester AC Timing Characteristics diagrams. Capacitive output loading CL=5 pF for TSHQZ and TGHQZ.
(2) Worst case operating conditions: VDD2=3.0V to 3.6V, TA=-55°C to 125°C, post total dose at 25°C.
(3) These parameters are tested as pass/fail.
(4) Values shown for 3.3V and 2.5V VDD2, respectively.
Read Cycle AC Timing
TAVAVR
ADDRESS
TAVQV
TSLQV
TAXQX
NCS
TSHQZ
TGHQZ
TSLQX
HIGH
DATA OUT
DATA VALID
IMPEDANCE
TGLQX
TGLQV
NOE
NWE = HIGH
Write Cycle AC Timing Characteristics (1)
Vdd2 = 3.3V / 2.5V
Min
Symbol
TAVAVW
TWLWH
TSLWH
TDVWH
TAVWH
TWHDX
TAVWL
Parameter
Max
Units
ns
Write Cycle Time (2)
10
6
Write Enable Write Pulse Width
ns
Chip Select to End of Write Time
Data Valid to End of Write Time
7
ns
2
ns
Address Valid to End of Write Time
Data Hold after End of Write Time (4)
Address Valid Setup to Start of Write Time (4)
Address Valid Hold after End of Write Time (4)
Write Enable to Output Disable Time (4)(5)
Write Disable to Output Enable Time (4)
Write Disable to Write Enable Pulse Width (3)
7
ns
0
ns
0
ns
TWHAX
TWLQZ
TWHQX
TWHWL
0
ns
2 / 2.5
ns
1
4
ns
ns
(1) Test conditions: VIL/VIH=0V/Vdd. Reference Tester Equivalent Load Circuit and Tester AC Timing Characteristics diagrams. Capacitive output loading C =5 pF for TWLQZ. Worst case
L
operating conditions: VDD2=3.0V to 3.6V, VDD=1.65V to 1.95V, -55°C to 125°C, post total dose 25°C
(2) TAVAVW = TWLWH + TWHWL
(3) Guaranteed but not tested.
(4) These parameters are tested as pass/fail.
(5) Values shown for 3.3V and 2.5V VDD2, respectively.
Write Cycle AC Timing
TAVAVW
ADDRESS
TAVWH
TWLWH
TWHAX
TAVWL
TWHWL
NWE
TWLQZ
TWHQX
TWHDX
HIGH
DATA OUT
DATA IN
IMPEDANCE
TDVWH
DATA VALID
TSLWH
NCS
Dynamic Electrical Operation
Asynchronous Operation
Write Operation
The RAM is asynchronous in operation. Read and Write cycles are
controlled by NWE, NCS, and Address signals.
To perform a write operation, both NWE and NCS must be low.
The write mode can be controlled via two different control signals:
NWE and NCS. Both modes of control are similar, except the
NCS controlled modes actually disable the RAM during the write
recovery pulse. Only the NWE controlled mode is shown in the
table and diagram on the previous page for simplicity; however,
each mode of control provides the same write cycle timing
characteristics. Thus, some of the parameter names referenced
below are not shown in the write cycle table or diagram, but
indicate which control pin is in control as it switches high or low.
To write data into the RAM, NWE and NCS must be held low for
at least TWLWH/TSLWH time. Any amount of edge skew between
the signals can be tolerated, and any one of the control signals can
initiate or terminate the write operation. The DATA IN must be valid
TDVWH time prior to switching high.
Read Operation
To perform a valid read operation, both chip select and output
enable (NOE) must be low and write enable (NWE) must be
high. The output drivers can be controlled independently by
the NOE signal.
It is important to have the address bus free of noise and glitches,
which can cause inadvertent read operations. The control and
address signals should have rising and falling edges that are fast
(<5 ns) and have good signal integrity (free of noise, ringing or
steps associated reflections).
To control a read cycle with NCS, all addresses must be valid prior
to or coincident with the enabling NCS edge transition. Address
edge transitions can occur later than the specified setup times
to NCS; however, the valid data access time will be delayed.
Any address edge transition, which occurs during the time when
NCS is low, will initiate a new read access, and data outputs will
not become valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance state TSHQZ
time following a disabling NCS edge transition.
Consecutive write cycles can be performed by toggling one of
the control signals while the other remains in their “write” state
(NWE or NCS held continuously low). At least one of the control
signals must transition to the opposite state between consecutive
write operations.
For consecutive write operations, write pulses (NWE) must be
separated by the minimum specified TWHWL/TSHSL time.
Address inputs must be valid at least TAVWL time before the
enabling NWE/NCS edge transition, and must remain valid during
the entire write time. A valid data overlap of write pulse width time
of TDVWH, and an address valid to end of write time of TAVWH
also must be provided for during the write operation. Hold times
for address inputs and data inputs with respect to the disabling
NWE/NCS edge transition must be a minimum of TWHAX time
and TWHDX time, respectively. The minimum write cycle time
is TAVAVW.
For an address activated read cycle, NCS must be valid prior to
or coincident with the address edge transition(s). Any amount of
toggling or skew between address edge transitions is permissible;
however, data outputs will become valid TAVQV time following the
latest occurring address edge transition. The minimum address
activated read cycle time is TAVAVR. When the RAM is operated
at the minimum address activated read cycle time, the data
outputs will remain valid on the RAM I/O until TAXQX time following
the next sequential address transition.
To perform consecutive read operations, NCS is required to
be held continuously low, and the toggling of the addresses will
start the new read cycle.
Tester AC Timing Characteristics
Tester AC Timing Characteristics
VDD2 – 0.5 V
Input
Levels*
VDD2/2
VDD2/2
+
-
Valid High
Output
VDD2/2 V
V1
0.5 V
249
+
-
V2
Valid Low
Output
DUT
Output
CI < 50 pf
VDD2 – 0.4 V
Output
Sense
Levels
High Z
Qualification and Screening
0.4 V
The S150 technology was qualified by Honeywell after meeting
the criteria of the General Manufacturing Standards. This approval
is the culmination of years of development and requires a
considerable amount of testing, documentation, and review.
The SRAM is also QML Certified, which required additional testing,
documentation, and DSCC approval.
High Z + 100mV
High Z – 100mV
High Z = VDD2/2
* Input rise and fall times < 5 ns
Reliability
The test flow includes screening units with the defined flow
(Class V and Q equivalent) and the appropriate periodic or lot
conformance testing (Groups B, C, D, and E). Both the S150
process and the SRAM products are subject to period or lot
based Technology Conformance Inspection (TCI) and Quality
Conformance Inspection (QCI) tests, respectively.
Since 1990 Honeywell has been producing integrated circuits that
meet the stringent reliability requirements of space and defense
systems. Honeywell has delivered thousands of QML parts since
first becoming QML qualified in 1990.
Using this proven approach Honeywell will assure the reliability
of the SRAMs manufactured with the S150 process technology.
This approach includes adhering to Honeywell’s General
Manufacturing Standards for:
Group A
Group B
General Electrical Tests
Mechanical – Dimensions, Bond Strength, Solvents, Die Shear,
Solderability, Lead Integrity, Seal, Acceleration
Life Tests – 1000 hours at 125°C or equivalent
Package related mechanical tests – Shock, Vibration, Accel, Salt, Seal,
Lead Finish Adhesion, Lid Torque, Thermal Shock, Moisture Resistance
Radiation Tests
Group C
Group D
• Designing in reliability by establishing electrical rules based
on wear out mechanism characterization performed on
specially designed test structures (electromigration, TDDB,
hot carriers, negative bias temperature instability, radiation)
Group E
• Utilizing a structured and controlled design process
Honeywell delivers products that are tested to meet your
requirements. Products can be screened to several levels
including Engineering Models and Flight Units. EMs are
available with limited screening for prototype development
and evaluation testing.
• A statistically controlled wafer fabrication process with a
continuous defect reduction process
• Individual wafer lot acceptance through process monitor testing
(includes radiation testing)
• The use of characterized and qualified packages
• A thorough product testing program based on MIL-PRF-38535
and MIL-STD 883.
Packaging
The 512k x 8 SRAM is offered in a 36-lead flat pack. This package
is constructed of multi-layer ceramic (Al2O3) and contains internal
power and ground planes. The package lid material is ceramic.
The finished, packaged part weighs 5.4 grams.
Packaging Outline
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1. Units in MM [In].
Common Dimensions - Millimeters
Common Dimensions - Inches
Symbol
Min
2.62
2.16
0.41
0.10
23.14
1.14
21.14
---
Nom
2.94
2.41
Max
3.28
2.66
0.51
0.20
23.60
1.40
21.54
---
Min
.103
.085
.016
.004
.911
.045
.832
---
Nom
Max
.129
.105
.020
.008
.929
.055
.848
---
2
Package may contain up to 6 CDR33
A
.116
chip capacitors. The standard
A1
b
.095
.018
.006
.920
.050
.840
.450
.104
configuration is 2 capacitors as shown.
0.46
0.15
C
D
e
3
4
A is height of package including lid,
no capacitors.
23.37
1.27
E1
L
21.34
11.43
2.64
Height of package including capacitors.
Q
---
---
---
---
Ordering Information (1)
H
RT
6408
A
V
F
Source
H = Honeywell
Process
RT = Rad Tolerant
Part Number Package Designation
Total Dose Hardness
5
0100 = 1 Meg
A = 34 Lead Flat pack
F = 3x10 rad (Si)
- = Bare Die (no package)
N = No Level Guaranteed (2)
Screen Level
V = QML Class V
W = QML Class Q+
E = Eng. Model (2)
(1) Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 1-800-323-8295 for further information.
(2) Engineering Device Description: Parameters are tested -55°C to 125°C, 24 hour burn-in, IDDSB = 12 mA, no
radiation guaranteed.
This product and related technical data is subject to the U.S. Department of State International Traffic in Arms Regulations (ITAR) 22 CFR 120-130 and may not be exported, as defined
by the ITAR, without the appropriate prior authorization from the Directorate of Defense Trade Controls, United States Department of State. Diversion contrary to U.S. export laws and
regulations is prohibited. This datasheet includes only basic marketing information on the function of the product and therefore is not considered technical data as defined in 22CFR 120.10.
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Find out more
To learn more about Honeywell’s radiation hardened
integrated circuit products and technologies, visit
www.honeywell.com/radhard.
Honeywell Aerospace
Honeywell
1944 E. Sky Harbor Circle
Phoenix, AZ 85034
Telephone: 1.800.601.3099
N61-1004-000-000
June 2010
International: 602.365.3099
www.honeywell.com
© 2010 Honeywell International Inc.
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