HT6256D [HONEYWELL]
Standard SRAM, 32KX8, 50ns, CDIP28, DIP-28;
| 型号： | HT6256D |
| 厂家： | 
Honeywell |
| 描述： | Standard SRAM, 32KX8, 50ns, CDIP28, DIP-28 |
| 文件： | 总8页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HTMOSTM High Temperature Products
HIGH TEMPERATURE 32K x 8 STATIC RAM
HT6256
FEATURES
APPLICATONS
• Specified Over -55 to +225°C
• Down-Hole Oil Well
• Avionics
• Fabricated with HTMOS™ IV Silicon on Insulator (SOI)
• Read/Write Cycle Times ≤ 50 ns Support 20 MHz Clock
• Asynchronous Operation
• Turbine Engine Control
• Industrial Process Control
• Nuclear Reactor
• CMOS Input/Output Buffers
• Single 5 V ± 10% Power Supply
• Electric Power Conversion
• Hermetic 28-Lead Ceramic DIP
• Heavy Duty Internal Combustion Engines
GENERAL DESCRIPTION
PACKAGE PINOUT
The 32K x 8 High Temperature Static RAM is a high
performance 32,768 word x 8-bit static random access
memory with industry-standard functionality. It is fabri-
cated with Honeywell’s HTMOS™ technology, and is
designed for use in systems operating in severe high
temperature environments.
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
NWE
A13
A8
2
3
4
5
A9
6
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
Top
View
7
The RAM requires only a single 5 V ± 10% power supply
and has CMOS compatible I/O. Power consumption is
typically less than 30 mW/MHz in operation, and less than
10 mW when de-selected. The RAM read operation is fully
asynchronous, with an associated typical access time of
50 ns at 5 V.
8
9
A0
10
11
12
13
14
DQ0
DQ1
DQ2
VSS
The RAM provides guaranteed performance over the full
-55 to +225°C temperature range. Typically, parts will
operate up to +300°C for a year, with derated perfor-
mance. All parts are burned in at 250°C to eliminate infant
mortality.
Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.ssec.honeywell.com
HT6256
FUNCTIONAL DIAGRAM
32,768 x 8
Memory
Array
•
•
•
Row
Decoder
A:0-8,12-13
11
CE*
NCS
•
•
•
8
Column Decoder
Data Input/Output
DQ:0-7
8
NWE
NOE
WE • CS • CE
1 = enabled
Signal
NWE • CS • CE • OE
(0 = high Z)
Signal
#
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
A:9-11, 14
4
SIGNAL DEFINITIONS
A: 0-14
DQ: 0-7
Address input pins which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers. If this signal is not used it must be connected to VSS.
NWE
NOE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in
a high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS and NWE. If this signal is not used it must be
connected to VSS.
CE*
ExternalcontrolofChipEnableisanextrafeatureavailableonlyinotherpackageoptions. Chipenable, when
at a high level allows normal operation. When at a low level CE forces the SRAM to a precharge condition,
holdsthedataoutputdriversinahighimpedancestateanddisablesalltheinputbuffersexcepttheNCSinput
buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE*
NWE
NOE
MODE
DQ
L
L
H
H
X
L
H
L
L
Read
Write
Data Out
Data In
Notes:
X: VI=VIH or VIL
X
XX: VSS≤VI≤VDD
H
X
XX
XX
XX
XX
Deselected High Z
Disabled High Z
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
2
HT6256
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Units
Symbol
VDD
Parameter
Min
-0.5
-0.5
-65
Max
Supply Voltage Range (2)
6.5
V
V
VPIN
Voltage on Any Pin (2)
VDD+0.5
TSTORE
TSOLDER
PD
Storage Temperature (Zero Bias)
Soldering Temperature (5 Seconds)
Maximum Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case)
325
355
2
°C
°C
W
IOUT
25
mA
V
VPROT
ΘJC
2000
28 DIP
10
°C/W
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Parameter
Units
Symbol
Typ
5.0
25
Max
5.5
Min
4.5
VDD
TA
Supply Voltage (referenced to VSS)
Ambient Temperature
V
°C
V
-55
-0.3
225
VPIN
Voltage on Any Pin (referenced to VSS)
VDD+0.3
CAPACITANCE (1)
Worst Case
Typical
Test Conditions
Units
Parameter
Symbol
(2)
Min
Max
7
CI
Input Capacitance
5
7
pF
pF
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
CO
Output Capacitance
9
(1) This parameter is tested during initial design characterization only
(2) Typical operating conditions: TA= 25°C.
DATA RETENTION CHARACTERISTICS (1)
Worst Case
Typical
Symbol
Parameter
Units
Test Conditions
Min
Max
NCS=VDR
VDR
IDR
Data Retention Voltage
Data Retention Current
2.5
V
VI=VDR or VSS
500
330
µA
µA
NCS=VDD=2.5V, VI=VDD or VSS
NCS=VDD=3.0V, VI=VDD or VSS
(1) Operating conditions: TA= -55°C to +125°C.
3
HT6256
DC ELECTRICAL CHARACTERISTICS
Worst Case (2)
Symbol
Parameter
Test Conditions
Typ (1)
Units
Min
Max
VIH=VDD, IO=0
VIL=VSS, f=0MHz
mA
IDDSB1
Static Supply Current
0.2
0.2
3.4
2.8
2.0
NCS=VDD, IO=0,
f=40 MHz
mA
mA
mA
IDDSBMF Standby Supply Current—Deselected
IDDOPW Dynamic Supply Current—Selected (Write)
IDDOPR Dynamic Supply Current—Selected (Read)
2.0
4.0
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
4.0
+5
II
Input Leakage Current
Output Leakage Current
VSS VI VDD
-5
µA
µA
VSS VIO VDD
Output=high Z
IOZ
-10
+10
VIL
Low-Level Input voltage
high-Level Input Voltage
March Pattern
March Pattern
1.7
3.2
0.3xVdd
V
V
VIH
0.7xVdd
VD =4.5V, IOL=10 mA (CMOS)
VDD=4.5V, IO =200 µA
0.3
0.005
0.4
0.05
V
V
VOL
VOH
Low-Level Output voltage
High-Level Output Voltage
VDD=4.5V, IOH=-5 mA
VDD=4.5V, IOH=-200 µA
4.3
4.5
4.2
Vdd-0.05
V
V
(1) Typical operating conditions: VDD= 5.0 V,TA=25°C.
(2) Worst case operating conditions: VDD= 5.0 V ±10%, TA=-55°C to +225°C.
(3) All inputs switching. DC average current. External control of Chip Enable (CE)
is available only in other package options.
2.9 V
Valid high
output
+
-
Vref1
Vref2
249Ω
+
-
Valid low
output
DUT
output
C
>50 pF*
L
*C = 5 pF for TWLQZ, TSHQZ, and TGHQZ
L
Tester Equivalent Load Circuit
Operating Current vs. Frequency @ 225°C
Cycle Times vs. Temperature
30
25
20
15
70
60
50
40
30
20
10
0
Write
Read
Read
Write
-100
0
100
200
300
0
5
10
15
20
25
Frequency (MHz)
Temperature (°C)
4
HT6256
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical (2)
Units
Min
Max
TAVAVR
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TGLQV
TGLQX
TGHQZ
TEHQV
TEHQX
TELQZ
Address Read Cycle Time
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
50
Address Change to Output Invalid Time
Chip Select Access Time
3
5
50
Chip Select Output Enable Time
Chip Select Output Disable Time
Output Enable Access Time
20
15
Output Enable Output Enable Time
Output Enable Output Disable Time
Chip Enable Output Access Time (4)
Chip Enable Output enable Time (4)
Chip Enable Output Disable Time (4)
0
5
15
25
17
10
4
10
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels
shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent capacitive output loading CL=5 pF for
TSHQZ and TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 225°C.
(4) External control of Chip Enable (CE) is available only in other package options.
T
AVAVR
ADDRESS
NCS
T
AVQV
TAXQX
T
SLQV
T
SLQX
TSHQZ
HIGH
IMPEDANCE
DATA OUT
DATA VALID
T
EHQX
EHQV
T
TELQZ
CE
T
GLQX
GLQV
T
TGHQZ
NOE
(NWE = high)
5
HT6256
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameters
Typical (2)
Units
Min
50
45
45
35
45
0
Max
TAVAVW
TWLWH
TSLWH
TDVWH
TAVWH
TWHDX
TAVWL
TWHAX
TWLQZ
TWHQX
TWHWL
TEHWH
Write Cycle Timing (4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Enable Write Pulse Width
Chip Select to End of Write Time
Data Valid to End of Write Time
Address Valid to End of Write Time
Data Hold Time after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid after End of Write Time
Write Enable to Output Disable Time
Write Disable to Ouput Enable Time
Write Disable to Write Enable Pulse Width (5)
Chip Enable to End of Write Time (6)
0
0
0
15
5
5
45
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V, input rise and fall times <1 ns/V, input and output timing reference levels
shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25°C.
(3) Worst case operation conditions: VDD=4.5 V to 5.5 V, -55 to 225°C.
(4) TAVAVW = TWLWH + TWHWL
(5) Guaranteed but not tested.
(6) External control of Chip Enable (CE) is available only in other package options.
T
AVAVW
ADDRESS
T
AVWH
TWHAX
T
AVWL
T
WHWL
TWLWH
NWE
T
WLQZ
T
WHQX
DATA OUT
DATA IN
HIGH
IMPEDANCE
T
DVWH
TWHDX
DATA VALID
T
SLWH
NCS
CE
T
EHWH
6
HT6256
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle
Write Cycle
The RAM is asynchronous in operation, allowing the read The write operation is synchronous with respect to the
cycle to be controlled by address, chip select (NCS), or chip address bits, and control is governed by write enable (NWE),
enable (CE) (refer to Read Cycle timing diagram). To per- chip select (NCS), or chip enable (CE) edge transitions (refer
form a valid read operation, both chip select and output toWriteCycletimingdiagrams).Toperformawriteoperation,
enable (NOE) must be low and chip enable and write enable both NWE and NCS must be low, and CE must be high.
(NWE) must be high. The output drivers can be controlled ConsecutivewritecyclescanbeperformedwithNWEorNCS
independently by the NOE signal. Consecutive read cycles held continuously low, or CE held continuously high. At least
can be executed with NCS held continuously low, and with oneofthecontrolsignalsmusttransitiontotheoppositestate
CE held continuously high, and toggling the addresses.
between consecutive write operations.
For an address activated read cycle, NCS and CE must be The write mode can be controlled via three different control
valid prior to or coincident with the activating address edge signals: NWE, NCS, and CE. All three modes of control are
transition(s). Any amount of toggling or skew between ad- similar except the NCS and CE controlled modes actually
dress edge transitions is permissible; however, data outputs disable the RAM during the write recovery pulse. Both CE
will become valid TAVQV time following the latest occurring and NCS fully disable the RAM decode logic and input
address edge transition. The minimum address activated buffers for power savings. Only the NWE controlled mode is
read cycle time is TAVAV. When the RAM is operated at the shown in the table and diagram on the previous page for
minimumaddressactivatedreadcycletime, thedataoutputs simplicity. However, each mode of control provides the
will remain valid on the RAM I/O until TAXQX time following same write cycle timing characteristics. Thus, some of the
the next sequential address transition.
parameter names referenced below are not shown in the
write cycle table or diagram, but indicate which control pin
To control a read cycle with NCS, all addresses and CE is in control as it switches high or low.
must be valid prior to or coincident with the enabling NCS
edge transition. Address or CE edge transitions can occur TowritedataintotheRAM, NWEandNCSmustbeheldlow
later than the specified setup times to NCS, however, the and CE must be held high for at least TWLWH/TSLSH/
valid data access time will be delayed. Any address edge TEHELtime. Anyamountofedgeskewbetweenthesignals
transition, which occurs during the time when NCS is low, can be tolerated, and any one of the control signals can
will initiate a new read access, and data outputs will not initiate or terminate the write operation. For consecutive
become valid until TAVQV time following the address edge write operations, write pulses must be separated by the
transition. Data outputs will enter a high impedance state minimum specified TWHWL/TSHSL/TELEH time. Address
TSHQZ time following a disabling NCS edge transition.
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
To control a read cycle with CE, all addresses and NCS must remain valid during the entire write time. A valid data
must be valid prior to or coincident with the enabling CE overlapofwritepulsewidthtimeofTDVWH/TDVSH/TDVEL,
edgetransition.AddressorNCSedgetransitionscanoccur andanaddressvalidtoendofwritetimeofTAVWH/TAVSH/
later than the specified setup times to CE; however, the TAVELalsomustbeprovidedforduringthewriteoperation.
valid data access time will be delayed. Any address edge Hold times for address inputs and data inputs with respect
transition which occurs during the time when CE is high will to the disabling NWE/NCS/CE edge transition must be a
initiate a new read access, and data outputs will not minimum of TWHAX/TSHAX/TELAX time and TWHDX/
become valid until TAVQV time following the address edge TSHDX/TELDXtime,respectively.Theminimumwritecycle
transition. Data outputs will enter a high impedance state time is TAVAV.
TELQZ time following a disabling CE edge transition.
7
HT6256
QUALITY ASSURANCE
nature. Reliability attributes of the HTMOS process were
characterized by testing test structures from which specific
failuremechanismswereevaluated.Thesespecificmecha-
nisms included, but were not limited to, hot carriers, electromi-
gration and time dependent dielectric breakdown. This data
was then used to make changes to the design models and
process to ensure reliable -55 to +225°C specified products.
Honeywellmaintainsahighlevelofproductintegritythrough
process control utilizing statistical process control, a com-
plete “Total Quality Assurance System,” and a computer
data base process performance tracking system. This
Total Quality approach ensures our customers of a reliable
product by engineering in reliability, starting with process
development and continuing through product qualification PACKAGING
and screening.
The standard package is a hermetic 28-lead DIP con-
SCREENING LEVELS
structed of multilayer ceramic (Al2O3) and features internal
power and ground planes. Ceramic chip capacitors can be
mounted to the package by the user to maximize supply
noise decoupling and increase board packing density.
These capacitors connect to the internal package power
and ground planes. This design minimizes resistance and
inductance of the bond wire and package. For packaging
Honeywell offers several levels of device screening to
meet your system needs. Hi-Rel Level B devices undergo
additional screening per the requirements of MIL-STD-883.
RELIABILITY
Honeywell understands the stringent reliability require- options with surface mount capability or external control of
ments for extreme environment systems and has exten- Chip Enable (CE), call Honeywell.
sive experience in reliability testing on programs of this
28-LEAD DIP PACKAGE
C
D
Y
All dimensions in inches
Z
Right
Reading
on Lid
A
b
0.175 (max)
0.018 ± 0.002
eA
E
b2 0.050 (typ)
C
D
E
e
0.010 to 0.002
1
1.400 ± 0.014
0.594 ± 0.010
0.100 ±0.005
Optional
Capacitors
Ceramic
Body
X
eA 0.600 ±0.010
S2
L
0.125 to 0.175
0.050 ±0.010
Q
Q
A
L
S1 0.005 (min)
S2 0.005 (min)
X
Y
Z
0.100 ref
0.050 ref
0.075 ref
S1
b2
b
e
(width)
(pitch)
ORDERING INFORMATION (1)
HT6256DC
C - Indicates screening level
B = High Temperature Class B
C = Commercial
D - Indicates package type
D = 28-Lead DIP
For packaging options, call Honeywell
(1) Orders may be faxed to 612-954-2257. Please contact our Customer Service Department at 612-954-2888 for further information.
To lea r n m or e a bou t Hon eyw ell Solid Sta te Electr on ics Cen ter ,
visit ou r w eb site a t h ttp ://w w w .ssec.h on eyw ell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
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