HX6356KSHT [HONEYWELL]
Standard SRAM, 32KX8, 25ns, CMOS, DIE;
| 型号： | HX6356KSHT |
| 厂家： | 
Honeywell |
| 描述： | Standard SRAM, 32KX8, 25ns, CMOS, DIE 输入元件 静态存储器 输出元件 内存集成电路 |
| 文件： | 总12页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Aerospace Electronics
32K x 8 STATIC RAM—SOI
HX6356
FEATURES
OTHER
RADIATION
• Fabricated with RICMOS™ IV Silicon on Insulator (SOI)
• Listed On SMD# 5962-95845
0.75 µm Process (Leff = 0.6 µm)
• Fast Read/Write Cycle Times
≤ 17 ns (Typical)
≤ 25 ns (-55 to 125°C)
• Total Dose Hardness through 1x106 rad(SiO2)
• Neutron Hardness through 1x1014 cm-2
• Typical Operating power < 15 mW/MHz
• Asynchronous Operation
• Dynamic and Static Transient Upset Hardness
through 1x1011 rad(Si)/s
• Dose Rate Survivability through 1x1012 rad(Si)/s
• CMOS or TTL Compatible I/O
• Single 5 V 10% Power Supply
• Packaging Options
• Soft Error Rate of <1x10-10 upsets/bit-day
in Geosynchronous Orbit
- 36-Lead CFP—Bottom Braze (0.630 in. x 0.650 in.)
- 36-Lead CFP—Top Braze (0.630 in. x 0.650 in.)
• Latchup Free
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 word x 8-bit static random access
memorywithindustry-standardfunctionality.Itisfabricated
with Honeywell’s radiation hardened technology, and is
designed for use in systems operating in harsh, transient
radiation environments. The RAM operates over the full
military temperature range and requires only a single 5 V
10% power supply. The RAM is available with either TTL or
CMOS compatible I/O. Power consumption is typically less
than 15 mW/MHz in operation, and less than 5 mW when
de-selected. The RAM read operation is fully asynchro-
nous, with an associated typical access time of 14 ns at 5V.
Honeywell’senhancedSOIRICMOS™IV(RadiationInsen-
sitive CMOS) technology is radiation hardened through the
use of advanced and proprietary design, layout and pro-
cess hardening techniques. The RICMOS™ IV process is a
5-volt, SIMOX CMOS technology with a 150 Å gate oxide
and a minimum drawn feature size of 0.75 µm (0.6 µm
effective gate length—Leff). Additional features include
tungsten via plugs, Honeywell’s proprietary SHARP pla-
narization process, and a lightly doped drain (LDD) struc-
ture for improved short channel reliability. A 7 transistor
(7T) memory cell is used for superior single event upset
hardening, while three layer metal power bussing and the
low collection volume SIMOX substrate provide improved
dose rate hardening.
HX6356
FUNCTIONAL DIAGRAM
32,768 x 8
Memory
Array
•
•
•
Row
Decoder
A:0-8,12-13
11
CE
•
•
•
NCS
8
Column Decoder
Data Input/Output
DQ:0-7
8
NWE
NOE
WE • CS • CE
1 = enabled
Signal
NWE • CS • CE • OE
(0 = high Z)
Signal
#
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
A:9-11, 14
4
SIGNAL DEFINITIONS
A: 0-14
DQ: 0-7
Address input pins which select a particular eight-bit word within the memory array.
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. If this signal is not used it must be connected to VSS.
NWE
NOE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE
NWE
NOE
MODE
DQ
L
L
H
H
X
L
H
L
L
Read
Write
Data Out
Data In
Notes:
X: VI=VIH or VIL
X
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
H
X
XX
XX
XX
XX
Deselected High Z
Disabled High Z
2
HX6356
RADIATION CHARACTERISTICS
The SRAM will meet any functional or electrical specifica-
tion after exposure to a radiation pulse up to the transient
dose rate survivability specification, when applied under
recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs,
and power supply may significantly exceed the normal
operating levels. The application design must accommo-
date these effects.
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
afterthespecifiedtotalionizingradiationdose. Allelectrical
and timing performance parameters will remain within
specifications after rebound at VDD = 5.5 V and T =125°C
extrapolatedtotenyearsofoperation. Totaldosehardness
isassuredbywaferleveltestingofprocessmonitortransis-
tors and RAM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correla-
tions have been made between 10 keV X-rays applied at a
dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This as-
sumes an equivalent neutron energy of 1 MeV.
Soft Error Rate
Transient Pulse Ionizing Radiation
The SRAM has an extremely low Soft Error Rate (SER) as
specified in the table below. This hardness level is defined
by the Adams 90% worst case cosmic ray environment.
ThelowSERisachievedbytheuseofaunique7-transistor
memory cell and the oxide isolation of the SOI substrate.
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse up to the transient dose rate upset
specification, when applied under recommended operat-
ing conditions. To ensure validity of all specified perfor-
mance parameters before, during, and after radiation
(timing degradation during transient pulse radiation (tim-
ing degradation during transient pulse radiation is ≤10%),
it is suggested that stiffening capacitance be placed on or
near the package VDD and VSS, with a maximum induc-
tance between the package (chip) and stiffening capaci-
tance of 0.7 nH per part. If there are no operate-through
or valid stored data requirements, typical circuit board
mounted de-coupling capacitors are recommended.
Latchup
TheSRAMwillnotlatchupduetoanyoftheaboveradiation
exposure conditions when applied under recommended
operatingconditions.FabricationwiththeSIMOXsubstrate
material provides oxide isolation between adjacent PMOS
and NMOS transistors and eliminates any potential SCR
latchup structures. Sufficient transistor body tie connec-
tionstothep-andn-channelsubstratesaremadetoensure
no source/drain snapback occurs.
RADIATION HARDNESS RATINGS (1)
Limits (2)
Units
Test Conditions
Parameter
Total Dose
≥1x106
≥1x1011
≥1x1012
<1x10-10
≥1x1014
rad(SiO2)
rad(Si)/s
TA=25°C
Pulse width ≤1 µs
Transient Dose Rate Upset
Transient Dose Rate Survivability
Soft Error Rate
Pulse width ≤50 ns, X-ray,
VDD=6.0 V, TA=25°C
rad(Si)/s
TA=125°C, Adams 90%
upsets/bit-day
N/cm2
worst case environment
1 MeV equivalent energy,
Unbiased, TA=25°C
Neutron Fluence
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, -55°C to 125°C.
3
HX6356
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Units
Symbol
VDD
Parameter
Positive Supply Voltage (2)
Min
-0.5
-0.5
-65
Max
6.5
V
V
VPIN
Voltage on Any Pin (2)
VDD+0.5
150
TSTORE
TSOLDER
PD
Storage Temperature (Zero Bias)
Soldering Temperature (5 Seconds)
Total Package Power Dissipation (3)
DC or Average Output Current
ESD Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case)
Junction Temperature
°C
°C
W
270
2.0
IOUT
25
mA
V
VPROT
ΘJC
2000
– 36 FP
2
°C/W
°C
TJ
175
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Parameter
Units
Symbol
Typ
5.0
25
Max
5.5
Min
4.5
VDD
TA
Supply Voltage (referenced to VSS)
Ambient Temperature
V
°C
V
-55
-0.3
125
VPIN
Voltage on Any Pin (referenced to VSS)
VDD+0.3
CAPACITANCE (1)
Worst Case
Typical
Test Conditions
Units
Parameter
Symbol
(1)
Min
Max
7
CI
Input Capacitance
pF
pF
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
CO
Output Capacitance
9
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Worst Case (2)
Typical
Symbol
Parameter
Units
Test Conditions
(1)
Min
Max
NCS=VDR
VDR
IDR
Data Retention Voltage
Data Retention Current
2.5
V
VI=VDR or VSS
500
330
µA
µA
NCS=VDD=2.5V, VI=VDD or VSS
NCS=VDD=3.0V, VI=VDD or VSS
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: -55°C to +125°C, post total dose at 25°C.
4
HX6356
DC ELECTRICAL CHARACTERISTICS
Worst Case (2)
Typical
(1)
Symbol
Parameter
Units
Test Conditions
Min
Max
VIH=VDD, IO=0
VIL=VSS, f=0MHz
IDDSB1
Static Supply Current
0.2
0.2
3.4
2.8
1.5
mA
mA
mA
mA
µA
NCS=VDD, IO=0,
f=40 MHz
IDDSBMF Standby Supply Current - Deselected
IDDOPW Dynamic Supply Current, Selected (Write)
IDDOPR Dynamic Supply Current, Selected (Read)
1.5
4.0
4.0
+1
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS (3)
VSS≤VI≤VDD
II
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
-1
-1
VSS≤VIO≤VDD
IOZ
VIL
+1
µA
Output=high Z
1.7
3.2
CMOS
TTL
0.3xVDD
V
V
March Pattern
VDD = 4.5V
0.8
CMOS
TTL
0.7xVDD
V
V
March Pattern
VDD = 5.5V
VIH
High-Level Input Voltage
2.2
0.3
0.4
0.1
V
V
VDD = 4.5V, IOL = 10 mA (CMOS)
= 8 mA (TTL)
VOL
VOH
Low-Level Output Voltage
High-Level Output Voltage
0.005
VDD = 4.5V, IOL = 200 µA
4.3
4.5
4.2
VDD-0.1
V
V
VDD = 4.5V, IOH = -5 mA
VDD = 4.5V, IOH = -200 µA
(1) Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
2.9 V
Valid high
output
+
-
Vref1
Vref2
249Ω
+
-
Valid low
output
DUT
output
C >50 pF*
L
*C = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
L
Tester Equivalent Load Circuit
5
HX6356
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical (2)
Units
Min
Max
TAVAVR
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TEHQV
TEHQX
TELQZ
TGLQV
TGLQX
TGHQZ
Address Read Cycle Time
17
14
9
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
25
Address Change to Output Invalid Time
Chip Select Access Time
3
5
17
10
4
25
Chip Select Output Enable Time
Chip Select Output Disable Time
Chip Enable Access Time (4)
Chip Enable Output Enable Time (4)
Chip Enable Output Disable Time (4)
Output Enable Access Time
10
25
17
10
4
5
0
10
9
4
Output Enable Output Enable Time
Output Enable Output Disable Time
4
2
9
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent
capacitive output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, post total dose at 25°C.
T
AVAVR
ADDRESS
NCS
T
AVQV
TAXQX
T
SLQV
T
SLQX
TSHQZ
HIGH
IMPEDANCE
DATA OUT
DATA VALID
T
EHQX
EHQV
T
TELQZ
CE
T
GLQX
GLQV
T
TGHQZ
NOE
(NWE = high)
6
HX6356
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical (2)
Units
Min
Max
TAVAVW
TWLWH
TSLWH
TDVWH
TAVWH
TWHDX
TAVWL
TWHAX
TWLQZ
TWHQX
TWHWL
TEHWH
Write Cycle Time (4)
13
9
25
20
20
15
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Enable Write Pulse Width
Chip Select to End of Write Time
10
5
Data Valid to End of Write Time
Address Valid to End of Write Time
Data Hold Time after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Write Enable to Output Disable Time
Write Disable to Output Enable Time
Write Disable to Write Enable Pulse Width(5)
Chip Enable to End of Write Time
9
0
0
0
0
0
3
0
9
9
5
4
5
12
20
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and
output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive
load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4) TAVAVW = TWLWH + TWHWL
(5) Guaranteed but not tested.
T
AVAVW
ADDRESS
T
AVWH
TWHAX
T
AVWL
T
WHWL
TWLWH
NWE
T
WLQZ
T
WHQX
DATA OUT
DATA IN
HIGH
IMPEDANCE
T
DVWH
TWHDX
DATA VALID
T
SLWH
NCS
CE
T
EHWH
7
HX6356
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle
Write Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (NCS), or chip
enable (CE) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and chip enable and write enable
(NWE) must be high. The output drivers can be controlled
independently by the NOE signal. Consecutive read cycles
can be executed with NCS held continuously low, and with
CE held continuously high, and toggling the addresses.
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To per-
form a write operation, both NWE and NCS must be low,
and CE must be high. Consecutive write cycles can be
performed with NWE or NCS held continuously low, or CE
held continuously high. At least one of the control signals
must transition to the opposite state between consecutive
write operations.
For an address activated read cycle, NCS and CE must be
valid prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between ad-
dress edge transitions is permissible; however, data outputs
will become valid TAVQV time following the latest occurring
address edge transition. The minimum address activated
read cycle time is TAVAV. When the RAM is operated at the
minimumaddressactivatedreadcycletime,thedataoutputs
will remain valid on the RAM I/O until TAXQX time following
the next sequential address transition.
The write mode can be controlled via three different control
signals: NWE, NCS, andCE. Allthreemodesofcontrolare
similar except the NCS and CE controlled modes actually
disable the RAM during the write recovery pulse. Both CE
and NCS fully disable the RAM decode logic and input
buffers for power savings. Only the NWE controlled mode
is shown in the table and diagram on the previous page for
simplicity. However, each mode of control provides the
same write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in the
write cycle table or diagram, but indicate which control pin
is in control as it switches high or low.
To control a read cycle with NCS, all addresses and CE
must be valid prior to or coincident with the enabling NCS
edge transition. Address or CE edge transitions can occur
later than the specified setup times to NCS, however, the
valid data access time will be delayed. Any address edge
transition, which occurs during the time when NCS is low,
will initiate a new read access, and data outputs will not
becomevaliduntilTAVQVtimefollowingtheaddressedge
transition. Data outputs will enter a high impedance state
TSHQZ time following a disabling NCS edge transition.
TowritedataintotheRAM,NWEandNCSmustbeheldlow
and CE must be held high for at least TWLWH/TSLSH/
TEHEL time. Any amount of edge skew between the
signals can be tolerated, and any one of the control signals
can initiate or terminate the write operation. For consecu-
tivewriteoperations, writepulsesmustbeseparatedbythe
minimumspecifiedTWHWL/TSHSL/TELEHtime.Address
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
must remain valid during the entire write time. A valid data
overlapofwritepulsewidthtimeofTDVWH/TDVSH/TDVEL,
and an address valid to end of write time of TAVWH/
TAVSH/TAVEL also must be provided for during the write
operation. Hold times for address inputs and data inputs
with respect to the disabling NWE/NCS/CE edge transition
must be a minimum of TWHAX/TSHAX/TELAX time and
TWHDX/TSHDX/TELDX time, respectively. The minimum
write cycle time is TAVAV.
To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edge transition. Address or NCS edge transitions can
occur later than the specified setup times to CE; however,
the valid data access time will be delayed. Any address
edge transition which occurs during the time when CE is
high will initiate a new read access, and data outputs will
not become valid until TAVQV time following the address
edge transition. Data outputs will enter a high impedance
state TELQZ time following a disabling CE edge transition.
8
HX6356
TESTER AC TIMING CHARACTERISTICS
TTL I/O Configuration
CMOS I/O Configuration
3 V
0 V
VDD-0.5 V
Input
Levels*
1.5 V
VDD/2
0.5 V
1.5 V
VDD/2
Output
Sense
Levels
VDD-0.4V
0.4 V
VDD-0.4V
High Z
High Z
0.4 V
3.4 V
2.4 V
3.4 V
2.4 V
High Z
High Z
High Z = 2.9V
High Z = 2.9V
* Input rise and fall times <1 ns/V
QUALITY AND RADIATION HARDNESS
ASSURANCE
Honeywellmaintainsahighlevelofproductintegritythrough
process control, utilizing statistical process control, a com-
plete “Total Quality Assurance System,” a computer data
base process performance tracking system, and a radia-
tion-hardness assurance strategy.
need to create detailed specifications and offer benefits of
improved quality and cost savings through standardization.
RELIABILITY
The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiationhardnessisassuredoneverywaferbyirradiating
test structures as well as SRAM product, and then monitor-
ingkeyparameterswhicharesensitivetoionizingradiation.
Conventional MIL-STD-883 TM 5005 Group E testing,
which includes total dose exposure with Cobalt 60, may
also be performed as required. This Total Quality approach
ensures our customers of a reliable product by engineering
in reliability, starting with process development and con-
tinuing through product qualification and screening.
Honeywell understands the stringent reliability require-
ments for space and defense systems and has extensive
experience in reliability testing on programs of this nature.
This experience is derived from comprehensive testing of
VLSI processes. Reliability attributes of the RICMOSTM
process were characterized by testing specially designed
irradiated and non-irradiated test structures from which
specificfailuremechanismswereevaluated.Thesespecific
mechanisms included, but were not limited to, hot carriers,
electromigration and time dependent dielectric breakdown.
This data was then used to make changes to the design
models and process to ensure more reliable products.
SCREENING LEVELS
In addition, the reliability of the RICMOSTM process and
product in a military environment was monitored by testing
irradiated and non-irradiated circuits in accelerated dy-
namic life test conditions. Packages are qualified for prod-
uct use after undergoing Groups B & D testing as outlined
in MIL-STD-883, TM 5005, Class S. The product is qualified
by following a screening and testing flow to meet the
customer’s requirements. Quality conformance testing is
performed as an option on all production lots to ensure the
ongoing reliability of the product.
Honeywell offers several levels of device screening to meet
your system needs. “Engineering Devices” are available
with limited performance and screening for breadboarding
and/or evaluation testing. Hi-Rel Level B and S devices
undergo additional screening per the requirements of MIL-
STD-883. As a QML supplier, Honeywell also offers QML
Class Q and V devices per MIL-PRF-38535 and are avail-
ablepertheapplicableStandardMicrocircuitDrawing(SMD).
QML devices offer ease of procurement by eliminating the
9
HX6356
PACKAGING
The 32K x 8 SRAM is offered in two custom 36-lead flat
packs (FP). The packages are constructed of multilayer
ceramic (Al2O3) and feature internal power and ground
planes. The 36-lead flat packs also feature a non-conduc-
tive ceramic tie bar on the lead frame. The tie bar allows
electrical testing of the device, while preserving the lead
integrity during shipping and handling, up to the point of
lead forming and insertion.
36-LEAD FP PINOUT
VSS
VDD
A14
A12
A7
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VSS
VDD
NWE
CE
2
3
4
5
A13
A8
A6
6
A5
7
A9
A4
8
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
Top
View
A3
9
On the bottom braze 36-lead FP, ceramic chip capacitors
can be mounted to the package by the user to maximize
supply noise decoupling and increase board packing den-
sity. These capacitors attach directly to the internal pack-
age power and ground planes. This design minimizes
resistance and inductance of the bond wire and package.
All NC (no connect) pins should be connected to VSS to
prevent charge build up in the radiation environment.
A2
10
11
12
13
14
15
16
17
18
A1
A0
DQ0
DQ1
DQ2
NC
VDD
VSS
36-LEAD FLAT PACK—Bottom Braze (22018131-001)
E
22018131-001
1
b
(width)
Top
View
e
(pitch)
H
L
L
Non-
Conductive
Tie-Bar
Ceramic
Body
Kovar
Lid [3]
A
J
0.004
C
M
S
N
I
X
Optional
Capacitors
All dimensions are in inches [1]
VDD
VSS
VSS
VDD
A
b
C
D
E
e
F
G
H
I
0.095 ± 0.014
0.008 ± 0.002
0.005 to 0.0075
0.650 ± 0.010
0.630 ± 0.007
0.025 ± 0.002 [2]
0.425 ± 0.005 [2]
0.525 ± 0.005
0.135 ± 0.005
0.030 ± 0.005
0.080 typ.
M
N
O
P
R
S
T
U
V
W
X
Y
0.008 ± 0.003
0.050 ± 0.010
0.090 ref
0.015 ref
0.075 ref
0.113 ± 0.010
0.050 ref
0.030 ref
0.080 ref
0.005 ref
Y
J
L
0.450 ref
0.400 ref
0.285 ± 0.015
1
1
[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS
O
V
W
T
P
U
R
10
HX6356
36-LEAD FLAT PACK—Top Braze (22019627-001)
E
1
22019627-001
b
(width)
Top
View
e
(pitch)
All dimensions are in inches
A
b
C
D
E
e
F
G
H
I
0.085 ± 0.010
0.008 ± 0.002
0.005 to 0.0075
0.650 ± 0.010
0.630 ± 0.007
0.025 ± 0.002 [2]
0.425 ± 0.005 [2]
0.525 ± 0.005
0.135 ± 0.005
0.030 ± 0.005
0.080 typ.
H
L
Ceramic
Body
Kovar
Lid [3]
Kovar Lead [1]
C
A
J
M
I
Non-Conductive
Tie-Bar
J
S
L
M
S
0.285 ± 0.015
0.009 ± 0.003
0.113 ± 0.010
[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS
Bottom
View
Pin 1 Index Bar
DYNAMIC BURN-IN DIAGRAM
STATIC BURN-IN DIAGRAM
VDD
VDD
1
2
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
1
2
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VSS
VSS
VSS
VDD
A14
A12
A7
VSS
VDD
NWE
CE
VSS
VDD
A14
A12
A7
VSS
VDD
NWE
CE
3
3
R
R
R
R
R
R
R
R
R
R
R
F0
F16
R
R
4
4
R
R
R
R
R
R
R
R
R
R
F17
R
R
R
R
R
R
R
R
R
R
F7
F6
5
5
F15
F12
F11
F10
F17
F9
A13
A8
R
R
R
R
R
A13
A8
6
6
A6
F5
A6
7
7
A5
A9
F4
A5
A9
8
8
A4
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
F3
A4
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
9
9
A3
F2
A3
10
11
12
13
14
15
16
17
18
10
11
12
13
14
15
16
17
18
A2
F8
R
R
A2
F17
F1
A1
F13
F14
F1
A1
A0
R
R
R
R
R
R
R
R
A0
F1
DQO
DQ1
DQ2
DQO
DQ1
DQ2
R
R
R
R
F1
F1
F1
F1
R
R
F1
NC
NC
VDD
VSS
VDD
VSS
VSS
VSS
VDD = 5.5V, R ≤ 10 KΩ
Ambient Temperature ≥ 125 °C
VDD = 5.6V, R ≤ 10 KΩ, VIH = VDD, VIL = VSS
Ambient Temperature ≥ 125 °C, F0 ≥ 100 KHz Sq Wave
Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
11
HX6356
ORDERING INFORMATION (1)
S
H
C
6356
H
X
X
INPUT
PART NUMBER
SCREEN LEVEL
V=QML Class V
Q=QML Class Q
S=Class S
BUFFER TYPE
C=CMOS Level
T=TTL Level
PROCESS
PACKAGE DESIGNATION
X=36-Lead FP (Bottom Braze)
P=36-Lead FP (Top Braze)
K=Known Good Die
TOTAL DOSE
HARDNESS
X=SOI
B=Class B
E=Engr Device (2)
R=1x105 rad(SiO2)
F=3x105 rad(SiO2)
SOURCE
H=HONEYWELL
- = Bare Die (No Package)
H=1x106 rad(SiO2)
N=No Level Guaranteed
(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information.
(2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.
Contact Factory with other needs.
To lea r n m or e a bou t Hon eyw ell Solid Sta te Electr on ics Cen ter ,
visit ou r w eb site a t h ttp ://w w w .ssec.h on eyw ell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Helping You Control Your World
900155 Rev. A
6-97
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