HX6408-VFN [HONEYWELL]
512k x 8 STATIC RAM; 512K ×8静态RAM
| 型号： | HX6408-VFN |
| 厂家： | 
Honeywell |
| 描述： | 512k x 8 STATIC RAM |
| 文件： | 总11页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HX6408
512k x 8 STATIC RAM
The 512K x 8 Radiation Hardened Static RAM is a high
performance 524,288 word x 8-bit static random access
memory with optional industry-standard functionality. It is
fabricated with Honeywell’s radiation hardened Silicon On
Insulator (SOI) technology, and is designed for use in low
voltage systems operating in radiation environments. The
RAM operates over the full military temperature range and
requires only a single 3.3 V ± 0.3V power supply. Power
consumption is typically <30 mW @ 1MHz in write mode,
<14 mW @ 1MHz in read mode, and is less than 5 mW
when in standby mode.
The RICMOS™ V low power process is a SOI CMOS
technology with an 80 Å gate oxide and a minimum
drawn feature size of 0.35 µm. Additional features
include tungsten via and contact plugs, Honeywell’s
proprietary SHARP planarization process and a lightly
doped drain (LDD) structure for improved short
channel reliability. A seven transistor (7T) memory cell
is used for superior single event upset hardening,
while three layer metal power busing and the low
collection volume SOI substrate provide improved
dose rate hardening.
Honeywell’s enhanced RICMOS™(Radiation Insensitive
CMOS) SOI V technology is radiation hardened through the
use of advanced and proprietary design, layout and process
hardening techniques.
FEATURES
No Latchup
Single Power Supply,
3.3 V ± 0.3 V
Fabricated with RICMOS™ V
Silicon On Insulator (SOI)
Read/Write Cycle Times
≤20 ns, (3.3 V), -55 to 125°C
Operating Range is
-55°C to +125°C
0.35 mm Process (Leff = 0.28 µm)
Total Dose ≥ 3x105 and 1X106 rad(SiO2)
Neutron ≥1x1014 cm-2
Typical Operating Power (3.3 V)
<14 mW @ 1MHz Read
<30 mW @ 1MHz Write
<5 mW Standby mode
36-Lead Flat Pack Package
Optional Low Power Sleep
Mode
Dynamic and Static Transient Upset
≥1x1010 rad(Si)/s (3.3 V)
Asynchronous Operation
CMOS Compatible I/O
Dose Rate Survivability ≥1x1012 rad(Si)/s
Soft Error Rate
≤1x10-10 Upsets/bit-day (3.3 V)
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HX6408
Advanced Information
FUNCTIONAL DIAGRAM
36 LEAD FLAT PACK PINOUT
HX6408
Top View
A0
A1
1
2
3
4
5
6
7
8
9
36 (NSL)
35 A18
34 A17
33 A16
32 A15
31 NOE
30 D4
Memory
Array
An
A2
A3
A4
NCS
D0
NWE
DQ(0:7)
D1
29 D5
WE • CS
VDD
28 VSS
27 VDD
26 D6
NSL
NCS
VSS 10
D2 11
D3 12
NWE 13
A5 14
NWE • CS
25 D7
24 A14
23 A13
22 A12
21 A11
20 A10
19 NAS
NOE
All controls must be enabled
for signal to pass.
A6 15
# = number of buffers,
Default = 1
A7 16
A8 17
1 = enabled
A9 18
Signal
Signal
#
SIGNAL DEFINITIONS
A: 0-18
Address input pins, which select a particular eight-bit word within the memory array.
DQ: 0-7 Bidirectional data pins, which serve as data outputs during a read operation and as data inputs
during a write operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level
NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance
state. If this signal is not used it must be connected to VSS.
NWE
NOE
Negative write enable, when at a low level activates a write operation and holds the data output
drivers in a high impedance state. When at a high level NWE allows normal read operation.
Negative output enable, when at a high level holds the data output drivers in a high impedance
state. When at a low level, the data output driver state is defined by NCS, NWE and NSL. This
signal is asynchronous.
NSL
Not sleep, when at a high level allows normal operation. When at a low level NSL forces the SRAM
to a precharge condition, holds the data output drivers in a high impedance state and disables all the
input buffers except the NCS and NOE input buffers. If this signal is not used it must be connected
to VDD. This signal is asynchronous. The HX6408 may be ordered without the sleep mode option
and pin 36 is then a NC.
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HX6408
Advanced Information
TRUTH TABLE
NCS NSL NWE
NOE
L
X
X
X
Mode
Read
Write
DQ
L
L
H
H
X
L
H
L
Data Out
Data In
High Z
High Z
H
X
X
X
Deselected
Sleep
X: VI = VIH or VIL,
NOE=H:
High Z output state maintained for NCS=X, NWE=X
RADIATION
significantly exceed the normal operating levels. The
application design must accommodate these effects.
Total Ionizing Radiation Dose
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature
range after the specified total ionizing radiation dose.
All electrical and timing performance parameters will
remain within specifications. Total dose hardness is
assured by wafer level testing of process monitor
transistors and RAM product using 10 KeV X-ray.
Transistor gate threshold shift correlations have been
made between 10 KeV X-rays applied at a dose rate of
1x105 rad(SiO2)/min at T= 25°C and gamma rays
(Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Neutron Radiation
The SRAM will meet any functional or timing
specification after exposure to the specified neutron
fluence under recommended operating or storage
conditions. This assumes an equivalent neutron energy
of 1 MeV.
Soft Error Rate
The SRAM is capable of meeting the specified Soft
Error Rate (SER), under recommended operating
conditions.
This hardness level is defined by the Adams 90%
worst case cosmic ray environment for
geosynchronous orbits.
Transient Pulse Ionizing Radiation
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient
dose rate upset specification, when applied under
recommended operating conditions. It is recommended
to provide external power supply decoupling capacitors
to maintain VDD voltage levels during transient events.
The SRAM will meet any functional or electrical
specification after exposure to a radiation pulse up to
the transient dose rate survivability specification, when
applied under recommended operating conditions.
Note that the current conducted during the pulse by the
RAM inputs, outputs, and power supply may
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under
recommended operating conditions. Fabrication with
the SOI substrate material provides oxide isolation
between adjacent PMOS and NMOS transistors and
eliminates any potential SCR latchup structures.
Sufficient transistor body tie connections to the p- and
n-channel substrates are made to ensure no
source/drain snapback occurs.
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HX6408
Advanced Information
RADIATION HARDNESS RATINGS (1)
Parameter
Limits (2)
Units
rad(SiO2)
Test Conditions
≥3X105
≥1X106
≥1X1010
TA=25°C
Total Dose
Transient Dose Rate Upset
rad(Si)/s
rad(Si)/s
Pulse width ≤50 ns
VDD>3.6V, TA=25°C
≥1X1012
Pulse width ≤50 ns, X-
ray,VDD=3.6V,
TA=25°C
Transient Dose Rate Survivability
<1X10-10
Upsets/bit-day
N/cm2
TA= 85°C, Adams 90%
worst case environment
Soft Error Rate
≥1X1014
1MeV equivalent
energy, Unbiased,
TA=25°C
Neutron Fluence
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=3.0V to 3.6V, TA=-55oC to 125oC
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Parameter
Rating
Units
Min
-0.5
-0.5
-65
Max
4.6
VDD+0.5
150
VDD
VPIN
TSTORE
TSOLDER
PD
IOUT
VPROT
ΘJC
Supply Voltage Range (2)
Voltage on Any Pin (2)
V
V
°C
°C
W
mA
V
°C/W
Storage Temperature (Zero Bias)
Soldering Temperature (5 seconds)
Maximum Power Dissipation (3)
DC or Average Output Current
EST Input Protection Voltage (4)
Thermal Resistance (Jct-to-Case)
270
2.5
25
2000
36 Pin FP
2
TJ
Junction Temperature
175
°C
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is
not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this
specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DSEC certified lab.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Description
Units
Min
3.0
-55
Typ
3.3
25
Max
3.6
125
VDD+0.3
50
VDD
TA
VPIN
Supply Voltage (referenced to VSS)
Ambient Temperature
Voltage on Any Pin (referenced to VSS)
VDD Turn on ramp time
V
°C
V
-0.3
VDDRAMP
ms
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HX6408
Advanced Information
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Worst Case (1)
Min
Units
Test Conditions
Max
IDDSB
Static Supply Current
TA=25°C
TA=125°C
Static Supply Current
5
10
24
mA
mA
VDD=max, Iout=0mA,
Inputs Stable
IDDOP3
VDD=max, Iout=0mA,
f=fmax, NSL=NCS=VIH (2)
Deselected
IDDOPW
Dynamic Supply Current,
Selected (Write)
1 MHz
9
18
89
160
260
mA/MHz
mA/MHz
VDD=max, Iout=0mA,
NSL=VIH, NCS=VIL (1)
2 MHz
10 MHz
25 MHz
40 MHz
IDDOPR
Dynamic Supply Current,
Selected (Read)
1 MHz
2 MHz
4
8
VDD=max, Iout=0mA,
NSL=VIH, NCS=VIL (1)
10 MHz
25 MHz
40 MHz
40
100
160
1.5
IDDOP1
IDDOP2
Dynamic Supply Current,
Deselected
mA
mA
VDD=max, Iout=0mA,
f=1MHz, NSL=VIH (2)
VDD=max, Iout=0mA,
f=1MHz, NSL=VIL (2)
Dynamic Supply Current,
Sleep
0.2
II
Input Leakage Current
Output Leakage Current
-5
5
µA
µA
Vss VI VDD
IOZ
-10
10
Vss VIO
VDD output = high Z
VDD=3.0V
VDD=3.6V
VDD=3.0V, IOL = 8mA
VDD=3.0V, IOH = 4mA
VIL
VIH
VOL
VOH
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
0.3xVDD
0.4
V
V
V
V
0.7xVDD
2.7
(1) Worst case operating conditions: VDD=3.0V to 3.6V, -55°C to +125°C, post total dose at 25°C.
(2) All inputs switching. DC average current.
CAPACITANCE (1)
Symbol
Parameter
Worst Case (1)
Units
Test Conditions
Min
Max
9
8
CI
CO
Input Capacitance
Output Capacitance
pF
pF
VI=VDD or VSS, f=1 MHz
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
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HX6408
Advanced Information
DATA RETENTION CHARACTERISTICS
Symbol Parameter
Typical
(1)
Worst Case (2)
Units Test Conditions
Min
Max
VDR
IDR
Data Retention Voltage
Data Retention Current
2.0
V
NCS=VDR
VI=VDR or VSS
NCS=VDD=VDR
VI=VRD or VSS
3
mA
(1) Typical operating conditions: TA=25°C, pre-radiation.
(2) Worst case operating conditions: TA=-55°C to +125°C, post dose at 25°C
TESTER EQUIVALENT LOAD CIRCUIT
Valid High
Output
1.9V
V1
V2
249
Valid Low
Output
DUT
Output
CL < 50 pf *
* CL = 5pf for TWQZ, TSHQZ, TPLQZ, and TGHQZ
Tester AC Timing Characteristics
Input Levels *
VDD
VSS
* Input rise and fall times <5 ns.
Output Sense
VDD/2
High Z
VDD – 0.4V
0.4V
High Z = VDD/2
(VDD/2) + 0.2V
High Z
(VDD/2) - 0.2V
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HX6408
Advanced Information
ASYCHRONOUS READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
-55 to 125°C
Symbol
Parameter
Typical
(2)
Units
Min
20
Max
TAVAVR
TAVQV
Address Read Cycle Time
Address Access Time
300KRad
1MRad
ns
ns
25
300KRad
1MRad
20
25
TAXQX
TSLQV
Address Change to Output Invalid Time
Chip Select Access Time
3
4
5
0
ns
ns
300KRad
1MRad
20
25
TSLQX
TSHQZ
TPHQV
TPHQX
TPLQZ
TGLQV
TGLQX
TGHQZ
Chip Select Output Enable Time
Chip Select Output Disable Time
Sleep Enable Access Time
ns
ns
ns
ns
ns
ns
ns
ns
8
25
Sleep Enable Output Enable Time
Sleep Enable Output Disable Time
Output Enable Access Time
10
5
Output Enable Output Enable Time
Output Enable Output Disable Time
5
(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in
the Tester AC Timing Characteristics table, capacitive output loading CL≥50 pF, or equivalent capacitive output loading CL=5 pF for
TSHQZ, TPLQZ TGHQZ. For CL>50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=3.3V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=3.0V to 3.6V, TA=-55°C to 125°C, post total dose 25°C at
TAVAVR
ADDRESS
TAVQV
TAXQX
TSLQV
NCS
TSLQX
TSHQZ
HIGH
IMPEDANCE
DATA VALID
DATA OUT
TPHQX
TPLQZ
TPHQV
NSL
TGLQX
TGLQV
TGHQZ
NOE
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HX6408
Advanced Information
ASYNCHRONOUS WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
-55 to 125°C
Symbol
TAVAVW
TWLWH
TSLWH
TDVWH
TAVWH
Parameter
Typical
(2)
Units
ns
Min
20
25
15
20
16
20
12
15
20
25
0
Max
Write Cycle Time (4)
300KRad
1MRad
Write Enable Write Pulse Width
Chip Select to End of Write Time
Data Valid to End of Write Time
Address Valid to End of Write Time
300KRad
1MRad
ns
300KRad
1MRad
ns
300KRad
1MRad
ns
300KRad
1MRad
ns
TWHDX
TAVWL
TWHAX
TWLQZ
TWHQX
TWHWL
Data Hold after End of Write Time
ns
ns
ns
ns
ns
ns
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Write Enable to Output Disable Time
Write Disable to Output Enable Time
0
0
7
4
5
Write Disable to Write Enable Pulse Width (5)
(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in
the Tester AC Timing Characteristics table, capacitive output loading ≥50 pF, or equivalent capacitive load 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=3.3V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=3.0V to 3.6V, -55°C to 125°C, post total dose 25°C
(4) TAVAVW = TWLWH + TWHWL
(5) Guaranteed but not tested
TAVAVW
ADDRESS
TAVWH
TWHAX
TAVWL
TWHWL
TWLWH
NWE
TWHQX
TWLQZ
HIGH
IMPEDANCE
DATA OUT
DATA IN
NCS
TWHDX
TDVWH
DATA VALID
TSLWH
TPHWH
NSL
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HX6408
Advanced Information
DYNAMIC ELECTRICAL CHARACTERISTICS
be delayed. Any address edge transition, which
occurs during the time when NSL is high will initiate a
new read access, and data outputs will not become
valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance
state TPLQZ time following a disabling NSL edge
transition.
Asynchronous Operation
The RAM is asynchronous in operation. Read and
Write cycles are controlled by NWE, NCS, NSL, and
Address signals.
Read Operation
To perform a valid read operation, both chip select
and output enable (NOE) must be low and not sleep
(NSL) and write enable (NWE) must be high. The
output drivers can be controlled independently by the
NOE signal.
Write Operation
To perform a write operation, both NWE and NCS
must be low, and NSL must be high.
To perform consecutive read operations, NCS is
required to be held continuously low, NSL held
continuously high, and the toggling of the addresses
will start the new read cycle.
Consecutive write cycles can be performed by
toggling one of the control signals while the other
remains in their “write” state (NWE or NCS held
continuously low, or NSL held continuously high). At
least one of the control signals must transition to the
opposite state between consecutive write operations.
It is important to have the address bus free of noise
and glitches, which can cause inadvertent read
operations. The control and address signals should
have rising and falling edges that are fast (<5 ns) and
have good signal integrity (free of noise, ringing or
steps associated reflections).
The write mode can be controlled via three different
control signals: NWE, NCS, and NSL. All three modes
of control are similar, except the NCS and NSL
controlled modes actually disable the RAM during the
write recovery pulse. NSL fully disables the RAM
decode logic and input buffers for power savings.
Only the NWE controlled mode is shown in the table
and diagram on the previous page for simplicity;
however, each mode of control provides the same
write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in
the write cycle table or diagram, but indicate which
control pin is in control as it switches high or low. To
write data into the RAM, NWE and NCS must be held
low and NSL must be held high for at least
For an address activated read cycle, NCS and NSL
must be valid prior to or coincident with the address
edge transition(s). Any amount of toggling or skew
between address edge transitions is permissible;
however, data outputs will become valid TAVQV time
following the latest occurring address edge transition.
The minimum address activated read cycle time is
TAVAV. When the RAM is operated at the minimum
address activated read cycle time, the data outputs
will remain valid on the RAM I/O until TAXQX time
following the next sequential address transition.
WLWH/TSLSH/TPHPH time. Any amount of edge
skew between the signals can be tolerated, and any
one of the control signals can initiate or terminate the
write operation. The DATA IN must be valid TDVWH
time prior to switching high.
To control a read cycle with NCS, all addresses and
NSL must be valid prior to or coincident with the
enabling NCS edge transition. Address or NSL edge
transitions can occur later than the specified setup
times to NCS; however, the valid data access time will
be delayed. Any address edge transition, which
occurs during the time when NCS is low, will initiate a
new read access, and data outputs will not become
valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance
state TSHQZ time following a disabling NCS edge
transition.
For consecutive write operations, write pulses (NWE)
must be separated by the minimum specified
WHWL/TSHSL/TPLPL time. Address inputs must be
valid at least TAVWL/TAVSL/TAVPH time before the
enabling NWE/NCS/NSL edge transition, and must
remain valid during the entire write time. A valid data
overlap of write pulse width time of TDVWH/TDVSH/
TDVPL, and an address valid to end of write time of
TAVWH/TAVSH/TAVPL also must be provided for
during the write operation. Hold times for address
inputs and data inputs with respect to the disabling
NWE/NCS/NSL edge transition must be a minimum of
TWHAX/TSHAX/TPLPX time and TWHDX/TSHDX
To control a read cycle with NSL, all addresses and
NCS must be valid prior to or coincident with the
enabling NSL edge transition. Address or NCS edge
transitions can occur later than the specified setup
times to NSL; however, the valid data access time will
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HX6408
Advanced Information
/TPLDX time, respectively. The minimum write cycle
time is TAVAV.
QUALITY AND RADIATION HARDNESS ASSURANCE
Honeywell maintains a high level of product integrity
through process control, utilizing statistical process
control, a complete
need to create detailed specifications and offer
benefits of improved quality and cost savings through
standardization.
“Total Quality Assurance System,” a computer data
base process performance tracking system and a
radiation-hardness assurance strategy.
RELIABILITY
Honeywell understands the stringent reliability
requirements for space and defense systems and has
extensive experience in reliability testing on programs
of this nature. This experience is derived from
comprehensive testing of VLSI processes. Reliability
attributes of the RICMOS™ SOI process were
characterized by testing specially designed irradiated
and non-irradiated test structures from which specific
failure mechanisms were evaluated. These specific
mechanisms included, but were not limited to, hot
carriers, electromigration and time dependent
dielectric breakdown. This data was then used to
make changes to the design models and process to
ensure more reliable products.
The radiation hardness assurance strategy starts with
a technology that is resistant to the effects of
radiation. Radiation hardness is assured on every
wafer by irradiating test structures as well as SRAM
product, and then monitoring key parameters, which
are sensitive to ionizing radiation. Conventional MIL-
STD-883 TM 5005 Group E testing, which includes
total dose exposure with Cobalt 60, may also be
performed as required. This Total Quality approach
ensures our customers of a reliable product. It starts
with process development and continuing through
product qualification and screening.
SCREENING LEVELS
In addition, the reliability of the RICMOS™ SOI
process and product in a military environment is
monitored by testing
irradiated and non-irradiated circuits in accelerated
dynamic life test conditions. Packages were qualified
for product use after undergoing Groups B & D testing
as outlined in MIL-STD-883, TM 5005, Class S.
Quality conformance testing is performed as an option
on all production lots to ensure the ongoing reliability
of the product.
Honeywell offers several levels of device screening to
meet your system needs. “Engineering Devices” are
available with limited performance and screening for
operational evaluation testing. Hi-Rel Level B and S
devices undergo additional screening per the
requirements of MILSTD-883. As a QML supplier,
Honeywell also offers QML Class Q and V devices
per MIL-PRF-38535 and are available per the
applicable Standard Microcircuit Drawing (SMD). QML
devices offer ease of procurement by eliminating the
PACKAGING
available as NC to conform to commercial
standards. All NC (no connect) pins should be
connected to VSS to prevent charge build up in
the radiation environment.
The 512K x 8 SRAM is offered in a commercially
compatible 36-lead flat pack. This package is
constructed of multi-layer ceramic (Al2O3) and
contains internal power and ground planes.
Parentheses denote pin options. These pins are
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HX6408
Advanced Information
PACKAGE OUTLINE
COMMON DIMENSIONS
SYM
A
A1
B
C
D
E
E1
L
MIN.
.102
.085
.016
.004
.910
.045
.832
-----
NOM.
.113
.095
.018
.006
.920
.050
.840
.450
.104
MAX.
.125
.105
.020
.008
.930
.055
.848
-----
Q
-----
-----
ORDERING INFORMATION (1)
H
X
6408
X
S
H
N
SCREEN LEVEL
V = QML Class V Equivalent (4)
Q = QML Class Q Equivalent (4)
S = Level S
MODE (3)
PART NUMBER
N = Non-Sleep Mode
M = Sleep Mode
PROCESS
X = SOI
E = Eng. Model (2)
Source
H = Honeywell
TOTAL DOSE HARDNESS
R = 1x105 rad (SiO2)
PACKAGE DESIGNATION
X = 36 Lead FP
K = Known Good Die
- = Bare Die (no package)
F = 3x105 rad (SiO2)
H = 1x106 rad (SiO2)
N = No Level Guaranteed (2)
(1) Orders may be faxed to 763-954-2051. Please contact our Customer Service Representative at 763-954-2888 for further information.
(2) Engineering Device Description: Parameters are tested -55°C to 125°C, 24 hour burn-in, IDDSB = 10 mA, no radiation Guaranteed.
(3) With the Non-Sleep Mode option, Pin 36 is a no-connect (NC), and is not wirebonded to the chip. With the Sleep Mode, Pin 36 has the
NSL function.
(4) These devices are screened to QML levels but are not QML certified.
For more information about Honeywell’s family of radiation hardened integrated circuit products and services,
visit www.myspaceparts.com.
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any
liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of
others.
Honeywell International Inc.
Aerospace Electronics Systems
Defense & Space Electronics Systems
12001 Highway 55
Form #900918
June 2005
©2005 Honeywell International Inc.
Plymouth, MN 55441
1-800-323-8295
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