HX6408KQFM25 [HONEYWELL]
Standard SRAM, 512KX8, 25ns, CMOS, DIE;
| 型号： | HX6408KQFM25 |
| 厂家： | 
Honeywell |
| 描述： | Standard SRAM, 512KX8, 25ns, CMOS, DIE 静态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：492K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HX6408
512K x 8 STATIC RAM
The monolithic 512K x 8 Radiation Hardened Static
RAM is a high performance 524,288 word x 8-bit
static random access memory. It is fabricated with
Honeywell’s radiation hardened technology. It is
QML qualified and is designed for use in systems
operating in radiation environments. The SRAM
operates over the full military temperature range and
requires only a single 3.3V power supply. The SRAM
is available with CMOS compatible I/O. Power
consumption is typically 710mW at 40MHz operation
and less than 5mW when de-selected.
SRAM
operation is fully asynchronous, with a typical access
time of 20ns. It is available in package and known
good die forms.
The memory cell is single event upset hardened,
while multi-layer metal power busing and small
collection volumes of SOI provides superior single
event effect and dose rate hardening.
Honeywell’s enhanced SOI RICMOS™ V (Radiation
Insensitive CMOS) technology is radiation hardened
through the use of advanced and proprietary design,
layout, and process hardening techniques. The
RICMOS™ V low power process is a 3.3V, SOI
CMOS technology with an 80 angstrom gate oxide
and a minimum drawn feature size of 0.35um.
FEATURES
Fabricated with RICMOSTM
Silicon on Insulator (SOI)
V
Total Dose 1x106 rad(Si)
Latchup Immune
Soft Error Rate
VDD Power Supply
0.35um Low Power Process
1x10-10 upsets/bit-day
3.3V
(Leff = 0.28um)
Neutron Irradiation 1x1014 n/cm2
Operating Temperature Range
High Speed
-55°C to +125°C
20ns Typical Write Cycle
20ns Typical Read Cycle
Dose Rate Upset
1x1010 rad(Si)/s
Optional Low Power Sleep Mode
Asynchronous Operation
CMOS Compatible I/O
Dose Rate Survivability
36-Lead Ceramic Flat Pack
1x1012 rad(Si)/s
Package
QML Qualified
SMD 5962-06203
HX6408
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
A[0-18]
Row
Memory Array
Driver
Column
Decoder
NWE
NOE
NSL
NCS
DQ[0-7]
36 LEAD FLAT PACK PINOUT
HX6408
Top View
A0
A1
1
2
3
4
5
6
7
8
9
36 NSL
35 A18
34 A17
33 A16
32 A15
31 NOE
30 D4
A2
A3
A4
NCS
D0
D1
29 D5
VDD
28 VSS
27 VDD
26 D6
VSS 10
D2 11
D3 12
NWE 13
A5 14
A6 15
A7 16
A8 17
A9 18
25 D7
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC*
* NC pin must be connected to VSS.
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HX6408
PIN NAME DEFINITIONS
Pin
Timing Definition
Name
A[0-18]
DQ[0-7]
Symbol
A
Address input pins. Selects a particular 8-bit word within the memory array.
Bi-directional data I/O pins. Data inputs (D) during a write operation. Data outputs (Q) during
a read operation.
D
Q
NCS
S
Negative chip select. Low allows normal read or write operation. High puts the SRAM into a
deselected condition and holds the data output drivers in a high impedance (High-Z) state. If
not used, it must be connected to VSS.
NWE
NOE
W
G
Negative write enable. Low activates a write operation and holds the data output drivers in a
high impedance (High-Z) state. High allows normal read operation.
Negative output enable. High holds the data output drivers in a high impedance (High-Z)
state. Low the data output driver state is defined by NCS, NSL and NWE. If not used, it must
be connected to VSS.
NSL
P
Not Sleep. High allows normal read or write operation. Low puts the SRAM into a deselected
condition and holds the data output drivers in a high impedance (High-Z) state and disables all
the input buffers except the NCS and NOE input buffers. If not used, it must be connected to
VDD. The HX6408 may be ordered without the sleep mode option and pin 36 is then a no-
connect (NC) and must be connected to VSS.
VDD
VSS
Power input. Supplies power to the SRAM.
Ground
TRUTH TABLE
NCS
NSL
NWE
NOE
Mode
Sleep
DQ Mode
High-Z
X
H
L
L
L
L
X
X
H
H
L
X
X
L
H
Deselected
Read
High-Z
H
Data Out
High-Z
H
H
X
Read Standby
Write
H
Data In
Available Device Types: Total Dose / Sleep Mode / Access Time
Device Type
Total Dose
(rad(Si))
3x105
Sleep Mode
Access Time
(ns)
01
02
03
04
05
Non-Sleep
Non-Sleep
Sleep
25
20
25
20
25
3x105
3x105
3x105
1x106
Sleep
Non-Sleep
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HX6408
ABSOLUTE MAXIMUM RATINGS (1)
Symbol
Parameter
Ratings
Unit
Min
-0.5
-0.5
Max
VDD
Positive Supply Voltage Referenced to VSS
Voltage on Any Input or Output Pin Referenced to VSS
Average Output Current
4.6
V
V
VIO
VDD + 0.5
25
IOUT
TSTORE
mA
C
C
W
Storage Temperature
-65
150
TSOLDER (2) Soldering Temperature
270
PD
(3) Package Power Dissipation
2.5
PJC
VHBM
TJ
Package Thermal Resistance (Junction to Case)
Electrostatic Discharge Protection Voltage (Human Body Model)
Junction Temperature
2.0
C/W
V
2000
175
C
(1) Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only and
operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Maximum soldering temperature can be maintained for no more than 5 seconds.
(3) IDDSB power + IDDOP power + Output driver power due to external loading must not exceed this specification.
RECOMMENDED OPERATING CONDITIONS (1)
Symbol
Parameter
Limits
Unit
Min
3.0
Typ
3.3
25
Max
3.6
VDD
TC
Positive Supply Voltage Referenced to VSS
Case Temperature
V
C
V
-55
125
VIO
Voltage on Any Input or Output Pin Referenced to VSS
VDD Power Supply Ramp Rate
-0.3
VDD + 0.3
50
TRAMP
ms
(1) Specifications listed in datasheet apply when operated under the Recommended Operating Conditions unless otherwise specified.
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HX6408
RADIATION HARDNESS RATINGS (1)
Symbol
Parameter
Environment Conditions
Limits
3x105
1x106
1x1010
1x1012
1x10-10
Unit
TID
Total Ionizing Dose, F-Level
Total Ionizing Dose, H-Level
Transient Dose Rate Upset
Transient Dose Rate Survivability
rad(Si)
rad(Si)
DRU
DRS
Pulse width ≤20ns
Pulse width ≤20ns
rad(Si)/s
rad(Si)/s
SER (2) Projected Soft Error Rate
Geosynchronous orbit during solar
minimum non-flare conditions
behind 100mil Aluminum shield
upsets/bit-day
Neutron Irradiation Damage
1 MeV equivalent energy
1x1014
n/cm2
(1) Device will not latchup when exposed to any of the specified radiation environments.
(2) Calculated using CREME96.
RADIATION CHARACTERISTICS
Total Ionizing Dose Radiation
data during and after exposure to a transient dose
rate ionizing radiation pulse, up to the DRU
specification. The SRAM will also meet functional and
timing specifications after exposure to a transient
dose rate ionizing radiation pulse up to the DRS
specification.
The SRAM radiation hardness assurance TID level
was qualified by 60Co testing, including overdose and
accelerated annealing, per MIL-STD-883 Method
1019. Ongoing assurance is provided by wafer level
X-ray testing during manufacturing.
Single Event Soft Error Rate
Neutron Irradiation Damage
Special process, memory cell, circuit and layout
design considerations are included in the SRAM to
minimize the impact of heavy ion and proton radiation
and achieve small projected SER. These techniques
sufficiently harden the SRAM such that cell
redundancy and scrubbing are not required to
achieve the projected SER.
SOI CMOS is inherently tolerant to damage from
neutron irradiation. The SRAM meets functional and
timing specifications after exposure to the specified
neutron fluence.
Latchup
The SRAM will not latchup when exposed to any of
the above radiation environments when applied
under recommended operating conditions. SOI
CMOS provides oxide isolation between adjacent
PMOS and NMOS transistors and eliminates any
potential SCR latchup structures.
Transient Dose Rate Ionizing Radiation
Many aspects of product design are addressed to
handle the high energy levels associated with the
transient dose rate events. This allows the SRAM to
be capable of writing, reading, and retaining stored
PIN CAPACITANCE (1)
Symbol
Parameter
Max
11
Unit
pF
CIN
Input Capacitance
Data I/O Capacitance
CDQ
9
pF
(1) Maximum capacitance is verified as part of initial qualification only.
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HX6408
POWER PIN ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Max Unit
IDDSB
Static
Supply Current
VIH = VDD,
VIL = VSS,
DQ = High-Z
10
mA
IDDOPW
IDDOPR
(1)(2) Dynamic
VIH = VDD,
VIL = VSS,
DQ = High-Z
1MHz
9
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply Current
Selected, Write
2MHz 17.9
10MHz 89
25MHz 160
40MHz 260
(1)(2) Dynamic
VIH = VDD,
VIL = VSS,
DQ = High-Z
1MHz
2MHz
4.4
9
Supply Current
Selected, Read
10MHz
40
25MHz 100
40MHz 160
IDDOPD1 (1)(2) Dynamic
Supply Current
VIH = VDD,
VIL = VSS,
NSL = VIH,
DQ = High-Z
1MHz
1.5
0.2
24
Deselected
IDDOPD2 (1)(2) Dynamic
Supply Current
VIH = VDD,
VIL = VSS,
NSL = VIL,
DQ = High-Z
1MHz
mA
mA
Sleep
IDDOPD3 (1)(2) Dynamic
Supply Current
VIH = VDD,
VIL = VSS,
NWE = VIH,
NSL = VIH,
DQ = High-Z
40MHz
Deselected
IDR
Data Retention
Supply Current
VDD = 2.0V
3
mA
(1) All inputs switching. DC average current.
(2) All dynamic operating mode current measurements (IDDOPx) exclude standby mode current (IDDSB). The total power is the
sum of the power from the standby current (IDDSB), dynamic current (IDDOPx) and output driver current driving the output load.
SIGNAL PIN ELECTRICAL CHARACTERISTICS (1)
Symbol
Parameter
Conditions
Min
-5
Max
Unit
uA
uA
V
IIN
Input Leakage Current
Output Leakage Current
Low-Level Input Voltage
High-Level Input Voltage
Low-Level Output Voltage
High-Level Output Voltage
VSS ≤ VIN ≤ VDD
DQ = High-Z
5
10
IOZ
-10
VIL
0.3 x VDD
VIH
0.7 x VDD
2.7
V
VOL
IOL = 8mA
0.4
V
VOH
IOH = -4mA
V
(1) Voltages referenced to VSS.
6
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HX6408
READ CYCLE TIMING CHARACTERISTICS (1)(2)
Symbol
Parameter
Limits
Limits
Unit
Devices
(02, 04)
Devices
(01, 03, 05)
Min
Max
Min
Max
TAVAVR
TAVQV
TAXQX
TSLQV
TSLQX
TSHQZ
TPHQV
TPHQX
TPLQZ
TGLQV
TGLQX
TGHQZ
Read Cycle Time
20
5
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Output Valid Access Time
Address Change to Output Invalid Time
Chip Select to Output Valid Access Time
Chip Select to Output Low-Z Time
20
25
25
5
4
20
4
Chip Select to Output High-Z Time
4
4
(3) Sleep Enable to Output Valid Access Time
(3) Sleep Enable to Output Low-Z Time
(3) Sleep Enable to Output High-Z Time
Output Enable to Output Valid Access Time
Output Enable to Output Low-Z Time
Output Enable to Output High-Z Time
25
25
5
5
10
5
10
5
0.4
0.4
3
3
(1) The timing specifications are referenced to the Timing Input / Output References diagrams and the
Timing Reference Load Circuit diagrams. IBIS models should be used to evaluate timing under application load and conditions.
(2) NWE = High
(3) Sleep Mode parameters only apply to device types 03 and 04.
READ CYCLE TIMING WAVEFORMS
TAVAVR
A
TAVQV
TSLQV
TAXQX
NCS
Q
TSHQZ
TSLQX
HIGH-Z
DATA VALID
TPHQX
TPHQV
TPLQZ
NSL
NOE
TGLQX
TGLQV
TGHQZ
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HX6408
WRITE CYCLE TIMING CHARACTERISTICS (1)(2)(3)
Symbol
Parameter
Limits
Limits
Unit
Devices
(02, 04)
Devices
(01, 03, 05)
Min
Max
Min
25
25
20
25
15
25
0
Max
TAVAVW
TWLWH
TSLWH
TPHWH
TDVWH
TAVWH
TWHDX
TAVWL
TWHAX
TWLQZ
TWHQX
TWHWL
Write Cycle Time
20
15
16
25
12
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Start of Write to End of Write Pulse Width
Chip Select to End of Write Time
(4) Sleep Disable to End of Write Time
Data Input Valid to End of Write Time
Address Valid to End of Write Time
Data Input Hold after End of Write Time
Address Valid Setup to Start of Write Time
Address Valid Hold after End of Write Time
Start of Write to Output High-Z Time
End of Write to Output Low-Z Time
(5) End of Write to Start of Write Pulse Width
0
0
0
0
6
6
6
5
6
5
(1) The timing specifications are referenced to the Timing Input / Output References diagrams and the
Timing Reference Load Circuit diagrams. IBIS models should be used to evaluate timing under application load and conditions.
(2) For an NWE controlled write, NCS must be Low and NSL must be High when NWE is Low.
(3) Can use NOE = High to hold Q in a High-Z state when NWE = High, NCS = Low and NSL = High.
(4) Sleep Mode parameters only apply to device types 03 and 04.
(5) Guaranteed but not tested.
WRITE CYCLE TIMING WAVEFORMS
TAVAVW
A
TAVWH
TWLWH
TWHAX
TAVWL
TWHWL
NWE
Q
TWHQX
TWLQZ
HIGH-Z
TDVWH
TWHDX
TSHQZ
HIGH-Z
D
DATA VALID
TSLQX
TPHQX
TSLWH
TPHWH
NCS
NSL
TPLQZ
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HX6408
TIMING REFERENCE LOAD CIRCUIT
TIMING INPUT / OUTPUT REFERENCES
VDD/2
Input
Levels (1)
VDD
90%
10%
90%
10%
VDD/2 (2)
50ohm
VSS
Zo = 50ohm
DUT
Output
30pF (1)
Output
Levels
VDD/2 (2)
High-Z (4)
Notes
(1) Set to 5pF for T*QZ (Low-Z to High-Z)
timing parameters.
VOHss - 0.1V (2)(3)
VOLss + 0.1V (2)(3)
VOHss - 0.1V (2)(3)
VOLss + 0.1V (2)(3)
High-Z (4)
Notes
(1) Input rise and fall times = 1ns between 90% and 10% levels.
(2) Timing parameter reference voltage level.
(3) ss: Low-Z VOH and VOL steady-state output voltage.
(4) High-Z output pin pulled to VDD/2 by Reference Load Circuit.
FUNCTIONAL DESCRIPTION
SRAM Operation
Address transition. The NCS/NSL active transition
can occur later; however, the valid Data Output (Q)
access time will then be defined by TSLQV/TPHQV
instead of TAVQV. To perform consecutive read
cycles, NCS/NSL is held continuously low/high, and
the toggling of any Address will start a new read
cycle. Any amount of toggling or skew between
Address transitions is permissible; however, Data
Output will not become valid until TAVQV following
the last occurring Address transition. The minimum
Address activated read cycle time is TAVAVR which
is the time between the last Address transition of the
previous cycle and the first Address transition of the
next cycle. The valid Data Output from a previous
cycle will remain valid until TAXQX following the first
Address transition of the next cycle.
SRAM operation is asynchronous. Operating modes
are defined in the Truth Table. Read operations can
be controlled by Address (A), Sleep (NSL) or Chip
Select (NCS). Write operations can be controlled by
Write Enable (NWE), Sleep (NSL) or Chip Select
(NCS).
Read Operation
A read operation occurs when Chip Select (NCS) is
low and Sleep (NSL) and Write Enable (NWE) are
high. The output drivers are controlled independently
by the Output Enable (NOE) signal.
To control a read cycle with NCS/NSL where
TSLQV/TPHQV is the access time, all addresses
must be valid TAVQV minus TSLQV/TPHQV prior to
the enabling NCS/NSL transition. Address transitions
can occur later; however, the valid Data Output (Q)
access time will then be defined by TAVQV instead of
TSLQV/TPHQV. NCS/NSL can disable the read at
any time; however, Data Output drivers will enter a
High-Z state TSHQZ/TPLQZ later.
Write Operation
A write operation occurs when Write Enable (NWE)
and Chip Select (NCS) are low and Sleep (NSL) is
high. The write mode can be controlled via three
different control signals: NWE, NCS or NSL can start
the write mode and end the write mode, but the write
operation itself is defined by the overlap of NWE low,
NCS low and NSL high. All three modes of control
are similar, except the NCS and NSL controlled
To control a read cycle with Address where TAVQV
is the access time, NCS/NSL must transition to active
TSLQV/TPHQV minus TAVQV prior to the last
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HX6408
modes deselect the SRAM when NCS is high or NSL
is low between writes.
Consecutive write cycles are performed by toggling at
least one of the start of write control signals for
TWHWL/TSHSL/TPLPH. If only one of these signals
is used, the other two must be in their write enable
states. The minimum write cycle time is
TAVAVW/TAVAVS/TAVAVP.
To write Data (D) into the SRAM, NWE and NCS
must be held low and NSL must be held high for at
least TWLWH, TSLSH and TPHPL respectively. Any
amount of skew between these signal transitions can
be tolerated, and any one of these control signals can
start or end the write operation as long as there is
sufficient overlap in these signals to ensure a valid
write time (e.g., TSLWH, TWLSH, TPHWH and
TWLPL).
Signal Integrity
As a general design practice, one should have good
signal integrity which means input signals that are
free of noise, glitches and ringing with rising and
falling edges of ≤10ns. More specifically, an input is
considered to have good signal integrity when the
input voltage monotonically traverses the region
between VIL and VIH in ≤10ns. This is especially
important in a selected and enabled state. When the
device is selected and enabled, the last transitioning
input for the desired operation must have good signal
integrity to maintain valid operation. The transitioning
inputs that bring the device into and out of a selected
and enabled state must also have good signal
integrity to maintain valid operation. When the device
is deselected and/or disabled, inputs can have poor
signal integrity and even float as long as the inputs
that are defining the deselected and/or disabled state
stay within valid VIL and VIH voltage levels.
However, floating inputs for an extended period of
time is not recommended.
Address inputs must
be valid
at
least
TAVWL/TAVSL/TAVPH before the start of write and
TAVWH/TAVSH/TAVPL before the end of write and
must remain valid during the write operation. Hold
times for address inputs with respect to the end of
write must be a minimum of TWHAX/TSHAX/TPLAX.
A Data Input (D) valid to the end of write time of
TDVWH/TDVSH/TDVPL must be provided during the
write operation. Hold times for Data Input with
respect to the end of write must be at least
TWHDX/TSHDX/TPLDX. To avoid Data Input driver
contention with the SRAM output driver, the Data
Input
(D)
must
not
be
applied
until
TWLQZ/TGHQZ/TSHQZ/TPLQZ after the output
drive (Q) is put into a High-Z condition by
NWE/NOE/NCS/NSL.
10
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HX6408
RELIABILITY
SCREENING AND CONFORMANCE
INSPECTION
For many years Honeywell has been producing
integrated circuits that meet the stringent reliability
requirements of space and defense systems.
Honeywell has delivered hundreds of thousands of
QML parts since first becoming QML qualified in
1990. Using this proven approach Honeywell will
assure the reliability of the products manufactured
with the SOI CMOS process technology. This
approach includes adhering to Honeywell’s Quality
Management Plan for:
The product test flow includes screening units with
the applicable flow (Engineering Model, Class V or
equivalent, Class
appropriate periodic or lot Conformance Testing
(Groups A, B, C, D, and E). Both the wafer process
and the products are subject to periodic or lot based
Technology Conformance Inspection (TCI) / Quality
Conformance Inspection (QCI) tests as defined by
Honeywell’s Quality Management Plan.
Q
or equivalent) and the
• Designing in reliability by establishing electrical
Conformance Testing Summary
Group A General Electrical Tests
rules
based
on
wear
out
mechanism
characterization performed on specially designed
test structures (electromigration, TDDB, hot
carriers, bias temperature instability and
radiation).
Group B Mechanical – Resistance to Solvents,
Bond Strength, Die Shear, Solderability
Group C Life Tests - 1000 hours at 125C or
equivalent
• Utilizing a structured and controlled design
process.
Group D Package Related Mechanical Tests –
Physical Dimensions, Lead Integrity,
Thermal Shock, Temp Cycle, Moisture
Resistance, Seal, Mechanical Shock,
Vibration, Acceleration, Salt
• Statistically controlling wafer fabrication process
with a continuous defect reduction process.
• Performing individual wafer lot acceptance
through process monitor testing (includes radiation
testing).
Atmosphere, Internal Water Vapor,
Adhesion of Lead Finish
• Using characterized and qualified packages.
Group E Radiation Tests
• Performing thorough product testing program
based on MIL-PRF-38535 and MIL-STD 883.
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HX6408
PACKAGE FEATURES
Feature
Description
Designation
X
Type
36-lead flat pack
Body Construct
Power Planes
Lid Construct
multi-layer ceramic (Al2O3)
Yes
Kovar
VSS
Lid Electrical Connection
PACKAGE DIAGRAMS
COMMON DIMENSIONS (in.)
SYM
A
A1
B
C
D
E
E1
L
MIN.
.102
.085
.016
.004
.910
.045
.832
-----
NOM.
.113
.095
.018
.006
.920
.050
.840
.450
.104
MAX.
.125
.105
.020
.008
.930
.055
.848
-----
Q
-----
-----
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HX6408
ORDERING INFORMATION (1)
Standard Microcircuit Drawing (SMD)
The QML qualified HX6408 SRAM can be ordered under the SMD drawing 5962-06203.
Order Code
H
X
6408
X
V
H
N
25
SOURCE
H = Honeywell
PROCESS
X = SOI
PART NUMBER
6408 = 512k x 8 SRAM
PACKAGE DESIGNATION
X = 36 Lead CFP
K = Known Good Die (3)
SCREEN LEVEL
V = QML Class V
Q = QML Class Q
Z = Class V Equivalent
E = Engineering Model (2)
TOTAL DOSE HARDNESS (4)
F = 3x105 rad(Si)
H = 1x106 rad(Si)
N = No Level Guaranteed (2)
MODE (4)
N = Non-Sleep Mode
M = Sleep Mode
ACCESS TIME (4)
20 = 20ns
25 = 25ns
(1) Orders may be faxed to 763-954-2051.
Please contact our Customer Service Representative at 763-954-2474 or 1-800-323-8295 for further information.
(2) Engineering Model Description: Screen Level and Total Dose Hardness codes must be “E” and “N” respectively.
Parameters are tested -55°C to 125°C, 24 hour burn-in, no radiation hardness guaranteed.
(3) Information herein applies to packaged parts. Contact Honeywell for known good die information.
(4) See Available Device Types Table for valid part offerings.
FIND OUT MORE
For more information about Honeywell’s family of radiation hardened integrated circuit products and services, visit
www.honeywellmicroelectronics.com.
Honeywell reserves the right to make changes of any sort without notice to any and all products, technology and testing identified herein. You
are advised to consult Honeywell or an authorized sales representative to verify that the information in this data sheet is current before ordering
this product. Absent express contract terms to the contrary, Honeywell does not assume any liability of any sort arising out of the application or
use of any product or circuit described herein; nor does it convey any license or other intellectual property rights of Honeywell or of third parties.
Honeywell International Inc.
12001 Highway 55
Plymouth, MN 55441
ADS-14132 Rev C
1-800-323-8295
www.honeywellmicroelectronics.com
August 2014
©2014 Honeywell International Inc.
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