HXNV0100AZF [HONEYWELL]
Memory Circuit, 64KX16, CMOS, CQFP64, QFP-64;
| 型号： | HXNV0100AZF |
| 厂家： | 
Honeywell |
| 描述： | Memory Circuit, 64KX16, CMOS, CQFP64, QFP-64 内存集成电路 |
| 文件： | 总11页 (文件大小：1407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HXNV0100
HXNV0100 1Megabit
64K x 16 Non-Volatile Magneto-Resistive RAM
Features
n
Fabricated on S150 Silicon On
Insulator (SOI) CMOS Underlayer
Technology
n
n
150 nm Process
Total Dose Hardness 3x105 and
1x106 rad (Si)
Dose Rate Upset Hardness 1x109
rad(Si)/s
n
n
n
Dose Rate Survivability 1x1012 rad(Si)/s
Soft Error Rate 1x10-10
upsets/bit-day
n
n
n
n
n
n
n
n
n
Neutron Hardness 1x1014 N/cm2
No Latchup
Read Access Time 80 ns
Read Cycle Time 110 ns
Write Cycle Time 140 ns
Unlimited Read (> 1x1015 Cycles)
15 years Data Retention
Synchronous Operation
Single-Bit Error Detection &
Correction (ECC)
n
n
n
n
Dual Power Supplies
1.8 V 0.15V, 3.3 V 0.3V
3.3V CMOS Compatible I/O
The Honeywell 1 Megabit radiation hardened low power non-volatile Magneto-Resistive
Random Access Memory (MRAM) offers high performance and is designed for space
and military applications. The part is configured as a 65,536 word x 16 bit MRAM.
Standard Operating Temperature
Range is -40°C to +105°C
n
Package: 64 Lead Shielded
Ceramic Quad Flat Pack
The MRAM is designed for very high
reliability. Redundant write control lines,
error correction coding and low-voltage
write protection ensure the correct
operation of the memory and protection
from inadvertent writes.
fabricated with Honeywell’s radiation
hardened Silicon On Insulator (SOI)
technology, and is designed for use in
low-voltage systems operating in radiation
environments. The MRAM operates over
a temperature range of -40°C to +105°C
and is operated with 3.3 ± 0.3V and
1.8 ± 0.15V power supplies.
Integrated Power Up and Power Down
circuitry controls the condition of the
device during power transitions. It is
Simplified Functional
Block Diagram
Digit Line Drivers
A(7:15)
CS
Q
D
C
Row
Decoder
Data Array
65,536 x 16
ECC Array
65,536 x 5
ECC Logic
WE
Q
D
C
NWI
Bit Line Drivers
OE
Q
D
C
A(0:6)
Column Decoder
Data Input/Output
Read Circuit
Q
D
C
DQ(0:15)
Signal Description
Signal
A(15:0)
DQ(15:0)
CS
Definition
A(15) is MSB, A(0) is LSB.
Data Input/Output Signals. Bi-directional data pins which serve as data outputs during a read operation and as data inputs during a write operation.
Chip select. Rising edge initiates an access of memory. A(15:0), WE and DQ(15:0) are latched on the rising edge. High level required for DQ(15:0)
outputs to be enabled.
WE
Write Enable. Active high write enable. High state at rising edge of CS initiates a write cycle. Low state at rising edge of CS initiates a read cycle.
Output Enable. Active high output enable. Low state puts outputs in high impedance state.
Not Write Inhibit – When set low, these signals inhibit writes to the memory. A high level allows the memory to be written.
NWI0 controls lower order 32K A(15)=0.
OE
NWI0
NWI1
NWI1 controls the upper order 32K A(15)=1.
(Note the VIL and VIH requirements for NWI)
TESTOUT
TESTIN1
TESTIN2
TESTIN3
TESTIN4
VDD1
This pin shall be treated as a “no connect” and have no connection on the circuit board.
These signals are for Honeywell test purposes only. These must be grounded. (Failure to hold these pins low may result in
permanent loss of functionality)
DC Power Source Input: nominal 1.8V
DC Power Source Input: nominal 3.3V
VDD2
2
Package
Pinout
VDD1
GND
1
2
3
4
5
6
7
8
9
48 VSS
47 VDD2
46 ADDR(6)
45 ADDR(15)
44 WE
DQ(1)
DQ(0)
CS
NWI(0)
VDD2
VDD1
VSS
43 TESTIN4
42 OE
41 VDD2
40 VDD1
39 VSS
HXNV0100
NWI(1) 10
TESTIN3 11
TESTOUT 12
DQ(8) 13
38 ADDR(14)
37 ADDR(13)
36 ADDR(12)
35 ADDR(11)
34 VSS
DQ(9) 14
VDD2 15
VSS 16
33 VDD1
Function Truth Table
NWI
CS
R
WE
Function
Write Cycle
Read Cycle
Write Inhibited
1
X
0
1
0
1
R
R
Output Driver Truth Table
Function
CS
1
OE
1
Data Outputs
Active
Hi-Z
Read Cycle
Read Cycle
Read Cycle
Write Cycle
Write Inhibited
1
0
0
X
Hi-Z
X
X
Hi-Z
X
X
Hi-Z
3
Radiation Characteristics
RAM and ROM Functional Capability
Total Ionizing Radiation Dose
This MRAM incorporates two write control signals allowing the two
sections of the memory to be controlled independently. The two
NOT WRITE INHIBIT signals, NWI(0) and NWI(1), allow one section
of the device to operate as a RAM and the other to operate as a
ROM at the full control of the user. These signals should be hard
wired to VDD2 or ground if active control is not needed. If control
is desired, maximum 5K ohms pull up or down resistor should be
used with care taken to insure that the VIH and VIL for the NWI
pins are met.
The MRAM has a radiation hardness assurance TID level of
300 Krad(Si) and 1Mrad(Si), including overdose and
accelerated annealing per MIL-STD-883 Method 1019. Total
dose hardness is assured by qualification testing with a 60Co
source and wafer level X-ray testing during manufacturing.
Soft Error Rate
Special process, cell, circuit and layout design considerations
are included in the MRAM to minimize the impact of heavy ion
and proton radiation and achieve a very low radiation induced
Soft Error Rate (SER). Weibull parameters and other relevant
attributes are available upon request to calculate projected upset
rate performance for other orbits and environments.
SOI CMOS and Magnetic Memory Technology
Honeywell’s S150 Silicon On Insulator (SOI) CMOS is radiation
hardened through the use of advanced and proprietary design,
layout, and process hardening techniques. The S150 150 nm
SOI CMOS process is a technology supporting 1.8 V and 3.3 V
transistors. The memory element is a magnetic tunnel junction
(MTJ) that is non-volatile and composed of a magnetic storage
layer structure and a magnetic pinned layer structure separated
by an insulating tunnel barrier. During a write cycle, the storage
layer is written by the application of two orthogonal currents using
row-and-column addressing. The resistance of the MTJ depends
on the magnetic state of the storage layer structure, which uses
the pinned layer structure as a reference, and which enables
non-destructive signal sensing, amplification, and readback.
The resistance change from the memory element is a result of
the change in Tunneling Magneto-Resistance (TMR) in the MTJ
that depends on the magnetic state of the storage layer.
Transient Pulse Ionizing Radiation
Many aspects of product design are addressed to handle
the high energy levels associated with the transient dose events.
This allows the MRAM to be capable of writing, reading, and
retaining stored data during and after exposure to a transient
ionizing radiation pulse, up to the specified transient dose rate
upset specification.
The MRAM will also meet functional and electrical specifications
after exposure to a radiation pulse up to the transient dose rate
survivability specification.
Neutron Radiation
SOI CMOS is inherently tolerant of neutron radiation. The
MRAM meets functional and timing specifications after exposure
to the specified neutron fluence, based on conventional neutron
irradiation testing, on unpowered MRAM parts.
Latchup
Error Correction Code (ECC)
The MRAM will not latch up due to any of the above radiation
exposure conditions when applied under recommended operating
conditions. Fabrication with the SOI CMOS substrate material
provides oxide isolation between adjacent PMOS and NMOS
transistors and eliminates any potential SCR latchup structures.
attributes are available upon request to calculate projected upset
rate performance for other orbits and environments.
Hamming 5-Bit ECC
A 5-bit Hamming ECC is generated for all data written into
memory. This code allows for the detection and correction of all
single-bit errors per address. On a read cycle, a data word is read
from memory and corrected, if necessary, before being placed on
the output data bus.
There is no change made to the actual data in the memory cells
based on the ECC results. Actual data in memory are changed
only upon writing new values.
4
Radiation-Hardness Ratings (1)
Parameter
Limits
Units
Environment Conditions
6
Rads(Si)
Total Dose: H-Level
1 x 10
5
F-Level
3 x 10
-10
l Soft Error Rate (2):
1 x 10
Upsets/bit-day (1)
Geosynchronous orbit during solar minimum non-flare conditions
behind 100mil Aluminum shield
Pulse Width ≤ 20nS
9
Transient Dose Rate Upset
Transient Dose Rate Survivability
Neutron Fluence
1 x 10
1 x 10
Rads(Si)/s
Rads(Si)/s
12
Pulse Width ≤ 20nS
14
1x10
2
N/cm
1 MeV equivalent energy
(1) Device will not latchup when exposed to any of the specified radiation environments.
(2) Calculated using CREME96.
Magnetic Field Characteristics
The MRAM will meet all stated functional and electrical specifications over the entire operating temperature range when exposed to magnetic
fields up to the rating supplied below. Exposure to larger magnetic fields may permanently affect functionality.
Magnetic Field Rating (1)
Parameter
Limits
Units
Magnetic Field
50
Oe
(1) Tested at 25°C
Recommended Operating Conditions (1)(2)
Limits
Symbol
VDD1
Parameter
Min
1.65
3.0
Typical
Max
1.95
Units
Volts
Volts
°C
Positive Supply Voltage
Positive Supply Voltage
External Package Temperature
Voltage On Any Pin
1.80
3.3
25
VDD2
3.6
T
-40
-0.3
-55
105
C
V
VDD2+0.3
105
Volts
°C
PIN
T
Storage Temperature
25
STORE
(1) Voltages referenced to GND
(2) Specifications listed in datasheet apply when operated under the Recommended Operating Conditions unless otherwise specified.
Absolute Maximum Ratings (1)
Ratings
Symbol
VDD1
Parameter
Min
-0.5
-0.5
-0.5
Max
2.5
Units
Volts
Volts
Volts
°C
Positive Supply Voltage (2)
VDD2
Positive Supply Voltage (2)
4.6
V
Voltage on Any Pin (2)
VDD2+ 0.5
PIN
T
Maximum Junction Temperature for Sustained Exposure
Soldering Temperature
125 (6)
260°C
2.5
Exp
T
°C *sec(5)
W
SOLDER
P
P
Package Power Dissipation (3)
Package Thermal Resistance (Junction to Case)
Electrostatic Discharge Protection Voltage (Human Body Model)
Junction Temperature Silicon
MTJ Temperature
D
4.0
°C /W
V
JC
V
2000
PROT
T
175
160
90
°C
J
T
°C
MTJ
OUT
I
Max Output Current (7)
mA
(1) Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only, and operation at these levels is not implied.
Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS
(3) MRAM power dissipation due to IDDS, IDDOP, and IDDSEI, plus MRAM output driver power dissipation due to external loading must not exceed this specification
(4) Not applicable.
(5) Maximum soldering temp of 250°C can be maintained for no more than 180 seconds over the lifetime of the part.
(6) Not to exceed 24 hours duration (or equivalent at temperature using Ea = 1.235 eV)
(7) Not to exceed 1 second
Capacitance (1)
Limit
Symbol
Parameter
Max
Units
pF
C
Data I/O Capacitance
Input Capacitance
15
IO
C
12
pF
I
Not Write Inhibit Capacitance
100
pF
C
NWI(0),(1)
(1) Maximum capacitance is verified as part of initial qualification only.
5
DC Electrical Characteristics
Parameter
VIL
Symbol
Min
Max
Units
Comments
Low Level Input Voltage
High-level Input Voltage
Low Level Input Voltage (NWI Signals)
High-level Input Voltage (NWI Signals)
Low-level Output Voltage
High-level Output Voltage
Output Leakage Current
0.3*VDD2
V
V
V
All inputs except NWI
All inputs except NWI
NWI Inputs
VIH
0.7*VDD2
0.9*VDD2
VIL (NWI)
VIH (NWI)
VOL
0.5
0.5
100
10
NWI Inputs
V
V
IOL = 6 mA
VOH
VDD2-0.5
-100
IOH = -6 mA
IOZ
μA
Chip deselected or output disabled
(CS=0V, OE=0V)
II
Input Leakage Current
-10
μA
IIL : Vin=0V, IIH : Vin=VDD2
All inputs except TEST pins
IDDSB
Standby Current
VDD1 (1.95V)
12
2
mA
mA
mA
VDD2 (3.60V)
IDDOPW1
IDDOPW7
IDD2OPW1
IDD2OPW7
IDDOPR1
IDDOPR9
IDD2OPR1
IDD2OPR9
VDD1 current at 1 MHZ write frequency
(frequency of CS rising edges)
VDD1 current at 7 MHZ write frequency
(frequency of CS rising edges)
VDD2 current at 1 MHZ of write frequency
(frequency of CS rising edges)
VDD2 current at 7 MHZ of write frequency
(frequency of CS rising edges)
VDD1 current at 1 MHZ of read frequency
(frequency of CS rising edges)
VDD1 current at 9 MHZ of read frequency
(frequency of CS rising edges)
VDD2 current at 1 MHZ of read frequency
(frequency of CS rising edges)
VDD2 current at 9 MHZ of read frequency
(frequency of CS rising edges)
15
30
30
196
14
30
8
mA
mA
mA
mA
mA
mA
mA
54
Data Endurance
Ratings
Min
Parameter
Units
15
Data Read Endurance
Data Write Endurance
1x10
Cycles
Cycles
15
1x10
Data Retention
Ratings
Parameter
Min
Max
Units
Conditions
Chip Power On or Off
Data Retention
15
years
6
Read Cycle
The MRAM is synchronous in operation relative to the rising edge
of the Chip Select (CS) signal. With the initiation of a CS signal,
the address and the Write Enable (WE) signal are latched into the
device and the read operation begins. The memory locations are
read and compared with the ECC values. Any single bit errors are
detected and corrected.
If WE was low when latched in, the data word is sent to the output
drivers. In addition to WE low being latched, Output Enable (OE)
must be set to a high value to enable the DQ output buffers. OE
is not latched, and may be set high before or after the rising edge
of CS.
Read Cycle AC Timing Characteristics
Tminr
CS
Tcspi
Tadsu
Tadhd
Twehd
ADDR Valid
ADDR
Don’t Care
Don’t Care
Don’t Care
Twesu
WE
Don’t Care
Tcsdv
DQ = HiZ or Prev. Read Data
Tcshz
DQ = HiZ
DQ Valid
DQ = HiZ
Toencbrcs
Toencarcs
Toedv
Toehz
See Note 1
OE
Don’t Care
(1) If OE is held high during no change window (Toencbrcs+Toencarcs), the DQ pins will drive the previously read data after rising CS.
If OE is held low during no change window, the DQ pins will remain at HiZ.
Name
TADSU
Description
Min
5
Max
Units
Address Setup Time
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TADHD
Address Hold Time
15
5
TWESU
TWEHD
TCSDV
WE Setup Time
–
WE Hold Time
15
–
–
DQ valid with respect to rising edge of CS
OE access time
80
15
15
20
–
TOEDV
–
TOEHZ
OE de-asserted to outputs Hi z
CS de-asserted to outputs Hi z
Read Cycle Time
–
TCSHZ
–
TMINR
110
–
TCSPI
CS ignored pulse width (glitch tolerance)
OE rising or falling edge to rising CS time (1)
CS rising edge to OE rising or falling edge (1)
4
TOENCBRCS
TOENCARCS
15
65
–
–
(1) Guaranteed by design, not tested.
(2) The timing specifications are referenced to the Timing Input / Output References diagrams and the Timing Reference Load Circuit diagrams.
IBIS models should be used to evaluate timing under application load and conditions.
8
Write Cycle
The MRAM is synchronous in operation relative to the rising edge
of the Chip Select (CS) signal. With the initiation of a CS signal,
the address and the Write Enable (WE) signal are latched into
the device.
The bit cell construction of this device does not provide a method
of simply writing a “1” or a “0” to match the data. The “write” to
a bit can only change its state, thus the need to read the bit
locations first. Only the bits which need to “change state” are
actually written.
The WRITE CYCLE begins by reading the currently addressed
value in memory. The current memory data are compared to
the data to be written. If the location needs to change value,
the data are then written.
Write Cycle AC Timing Characteristics
Tminw
Tcspw, Tcspi
CS
Tdqsu
Tdqhd
DQ Valid
Data Written
DQ = HiZ
ADDR
WE
Tadsu
Tadhd
ADDR Valid
Twesu
Twehd
Tnwisu
NWI
Tnwihd
Tnwihd
To use NWI to inhibit a
WRITE operation
NWI
Tnwisu
Name
TADSU
Description
Min
5
Max
Units
ns
Address Setup Time
Address Hold Time
WE Setup Time
WE Hold Time
–
–
–
–
–
4
–
–
–
–
–
TADHD
TWESU
TWEHD
TCSPW
TCSPI
15
5
ns
ns
15
10
–
ns
CS Pulse Width (for valid write)
CS ignored pulse width (glitch tolerance)
Data Setup Time (relative to CS rising edge)
Data Hold Time (relative to CS rising edge)
NWI Setup Time
ns
ns
TDQSU
TDQHD
TNWISU
TNWIHD
TMINW
5
ns
15
-40
140
140
ns
ns
NWI Hold Time
ns
Write Cycle Time
ns
(1) The timing specifications are referenced to the Timing Input / Output References diagrams and the Timing Reference Load Circuit diagrams.
IBIS models should be used to evaluate timing under application load and conditions.
9
Power Up Timing
Screening and Conformance Inspection
The product test flow includes screening units with the applicable
flow (Engineering Model, QML V, QML Q, Class V and Q equivalent)
and the appropriate periodic or lot conformance testing (Groups A,
B, C, D, and E). Both the wafer process and the products are
subject to periodic or lot based Technology Conformance
Inspection (TCI) and Quality Conformance Inspection (QCI)
tests as defined by Honeywell’s Quality Management Plan.
During power-up there are no restrictions on which supply
comes up first provided NWI is asserted (low). NWI is de-asserted
within 1us of both supplies reaching their 90% values.
POWER UP SEQUENCE
VDD1
VDD2
1us
Conformance Summary
NWI
Group A
Group B
General Electrical Tests
Mechanical – Resistance to Solvents, Bond Strength, Die Shear,
Solderability
Power Down Timing
Group C
Group D
Life Tests – 1000 hours at 125°C or equivalent
Package related mechanical tests – Physical Dimensions, Lead Integrity,
Thermal Shock, Temp Cycle, Moisture Resistance, Seal, Mechanical
Shock, Vibration, Acceleration, Salt Atmosphere, Internal Water Vapor,
Adhesion of Lead Finish
POWER DOWN SEQUENCE
Group E
Radiation Tests
VDD1
AC Timing Input and Output References
VDD2
100ns
VIHac
90%
10%
90%
10%
Input
Levels(1)
NWI
VREF(2)
VILac
Reliability
VREF(2)
For many years Honeywell has been producing integrated circuits
that meet the stringent reliability requirements of space and defense
systems. Honeywell has delivered hundreds of thousands of QML
parts since the early 1990’s. Using this proven approach Honeywell
will assure the reliability of the products manufactured with the SOI
CMOS process technology. This approach includes adhering to
Honeywell’s Quality Management Plan for:
Output
Sense
Levels
VOHss-0.1V(2,3)
VOLss+0.1V(2,3)
High-Z(4)
VOHss-0.1V(2,3)
VOLss+0.1V(2,3)
High-Z(4)
Notes:
• Designing in reliability by establishing electrical rules based on
wear out mechanism characterization performed on specially
designed test structures (electromigration, TDDB, hot carriers,
bias temperature instability and radiation).
(1) All input rise and fall times =1ns between the 90% and 10% levels.
(2) Timing parameters reference voltage level.
(3) ss: Low_Z VOH and VOL steady-state output voltage.
(4) High-Z output pin pulled to VDD2 by Output Load Circuit.
I/O Type
VIHac
VDD2
VILac
VSS
VREF
• Utilizing a structured and controlled design process.
3.3V CMOS
VDD2/2
• Statistically controlling wafer fabrication process with a
continuous defect reduction process.
AC Timing Output Load Circuit
• Performing individual wafer lot acceptance through process
monitor testing (includes radiation testing).
VLOAD
• Using characterized and qualified packages.
50 ohms
• Performing thorough product testing program based on
MIL-PRF-38535 and MIL-STD 883.
DUT
Output
o
o
Zo=50 ohms
o
30pF (1)
Notes:
(1) Set to 5pF for T*QZ (Low-Z to High-Z)
timing parameters
I/O Type
VLOAD
3.3V CMOS
VDD2/2
10
Package Outline
The 64 Lead Shielded Ceramic QFP Package, including
external capacitors. Magnetic shielding is tied to ground
on the package.
L1
A
2
b x 64
R
A1
48
33
32
49
Pkg
X
C
L
4
E2
E1
L2 L1
E4
3
E3
TOP
SHIELD
Cavity
BOTTOM
SHIELD SQ
C
L
64
17
1
16
e
F
c
D2
D1
Controlling dimensions are in millimeters.
1.
2
Common Dimensions - Millimeters
Common Dimensions - Inches
Symbol
Min
Nom
Max
Min
Nom
Max
A is the total thickness of the top shield,
lid, seal ring, ceramic body, bottom
4.34
3.85
4.83
.151
.171
.190
A
A1
b
1.44
0.41
1.60
0.46
1.76
0.51
.057
.016
.004
.891
.063
.018
.006
.900
.750
.525
.800
.070
.020
.008
.909
.755
.530
.805
.055
shield, and shield adhesives.
c
0.10
0.15
0.20
3
No edge of the shield shall extend past
the outer edge of the lid flange.
D1/E1
D2/E2
E3
E4
e
22.63
18.92
13.21
22.86
19.05
13.34
23.09
19.18
13.46
.745
.520
.795
20.19
1.14
4.44
---
20.32
1.27
5.08
20.45
1.40
All edges of the bottom shield shall
be a minimum of 0.030" to the edge
of the ceramic body.
4
.050
.200
---
.045
.175
5.72
.225
F
L1
---
---
2.060
52.32
L2
R
1.185
.316
---
1.200
---
30.10
8.03
---
1.215
---
30.48
---
30.86
---
.066
---
X
---
1.687
11
Ordering Information (1)
H
Source
X
NV
Part Type
0100
A
Z
H
Total Dose Hardness
Process
X = SOI
Package Designation
6
H = 1x10 rad (Si)
H = Honeywell
NV = Non Volatile
A = 64 Lead QFP
F = 3x105 rad (Si)
N = No Level Guaranteed
Part Number
0100 = 1 Meg
Screen Level
Z = Class V Equivalent
E = Eng. Model (2)
(1) To order parts or obtain technical assistance, call 1-800-323-8295
(2) Engineering Model Description: Parameters are tested from -40°C to 105°C, 24-hour burn-in, no radiation guarantee.
QCI Testing (1)
Classification
QCI Testing
Lot specific testing required in accordance with MIL-PRF-38535 Appendix B.
V Equivalent
(1) QCI groups, subgroups and sample sizes are defined in MIL-PRF38535 and the Honeywell QM Plan. Quarterly testing is done in accordance with the Honeywell QM Plan.
(2) If customer requires lot specific testing, the purchase order must indicate specific tests and sample sizes.
Honeywell reserves the right to make changes of any sort without notice to any and all products, technology and testing identified herein.
You are advised to consult Honeywell or an authorized sales representative to verify that the information in this data sheet is current before
ordering this product. Absent express contract terms to the contrary, Honeywell does not assume any liability of any sort arising out of
the application or use of any product or circuit described herein; nor does it convey any license or other intellectual property rights of
Honeywell or of third parties.
Find out more
To learn more about Honeywell’s radiation hardened
integrated circuit products and technologies, visit
www.honeywell.com/microelectronics.
Honeywell Aerospace
Honeywell
12001 Highway 55
Plymouth, MN 55441
ADS-14191 Rev. B
March 2015
Tel: 800-323-8295
© 2015 Honeywell International Inc.
www.honeywellmicroelectronics.com/
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