HPZB01_技术文档

HPZB01 /HPZB01P V1.0

HPZB01/HPZB01P

ZigBee RF Transceiver Module (IEEE802.15.4)

General Description

The HopeRF HPZB01/HPZB01P RF Transceiver Module is low

cost, high performance and ultra compact size Module

specially designed for Ember ZigBee protocol stack for

wireless networks, EmberZNet, based on IEEE 802.15.4‐

2003 standard in the 2.4GHz ISM band. Built‐in EM357 of

ember integrated a 2.4GHz IEEE 802.15.4‐2003 transceiver,

a 32‐bit ARM® Cortex™‐M3 processor, a 192KB Flash and

12KB RAM for program and data storage. It utilizes the non‐

intrusive SIF module for powerful software debugging and

programming of the network processor. The modules

HPZB01

HPZB01P

eliminate the need for costly and time‐ consuming RF

development, and shortens time to market for wireless

applications with extended range requirements.

HPZB01 output power is up to +8dBm, Size is 22X15X3.2mm.

HPZB01P is base on HPZB01 with additional PA , Its output

power is up to +20dBm. ,Size is 26X15X3.2mm.

Three different versions of the HPZB01/HPZB01P modules

are available: HPZP01‐ANT/HPZB01P‐ANT with built‐in SMD

antenna, HPZP01‐IPEX/HPZB01P‐IPEX with built‐in IPEX

connector for external antenna and HPZP01‐UO/HPZB01P‐

UO with unbalanced RF output for external antenna.

Features

z Low cost, High performance

Applications

The applications include, but are not limited to:

z Easy to use, Support all ZigBee clusters

z Can be used for coordinator, router or sleeping device

z Integrated IEEE 802.15.4‐2003 PHY and MAC layer

z 32‐bit ARM® Cortex™‐M3 processor

z 2.4 GHz ISM band ,Up to 16 channels

z Direct sequence spread spectrum RF transceiver

z Flexible ADC, UART/SPI/TWI serial communications

and general purpose timers

z

Home automation

lighting controls

building control

Inventory management

Environmental monitoring

Automated meter reading

Industrial monitoring

Security systems

Ultra compact size: 22X15X3.2mm (HPZB01)

26X15X3.2mm (HPZB01P)

z

Sensor data capture

High Rx sensitivity: ‐102dBm (HPZB01 Boost mode)

‐110dBm (HPZB01P)

High Output power: +8dBm (HPZB01 Boost mode)

+20dBm (HPZB01P)

Very low power consumption(＜1uA in sleep mode)

192KB Flash and 12KB RAM

Non‐intrusive debug interface (SIF)

AES128 encryption accelerator

z

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HPZB01 /HPZB01P V1.0

1 Pin Assignment and Pin Description

Figure 1‐1:HPZB01/HPZB01P Pin Assignment

HPZB01

HPZB01P

Table 1‐1:HPZB01/HPZB01P Pin Description

(For more details about the Pin description, Please take the datasheet of Ember EM357 as reference)

Pin#

Signal

HPZB01

GND

PC5

TX_ACTIVE

-

nRESET

PC6

OSC32B

Signal

HPZB01P

GND

‐

Direction

Description

1

2

3

4

Ground

I/O

O

-

I

I/O

O

Connect to ground

Digital I/O

‐

Logic‐level control for external Rx/Tx switch

Do not connect

Active low chip reset (internal pull‐up)

Digital I/O

32.768 kHz crystal oscillator

Inverted TX_ACTIVE signal

Digital I/O

NC

nRESET

PC6

OSC32B

nTX_ACTIVE nTX_ACTIVE

PC7

I/O

OSC32A

I/O

5

6

32.768 kHz crystal oscillator

Digital 32.768 kHz clock input source

Digital I/O

Disable REG_EN with GPIO_DBGCFG[4]

Timer 1 Channel 4 output

OSC32_EXT OSC32_EXT

I

I/O High

current

PA7

TIM1C4

REG_EN

TIM1C4

REG_EN

O

I

Timer 1 Channel 4 input

O

External regulator open drain output

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HPZB01 /HPZB01P V1.0

Pin#

Signal

HPZB01

PB3

Signal

HPZB01P

PB3

Direction

Description

I/O

Digital I/O

TIM2C3

SC1nCTS

SC1SCLK

PB4

TIM2C3

SC1nCTS

SC1SCLK

PB4

O

I

O

Timer 2 channel 3 output

Timer 2 channel 3 input

UART CTS handshake of Serial Controller 1

SPI master clock of serial Controller 1

SPI slave clock of serial Controller 1

Digital I/O

7

I

I/O

TIM2C4

SC1nRTS

SC1nSSEL

PA0

TIM2C1

SC2MOSI

PA1

TIM2C4

SC1nRTS

SC1nSSEL

PA0

TIM2C1

SC2MOSI

PA1

O

I

O

I

I/O

O

I

O

Timer 2 channel 4 output

Timer 2 channel 4 input

UART RTS handshake of Serial Controller 1

SPI slave select of serial controller 1

Digital I/O

Timer 2 channel 1 output

Timer 2 channel 1 input

SPI master data out of serial controller 2

SPI slave data in of serial controller 2

Digital I/O

8

9

I

I/O

TIM2C3

SC2SDA

SC2MISO

GND

TIM2C3

SC2SDA

SC2MISO

GND

O

I

I/O

O

Timer 2 channel 3 output

Timer 2 channel 3 input

TWI data of serial controller 2

SPI slave data out of serial controller 2

SPI master data in of serial controller 2

Connect to ground

10

I

11

12

13

Ground

Power

Ground

VDD

GND

VDD

GND

Supply voltage (2.1V‐3.6V)

Connect to ground

PA2

I/O

Digital I/O

TIM2C4

SC2SCL

SC2SCLK

PA3

TIM2C4

SC2SCL

SC2SCLK

PA3

O

I

I/O

O

Timer 2 channel 4 output

Timer 2 channel 4 input

TWI clock of serial controller 2

SPI master clock of serial controller 2

SPI slave clock of serial controller 2

Digital I/O

14

I

I/O

SC2nSSEL

TRACECLK

TIM2C2

GND

SC2nSSEL

TRACECLK

TIM2C2

GND

I

O

I

SPI slave select of serial controller 2

Synchronous CPU trace clock

Timer 2 channel 2 output

Timer 2 channel 2 input

Connect to ground

15

16

17

Ground

I/O

GND

PA4

GND

PA4

Connect to ground

Digital I/O

ADC4

PTI_EN

TRACEDATA2 TRACEDATA2

ADC4

PTI_EN

Analog

O

ADC input 4

Frame signal of packet trace interface(PTI)

Synchronous CPU trace data bit 2

18

O

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HPZB01 /HPZB01P V1.0

Pin#

Signal

HPZB01

PA5

ADC5

PTI_DATA

Signal

HPZB01P

PA5

ADC5

PTI_DATA

Direction

Description

I/O

Analog

O

Digital I/O

ADC input 5

Data signal of packet trace interface(PTI)

Embedded serial bootloader activation out of

reset

19

nBOOTMODE nBOOTMODE

TRACEDATA3 TRACEDATA3

I

O

Synchronous CPU trace data bit 3

I/O High Digital I/O

current

PA6

20

21

TIM1C3

PB1

SC1MISO

SC1MOSI

SC1SDA

SC1TXD

TIM2C1

PB2

SC1MISO

SC1MOSI

SC1SC

SC1RXD

TIM2C2

JTCK

TIM1C3

PB1

SC1MISO

SC1MOSI

SC1SDA

SC1TXD

TIM2C1

PB2

SC1MISO

SC1MOSI

SC1SC

SC1RXD

TIM2C2

JTCK

O

I

Timer 1 channel 3 output

Timer 1 channel 3 input

I/O

O

I/O

O

I

Digital I/O

SPI slave data out of serial controller 1

SPI master data out of serial controller 1

TWI data of serial controller 1

UART transmit data of serial controller 1

Timer 2 channel 1 output

Timer 2 channel 1 input

I/O

I

I/O

I

O

I

Digital I/O

SPI master data in of serial controller 1

SPI slave data in of serial controller 1

TWI clock of serial controller 1

UART receive data of serial controller 1

Timer 2 channel 2 output

Timer 2 channel 2 input

22

I

JTAG clock input from debugger

Serial Wire Clock input/output with debugger

Digital I/O

JTAG data out to debugger

Serial Wire Output asynchronous trace output

to debugger

23

24

25

26

SWCLK

PC2

JTDO

SWCLK

PC2

JTDO

I/O

O

SWO

O

PC3

JTDI

PC4

PC3

JTDI

PC4

I/O

Digital I/O

I

I/O

I

JTAG data in from debugger

Digital I/O

JTAG mode select from debugger

Serial Wire bidirectional data to/from

debugger

JTMS

SWDIO

I/O

PC1

I/O

Digital I/O

ADC3

Analog

ADC input 3

27

28

Serial Wire Output asynchronous trace output

to debugger

Synchronous CPU trace data bit 0

SWO

O

TRACEDATA0 TRACEDATA0

O

I/O High Digital I/O

current

PC0

JRST

I

O

JTAG reset input from debugger

Default external interrupt source D

Synchronous CPU trace data bit 1

IRQD¹

TRACEDATA1 TRACEDATA1

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HPZB01 /HPZB01P V1.0

Pin#

Signal

Direction

Description

HPZB01

HPZB01P

I/O High Digital I/O

current

PB7

ADC2

IRQC¹

TIM1C2

ADC2

IRQC¹

TIM1C2

Analog

ADC Input 2

Default external interrupt source C

Timer 1 channel 2 output

29

I

O

I

Timer 1 channel 2 input

I/O High Digital I/O

current

PB6

ADC1

IRQB

TIM1C1

PB5

ADC1

IRQB

TIM1C1

PB5

ADC0

TIM2CLK

TIM1MSK

Analog

ADC Input 1

30

31

I

O

I

External interrupt source B

Timer 1 channel 1 output

Timer 1 channel 1 input

Digital I/O

I/O

Analog

ADC0

ADC Input 0

TIM2CLK

TIM1MSK

PB0

I

Timer 2 external clock input

Timer 1 external clock mask input

Digital I/O

‐

I/O

VREF

‐

Analog O ADC reference output

Analog I ADC reference input

IRQA

‐

I

O

I

External interrupt source A

Synchronous CPU trace clock

Timer 1 external clock input

Timer 2 external clock mask input

Do not connect

32

TRACECLK

TIM1CLK

TIM2MSK

‐

NC

GND

‐

33

34

GND

Ground

Connect to ground

Unbalanced RF input/output , Connect to

external antenna for HPZB01‐UO and

HPZB01P‐UO

ANT

I/O

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HPZB01 /HPZB01P V1.0

2 Electrical Characteristics

2.1 Absolute Maximum Ratings

Table 2‐1: Absolute Maximum Ratings

Test Conditions

Parameter

Min.

Max.

+3.6

+15

Unit

V

Regulator input voltage (VDD)

RF Input Power

‐0.3

(for max level for correct packet

reception)

dBm

Voltage on any GPIO pin (PA4, PA5, PB5,

PB6, PB7, PC1), when used as an input

to the general purpose ADC with the

low voltage range selected

Voltage on any GPIO (PA[7:0], PB[7:0],

PC[7:0]), SWCLK, nRESET, VREG_OUT

Voltage on OSCA, OSCB, NC

‐0.3

2.0

V

VDD

+0.3

1.9V

+0.3

+140

‐0.3

‐40

V

Storage temperature

°C

2.2 Recommended Operating Conditions

Table 2‐2: Operating Conditions

Parameter

Test Conditions

Min.

Typ.

Max. Unit

Regulator input voltage (VDD)

2.1

3.6

V

Operating temperature range(note1)

‐20

+70

°C

note1: ‐40°C to +85°C operational

2.3 Electrical Specifications

Table 2‐3: Electrical Specifications

(VCC = 3.0V, Fo =2440MHZ, T=25°C, if nothing else stated)

Parameter Test Conditions

Min.

Typ.

Max. Unit

Operating frequency

Supply voltage

2405

2.1

2485 MHZ

3.6

V

Numbers of channels

Channel spacing

For IEEE 802.15.4 compliance

HPZB01

Programmable

HPZB01P with PA

16

5

MHz

dBm

‐20

+8

Maximum output power

+20

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HPZB01 /HPZB01P V1.0

Parameter

Test Conditions

HPZB01

Min.

Typ.

Max. Unit

PER = 1% PER, 20byte packet

defined by IEEE 802.15.4

Boost mode

‐102

dBm

HPZB01

Sensitivity

PER = 1% PER, 20byte packet

defined by IEEE 802.15.4

HPZB01P with LNA

PER = 1% PER, 20byte packet

defined by IEEE 802.15.4

HPZB01

+8dBm transmission power

HPZB01

+3dBm transmission power

HPZB01P with PA

+20dBm transmission power

‐100

‐110

dBm

42

29

mA

Tx Current

Rx Current

170

29

HPZB01

boost mode

HPZB01

normal mode

27

HPZB01P with LNA

38

250

0.7

mA

Kbps

uA

On‐Air Data Rate

Deep sleep current

Frequency stability

+/‐40 ppm

IPEX connector output

Unbalanced output

RF Input/output impedance

50

Ohm

Flash Memory Size

RAM Size

192

12

KB

Main system clock frequency

Sub system clock frequency

24

32.768

MHz

KHz

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HPZB01 /HPZB01P V1.0

3 Block Diagram

Figure 3‐1: HPZB01‐ANT Block Diagram

Figure 3‐2: HPZB01‐IPEX Block Diagram

Figure 3‐3: HPZB01‐UO Block Diagram

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HPZB01 /HPZB01P V1.0

Figure 3‐4: HPZB01P‐ANT Block Diagram

Figure 3‐5: HPZB01P‐IPEX Block Diagram

Figure 3‐6: HPZB01P‐UO Block Diagram

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HPZB01 /HPZB01P V1.0

4 PCB Layout Recommendations

As the HPZB01(P)‐ANT module integrated with SMD antenna, The mounting position of the module will

have great impact on the RF performance. There should not be any trace, ground plane , metal part and

PCB underneath or nearby the area of the SMD antenna. Except the area of the SMD antenna, A ground

plane under the module is preferred. The figure below shows an example how the module positioned on

the mother PCB.

Figure 4‐1: A recommended placement of the module on a main PCB

Use ferrite bead and 1uF capacitor located closely to the power supply pin is recommended, As shown

below.

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HPZB01 /HPZB01P V1.0

5 Mechanical Dimensions

All dimensions in MM

Figure 5‐1: HPZB01 Mechanical Dimensions

Figure 5‐2: HPZB01P Mechanical Dimensions

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HPZB01 /HPZB01P V1.0

6 Mounting Information

The below diagrams show the PCB footprint recommended for the modules.

All dimensions in MM

Figure6‐1: HPZB01(P)‐ANT and HPZB01(P)‐IPEX module Recommended PCB footprint ,Top View

Figure6‐2: HPZB01‐UO module Recommended PCB footprint, Top View

Figure6‐3: HPZB01P‐UO module Recommended PCB footprint, Top View

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HPZB01 /HPZB01P V1.0

7 Soldering Profile

Table7‐1: Soldering Profile

Profile Feature

Green Package

Average ramp‐up rate(217°C to peak)

Preheat temperature 175°C +/‐25°C

Temperature maintained above 217°C

Time within 5°C of actual peak temperature

Peak temperature rang

3°C/s max

180s max

60S to 150S

20s to 40s

260°C

Ramp-down rate

Time within 25°C to peak temperature

6°C/s max

8 minutes max

8 Ordering Information

Table8‐1: Ordering Information

Description

Part Number

HPZB01‐ANT

HPZB01P‐ANT

+8dBm output power, ‐102dBm sensitivity, With built-in SMD antenna

+20dBm output power, ‐110dBm sensitivity, With built-in SMD antenna

+8dBm output power, ‐102dBm sensitivity, With Built-in IPEX connector for

external antenna

+20dBm output power, ‐110dBm sensitivity, With Built-in IPEX connector for

external antenna

HPZB01‐IPEX

HPZB01P‐IPEX

HPZB01‐UO

+8dBm output power, ‐102dBm sensitivity, With unbalanced RF output for

external antenna

+20dBm output power, ‐110dBm sensitivity, With unbalanced RF output for

external antenna

HPZB01P‐UO

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HPZB01 /HPZB01P V1.0

This document may contain preliminary information and is subject to change by Hope

Microelectronics without notice. Hope Microelectronics assumes no responsibility or

liability for any use of the information contained herein. Nothing in this document shall

operate as an express or implied license or indemnity under the intellectual property rights of

Hope Microelectronics or third parties. The products described in this document are not

intended for use in implantation or other direct life support applications where malfunction

may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY

KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

HOPE MICROELECTRONICS CO.,LTD

Add:4/F, Block B3, East Industrial Area, Huaqiaocheng,

Shenzhen, Guangdong, China

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trade@hoperf.com

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MECHANTABILITY OR FITNESS FOR

THIS DOCUMENT.

AARTICULAR PURPOSE, ARE OFFERED IN

http://hoperf.en.alibaba.com

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型号：	HPZB01
厂家：	HOPERF
描述：	ZigBee RF Transceiver Module
文件：	总14页 (文件大小：1352K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HPZB01 [HOPERF]

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