RF02 [HOPERF]
Universal ISM Band FSK Transmitter; 通用ISM频段FSK发射器
| 型号： | RF02 |
| 厂家： | 
HOPERF |
| 描述： | Universal ISM Band FSK Transmitter |
| 文件： | 总24页 (文件大小：1085K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF02
RF02 Universal ISM Band
FSK Transmitter
RF02
DESCRIPTION
Hope’s RF02 is a single chip, low power, multi-channel
FSK transmitter designed for use in applications requiring
FCC or ETSI conformance for unlicensed use in the 433, 868,
and 915 MHz bands. Used in conjunction with RF01, Hope’s
FSK receiver, the RF02 transmitter produces a flexible, low
cost, and highly integrated solution that does not require
production alignments. All required RF functions are
integrated. Only an external crystal and bypass filtering are
needed for operation. The RF02 offering a higher output
power and an improved phase noise characteristic.
The RF02 features a completely integrated PLL for easy
RF design, and its rapid settling time allows for fast frequency hopping, bypassing multipath fading and
interference to achieve robust wireless links. In addition, highly stable and accurate FSK modulation is
accomplished by direct closed-loop modulation with bit rates up to 115.2 kbps. The PLL’s high resolution
allows the use of multiple channels in any of the bands.
The integrated power amplifier of the transmitter has an open-collector differential output that directly
drive a loop antenna with programmable output level. No additional matching network is required. An
automatic antenna tuning circuit is built in to avoid costly trimming procedures and de-tuning due to the
“hand effect”.
For low-power applications, the device supports automatic activation from sleep mode. Active mode
can be initiated by several wake-up events (on-chip timer timeout, low supply voltage detection).
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RF02
FEATURES
Fully integrated (low BOM, easy design-in)
No alignment required in production
Fast settling, programmable, high-resolution PLL
Fast frequency hopping capability
Stable and accurate FSK modulation with programmable deviation
Programmable PLL loop bandwidth
Direct loop antenna drive
Automatic antenna tuning circuit
Programmable output power level
SPI bus for applications with microcontroller
Clock output for microcontroller
Integrated programmable crystal load capacitor
Multiple event handling options for wake-up activation
Wake-up timer
Low battery detection
2.2V to 5.4V supply voltage
Low power consumption
Low standby current (0.3 μA)
Transmit bit synchronization
TYPICAL APPLICATIONS
Remote control
Home security and alarm
Wireless keyboard/mouse and other PC peripherals
Toy control
Remote keyless entry
Tire pressure monitoring
Telemetry
Personal/patient data logging
Remote automatic meter reading
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RF02
DETAILED FEATURE-LEVEL DESCRIPTION
The RF02 FSK transmitter is designed to cover the unlicensed frequency bands at 433, 868, and
915 MHz. The device facilitates compliance with FCC and ETSI requirements.
PLL
The programmable PLL synthesizer determines the operating frequency, while preserving accuracy
based on the on-chip crystal-controlled reference oscillator. The PLL’s high resolution allows the usage of
multiple channels in any of the bands. The FSK deviation is selectable (from 30 to 210 kHz with 30 kHz
increments) to accommodate various bandwidth, data rate and crystal tolerance requirements, and it is
also highly accurate due to the direct closed-loop modulation of the PLL. The transmitted digital data can
be sent asynchronously through the FSK pin or over the control interface using the appropriate
command.
RF Power Amplifier (PA)
The power amplifier has an open-collector differential output and can directly drive a loop antenna
with a programmable output power level. An automatic antenna tuning circuit is built in to avoid costly
trimming procedures and the so-called “hand effect.”
Crystal Oscillator
The chip has a single-pin crystal oscillator circuit, which provides a 10 MHz reference signal for the
PLL. To reduce external parts and simplify design, the crystal load capacitor is internal and
programmable. Guidelines for selecting the appropriate crystal can be found later in this datasheet.
The transmitters can supply the clock signal for the microcontroller, so accurate timing is possible
without the need for a second crystal. When the chip receives a Sleep Command from the microcontroller
and turns itself off, it provides several further clock pulses (“clock tail”) for the microcontroller to be able to
go to idle or sleep mode. The length of the clock tail is programmable.
Low Battery Voltage Detector
The low battery voltage detector circuit monitors the supply voltage and generates an interrupt if it
falls below a programmable threshold level.
Wake-Up Timer
The wake-up timer has very low current consumption (1.5 uA typical) and can be programmed from
1 ms to several days with an accuracy of ±5%.
It calibrates itself to the crystal oscillator at every startup, and then every 30 seconds. When the
oscillator is switched off, the calibration circuit switches on the crystal oscillator only long enough for a
quick calibration (a few milliseconds) to facilitate accurate wake-up timing.
Event Handling
In order to minimize current consumption, the device supports sleep mode. Active mode can be
initiated by several wake-up events: timeout of wake-up timer, detection of low supply voltage or through
the serial interface.
If any wake-up event occurs, the wake-up logic generates an interrupt, which can be used to wake
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RF02
up the microcontroller, effectively reducing the period the microcontroller has to be active. The cause of
the interrupt can be read out from the transmitters by the microcontroller through the nIRQ pin.
Interface
An SPI compatible serial interface lets the user select the operating frequency band and center
frequency of the synthesizer, polarity and deviation of FSK modulation, and output power level. Division
ratio for the microcontroller clock, wake-up timer period, and low battery detector threshold are also
programmable. Any of these auxiliary functions can be disabled when not needed. All parameters are set
to default after power-on; the programmed values are retained during sleep mode.
PACKAGE PIN DEFINITIONS
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
PinP Name
Type Function
1
2
3
4
5
6
7
8
SDI
DI
DI
DI
DO
AIO
S
Data input of serial control interface
SCK
Clock input of serial control interface
Chip select input of serial control interface (active low)
Microcontroller clock (1 MHz-10 MHz)
Crystal connection (other terminal of crystal to VSS)
Digital VSS(Connect to VSS)
nSEL
CLK
XTL
VSS_D
VSS_A
VSS_RF
S
Analog VSS(Connect to VSS)
S
RF VSS(Connect to VSS)
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RF02
9
MOD
RFN
RFP
DI
Connect to logic high
10
11
AO
AO
Power amplifier output (open collector)
Power amplifier output (open collector)
Interrupt request output for microcontroller (active low) and status read output
12
nIRQ
DO
13
14
15
16
VDD_RF
VDD_A
VDD_D
FSK
S
RF VDD(Connect to VDD)
S
Analog VDD(Connect to VDD)
Digital VDD(Connect to VDD)
Serial data input for FSK modulation
S
DI
Typical application
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RF02
GENERAL DEVICE SPECIFICATION
All voltages are referenced to Vss, the potential on the ground reference pin VSS.
Absolute Maximum Ratings (non-operating)
Symbol
Vdd
Parameter
Min
-0.5
-0.5
-0.5
-25
Max
6.0
Units
Positive supply voltage
V
Vin
Voltage on any pin except open collector outputs
Voltage on open collector outputs
Input current into any pin except VDD and VSS
Electrostatic discharge with human body model
Storage temperature
Vdd+0.5
6.0
V
Voc
V
Iin
25
mA
V
ESD
Tst
1000
125
-55
℃
Recommended Operating Range
Symbol
Vdd
Parameter
Min
Max
5.4
Units
V
Positive supply voltage
2.2
Voc
Voltage on open collector outputs (Max 6.0 V)
Ambient operating temperature
Vdd - 1
-40
Vdd + 1
85
V
Top
℃
ELECTRICAL SPECIFICATION
(Min/max values are valid over the whole recommended operating range, typ conditions:
Top =27℃;Vdd =Voc=2.7V)
DC Characteristics
Symbol
Parameter
Conditions/Notes
Min
Typ
Max
Units
Idd_TX_0
Supply current 433 MHz band
Active state with
0dBm
12
14
15
mA
(TX mode,
868 MHz band
915 MHz band
Pout =0dBm)
output power
Idd_TX_PMAX Supply current 433 MHz band
Active state with
maximum output
power
21
23
24
mA
(TX mode,
Pout =Pmax
868 MHz band
915 MHz band
)
Ipd
Iwt
Ilb
Ix
Standby current in sleep mode
(Note 1)
All blocks
disabled
0.3
1.5
0.5
1.5
µA
µA
µA
mA
Wake-up timer current
consumption
Low battery detector current
consumption
Idle current
Only crystal
oscillator is on
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RF02
Vlba
Vlb
Low battery detection accuracy
Low battery detector threshold
+/-3
%
Programmable in
0.1 V steps
2.2
5.3
V
Vil
Vih
Iil
Digital input low level
Digital input high level
Digital input current
Digital input current
0.3*Vdd
V
0.7*Vdd
-1
V
Vil = 0 V
1
1
µA
µA
Iih
Vih = Vdd, Vdd = 5.4 -1
V
Vol
Digital output low level
Digital output high level
Iol = 2 mA
0.4
V
V
Voh
Ioh = -2 mA
Vdd-0.4
AC Characteristic
Min
9
Typ
10
Max
11
Symbol
Parameter
Conditions/Notes
Units
MHz
PLL reference
frequency
Crystal operation mode is
parallel (Note 2)
fref
433MHz band, 2.5kHz
resolution
430.24
860.48
900.72
439.75
879.51
929.27
868MHz band, 5.0kHz
resolution
fo
MHz
915MHz band, 7.5kHz
resolution
Frequency error < 10 kHz after
10 MHz step, POR default PLL
setting(Note 7)
20
tlock
PLL lock time
µs
µs
After turning on from idle
mode, with crystal oscillator
already stable, POR default
PLL setting (Note 7)
250
tsp
PLL startup time
0.5
6
Open collector output
current (Note 3)
IOUT
At all bands
mA
Available output power With opt. antenna impedance
8
6
PmaxL
dBm
(433MHz band)
(Note 4)
Available output power
(868 and 915 MHz
band)
With opt. antenna impedance
(Note 4)
PmaxH
dBm
Selectable in 3 dB steps (Note
3)
Pmax-21
Pmax
-50
Pout
Typical output power
Spurious emission
dBm
dBc
At max power with loop
antenna (Note 5)
Psp
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RF02
Output capacitance
(set by the automatic
antenna tuning circuit)
At low bands
At high bands
1.5
1.6
2.3
2.2
2.8
Co
Qo
3.1
pF
Quality factor of the
output capacitance
16
18
22
pF
100 kHz from carrier
-85
Lout
BRFSK
dffsk
Output phase noise
dBc/Hz
kbps
1 MHz from carrier (Note 7)
-105
FSK bit rate
(Note 7)
115.2
210
FSK frequency
deviation
30
Programmable in 30 kHz steps
kHz
Crystal load
Programmable in 0.5 pF steps,
tolerance +/-10%
8.5
16
capacitance See
Crystal Selection
Guidelines
Cxl
pF
Internal POR timeout
(Note 6)
After Vdd has reached 90% of
final value
50
5
tPOR
ms
ms
ms
ms
pF
ns
Crystal oscillator
startup time
1.5
tsx
Crystal ESR < 100 Ohms
Wake-up timer clock
period
0.95
1
1.05
5 *1011
2
tPBt
Calibrated every 30 seconds
Programmable
wake-up time
twake-up
Cin, D
tr, f
Digital input
capacitance
Digital output rise/fall
time
10
15 pF pure capacitive load
Note 1: Using a CR2032 battery (225 mAh capacity), the expected battery life is greater than 2 years
using a 60-second wake-up period for sending 50 byte packets in length at 19.2 kbps with +6 dBm output
power in the 915 MHz band.
Note 2: Using anything but a 10 MHz crystal is allowed but not recommended because all
crystal-referred timing and frequency parameters will change accordingly.
Note 3: Adjustable in 8 steps.
Note 4: Optimal antenna admittance/impedance for the RF02:
Yantenna [S]
Zantenna [Ohm]
31 + j152
Lantenna [nH]
58.00
434 MHz
868 MHz
915 MHz
1.3E-3 - j6.3E-3
1.35E-3 - j1.2E-2
1.45E-3 - j1.3E-2
9 + j82
15.20
8.7 + j77
13.60
Note 5: With selective resonant antennas .
Note 6: During this period, no commands are accepted by the chip.
Note 7: The maximum FSK bitrate and the Output phase noise are dependent on the actual setting of the
PLL Setting Command.
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RF02
TYPICAL PERFORMANCE DATA (RF02)
Phase noise measurements in the 868 MHz ISM band
Unmodulated RF Spectrum
The output spectrum is measured at different frequencies. The output is loaded with 50 Ohms through a
matching network.
Modulated RF Spectrum
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Other Important Characteristics
The antenna tuning characteristics was recorded in “max-hold” state of the spectrum analyzer. During the
measurement, the transmitters were forced to change frequencies by forcing an external reference signal
to the XTL pin. While the carrier was changing the antenna tuning circuit switched trough all the available
states of the tuning circuit. The graph clearly demonstrates that while the complete output circuit had
about a 40 MHz bandwidth, the tuning allows operating in a 220 MHz band. In other words the tuning
circuit can compensate for 25% variation in the resonant frequency due to any process or manufacturing
spread.
CONTROL INTERFACE
Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the
rising edge of the clock on pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is
high, it initializes the serial interface. The number of bits sent is an integer multiple of 8. All commands
consist of a command code, followed by a varying number of parameter or data bits. All data are sent
MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (don’t care) are indicated with X.
The Power On Reset (POR) circuit sets default values in all control and command registers.
Timing Specification
Symbol
tCH
Parameter
Minimum Value [ns]
Clock high time
25
25
10
10
25
5
tCL
Clock low time
tSS
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
tSH
tSHI
tDS
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
tDH
5
tOD
10
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RF02
Timing Diagram
Control Commands
Control Command
Related Parameters/Functions
Frequency band, microcontroller clock output, crystal load
capacitance, frequency deviation
Crystal oscillator, synthesizer, power amplifier, low battery
detector, wake-up timer, clock output buffer
Carrier frequency
1
2
Configuration Setting Command
Power Management Command
3
Frequency Setting Command
Data Rate Command
4
Bit rate
5
Power Setting Command
Nominal output power, OOK mode
6
Low Battery Detector Command Low battery threshold limit
7
Sleep Command
Length of the clock tail after power down
8
Wake-Up Timer Command
Data Transmit Command
Status Register Command
Wake-up time period
Data transmission
9
10
Transmitter status read
11
PLL Setting Command
PLL bandwidth can be modified by this command
Note: In the following tables the POR column shows the default values of the command registers after
power-on.
1. Configuration Setting Command
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
POR
1
0
0
b1 b0 d2 d1 d0 x3 x2 x1 x0 ms m2 m1 m0 8080h
b1
0
b0
1
Frequency Band [MHz]
x3 x2 x1 x0 Crystal Load Capacitance [pF]
433
868
915
0
0
0
0
0
0
0
0
1
1
0
1
0
1
8.5
9.0
9.5
1
0
1
1
1
0
1
0
16.0
0
……
1
……
15.5
1
1
0
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RF02
d2
d1
d0
Clock Output
Frequency [MHz]
The resulting output frequency can be calculated as:
fout = f0 – (-1)SIGN * (M + 1) * (30 kHz)
where:
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1.25
1.66
2
f0 is the channel center frequency (see the next
command)
M is the three bit binary number <m2 : m0>
SIGN = (ms) XOR (FSK input)
Note:
2.5
3.33
5
• Use M in a range from 0 to 6.
10
2. Power Management Command
bit 15 14 13 12 11 10
9
0
8
0
7
6
5
4
3
2
1
0
POR
1
1
0
0
0
0
a1 a0 ex es ea eb et dc C000h
Bits 5-0, enable the corresponding block of the transmitters, i.e. the crystal oscillator is enabled by
the ex bit, the synthesizer by es, the power amplifier by ea and the low battery detector by eb, while the
wake-up timer by et. The bit dc disables the clock output buffer.
When receiving the Data Transmit Command, the chip supports automatic on/off control over the
crystal oscillator, the PLL and the PA.
If bit a1 is set, the crystal oscillator and the synthesizer are controlled automatically. Data Transmit
Command starts up the crystal oscillator and as soon as a stable reference frequency is available the
synthesizer starts. After a subsequent delay to allow locking of the PLL, if a0 is set the power amplifier is
turned on as well.
Note:
To enable the automatic internal control of the crystal oscillator, the synthesizer and the power
amplifier, the corresponding bits (ex, es, ea) must be zero in the Power Management Command.
The ex bit should be set in the Power Management Command for the correct control of es and ea.
The oscillator can be switched off by clearing the ex bit after the transmission.
The Sleep Command can be used to indicate the end of the data transmission process.
For processing the events caused by the peripheral blocks (POR, LBD or wake-up timer) the chip
requires operation of the crystal oscillator. This operation is fully controlled internally, independently from
the status of the ex bit, but if the dc bit is zero, the oscillator remains active until Sleep Command is
issued. (This command can be considered as an event controller reset.)
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Oscillator control logic
3. Frequency Setting Command
bit 15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
POR
1
0
1
0
f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 A7D0h
The 12-bit parameter of the Frequency Setting Command <f11 : f0> has the value F. The value F should
be in the range of 96 and 3903. When F is out of range, the previous value is kept. The synthesizer
center frequency f0 can be calculated as:
f0 = 10 MHz * C1 * (C2 + F/4000)
The constants C1 and C2 are determined by the selected band as:
Band [MHz]
433
C1
1
C2
43
43
30
868
2
915
3
Note:
• For correct operation of the frequency synthesizer, the frequency and band of operation need to be
programmed before the synthesizer is started. Directly after activation of the synthesizer, the RF VCO is
calibrated to ensure proper operation in the programmed frequency band.
4. Data Rate Command
bit 15 14 13 12 11
10
0
9
0
8
0
7
6
5
4
3
2
1
0
POR
1
1
0
0
1
r7 r6 r5 r4 r3 r2 r1 r0 C800h
The transmitted bit rate is determined by the 8-bit value R (bits <r7 : r0>) as:
BR = 10 MHz / 29 / (R+1)
Apart from setting custom values, the standard bit rates from 2.4 to 115.2 kbps can be approximated with
minimal error.
Note:
• PLL bandwidth should be set according the data rate. Please see the PLL Setting Command.
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RF02
5. Power Setting Command
bit
7
1
6
0
5
1
4
1
3
0
2
1
0
POR
p2 p1
p0 B0h
2
0
0
0
0
1
1
1
1
p1
0
p0
Output Power [dB]
0
1
0
1
0
1
0
1
0
The output power is given in the table
0
-3
as relative to the maximum available
power, which depends on the actual
antenna impedance.
1
-6
1
-9
0
-12
-15
-18
-21
0
1
1
6. Low Battery Detector and TX Bit Synchronization Command
bit 15 14 13 12 11 10
9
1
8
0
7
6
0
5
4
3
2
1
0
POR
1
1
0
0
0
0
dwc
ebs t4 t3 t2 t1 t0 C200h
Bit 7 <dwc> Disables the Wake-up timer periodical (every 30 second) calibration if this bit is set.
Bit 5 <ebs> Enables the TX bit synchronization circuit. The data rate must be set by the Data Rate
Command.5
The 5-bit value T of <t4 : t0> determines the threshold voltage V lb of the detector:
V lb= 2.2 V + T * 0.1 V
7. Sleep Command
bit 15 14 13 12 11 10
9
0
8
0
7
6
5
4
3
2
1
0
POR
1
1
0
0
0
1
s7 s6 s5 s4 s3 s2 s1 s0 C400h
The effect of this command depends on the Power Management Command. It immediately disables the
power amplifier (if a0=1 and ea=0) and the synthesizer (if a1=1 and es=0). Stops the crystal oscillator
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RF02
after S periods of the microcontroller clock (if a1=1 and ex=0) to enable the microcontroller to execute all
necessary commands before entering sleep mode itself. The 8-bit value S is determined by bits <s7:s0>.
8. Wake-Up Timer Command
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
POR
1
1
1
r4 r3 r2 r1 r0 m7 m6 m5 m4 m3 m2 m1 m0 E000h
The wake-up time period can be calculated as:
wake-up = M * 2R [ms],
T
where M is defined by the <m7 : m0> digital value and R is defined by the <r4 : r0> digital value.
Note:
•
For continual operation the et bit should be cleared and set at the end of every cycle.
9. Data Transmit Command
bit
7
1
6
1
5
0
4
0
3
0
2
1
1
1
0
0
This Command Indicates that the following bitstream coming in via the serial interface is to be
transmitted.
Note
•
This command is not needed if the transmitters’ power management bits (ex, es and ea) are fully
controlled by the microcontroller and TX data comes through the FSK pin.
If the crystal oscillator was formerly switched off (ex=0), the internal oscillator needs tsx time, to
switch on. The actual value depends on the type of quartz crystal used.
If the synthesizer was formerly switched off (es=0), the internal PLL needs tsp startup time. Valid data
•
•
can be transmitted only when the internal locking process is finished.
Data Transmit Sequence Through the FSK Pin
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RF02
Data Transmit Sequence Through the SDI Pin
Note:
Do not send CLK pulses with the TX data bits, otherwise they will be interpreted as commands.
This mode is not SPI compatible.
If the crystal oscillator and the PLL are running, the tsx+tsp delay is not needed.
10 . Status Register Read Command
bit
15
1
14
1
13
0
12
0
11
1
10
1
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POR
--
With this command, it is possible to read the chip’s status register through the nIRQ pin. This command
clears the last serviced interrupt and processing the next pending one will start (if there is any).
Status Register Read Sequence
11. PLL Setting Command
PLL bandwidth can be selected by this command
PLL command
Max data rate
[kbps]
Phase noise at 1MHz offset
Comments
[dbc/Hz]
-112
D240h
D2C0h
D200h
D280h
19.2
38.4
68.9
115.2
25%current
33%current
50%current
100%current
-110
-107
-102
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RF02
RX-TX ALIGNMENT PROCEDURES
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To
minimize these errors it is suggested to use the same crystal type and the same PCB layout for the
crystal placement on the RX and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a
high level of accuracy. Do not measure the output at the XTL pin since the measurement process itself
will change the reference frequency. Since the carrier frequencies are derived from the reference
frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side
there should be no offset if the CLK signals have identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status
byte of the receiver. By reading out the status byte from the receiver the actual measured offset
frequency will be reported. In order to get accurate values the AFC has to be disabled during the read by
clearing the "en" bit in the AFC Control Command (bit 0).
CRYSTAL SELECTION GUIDELINES
The crystal oscillator of the RF02 requires a 10 MHz parallel mode crystal. The circuit contains an
integrated load capacitor in order to minimize the external component count. The internal load
capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With appropriate PCB layout,
the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used.
When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance
(C0) value is expected for the crystal, the oscillator is able to start up with any crystal having less than
100 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR values guarantee faster
oscillator startup. It is recommended to keep the PCB parasitic capacitances on the XTL pin as low as
possible.
The crystal frequency is used as the reference of the PLL, which generates the RF carrier frequency
(fc). Therefore fc is directly proportional to the crystal frequency. The accuracy requirements for
production tolerance, temperature drift and aging can thus be determined from the maximum allowable
carrier frequency error.
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RF02
Maximum XTAL Tolerances Including Temperature and Aging [ppm]
Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the
accurate frequency by changing the load capacitor value. The widest pulling range can be achieved if the
nominal required load capacitance of the crystal is in the “midrange”, for example 16 pF. The “pull-ability”
of the crystal is defined by its motional capacitance and C0
Note:
• There may be other requirements for the TX carrier accuracy with regards to the requirements as
defined by standards and/or channel separations.
EXAMPLE APPLICATIONS: DATA PACKET TRANSMISSION
Data packet structure
An example data packet structure using the RF02X - RF01 pair for data transmission. This packet
structure is an example of how to use the high efficiency FIFO mode at the receiver side:
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RF02
The first 3 bytes compose a 24 bit length ‘01’ pattern to let enough time for the clock recovery of the
receiver to lock. The next two bytes compose a 16 bit synchron pattern which is essential for the
receiver’s FIFO to find the byte synchron in the received bit stream. The synchron patters is followed by
the payload. The first byte transmitted after the synchron pattern (D0 in the picture above) will be the first
received byte in the FIFO.
Important: The bytes of the data stream should follow each other continuously, otherwise the clock
recovery circuit of the receiver side will be unable to track.
Further details of packet structures can be found in the RF ISM-UGSB1 software development kit manual
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RF02
REFERENCE DESIGNS
Schematic
PCB layout
Top view
Bottom view
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RF02
SGS Reports
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RF02
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RF02
RF02 BONDING DIAGRAM
Pad Opening: 85um square, except 76um octagon pads (AN1, AN2)
Die Size: 2220 X 2525 um
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RF02
This document may contain preliminary information and is subject to
change by Hope Microelectronics without notice. Hope Microelectronics
assumes no responsibility or liability for any use of the information
contained herein. Nothing in this document shall operate as an express
or implied license or indemnity under the intellectual property rights of
HOPE MICROELECTRONICS CO.,LTD
Add:4/F, Block B3, East Industrial Area, Hope Microelectronics or third parties. The products described in this
Huaqiaocheng, Shenzhen, Guangdong, document are not intended for use in implantation or other direct life
China
support applications where malfunction may result in the direct physical
harm or injury to persons. NO WARRANTIES OF ANY KIND,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE
OFFERED IN THIS DOCUMENT.
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