HCPL-2200 [HP]
Low Input Current Logic Gate Optocouplers; 低输入电流逻辑门光电耦合器
| 型号： | HCPL-2200 |
| 厂家： | 
HEWLETT-PACKARD |
| 描述： | Low Input Current Logic Gate Optocouplers |
| 文件： | 总11页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
H
Low Input Current Logic Gate
Optocouplers
Technical Data
HCPL-2200
HCPL-2219
detector threshold with hysteresis.
The three state output eliminates
the need for a pullup resistor and
allows for direct drive of data
busses. The hysteresis provides
differential mode noise immunity
and eliminates the potential for
output signal chatter.
Features
• Ground Loop Elimination
• Pulse Transformer
Replacement
• Isolated Buss Driver
• High Speed Line Receiver
• 2.5 kV/µs Minimum Common
Mode Rejection (CMR) at
VCM = 400 V (HCPL-2219)
• Compatible with LSTTL,
TTL, and CMOS Logic
• Wide VCC Range (4.5 to 20 V)
• 2.5 Mbd Guaranteed over
Temperature
Description
The HCPL-2200/2219 are
• Low Input Current (1.6 mA)
• Three State Output (No
Pullup Resistor Required)
• Guaranteed Performance
from 0°C to 85°C
optically coupled logic gates that
combine a GaAsP LED and an
integrated high gain photo
detector. The detector has a three
state output stage and has a
A superior internal shield on the
HCPL-2219 guarantees common
mode transient immunity of
2.5 kV/µs at a common mode
voltage of 400 volts.
• Hysteresis
• Safety Approval
UL Recognized -2500 V rms
for 1 minute
Functional Diagram
CSA Approved
NC
ANODE
CATHODE
NC
1
2
3
4
8
7
6
5
V
V
V
CC
VDE 0884 Approved with
TRUTH TABLE
(POSITIVE LOGIC)
VIORM = 630 V peak
O
LED
ENABLE OUTPUT
(HCPL-2219 Option 060
Only)
ON
OFF
ON
H
H
L
L
Z
Z
H
L
E
• MIL-STD-1772 Version
Available (HCPL-5200/1)
OFF
GND
SHIELD
Applications
• Isolation of High Speed
Logic Systems
• Computer-Peripheral
Interfaces
• Microprocessor System
Interfaces
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
1-120
5965-3596E
The Electrical and Switching
Characteristics of the HCPL-
2200/2219 are guaranteed over
the temperature range of 0°C to
TTL, LSTTL, and CMOS logic and
result in lower power consump-
tion compared to other high
speed optocouplers. Logic signals
are transmitted with a typical
propagation delay of 160 nsec.
The HCPL-2200/2219 are useful
for isolating high speed logic
interfaces, buffering of input and
output lines, and implementing
isolated line receivers in high
noise environments.
85°C and a V range of 4.5 volts
CC
to 20 volts. Low I and wide V
F
CC
range allow compatibility with
Selection Guide
Small-Outline Widebody
SO-8 (400 Mil)
Single Single
Minimum CMR
Input On-
8-Pin DIP (300 Mil)
Hermetic
Single and Dual
Channel
Single
Channel
Package
Dual
Channel
Package
dV/dt
(V/µs)
V
(V)
Current
(mA)
Channel
Package
Channel
Package
CM
Packages
[1]
1,000
50
1.6
HCPL-2200
HCPL-0201 HCNW2201
HCPL-2201
HCPL-2202
1.8
1.6
1.6
HCPL-2231
HCPL-2232
[1]
2,500
5,000
400
300
HCPL-2219
[2]
[2]
HCPL-2211
HCPL-2212
HCPL-0211 HCNW2211
1.8
2.0
1,000
50
HCPL-52XX
HCPL-62XX
Notes:
1. HCPL-2200/2219 devices include output enable/disable functionality.
2. Minimum CMR of 10 kV/µs with VCM = 1000 V can be achieved with input current, IF, of 5 mA.
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-2219#XXX
060 = VDE 0884 VIORM = 630 Vpeak Option*
300 = Gull Wing Surface Mount Option
500 = Tape and Reel Packaging Option
Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for
information.
*For HCPL-2219 only.
I
Schematic
CC
V
CC
8
I
F
I
O
+
–
V
V
O
E
2
7
6
5
V
F
I
E
3
GND
SHIELD
1-121
Package Outline Drawings
8-Pin DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
1
7
6
5
TYPE NUMBER
6.35 ± 0.25
(0.250 ± 0.010)
OPTION CODE*
DATE CODE
HP XXXXZ
YYWW
U R
4
UL
2
3
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS.
"V" = OPTION 060
2.92 (0.115) MIN.
OPTION NUMBERS 300 AND 500 NOT MARKED.
1.080 ± 0.320
0.65 (0.025) MAX.
(0.043 ± 0.013)
2.54 ± 0.25
(0.100 ± 0.010)
8-Pin DIP Package with Gull Wing Surface Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
1.016 (0.040)
1.194 (0.047)
6
5
8
1
7
4.826
(0.190)
TYP.
6.350 ± 0.25
(0.250 ± 0.010)
9.398 (0.370)
9.906 (0.390)
2
3
4
0.381 (0.015)
0.635 (0.025)
1.194 (0.047)
1.778 (0.070)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
- 0.051
0.254
4.19
+ 0.003)
- 0.002)
MAX.
(0.165)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
1-122
Maximum Solder Reflow Thermal Profile
260
240
∆T = 145°C, 1°C/SEC
220
200
180
160
140
120
100
80
∆T = 115°C, 0.3°C/SEC
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
Note: Use of nonchlorine activated fluxes is highly recommended.
Regulatory Information
CSA
The HCPL-2200/2219 have been
approved by the following
organizations:
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
UL
VDE
Recognized under UL 1577,
Component Recognition
Program, File E55361.
Approved according to VDE
0884/06.92. (HCPL-2219 Option
060 Only)
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Units
Conditions
Min. External Air Gap L(IO1)
(External Clearance)
7.1
mm
Measured from input terminals to output terminals,
shortest distance through air.
Min. External
Tracking Path
(External Creepage)
Minimum Internal
Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative
Tracking Index)
Isolation Group
L(IO2)
7.4
0.08
200
IIIa
mm
mm
V
Measured from input terminals to output terminals,
shortest distance path along body.
Through insulation distance, conductor to conductor,
usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity.
CTI
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
1-123
VDE 0884 Insulation Related Characteristics (HCPL-2219 OPTION 060 ONLY)
Description
Symbol
Characteristic
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
I-IV
I-III
for rated mains voltage ≤ 450 V rms
Climatic Classification
55/85/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
V
IORM
630
V peak
V peak
V
x 1.875 = V , 100% Production Test with t = 1 sec,
V
PR
1181
945
IORM
PR
m
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
x 1.5 = V , Type and sample test,
V
PR
V peak
V peak
IORM
PR
t = 60 sec, Partial Discharge < 5 pC
m
Highest Allowable Overvoltage*
(Transient Overvoltage, t = 10 sec)
V
IOTM
6000
ini
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 12, Thermal Derating curve.)
Case Temperature
Input Current
Output Power
T
175
230
600
°C
mA
mW
S
I
P
S,INPUT
S,OUTPUT
9
Insulation Resistance at T , V = 500 V
R
S
≥ 10
Ω
S
IO
*Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-124
Absolute Maximum Ratings
(No Derating Required up to 70°C)
Parameter
Storage Temperature
Operating Temperature
Average Forward Input Current
Symbol
Min.
-55
-40
Max.
125
85
10
1.0
Units
°C
°C
mA
A
Note
T
S
T
1
A
I
F(AVG)
Peak Transient Input Current
I
F(TRAN)
(≤ 1 µs Pulse Width, 300 pps)
Reverse Input Voltage
Average Output Current
Supply Voltage
Three State Enable Voltage
Output Voltage
Total Package Power Dissipation
Lead Solder Temperature
Solder Reflow Temperature Profile
V
I
O
5
25
20
20
20
210
V
mA
V
V
V
R
V
0
-0.5
-0.5
CC
V
E
V
O
P
T
mW
1
260°C for 10 sec., 1.6 mm below seating plane
See Package Outline Drawings section
Recommended Operating Conditions
Parameter
Symbol
Min.
4.5
2.0
0
1.6*
–
Max.
20
20
0.8
5
0.1
85[1]
4
Units
V
V
V
mA
Power Supply Voltage
Enable Voltage High
Enable Voltage Low
Forward Input Current
Forward Input Current
Operating Temperature
Fan Out
VCC
VEH
VEL
IF(ON)
IF(OFF)
TA
mA
°C
TTL Loads
0
N
*The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be
used to permit at least a 20% CTR degradation guardband.
1-125
Electrical Specifications
For 0°C ≤ TA[1] ≤ 85°C, 4.5 V ≤ VCC ≤ 20 V, 1.6 mA ≤ IF(ON) ≤ 5 mA, 2.0 V ≤ VEH ≤ 20 V,
0.0 V ≤ VEL ≤ 0.8 V, 0 mA ≤ IF(OFF) ≤ 0.1 mA. All Typicals at TA = 25°C, VCC = 5 V, IF(ON) = 3 mA unless
otherwise specified. See Note 7.
Parameter
Logic Low
Output Voltage
Logic High
Output Voltage
Sym. Min. Typ. Max. Units
Test Conditions
IOL = 6.4 mA (4 TTL Loads)
Fig. Note
1
VOL
VOH
IOHH
0.5
V
2.4
2.0
*
V
IOH = -2.6 mA *VOH = VCC - 2.1 V
2
Output Leakage
Current (VOUT > VCC)
100
µA
VO = 5.5 V
VO = 20 V
IF = 5 mA
V = 4.5 V
CC
500 µA
Logic High Enable
Voltage
Logic Low Enable
Voltage
Logic High Enable
Current
VEH
VEL
IEH
V
0.8
V
20
µA
µA
µA
VEN = 2.7 V
VEN = 5.5 V
VEN = 20 V
100
0.004 250
Logic Low Enable
Current
IEL
-0.32 mA VEN = 0.4 V
Logic Low Supply
Current
ICCL
IF = 0 mA
IO = Open
VE = Don’t Care
IF = 5 mA
IO = Open
VE = Don’t Care
4.5
5.25
2.7
3.1
6.0 mA
7.5 mA
VCC = 5.5 V
VCC =20V
Logic High Supply
Current
ICCH
4.5 mA VCC =5.5V
6.0 mA VCC =20V
High Impedance
State Output
Current
IOZL
IOZH
-20
µA
VO = 0.4 V
VEN = 2 V,
IF = 5 mA
VEN = 2 V,
IF = 5 mA
20
100
500
µA
µA
µA
VO = 2.4 V
VO = 5.5 V
VO = 20 V
Logic Low Short
Circuit Output
Current
Logic High Short
Circuit Output
Current
Input Current
Hysteresis
Input Forward
Voltage
IOSL
2
2
mA
mA
mA
VO = VCC = 5.5V IF = 0 mA
25
VO =VCC = 20 V
40
IOSH
I = 5 mA,
VO = GND
F
-10
VCC = 5.5 V
VCC = 20 V
mA
mA
-25
IHYS
VF
0.12
1.5
V
CC
= 5 V
3
4
1.7
1.75
V
V
T = 25°C
A
IF = 5 mA
Input Reverse
BVR
5
IR = 10 µA
Breakdown Voltage
Input Diode
Temperature
Coefficient
∆VF
-1.7
60
mV/°C IF = 5 mA
∆T
A
Input Capacitance
CIN
pF
f = 1 MHz, VF = 0 V, Pins 2 and 3
1-126
Switching Specifications (AC)
For 0°C ≤ TA[1] ≤ 85°C, 4.5 V ≤ VCC ≤ 20 V, 1.6 mA ≤ IF(ON) ≤ 5 mA, 0.0 mA ≤ IF(OFF) ≤ 0.1 mA.
All Typicals at TA = 25°C, VCC = 5 V, IF(ON) = 3 mA unless otherwise specified.
Parameter
Sym. Min. Typ. Max. Units
Test Conditions
Fig. Note
Propagation Delay Time to
Logic Low Output Level
tPHL
210
160 300
170
115 300
25
ns
Without Peaking Capacitor 5, 6 4, 5
With Peaking Capacitor
Without Peaking Capacitor 5, 6 4, 5
With Peaking Capacitor
Propagation Delay Time to
Logic High Output Level
tPLH
ns
Output Enable Time to
Logic High
Output Enable Time to
Logic Low
Output Disable Time from
Logic High
Output Disable Time from
Logic Low
tPZH
tPZL
tPHZ
tPLZ
ns
ns
ns
ns
7, 9
28
105
60
7, 8
7, 9
7, 8
Output Rise Time (10-90%)
Output Fall Time (90-10%)
tr
tf
55
15
ns
ns
5, 10
5, 10
Parameter
Sym.
Device
Min.
Units
Test Conditions
Fig. Note
Logic High
Common Mode
Transient
|CMH|
IF = 1.6 mA
VCC = 5 V
TA = 25°C
11
6
HCPL-2200 1,000
HCPL-2219 2,500
HCPL-2200 1,000
HCPL-2219 2,500
V/µs |VCM| = 50 V
V/µs |VCM| = 400 V
V/µs |VCM| = 50 V
V/µs |VCM| = 400 V
Immunity
Logic Low
Common Mode
Transient
|CML|
VF = 0 V
VCC = 5 V
TA = 25°C
11
6
Immunity
Package Characteristics
Parameter
Sym. Min. Typ. Max. Units
Test Conditions
Fig. Note
Input-Output Momentary
Withstand Voltage*
Input-Output Resistance
Input-Output Capacitance
VISO
2500
V rms RH ≤ 50%, t = 1 min.,
3, 8
T = 25°C
A
RI-O
CI-O
1012
0.6
Ω
VI-O = 500 VDC
3
3
pF
f = 1 MHz, VI-O = 0 VDC
*The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Characteristics Table (if applicable), your equipment level
safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage,” publication number 5963-2203E.
1-127
Notes:
output pulse. The tPHL propagation
delay is measured from the 50% point
on the trailing edge of the input pulse
to the 1.3 V point on the trailing edge
of the output pulse.
5. When the peaking capacitor is omitted,
propagation delay times may increase
by 100 ns.
6. CML is the maximum rate of rise of the
common mode voltage that can be
sustained with the output voltage in the
logic low state (VO < 0.8 V). CMH is
the maximum rate of fall of the
common mode voltage that can be
sustained with the output voltage in the
logic high state (VO > 2.0 V).
7. Use of a 0.1 µF bypass capacitor
connected between pins 5 and 8 is
recommended.
8. In accordance with UL1577, each
optocoupler is proof tested by applying
an insulation test voltage ≥ 3000 V rms
for one second (leakage detection
current limit, II-O ≤ 5 µA). This test is
performed before the 100% production
test for partial discharge (Method b)
shown in the VDE 0884 Insulation
Characteristics Table, if applicable.
1. Derate total package power dissipa-
tion, PT, linearly above 70°C free air
temperature at a rate of 4.5 mW/°C.
2. Duration of output short circuit time
should not exceed 10 ms.
3. Device considered a two-terminal
device: pins 1, 2, 3, and 4 shorted
together and pins 5, 6, 7, and 8
shorted together.
4. The tPLH propagation delay is
measured from the 50% point on the
leading edge of the input pulse to the
1.3 V point on the leading edge of the
1.0
5
0
V
T
= 4.5 V
V
I
= 4.5 V
CC
= 25 °C
CC
= 0 mA
V
= 4.5 V
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
CC
I = 5 mA
F
-1
-2
-3
-4
A
F
4
3
V
= 6.4 mA
O
V
= 2.7 V
O
I
= -2.6 mA
OH
2
1
0
-5
-6
V
= 2.4 V
O
-7
-8
I
= 6.4 mA
0.5
OL
0.1
0
-60 -40 -20
0
20 40 60 80 100
0
1.0
1.5
2.0
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
I
– INPUT CURRENT – mA
T
– TEMPERATURE – °C
A
F
A
Figure 1. Typical Logic Low Output
Voltage vs. Temperature.
Figure 2. Typical Logic High Output
Current vs. Temperature.
Figure 3. Output Voltage vs. Forward
Input Current.
V
CC
PULSE GEN.
t
= t = 5 ns
r
f
OUTPUT V
MONITORING
NODE
f = 100 kHz
10 % DUTY
CYCLE
O
5 V
HCPL-2200
V
V
= 5 V
O
1
2
3
4
8
7
6
5
CC
619 Ω
D
1
I
F
INPUT
MONITORING
NODE
D
D
D
2
3
4
C
15 pF
=
2
GND
5 kΩ
1000
R
1
C
=
1
T
= 25 °C
120 pF
A
100
10
I
F
+
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C AND
V
F
C
.
1
2
–
R
2.15 kΩ 1.10 kΩ 681 Ω
1.0
I
I
(ON) 1.6 mA 3 mA
5 mA
F
0.1
0.01
ALL DIODES ARE 1N916 OR 1N3064.
I
(ON)
F
INPUT I
F
50 % I (ON)
F
0 mA
0.001
1.1
1.2
1.3
1.4
1.5
t
t
PHL
PLH
V
– FORWARD VOLTAGE – V
V
F
OH
OUTPUT
1.3 V
V
O
V
OL
Figure 4. Typical Input Diode Forward
Characteristic.
Figure 5. Test Circuit for t
, t
, t , and t .
PLH PHL r f
1-128
250
C = 15 pF INCLUDING PROBE
V
= 5 V
L
CC
PULSE
GENERATOR
AND JIG CAPACITANCES
.
C1 (120 pF) PEAKING
CAPACITOR IS USED.
SEE FIGURE 5.
I
(mA)
5
3
F
+5 V
V
Z
= 50 Ω
CC
O
200
150
t = t
= 5 ns
r
f
1.6
V
HCPL-2200
V
O
S1
1.6
3
5
1
2
3
4
8
7
6
5
CC
619 Ω
D
t
1
PHL
I
F
D
2
100
50
C
L
5 kΩ
D
3
t
PLH
GND
INPUT V
D
4
C
-60 -40 -20
0
20 40 60 80 100
MONITORING
NODE
T
– TEMPERATURE – °C
A
S2
D
ARE 1N916 OR 1N3064.
1-4
Figure 6. Typical Propagation Delays
vs. Temperature.
3.0 V
INPUT
1.3 V
0 V
V
E
t
t
PLZ
PZL
S1 AND
S2 CLOSED
0.5 V
0.5 V
OUTPUT
S1 CLOSED
S2 OPEN
1.3 V
V
O
V
V
OL
t
PZH
OH
≈1.5 V
OUTPUT
1.3 V
0 V
V
O
S1 OPEN
S2 CLOSED
S1 AND
S2 CLOSED
t
PHZ
Figure 7. Test Circuit for t
, t
, t
, and t
.
PZL
PHZ PZH PLZ
100
200
120
100
80
V
20 V
C
= 15 pF
CC
V
C
= 5 V
= 15 pF
L
CC
2
C
= 15 pF
L
V
CC
80
60
40
150
100
4.5 V
20 V
t
PHZ
t
PLZ
PZL
4.5 V
20 V
60
t
t
r
4.5 V
40
t
20 V
50
0
20
0
4.5 V
20
0
t
PZH
f
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
A
Figure 8. Typical Logic Low Enable
Propagation Delay vs. Temperature.
Figure 10. Typical Rise, Fall Time vs.
Temperature.
Figure 9. Typical Logic High Enable
Propagation Delay vs. Temperature.
1-129
V
CC
HCPL-2219 OPTION 060 ONLY
(mW)
HCPL-2200
V
800
700
600
500
400
300
200
100
0
P
OUTPUT V
MONITORING
NODE
S
1
2
3
4
8
7
6
5
O
CC
A
B
I
(mA)
S
R
IN
0.1 µF
BYPASS
V
FF
GND
V
CM
+
–
PULSE GENERATOR
50 V
SWITCH AT A: I = 1.6 mA
V
0
25 50 75 100 125 150 175 200
– CASE TEMPERATURE – °C
CM
0 V
T
S
F
V
OH
V
(MIN.)*
O
Figure 12. Thermal Derating Curve,
Dependence of Safety Limiting Value
with Case Temperature per
VDE 0884.
OUTPUT
SWITCH AT B: I = 0 mA
F
V
O
V
(MAX.)*
O
V
OL
* SEE NOTE 6.
Figure 11. Test Circuit for Common Mode Transient Immunity and Typical
Waveforms.
V
CC1
(+5 V)
V
CC2
120 pF (OPTIONAL*)
HCPL-2200
(4.5 TO 20 V)
V
V
CC2
CC1
(+5 V)
120 pF
(+5 V)
HCPL-2200
1.1
DATA
OUTPUT
kΩ
1.1
kΩ
R
L
V
CC
1
2
3
4
8
7
6
5
V
1
2
3
4
8
7
6
5
CC
DATA
OUTPUT
CMOS
UP TO 16
LSTTL
LOADS
OR 4 TTL
LOADS
DATA
INPUT
DATA
INPUT
TTL OR
LSTTL
GND
TTL OR
LSTTL
GND
TOTEM
TOTEM
POLE
OUTPUT
GATE
POLE
OUTPUT
GATE
V
5 V
10 V
15 V
20 V
R
L
CC2
2
1.1 K
2.37 K
3.83 K
5.11 K
1
1
2
Figure 13. Recommended LSTTL to LSTTL Circuit.
Figure 14. LSTTL to CMOS Interface Circuit.
V
(+5 V)
CC
120 pF (OPTIONAL*)
HCPL-2200
1.1
kΩ
HCPL-2200
V
(+5 V)
CC1
1.1 kΩ
V
V
CC
CC
1
2
3
4
8
7
6
5
1
2
3
4
8
DATA
INPUT
7
6
5
4.7 kΩ
D1
DATA
INPUT
TTL OR
LSTTL
TTL OR
LSTTL
GND
GND
OPEN
COLLECTOR
GATE
D1 (1N4150) REQUIRED FOR
ACTIVE PULL-UP DRIVER.
Figure 16. Series LED Drive with Open Collector Gate
(4.7 kΩ Resistor Shunts I from the LED).
Figure 15. Recommended LED Drive Circuit.
OH
*The 120 pF capacitor may be omitted in applications where 500 ns propagation delay is sufficient.
1-130
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