HCPL0454 [HP]
High CMR, High Speed Optocouplers; 高CMR ，高速光电耦合器
| 型号： | HCPL0454 |
| 厂家： | 
HEWLETT-PACKARD |
| 描述： | High CMR, High Speed Optocouplers |
| 文件： | 总16页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
H
High CMR, High Speed
Optocouplers
Technical Data
HCPL-4504
HCPL-0454
HCNW4504
Features
• Short Propagation Delays
for TTL and IPM
Applications
Description
• Inverter Circuits and
Intelligent Power Module
(IPM) interfacing -
High Common Mode Transient
Immunity (> 10 kV/µs for an
IPM load/drive) and (tPLH - tPHL
Specified (See Power Inverter
Dead Time section)
• Line Receivers -
Short Propagation Delays and
Low Input-Output Capacitance
• High Speed Logic Ground
Isolation - TTL/TTL, TTL/
CMOS, TTL/LSTTL
• Replaces Pulse
Transformers -
Save Board Space and Weight
• Analog Signal Ground
Isolation -
Integrated Photodetector
Provides Improved Linearity
over Phototransistors
These optocouplers are similar to
HP’s other high speed transistor
optocouplers but with shorter
propagation delays and higher
CTR. The HCPL-4504/0454 and
HCNW4504 also have a guaran-
teed propagation delay difference
(tPLH - tPHL). These features make
these optocouplers an excellent
solution to IPM inverter dead time
and other switching problems.
Applications
• 15 kV/µs Minimum Common
Mode Transient Immunity at
VCM = 1500 V for TTL/Load
Drive
• High CTR at TA = 25°C
>25% for HCPL-4504/0454
>23% for HCNW4504
• Electrical Specifications for
Common IPM Applications
• TTL Compatible
• Guaranteed Performance
from 0°C to 70°C
• Open Collector Output
• Safety Approval
UL Recognized - 2500 V rms
for 1 minute (5000 V rms for
1 minute for
HCPL-4504#020 and
HCNW4504)per UL1577
CSA Approved
)
Functional Diagram
VDE 0884 Approved
-VIORM = 630 V peak for
HCPL-4504#060
-VIORM = 1414 V peak for
HCNW4504
BSI Certified (HCNW4504)
8
7
6
5
NC
ANODE
CATHODE
NC
1
2
3
4
V
CC
TRUTH TABLE
NC
LED
V
O
ON
OFF
LOW
HIGH
• Available in 8-Pin DIP, SO-8,
Widebody Packages
V
O
GND
A 0.1 µF bypass capacitor between pins 5 and 8 is recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to
prevent damage and/or degradation which may be induced by ESD.
1-33
5965-3604E
The HCPL-4504/0454 and
These single channel, diode-
transistor optocouplers are
available in 8-Pin DIP, SO-8, and
Widebody package configura-
tions. An insulating layer between
a LED and an integrated
photodetector provide electrical
insulation between input and
output. Separate connections for
the photodiode bias and output-
transistor collector increase the
speed up to a hundred times that
of a conventional phototransistor
coupler by reducing the base
collector capacitance.
HCNW4504 CTR, propagation
delay, and CMR are specified for
both TTL and IPM load/drive
conditions. Specifications and
typical performance plots for both
TTL and IPM conditions are
provided for ease of application.
Selection Guide
Single Channel Packages
Small Outline
8-Pin DIP
(300 Mil)
Widebody
(400 Mil)
SO-8
HCPL-4504
HCPL-0454
HCNW4504
Ordering Information
Specify Part Number followed by Option Number (if desired).
Example:
HCPL-4504#XXX
020 = UL 5000 V rms/1 Minute Option*
060 = VDE 0884 VIORM = 630 V peak Option*
300 = Gull Wing Surface Mount Option†
500 = Tape and Reel Packaging Option
Option data sheets available. Contact your Hewlett-Packard sales representative or authorized distributor for
information.
*For HCPL-4504 only. Combination of Option 020 and Option 060 is not available.
†Gull wing surface mount option applies to through hole parts only.
Schematic
I
CC
8
V
CC
I
F
+
2
ANODE
V
F
I
O
6
5
–
3
V
O
CATHODE
SHIELD
GND
1-34
Package Outline Drawings
8-Pin DIP Package (HCPL-4504)
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
1
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
TYPE NUMBER
OPTION CODE*
DATE CODE
HP XXXXZ
YYWW
U R
4
UL
2
3
RECOGNITION
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
- 0.051
0.254
5° TYP.
+ 0.003)
- 0.002)
(0.010
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
DIMENSIONS IN MILLIMETERS AND (INCHES).
* MARKING CODE LETTER FOR OPTION NUMBERS.
"L" = OPTION 020
"V" = OPTION 060
1.080 ± 0.320
(0.043 ± 0.013)
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
OPTION NUMBERS 300 AND 500 NOT MARKED.
8-Pin DIP Package with Gull Wing Surface Mount Option 300 (HCPL-4504)
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
1.016 (0.040)
1.194 (0.047)
6
5
8
1
7
4.826
(0.190)
TYP.
6.350 ± 0.25
(0.250 ± 0.010)
9.398 (0.370)
9.906 (0.390)
2
3
4
0.381 (0.015)
0.635 (0.025)
1.194 (0.047)
1.778 (0.070)
9.65 ± 0.25
(0.380 ± 0.010)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
7.62 ± 0.25
(0.300 ± 0.010)
+ 0.076
- 0.051
0.254
4.19
+ 0.003)
- 0.002)
MAX.
(0.165)
(0.010
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
0.635 ± 0.130
(0.025 ± 0.005)
2.54
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
1-35
Small Outline SO-8 Package (HCPL-0454)
8
7
6
5
5.842 ± 0.203
(0.236 ± 0.008)
XXX
3.937 ± 0.127
(0.155 ± 0.005)
YWW
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
1
2
3
4
0.381 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSG
0.432
(0.017)
7°
5.080 ± 0.127
(0.200 ± 0.005)
45° X
3.175 ± 0.127
(0.125 ± 0.005)
0.228 ± 0.025
(0.009 ± 0.001)
1.524
(0.060)
0.152 ± 0.051
(0.006 ± 0.002)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.305
(0.012)
MIN.
8-Pin Widebody DIP Package (HCNW4504)
11.00
MAX.
11.15 ± 0.15
(0.442 ± 0.006)
(0.433)
9.00 ± 0.15
(0.354 ± 0.006)
7
6
5
8
TYPE NUMBER
DATE CODE
HP
HCNWXXXX
YYWW
1
3
2
4
10.16 (0.400)
TYP.
1.55
(0.061)
MAX.
7° TYP.
+ 0.076
- 0.0051
0.254
+ 0.003)
- 0.002)
(0.010
5.10
(0.201)
MAX.
3.10 (0.122)
3.90 (0.154)
0.51 (0.021) MIN.
2.54 (0.100)
TYP.
1.78 ± 0.15
(0.070 ± 0.006)
0.40 (0.016)
0.56 (0.022)
DIMENSIONS IN MILLIMETERS (INCHES).
1-36
8-Pin Widebody DIP Package with Gull Wing Surface Mount Option 300 (HCNW4504)
11.15 ± 0.15
(0.442 ± 0.006)
PAD LOCATION (FOR REFERENCE ONLY)
7
6
5
8
6.15
TYP.
(0.242)
9.00 ± 0.15
(0.354 ± 0.006)
12.30 ± 0.30
(0.484 ± 0.012)
1
3
2
4
0.9
(0.035)
1.3
(0.051)
12.30 ± 0.30
(0.484 ± 0.012)
1.55
(0.061)
MAX.
11.00
MAX.
(0.433)
4.00
MAX.
(0.158)
1.78 ± 0.15
(0.070 ± 0.006)
1.00 ± 0.15
(0.039 ± 0.006)
0.75 ± 0.25
(0.030 ± 0.010)
+ 0.076
- 0.0051
2.54
(0.100)
BSC
0.254
+ 0.003)
- 0.002)
(0.010
DIMENSIONS IN MILLIMETERS (INCHES).
7° NOM.
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
Solder Reflow Temperature Profile
(HCPL-0454 and Gull Wing Surface Mount Option Parts)
260
240
∆T = 145°C, 1°C/SEC
220
∆T = 115°C, 0.3°C/SEC
200
180
160
140
120
100
80
∆T = 100°C, 1.5°C/SEC
60
40
20
0
0
1
2
3
4
5
6
7
8
9
10
11
12
TIME – MINUTES
Note: Use of nonchlorine activated fluxes is highly recommended.
1-37
Regulatory Information
CSA
BSI
The devices contained in this data
sheet have been approved by the
following organizations:
Approved under CSA Component
Acceptance Notice #5, File CA
88324.
Certification according to
BS451:1994,
(BS EN60065:1994);
BS EN60950:1992
UL
VDE
(BS7002:1992) and
EN41003:1993 for Class II
applications (HCNW4504 only).
Recognized under UL 1577,
Component Recognition
Program, File E55361.
Approved according to VDE
0884/06.92 (HCNW4504 and
HCPL-4504#060 only).
Insulation and Safety Related Specifications
8-Pin DIP
Widebody
(300 Mil) SO-8 (400 Mil)
Parameter
Symbol
Value
Value
Value
Units
Conditions
Minimum External
Air Gap (External
Clearance)
L(101)
7.1
4.9
9.6
mm
Measured from input terminals
to output terminals, shortest
distance through air.
Minimum External
Tracking (External
Creepage)
L(102)
7.4
4.8
10.0
1.0
mm
mm
Measured from input terminals
to output terminals, shortest
distance path along body.
Minimum Internal
Plastic Gap
(Internal Clearance)
0.08
0.08
Through insulation distance,
conductor to conductor, usually
the direct distance between the
photoemitter and photodetector
inside the optocoupler cavity.
Minimum Internal
Tracking (Internal
Creepage)
NA
200
IIIa
NA
200
IIIa
4.0
200
IIIa
mm
Measured from input terminals
to output terminals, along
internal cavity.
Tracking Resistance
(Comparative
Tracking Index)
CTI
Volts DIN IEC 112/VDE 0303 Part 1
Isolation Group
Material Group
(DIN VDE 0110, 1/89, Table 1)
Option 300 - surface mount classification is Class A in accordance with CECC 00802.
1-38
VDE 0884 Insulation Related Characteristics
(HCPL-4504 OPTION 060 ONLY)
Description
Symbol
Characteristic
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 300 V rms
I-IV
I-III
55/100/21
2
for rated mains voltage ≤ 450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
V
630
V peak
V peak
IORM
V
IORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
VPR
VPR
1181
945
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
V
IORM x 1.5 = VPR, Type and sample test,
V peak
V peak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
V
6000
IOTM
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 15, Thermal Derating curve.)
Case Temperature
TS
IS,INPUT
PS,OUTPUT
175
230
600
≥ 109
°C
mA
mW
Input Current
Output Power
Insulation Resistance at TS, V = 500 V
RS
Ω
IO
VDE 0884 Insulation Related Characteristics (HCNW4504 ONLY)
Description
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 600 V rms
for rated mains voltage ≤ 1000 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
Symbol Characteristic Units
I-IV
I-III
55/85/21
2
V
1414
V peak
V peak
IORM
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
VPR
VPR
2652
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and sample test,
2121
8000
V peak
V peak
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage*
(Transient Overvoltage, tini = 10 sec)
V
IOTM
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Figure 15, Thermal Derating curve.)
Case Temperature
TS
IS,INPUT
PS,OUTPUT
150
400
700
≥ 109
°C
mA
mW
Input Current
Output Power
Insulation Resistance at TS, V = 500 V
RS
Ω
IO
*Refer to the front of the optocoupler section of the current catalog under Product Safety Regulations section (VDE 0884), for a
detailed description.
Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in
application.
1-39
Absolute Maximum Ratings
Parameter
Symbol
Device
Min.
Max. Units Note
Storage Temperature
Operating Temperature
T
T
A
-55
125
100
°C
°C
S
HCPL-4504 -55
HCPL-0454
HCNW4504 -55
85
25
Average Forward Input Current
Peak Forward Input Current
(50% duty cycle, 1 ms pulse width)
(50% duty cycle, 1 ms pulse width)
Peak Transient Input Current
I
mA
mA
1
2
F(AVG)
I
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
F(PEAK)
50
40
1
I
A
V
F(TRANS)
(≤ 1 µs pulse width, 300 pps)
0.1
5
Reverse LED Input Voltage (Pin 3-2)
Input Power Dissipation
V
R
3
45
P
IN
mW
3
4
40
8
16
30
20
100
Average Output Current (Pin 6)
Peak Output Current
Supply Voltage (Pin 8-5)
Output Voltage (Pin 6-5)
Output Power Dissipation
I
mA
mA
V
V
mW
O(AVG)
I
O(PEAK)
V
-0.5
-0.5
CC
V
O
P
O
Lead Solder Temperature
(Through-Hole Parts Only)
1.6 mm below seating plane,
10 seconds up to seating plane, 10 seconds
T
HCPL-4504
260
260
°C
°C
LS
HCNW4504
HCPL-0454
and
Option 300
Reflow Temperature Profile
T
RP
See Package Outline
Drawings section
1-40
Electrical Specifications (DC)
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified. See note 12.
Parameter
Current
Transfer Ratio
Symbol
CTR
Device
Min. Typ.* Max. Units
Test Conditions
TA = 25°C VO = 0.4 V
VO = 0.5 V
TA = 25°C VO = 0.4 V
VO = 0.5 V
TA = 25°C VO = 0.4 V
VO = 0.5 V
TA = 25°C VO = 0.4 V
VO = 0.5 V
Fig. Note
HCPL-4504
HCPL-0454
HCNW4504
25
21
23
19
26
22
25
21
32
34
29
31
35
37
33
35
0.2
60
%
IF = 16 mA, 1, 2,
VCC = 4.5 V
5
4
60
63
65
Current
Transfer Ratio
CTR
VOL
HCPL-4504
HCPL-0454
HCNW4504
%
IF = 12 mA, 1, 2,
5
VCC = 4.5 V
4
65
68
Logic Low
Output Voltage
HCPL-4504
HCPL-0454
HCNW4504
0.4
0.5
0.4
0.5
0.5
1
V
TA = 25°C IO = 4.0 mA
IO = 3.3 mA
TA = 25°C IO = 3.6 mA
IF = 16 mA,
VCC = 4.5 V
0.2
I
O = 3.0 mA
Logic High
Output Current
IOH
0.003
0.01
µA
TA = 25°C VO = VCC = 5.5 V IF = 0 mA
TA = 25°C VO = VCC = 15 V
5
50
Logic Low
Supply Current
Logic High
Supply Current
Input Forward
Voltage
ICCL
ICCH
VF
50
200
µA
µA
V
IF = 16 mA, VO = Open, VCC = 15 V
12
12
0.02
1.5
1
2
1.7
1.8
1.85
1.95
TA = 25°C IF = 0 mA, VO = Open,
VCC = 15 V
TA = 25°C IF = 16 mA
HCPL-4504
HCPL-0454
HCNW4504 1.45
1.35
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
HCPL-4504
HCPL-0454
HCNW4504
3
1.59
TA = 25°C IF = 16 mA
IR = 10 µA
Input Reverse
Breakdown
Voltage
Temperature
Coefficient of
Forward Voltage
Input
BVR
5
V
3
IR = 100 µA, TA = 25°C
∆VF
∆TA
-1.6
mV/°C IF = 16 mA
-1.4
60
CIN
pF
f = 1 MHz, VF = 0 V
Capacitance
70
*All typicals at TA = 25°C.
1-41
AC Switching Specifications
Over recommended temperature (TA = 0°C to 70°C) unless otherwise specified.
Parameter
Symbol
Min. Typ. Max. Units
Test Conditions
Fig. Note
Propagation
Delay Time
to Logic Low
at Output
0.2
0.3
TA = 25°C Pulse: f = 20 kHz,
Duty Cycle = 10%,
6,
8, 9
tPHL
µs
9
10
9
0.2
0.5
IF = 16 mA, VCC = 5.0 V,
RL = 1.9 kΩ, CL = 15 pF,
V
THHL = 1.5 V
0.2
0.1
0.5
0.5
0.7
1.0
TA = 25°C Pulse: f = 10 kHz,
6,
10-14
Duty Cycle = 50%,
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
THHL = 1.5 V
V
Propagation
Delay Time
to Logic
0.3
0.3
0.5
0.7
TA = 25°C Pulse: f = 20 kHz,
Duty Cycle = 10%,
6,
8, 9
tPLH
µs
IF = 16 mA, VCC = 5.0 V,
RL = 1.9 kΩ, CL = 15 pF,
High at
Output
VTHLH = 1.5 V
0.3
0.2
0.8
0.8
1.1
1.4
TA = 25°C Pulse: f = 10 kHz,
6,
10-14
Duty Cycle = 50%,
10
15
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
THLH = 2.0 V
V
Propagation
Delay
-0.4
-0.7
0.3
0.3
0.9
1.3
TA = 25°C Pulse: f = 10 kHz,
6,
10-14
t
PLH-tPHL
µs
Duty Cycle = 50%,
Difference
Between
Any 2 Parts
IF = 12 mA, VCC = 15.0 V,
RL = 20 kΩ, CL = 100 pF,
THHL = 1.5 V, VTHLH = 2.0 V
V
Common
VCC = 5.0 V, RL = 1.9 kΩ,
Mode
15
15
30
30
CL = 15 pF, IF = 0 mA
7
7
7, 9
Transient
Immunity at
Logic High
Level Output
|CMH|
|CML|
kV/µs TA = 25°C
VCC = 15.0 V, RL = 20 kΩ,
VCM
=
CL = 100 pF, IF = 0 mA
8, 10
1500 VP-P
Common
Mode
Transient
Immunity at
Logic Low
Level Output
VCC = 5.0 V, RL = 1.9 kΩ,
CL = 15 pF, IF = 16 mA
15
10
30
30
7
7
7, 9
kV/µs TA = 25°C
VCC = 15.0 V, RL = 20 kΩ,
VCM
=
CL = 100 pF, IF = 12 mA
8, 10
1500 VP-P
15
30
VCC = 15.0 V, RL = 20 kΩ,
CL = 100 pF, IF = 16 mA
7
7
8, 10
8, 10
*All typicals at TA = 25°C.
1-42
Package Characteristics
Over recommended temperature (TA = 0°C to 25°C) unless otherwise specified.
Parameter
Sym.
Device
Min. Typ.* Max. Units Test Conditions
Fig. Note
Input-Output
Momentary
Withstand
Voltage†
V
ISO
HCPL-4504 2500
HCPL-0454
HCNW4504 5000
V rms RH ≤ 50%,
6, 13
t = 1 min.,
T = 25°C
A
6, 14
HCPL-4504 5000
(Option 020)
6, 11,
14
Input-Output
Resistance
RI-O
HCPL-4504
HCPL-0454
HCNW4504
1012
1013
Ω
VI-O = 500 Vdc
6
1012
1011
T = 25°C
A
T = 100°C
A
Input-Output
Capacitance
CI-O
HCPL-4504
HCPL-0454
HCNW4504
0.6
0.5
pF
f = 1 MHz
6
0.6
*All typicals at TA = 25°C..
†The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage.”
Notes:
1. Derate linearly above 70°C free-air temperature at a rate of 0.8 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 0.5 mA/°C (SO-8).
2. Derate linearly above 70°C free-air temperature at a rate of 1.6 mA/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.0 mA/°C (SO-8).
3. Derate linearly above 70°C free-air temperature at a rate of 0.9 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 1.1 mW/°C (SO-8).
4. Derate linearly above 70°C free-air temperature at a rate of 2.0 mW/°C (8-Pin DIP).
Derate linearly above 85°C free-air temperature at a rate of 2.3 mW/°C (SO-8).
5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current, IO, to the forward LED input current,
IF, times 100.
6. Device considered a two-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
7. Under TTL load and drive conditions: Common mode transient immunity in a Logic High level is the maximum tolerable (positive)
dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state
(i.e., VO > 2.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the
trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V).
8. Under IPM (Intelligent Power Module) load and LED drive conditions: Common mode transient immunity in a Logic High level is
the maximum tolerable dVCM/dt on the leading edge of the common mode pulse, VCM, to assure that the output will remain in a
Logic High state (i.e., VO > 3.0 V). Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt on
the trailing edge of the common mode pulse signal, VCM, to assure that the output will remain in a Logic Low state
(i.e., VO < 1.0 V).
9. The 1.9 kΩ load represents 1 TTL unit load of 1.6 mA and the 5.6 kΩ pull-up resistor.
10. The RL = 20 kΩ, CL = 100 pF load represents an IPM (Intelligent Power Module) load.
11. See Option 020 data sheet for more information.
12. Use of a 0.1 µF bypass capacitor connected between pins 5 and 8 is recommended.
13. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second
(leakage detection current limit, Ii-o ≤ 5 µA). This test is performed before the 100% Production test shown in the VDE 0884
Insulation Related Characteristics Table, if applicable.
14. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second
(leakage detection current limit, Ii-o ≤ 5 µA). This test is performed before the 100% Production test shown in the VDE 0884
Insulation Related Characteristics Table, if applicable.
15. The difference between tPLH and tPHL between any two devices (same part number) under the same test condition. (See Power
Inverter Dead Time and Propagation Delay Specifications section.)
1-43
HCPL-4504/0454
HCNW4504
40 mA
35 mA
T
= 25°C
= 5.0 V
T = 25°C
A
CC
A
10
20
18
16
14
12
10
8
V
V
= 5.0 V
CC
40 mA
35 mA
30 mA
25 mA
20 mA
30 mA
25 mA
20 mA
5
15 mA
10 mA
15 mA
10 mA
6
4
I
= 5 mA
F
2
0
I
= 5 mA
F
0
0
20
0
20
10
– OUTPUT VOLTAGE – V
10
– OUTPUT VOLTAGE – V
V
V
O
O
Figure 1. DC and Pulsed Transfer Characteristics.
HCPL-4504/0454
1.5
HCNW4504
NORMALIZED
2.0
I
= 16 mA
F
V
= 0.4 V
O
V
T
= 5.0 V
= 25°C
A
CC
1.6
1.0
1.2
0.8
0.5
0.0
NORMALIZED
= 16 mA
I
F
V
= 0.4 V
O
0.4
0
V
= 5.0 V
= 25°C
CC
T
A
0
2
4
6
8 10 12 14 16 18 20 22 24 26
0
5
10
15
20
25
I
– INPUT CURRENT – mA
I – INPUT CURRENT – mA
F
F
Figure 2. Current Transfer Ratio vs. Input Current.
HCNW4504
HCPL-4504/0454
1000
100
10
1000
100
10
T
A
= 25°C
I
I
F
F
T
A
= 25°C
+
V
–
+
V
–
F
F
1.0
1.0
0.1
0.1
0.01
0.001
0.01
0.001
1.2
1.3
1.4
1.5
1.6
1.7
1.1
1.2
1.3
1.4
1.5
1.6
V
– FORWARD VOLTAGE – VOLTS
V
– FORWARD VOLTAGE – VOLTS
F
F
Figure 3. Input Current vs. Forward Voltage.
1-44
HCPL-4504/0454
HCNW4504
NORMALIZED
4
3
2
10
10
10
1.1
1.0
1.05
1.0
I
= 16 mA
F
V
= 0.4 V
= 5.0 V
O
I
= 0 mA
F
V
CC
V
O
= V = 5.0 V
CC
T
= 25°C
A
0.9
0.8
0.7
0.6
NORMALIZED
= 16 mA
1
0
10
10
0.95
0.9
I
F
V
= 0.4 V
O
V
= 5.0 V
CC
= 25°C
T
A
-1
10
10
-2
0.85
-60 -40 -20
0
20 40 60 80 100 120
-60 -40 -20
0
20 40 60 80 100 120
-60 -40 -20
0
20 40 60 80 100 120
T
A
– TEMPERATURE – °C
T
– TEMPERATURE – °C
T
A
– TEMPERATURE – °C
A
Figure 4. Current Transfer Ratio vs. Temperature.
Figure 5. Logic High Output Current
vs. Temperature.
I
F
I
F
PULSE
GEN.
8
7
6
5
1
2
3
4
V
CC
0
Z
t
= 50 Ω
= 5 ns
O
r
R
V
L
CC
V
O
V
O
V
V
THLH
THHL
0.1µF
V
I
MONITOR
F
OL
C
L
R
M
t
t
PHL
PLH
Figure 6. Switching Test Circuit.
8
7
6
5
V
CC
1
2
3
4
V
CM
90% 90%
0 V
I
F
10%
10%
R
L
t
r
A
t
f
B
V
O
0.1µF
V
V
O
CC
SWITCH AT A: I = 0 mA
F
C
L
V
FF
V
V
O
V
CM
OL
+
–
SWITCH AT B: I = 12 mA, 16 mA
F
PULSE GEN.
Figure 7. Test Circuit for Transient Immunity and Typical Waveforms.
1-45
HCPL-4504/0454
= 5.0 V
R = 1.9 kΩ
C = 15 pF
HCNW4504
= 1.5 V
1.4
1.2
1.0
0.8
0.50
0.45
0.50
0.45
V
= 5.0 V
= 25° C
= 15 pF
= V
CC
V
V
= 5.0 V
CC
CC
T
A
R = 1.9 kΩ
L
L
C
L
C = 15 pF
L
L
V
= 1.5 V
THLH
0.40
0.40
THHL
V
= V
= 1.5 V
THLH
V
= V
THLH
THHL
10% DUTY CYCLE
THHL
t
t
PLH
PLH
10% DUTY CYCLE
10% DUTY CYCLE
t
PLH
0.35
0.30
0.25
0.35
0.30
0.25
t
PHL
0.6
0.4
0.2
0.0
t
PHL
I
= 10 mA
= 16 mA
F
t
PHL
I
F
0.20
0.20
I
= 10 mA
= 16 mA
I
= 10 mA
= 16 mA
F
F
0.15
0.10
0.15
0.10
I
I
F
F
0
2
4
6
8
10 12 14 16 18 20
-60 -40 -20
0
20 40 60 80 100 120
-60 -40 -20
0
20 40 60 80 100
120
R
– LOAD RESISTANCE – kΩ
L
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
Figure 8. Propagation Delay Time vs. Temperature.
Figure 9. Propagation Delay Time vs.
Load Resistance.
1.8
1.1
1.0
2.6
2.4
V
= 15.0 V
V
R
= 15.0 V
= 20 kΩ
I
= 10 mA
I = 16 mA
F
V
= 5.0 V
= 25° C
CC
= 25° C
CC
L
F
CC
1.6
1.4
T
T
A
A
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
C = 100 pF
C = 100 pF
C = 100 pF
L
L
L
0.9
V
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
= 2.0 V
V
= 1.5 V
= 2.0 V
THHL
THLH
THHL
THLH
THHL
t
PLH
1.2
1.0
0.8
0.6
0.4
V
THLH
t
PLH
0.8
0.7
0.6
50% DUTY CYCLE
50% DUTY CYCLE
50% DUTY CYCLE
t
PLH
t
PHL
I
= 10 mA
I = 16 mA
F
F
t
PHL
8
0.5
t
PHL
I
I
= 10 mA
= 16 mA
F
0.4
0.3
0.2
0.0
0.2
0.0
F
-60 -40 -20
0
20 40
0
2
4
6
10 12 14 16 18 20
60 80 100 120
0
5
10 15 20 25 30 35 40 45 50
R
– LOAD RESISTANCE – kΩ
R – LOAD RESISTANCE – kΩ
T
A
– TEMPERATURE – °C
L
L
Figure 10. Propagation Delay Time vs.
Load Resistance.
Figure 11. Propagation Delay Time vs.
Temperature.
Figure 12. Propagation Delay Time vs.
Load Resistance.
3.5
1.2
V
= 15.0 V
= 25° C
T
R
= 25° C
= 20 kΩ
C = 100 pF
L
CC
A
L
t
PLH
PHL
1.1
1.0
T
A
3.0
2.5
2.0
1.5
1.0
0.5
R = 20 kΩ
L
V
= 1.5 V
= 2.0 V
V
V
= 1.5 V
THHL
THLH
THHL
0.9
0.8
0.7
V
= 2.0 V
THLH
50% DUTY CYCLE
50% DUTY CYCLE
t
PLH
t
0.6
0.5
0.4
0.3
0.2
t
PHL
I
= 10 mA
= 16 mA
F
I
= 10 mA
= 16 mA
F
I
F
I
F
0.0
0
100 200 300 400 500 600 700 800 9001000
– LOAD CAPACITANCE – pF
10 11 12 13 14 15 16 17 18 19 20
– SUPPLY VOLTAGE – V
R
V
L
CC
Figure 13. Propagation Delay Time vs.
Load Capacitance.
Figure 14. Propagation Delay Time vs.
Supply Voltage.
1-46
HCPL-4504 OPTION 060
(mW)
800
700
600
500
400
300
+HV
P
S
+
I
(mA)
S
HCPL-4504/0454
HCNW4504
8
7
6
2
3
LED 1
BASE/GATE
DRIVE CIRCUIT
Q1
OUT 1
(230)
200
5
100
0
0
25 50 75 100 125 150 175 200
+
HCPL-4504/0454
HCNW4504
T
– CASE TEMPERATURE – °C
S
8
7
6
HCNW4504
2
3
LED 2
1000
P
(mW)
S
900
800
700
600
500
400
300
200
BASE/GATE
DRIVE CIRCUIT
Q2
I
(mA)
S
OUT 2
5
–HV
Figure 16. Typical Power Inverter.
100
0
0
25
50 75 100 125 150 175
T
– CASE TEMPERATURE – °C
S
Figure 15. Thermal Derating Curve,
Dependence of Safety Limiting Valve
with Case Temperature per VDE 0884.
LED 1
OUT 1
Power Inverter Dead
Time and Propagation
Delay Specifications
t
PLH min
(t
–t )
PLH max PLH min
The HCPL-4504/0454 and
t
PLH max
HCNW4504 include a specifica-
tion intended to help designers
minimize “dead time” in their
power inverter designs. The new
“propagation delay difference”
specification (tPLH - tPHL) is useful
for determining not only how
much optocoupler switching delay
is needed to prevent “shoot-
through” current, but also for
determining the best achievable
worst-case dead time for a given
design.
TURN-ON DELAY
–t
(t
)
PLH max PLH min
LED 2
OUT 2
t
PHL min
(t
–t
)
PHL max PHL min
t
PHL max
MAXIMUM DEAD TIME
When inverter power transistors
switch (Q1 and Q2 in Figure 17),
it is essential that they never
Figure 17. LED Delay and Dead Time Diagram.
1-47
conduct at the same time.
transistor turns off when the
optocoupler LED turns on; this
type of design, however, requires
additional fail-safe circuitry to
turn off the power transistor if an
over-current condition is
detected. The timing illustrated in
Figure 17 assumes that the power
transistor turns on when the
optocoupler LED turns on.
time is the sum of the maximum
difference in turn-on delay plus
the maximum difference in turn-
off delay,
Extremely large currents will flow
if there is any overlap in their
conduction during switching
transitions, potentially damaging
the transistors and even the sur-
rounding circuitry. This “shoot-
through” current is eliminated by
delaying the turn-on of one
transistor (Q2) long enough to
ensure that the opposing
transistor (Q1) has completely
turned off. This delay introduces a
small amount of “dead time” at
the output of the inverter during
which both transistors are off
during switching transitions.
Minimizing this dead time is an
important design goal for an
inverter designer.
[(tPLHmax-tPLHmin)+(tPHLmax-tPHLmin)].
This expression can be
rearranged to obtain
[(tPLHmax-tPHLmin)-(tPHLmin-tPHLmax)],
and further rearranged to obtain
The LED signal to turn on Q2
should be delayed enough so that
an optocoupler with the very
fastest turn-on propagation delay
(tPHLmin) will never turn on before
an optocoupler with the very
[(tPLH-tPHL max
)
-(tPLH-tPHL)min],
which is the maximum minus the
slowest turn-off propagation delay minimum data sheet values of
(tPLHmax) turns off. To ensure this, (tPLH-tPHL). The difference
the turn-on of the optocoupler
should be delayed by an amount
no less than (tPLHmax - tPHLmin),
which also happens to be the
maximum data sheet value for the
propagation delay difference
specification, (tPLH - tPHL). The
HCPL-4504/0454 and
HCNW4504 specify a maximum
(tPLH - tPHL) of 1.3 µs over an
operating temperature range
of 0-70°C.
between the maximum and
minimum values depends directly
on the total spread in propagation
delays and sets the limit on how
good the worst-case dead time
can be for a given design.
Therefore, optocouplers with tight
propagation delay specifications
(and not just shorter delays or
lower pulse-width distortion) can
achieve short dead times in power
inverters. The HCPL-4504/0454
and HCNW4504 specify a
The amount of turn-on delay
needed depends on the propaga-
tion delay characteristics of the
optocoupler, as well as the
characteristics of the transistor
base/gate drive circuit. Consider-
ing only the delay characteristics
of the optocoupler (the charac-
teristics of the base/gate drive
circuit can be analyzed in the
same way), it is important to
know the minimum and maximum
Although (tPLH-tPHL max
)
tells the
minimum (tPLH - tPHL) of -0.7 µs
over an operating temperature
range of 0-70°C, resulting in a
turn-on (tPHL) and turn-off (tPLH
propagation delay specifications,
preferably over the desired
)
designer how much delay is
needed to prevent shoot-through
current, it is insufficient to tell the maximum dead time of 2.0 µs
operating temperature range. The
importance of these specifications
is illustrated in Figure 17. The
waveforms labeled “LED1”,
designer how much dead time a
design will have. Assuming that
the optocoupler turn-on delay is
when the LED turn-on delay is
equal to (tPLH-tPHL max, or 1.3 µs.
)
exactly equal to (tPLH - tPHL max
)
,
It is important to maintain
accurate LED turn-on delays
because delays shorter than
“LED2”, “OUT1”, and “OUT2” are
the input and output voltages of
the optocoupler circuits driving
Q1 and Q2 respectively. Most
inverters are designed such that
the power transistor turns on
when the optocoupler LED turns
on; this ensures that both power
transistors will be off in the event
of a power loss in the control
circuit. Inverters can also be
designed such that the power
the minimum dead time is zero
(i.e., there is zero time between
the turn-off of the very slowest
optocoupler and the turn-on of
the very fastest optocoupler).
(tPLH - tPHL max may allow shoot-
)
through currents, while longer
delays will increase the worst-case
dead time.
Calculating the maximum dead
time is slightly more complicated.
Assuming that the LED turn-on
delay is still exactly equal to
(tPLH - tPHL max
)
, it can be seen in
Figure 17 that the maximum dead
1-48
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