MSO8000 [HP]
FPGA Dynamic Probe for Xilinx; FPGA动态探头用于Xilinx
| 型号： | MSO8000 |
| 厂家： | 
HEWLETT-PACKARD |
| 描述： | FPGA Dynamic Probe for Xilinx |
| 文件： | 总8页 (文件大小：1061K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Agilent Technologies
Infiniium MSO8000 and MSO9000 Series
N5433A FPGA Dynamic Probe for Altera
Data Sheet
The challenge
You rely on the insight a MSO
(mixed-signal oscilloscope)
provides to understand the
behavior of your FPGA in
the context of the surrounding
system. Design engineers
typically take advantage of the
programmability of the FPGA to
route internal nodes to a small
number of physical pins for
debugging. While this approach
is very useful, it has significant
limitations.
• Since pins on the FPGA
are typically an expensive
resource, there are a relatively
small number available for
debug. This limits internal
visibility (i.e. one pin is
required for each internal
signal to be probed).
Figure 1. FPGA dynamic probe for Altera used in conjunction with an Agilent MSO
provides an effective solution for simple through complex debugging of systems
incorporating Altera FPGAs.
• Finally, the process required
to map the signal names from
your FPGA design to the
out, you need to manually
update these signal names
on the MSO, which takes
additional time and is a
potential source of confusing
errors.
• When you need to access
different internal signals,
MSO digital channel labels is
manual and tedious.
you must change your design
to route these signals to the
available pins. This can be time
consuming and can affect the
timing of your FPGA design.
When new signals are routed
Debug your FPGAs faster and more effectively with a MSO
FPGA dynamic probe lets you:
Probe outputs
on FPGA pins
SW application supported
by all Infiniium MSOs.
View internal activity – With the
digital channels on your MSO, you
are normally limited to measuring
Board
signals at the periphery of the
FPGA. With the FPGA dynamic
FPGA
LAI
probe, you can now access signals
internal to the FPGA. You can
measure up to 256 internal
signals for each external pin
Parallel
or USB
dedicated to debug, unlocking
visibility into your design that
you never had before.
JTAG
Make multiple measurements in
seconds – Moving probe points
internal to an FPGA used to be
time consuming. Now, in less than
a second, you can easily measure
different sets of internal signals
without design changes. FPGA
timing stays constant when you
select new sets of internal signals
for probing.
Altera programming hardware
Figure 2. The FPGA dynamic probe requires Altera’s Quartus II design software
with its LAI (logic analyzer interface) and Altera programming hardware setup.
The Quartus II (ver. 6.0 or higher) LAI allows you to create and insert a debug core
that interacts with the FPGA dynamic probe application on your MSO. The FPGA
dynamic probe controls which group of internal signals to measure via the Altera
programming hardware connected to the JTAG port of the FPGA.
Leverage the work you did in your
design environment – The FPGA
dynamic probe maps internal
signal names from your FPGA
design tool to your Agilent MSO.
Eliminate unintentional mistakes
and save hours of time with this
automatic setup of signal and bus
names on your MSO.
1-256
1-256
1-256
1-256
To FPGA pins
1-256
Change signal bank
selection via JTAG
JTAG
Figure 3: Access up to 256 internal signals for each debug pin. Signal banks
all have identical width (1 to 256 signals wide) determined by the number
of device pins you devote for debug. MSO8000 series can acquire up to 16
signals using digital channels. Each pin provides sequential access to one
signal from every input bank.
2
A quick tour of the application
Design step 1: Configure the logic
analyzer interface file and core
parameters
You need to create a Altera LAI
file with MSO in Quartus II. This
file defines the interface that
builds a connection between
the internal FPGA signals and
the MSO digital channels. You
can then configure the core
parameters, which include
number of pins, number of signal
banks, the type of measurement
(state or timing), clock and the
power-up state.
Design step 2: Map the Altera LAI
core outputs to available
I/O pins
Use Pin Planner in Quartus II to
assign physical pin locations for
the LAI.
3
A quick tour of the application (continued)
Design step 3: Assign LAI bank
parameters
Assign internal signals to each
bank in the LAI after you have
specified the number of banks to
use in the core parameters. Find
the signals you want to acquire
with the Node Finder and assign
them to the banks.
With the LAI core fully
configured and instantiated
into your FPGA design, you’re
ready to compile your design to
create the device programming
file (.sof). Then, to make
measurements you’ll move
to the Agilent MSO with FPGA
dynamic probe software.
Activate FPGA dynamic probe
for Altera
The FPGA dynamic probe
application allows you to control
the LAI and set up the MSO for
the desired measurements.
4
A quick tour of the application (continued)
Measurement setup step 1: Establish
a connection between the MSO and
the LAI
The FPGA dynamic probe
application establishes a
connection between the MSO and
the FPGA via a JTAG cable. It also
determines what devices are on
the JTAG scan chain and lets you
pick the one with which you wish
to communicate.
Measurement setup step 2: Configure
the device and import signal names
If needed, you can configure the
device with the SRAM object
file (.sof) that includes the logic
analyzer interface file. The FPGA
dynamic probe application reads
a .lai file produced by Quartus II.
The names of signals you measure
will now automatically appear in
the label names on your Agilent
MSO.
Measurement setup step 3: Map
FPGA pins
Select your probe type and easily
provide the information needed
for the MSO to automatically
track names of signals routed
through the LAI file.
5
A quick tour of the application (continued)
Setup complete: Make measurements
Quickly change which signal bank
is routed to the MSO. A single
mouse click tells the LAI core
to switch to the newly specified
signal bank without any impact
to the timing of your design. To
make measurements throughout
your FPGA, change signal banks
as often as needed. With each
new selection of a signal bank,
FPGA Dynamic Probe updates
new signal names from your
design to the MSO. User-definable
signal bank names make it
straight forward to select a part
of your design to measure.
Make state measurements
with your MSO
MSOs incorporate some logic
analysis state capabilities useful
for making FPGA measurements.
Using pattern trigger, setup a
state trigger on LAI clock output
edge and desired digital pattern.
After acquiring the data, use the
post-processing “State clock”
feature to transform the timing
waveforms into state waveforms.
Valid states are shown and
invalid states are filtered. Any of
the 16 digital channels or any of
the analog channels can be set as
the state clock. Using an analog
channel state clock allows you to
retain all 16 digital channels for
bus measurement.
Correlate internal FPGA activity with
external measurements
View internal FPGA activity and
time-correlate internal FPGA
measurements with external
analog and digital events in
the surrounding system. FPGA
Dynamic Probe unlocks the power
of the MSO for system-level debug
with FPGAs.
6
Agilent N5433A specifications and characteristics
Supported oscilloscopes
Standalone oscilloscopes
MSO Digital Channels
Bus groupings
All Infiniium 8000 and 9000 Series MSOs.
16
Up to 4, each with 16 character labels
Determined by MSO, all have state triggering
Triggering capabilities
Supported Altera FPGA families
All families that the Altera LAI core supports including, Stratix IV, Stratix III, Stratix II and
Stratix, Cyclone III, Cyclone II and Cyclone, Arria II and Arria.
Supported Altera cables (required)
Supported probing mechanisms
Altera USB Blaster or ByteBlaster
Soft touch (34-channel and 17-channel), Mictor, Samtec, Flying lead, Infiniium MSOs
come standard with a 40 pin probe cable and flying leads.
Altera LAI characteristics
Number of output signals
User definable: 1 to 256 signals in 1 signal increments. MSO can measure maximum of
16 digital channels
Signal banks
Modes
User definable: 1 to 256 banks
State (synchronous) or timing (asynchronous) mode
Compatible software
Altera Quartus II 6.0 or greater
Infiniium 8000 version 5.2 or greater. Infiniium 9000 version 2.0 or greater.
Additional information available via the Internet www.agilent.com/find/8000-altera
Ordering information
Ordering options for the Agilent N5433A FPGA dynamic probe for Altera
Option 001
• Entitlement certificate for perpetual node-locked license locked to oscilloscope
(most common license type)
Option 002
• Entitlement certificate for PC locked license. PC and MSO must both connect to LAN.
(less common license type)
Related literature
Product Web site
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information, please visit our
product Web site at:
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MSO FPGA Dynamic Probe for Altera
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