GM71S17400CT-7 [HYNIX]
Fast Page DRAM, 4MX4, 70ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, TSOP2-26/24;
| 型号： | GM71S17400CT-7 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Fast Page DRAM, 4MX4, 70ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, TSOP2-26/24 动态存储器 ISM频段 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM71C(S)17400C/CL
4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
Features
•* 4,194,304 Words x 4 Bit Organization
•* Fast Page Mode Capability
•* Single Power Supply (5.0V+/-10%)
•* Fast Access Time & Cycle Time
The GM71C(S)17400C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71C(S)17400C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71C(S)17400C/CL
offers Fast Page Mode as a high speed access
mode. Multiplexed address inputs permit the
GM71C(S)17400C/CL to be packaged in a
standard 300 mil 24(26) pin SOJ, and a standard
300 mil 24(26) pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
System oriented features include single power
supply 5.0V+/-10% tolerance, direct interfacing
capability with high performance logic families
such as Schottky TTL.
(Unit: ns)
tRAC
tCAC
t
RC
tPC
50
60
70
13
15 110
18 130
90
35
40
45
GM71C(S)17400C/CL-5
GM71C(S)17400C/CL-6
GM71C(S)17400C/CL-7
* Low Power
Active : 660/605/550mW (MAX)
Standby : 11mW (CMOS level : MAX)
: 0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Battery backup operation (L-version)
* Test function : 16bit parallel test mode
Pin Configuration
24(26) SOJ
24(26) TSOP II
1
26
1
26
VCC
I/O1
I/O2
WE
VSS
VCC
I/O1
I/O2
WE
VSS
2
3
4
5
6
25
24
23
22
21
2
3
4
5
6
25
24
23
22
21
I/O4
I/O3
CAS
OE
I/O4
I/O3
CAS
OE
RAS
NC
RAS
A11
A9
A9
8
9
19
18
8
9
19
18
A10
A0
A8
A7
A6
A5
A4
VSS
A10
A0
A8
A7
A6
A5
A4
VSS
10
11
12
13
17
16
15
14
10
11
12
13
17
16
15
14
A1
A1
A2
A2
A3
A3
VCC
VCC
(Top View)
1
GM71C(S)17400C/CL
Pin Description
Pin
A0-A10
A0-A10
I/O1-I/O4
RAS
Function
Pin
Function
Read/Write Enable
Output Enable
Power (5.0V)
Address Inputs
WE
OE
Refresh Address Inputs
Data Input/Data Output
Row Address Strobe
V
CC
V
SS
Ground
NC
No Connection
CAS
Column Address Strobe
Ordering Information
Type No.
Access Time
Package
GM71C(S)17400CJ/CLJ-5
GM71C(S)17400CJ/CLJ-6
GM71C(S)17400CJ/CLJ-7
50ns
60ns
70ns
300 Mil
24(26) Pin
Plastic SOJ
GM71C(S)17400CT/CLT-5
GM71C(S)17400CT/CLT-6
GM71C(S)17400CT/CLT-7
50ns
60ns
70ns
300 Mil
24(26) Pin
Plastic TSOP II
Absolute Maximum Ratings*
Symbol
TA
Parameter
Rating
0 ~ 70
Unit
C
Ambient Temperature under Bias
Storage Temperature (Plastic)
Voltage on any Pin Relative to VSS
Voltage on VCC Relative to VSS
Short Circuit Output Current
Power Dissipation
-55 ~ 125
-1.0 ~ 7.0
-1.0 ~ 7.0
50
C
TSTG
V
VIN/VOUT
VCC
V
mA
W
IOUT
1.0
PD
*Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
VCC
Parameter
Min
4.5
Typ
Max
5.5
Unit
Supply Voltage
5.0
V
V
V
Input High Voltage
Input Low Voltage
2.4
-
-
6.0
VIH
-1.0
0.8
VIL
Note: All voltage referred to Vss.
2
GM71C(S)17400C/CL
DC Electrical Characteristics (VCC = 5.0V+/-10%, Vss = 0V, TA = 0 ~ 70C)
Symbol
Parameter
Min Max Unit Note
Output Level
Output "H" Level Voltage (IOUT = -5mA)
V
OH
2.4
0
V
CC
V
V
Output Level
Output "L" Level Voltage (IOUT = 4.2mA)
V
OL
0.4
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling : tRC = tRC min)
50ns
60ns
-
-
100
90
I
CC1
mA
mA
mA
1, 2
-
70ns
80
I
I
CC2
CC3
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)
-
2
50ns
60ns
-
-
100
90
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(tRC = tRC min)
2
-
70ns
50ns
60ns
80
90
80
I
CC4
Fast Page Mode Current
Average Power Supply Current
Fast Page Mode
-
-
mA
1, 3
(tPC = tPC min)
-
-
-
70ns
70
1
I
CC5
CC6
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= VCC - 0.2V, DOUT = High-Z)
mA
uA
150
4
I
CAS-before-RAS Refresh Current
(tRC = tRC min)
50ns
60ns
70ns
-
-
-
100
90
mA
uA
80
Battery Backup Operating Current(Standby with CBR Refresh)
(CBR refresh, tRC=62.5us, tRAS<=0.3us,
I
CC7
CC8
-
-
350
5
4
1
D
OUT=High-Z, CMOS interface)
Standby Current RAS = VIH
CAS = VIL
mA
I
D
OUT = Enable
I
L(I)
Input Leakage Current
Any Input (0V<=VIN<= 6V)
-10
-10
10
10
uA
uA
IL(O)
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<= 6V)
Note: 1. ICC depends on output load condition when the device is selected.
CC(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL
I
.
3. Address can be changed once or less while CAS = VIH
.
4. L-version.
3
GM71C(S)17400C/CL
Capacitance (VCC = 5.0V+/-10%, TA = 25C)
Symbol
CI1
Parameter
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
Min
Max
Unit
pF
Note
1
-
-
-
5
7
7
CI2
pF
1
CI/O
pF
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT
.
AC Characteristics (VCC = 5.0V+/-10%, Vss=0V, TA = 0 ~ 70C, Notes 1, 2, 18,19)
Test Conditions
Input rise and fall times : 5ns
Input timing reference levels : 0.8V, 2.4V
Output timing reference levels : 0.4V, 2.4V
Output load : 2 TTL gate + C (100pF)
(Including scope and jig)
L
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5
C/CL-6
C/CL-7
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
Random Read or Write Cycle Time
RAS Precharge Time
90
30
-
-
110
40
-
-
130
50
-
-
ns
ns
t
RC
tRP
CAS Precharge Time
7
-
10
60
-
10
70
-
ns
ns
t
CP
t
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
ODD
DZO
DZC
RAS Pulse Width
50 10,000
10,000
10,000
t
CAS Pulse Width
13 10,000 15 10,000 18 10,000 ns
t
Row Address Set up Time
Row Address Hold Time
Column Address Set-up Time
0
-
-
-
0
10
0
-
-
-
-
0
10
0
-
-
-
ns
ns
t
7
t
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
7
-
45
30
-
10
20
15
15
60
5
15
-
52
35
-
17
12
13
50
5
45 20
30 15
3
4
t
t
t
-
-
18
70
5
CAS Hold Time
-
-
t
CAS to RAS Precharge Time
OE to DIN Delay Time
-
-
-
t
t
13
0
-
15
0
-
18
0
-
5
6
6
7
t
OE Delay Time from DIN
CAS Delay Time from DIN
Transition Time (Rise and Fall)
-
-
-
0
-
0
-
0
-
t
tT
3
50
3
50
3
50
4
GM71C(S)17400C/CL
Read Cycle
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5 C/CL-6 C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
Access Time from RAS
-
-
50
13
-
-
60
15
-
-
70
18
ns
ns
8,9,20
t
RAC
9,11,
17,20
tCAC
Access Time from CAS
9,10,
17,20
tAA
Access Time from Address
-
25
-
30
-
35
ns
Access Time from OE
-
0
13
-
-
0
15
-
-
0
18
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
t
OAC
RCS
RCH
RRH
RAL
CAL
CLZ
OH
OHO
OEZ
OFF
CDD
Read Command Setup Time
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Column Address to CAS Lead Time
CAS to Output in low-Z
t
0
-
0
-
0
-
12
12
t
5
-
5
-
5
-
t
25
25
0
-
30
30
0
-
35
35
0
-
t
-
-
-
t
-
-
-
t
Output Data Hold Time
3
-
3
-
3
-
t
Output Data Hold Time from OE
Output Buffer Turn-off Time to OE
Output Buffer Turn-off Time
CAS to DIN Delay Time
3
-
3
-
3
-
t
-
13
13
-
-
15
15
-
-
15
15
-
13
13
5
t
-
-
-
t
t
13
15
18
Write Cycle
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5 C/CL-6 C/CL-7
Symbol
Parameter
Unit
Note
Min Max Min Max Min Max
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
14
0
7
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
t
WCS
10
10
15
15
0
15
10
18
18
0
tWCH
7
t
t
WP
RWL
CWL
13
13
0
t
15
15
tDS
Data-in Hold Time
7
10
15
t
D
H
5
GM71C(S)17400C/CL
Read- Modify-Write Cycle
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5 C/CL-6 C/CL-7
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
Read-Modify-Write Cycle Time
RAS to WE Delay Time
131
73
-
-
-
-
-
155
85
-
-
-
-
-
181
98
-
-
-
-
-
ns
t
RWC
RWD
CWD
AWD
OEH
ns
ns
ns
ns
14
14
14
t
CAS to WE Delay Time
36
40
46
t
Column Address to WE Delay Time
OE Hold Time from WE
48
55
63
t
13
15
18
t
Refresh Cycle
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5 C/CL-6 C/CL-7
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
CAS Setup Time
(CAS-before-RAS Refresh Cycle)
t
CSR
5
7
0
-
-
-
5
10
0
-
-
-
5
10
0
-
-
-
ns
ns
ns
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
tCHR
WE Setup Time
(CAS-before-RAS Refresh Cycle)
tWRP
WE Hold Time
(CAS-before-RAS Refresh Cycle)
t
WRH
10
5
-
-
10
5
-
-
10
5
-
-
ns
ns
tRPC
RAS Precharge to CAS Hold Time
Fast Page Mode Cycle
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5 C/CL-6 C/CL-7
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
Fast Page Mode Cycle Time
35
-
-
40
-
-
45
-
-
ns
t
PC
RASP
ACP
RHCP
100,000
100,000
100,000
16
Fast Page Mode RAS Pulse Width
Access Time from CAS Precharge
RAS Hold Time from CAS Precharge
ns
ns
ns
t
9,17,20
-
30
-
-
35
-
-
40
-
t
30
35
40
t
6
GM71C(S)17400C/CL
Fast Page Mode Read-Modify-Write Cycle
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5
C/CL-6
C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
t
PRWC
Fast Page Mode Read-Modify-Write
Cycle Time
76
53
-
-
85
60
-
-
96
68
-
-
ns
ns
tCPW
WE Delay Time from CAS Precharge
14
Test Mode Cycle*19
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5 C/CL-6 C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
Test Mode WE Setup Time
Test Mode WE Hold Time
0
-
-
0
-
-
0
-
-
ns
ns
t
WTS
10
10
10
tWTH
Refresh
GM71C(S)17400 GM71C(S)17400 GM71C(S)17400
C/CL-5 C/CL-6 C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
2048
ms
ms
Refresh Period
t
REF
-
-
32
-
-
32
-
-
32
cycles
2048
Refresh Period (L - version)
tREF
128
128
128
cycles
7
GM71C(S)17400C/CL
Notes:
1. AC Measurements assume tT =5ns.
2. An initial pause of 200us is required after power up followed by a minimum of eight
initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS
refresh cycles are required.
3. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tODD or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL(max).
7.
8. Assume that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 2 TTL loads and 100pF. (VOH = 2.4V, VOL = 0.8V)
Assume that tRCD >=tRCD(max) and tRCD +
t
CAC(max) >= tRAD + AA(max).
t
10.
11. Assume that tRAD >=tRAD(max) and tRCD +
tCAC(max) <= tRAD + tAA(max).
12.
13.
Either tRCH or tRRH must be satisfied for a read cycles.
tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition
and are not referenced to output voltage levels.
14.
tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS>=tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
t
RWD>=tRWD(min), tCWD>=tCWD(min), and tAWD>=tAWD(min), or tCWD>=tCWD(min), tAWD>=
tAWD(min) and tCPW>=tCPW(min), the cycle is a read-modify-write and the data output will contain
data read from the selected cell; if neither of the above sets of conditions is satisfied, the
condition of the data out (at access time) is indeterminate.
15. These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
t
RASP defines RAS pulse width in Fast page mode cycles.
16.
17.
Access time is determined by the longest among tAA or tCAC or tACP.
8
GM71C(S)17400C/CL
18.
19.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high
impedance); if tOEH < tCWL, invalid data will be out at each I/O.
The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the
4M x 4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-before-
RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O
(I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data
output pin is a high state during test mode read cycle, then the device has passed. If they are not
equal, data output pin is a low state, then the device has failed. Refresh during test mode
operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test
mode and enter a normal operation mode, perform either a regular CAS-before-RAS refresh
cycle or RAS-only refresh cycle.
In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed by 2ns to 5ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
20.
9
GM71C(S)17400C/CL
Unit: Inches (mm)
Package Dimension
24(26) SOJ
0.025(0.64)
MIN
0.085(2.16)
MIN
0.661(16.80) MIN
0.669(17.00) MAX
0.128(3.25) MIN
0.147(3.75) MAX
0.026(0.66) MIN
0.032(0.81) MAX
0.050(1.27)
TYP
0.015(0.38) MIN
0.020(0.50) MAX
24(26) TSOP (TYPE II)
0 ~ 5o
0.016(0.40) MIN
0.024(0.60) MAX
0.670(17.04) MIN
0.678(17.24) MAX
0.004(0.12) MIN
0.008(0.21) MAX
0.037(0.95) MIN
0.041(1.05) MAX
0.047(1.20)
MAX
0.012(0.30) MIN
0.020(0.50) MAX
0.050(1.27)
0.003(0.08) MIN
0.007(0.18) MAX
TYP
23
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