GM72V66841GLT-S [HYNIX]
Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54;
| 型号： | GM72V66841GLT-S |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Synchronous DRAM, 8MX8, 6ns, CMOS, PDSO54 时钟 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：49K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM72V66841G
4 Banks x 2M x 8Bit Synchronous DRAM
DESCRIPTION
The Hyundai GM72V66841G is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. GM72V66841G is organized as 4banks of 2,097,152x8.
GM72V66841G is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Single 3.3±0.3V power supply
•
•
•
Auto refresh and self refresh
All device pins are compatible with LVTTL interface
4096 refresh cycles / 64ms
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
All inputs and outputs referenced to positive edge of sys-
tem clock
•
•
Data mask function by DQM
Internal four banks operation
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
GM72V66841GT-5/55/67
GM72V66841GT-K
200/183/166/143MHz
133MHz
GM72V66841GT-H
GM72V66841GT-P
133MHz
Normal
100MHz
GM72V66841GT-S
100MHz
4Banks x 2Mbits x8
LVTTL
400mil 54pin TSOP II
GM72V66841GLT-5/55/6/7
GM72V66841GLT-K
GM72V66841GLT-H
GM72V66841GLT-P
GM72V66841GLT-S
200/183/166/143MHz
133MHz
133MHz
Low power
100MHz
100MHz
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.2/Oct.00
GM72V66841G
PIN CONFIGURATION
DD
SS
V
V
1
2
3
4
5
6
7
8
9
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC 10
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
DQ3 11
VSSQ
NC 13
12
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
DD
V
SS
V
14
NC 15
/WE 16
/CAS 17
/RAS 18
/CS 19
BA0 20
BA1 21
A10/AP 22
A0 23
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A1 24
A2 25
A3 26
A4
SS
V
DD
V
27
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CLK
Clock
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CKE
CS
Clock Enable
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
BA0, BA1
A0 ~ A11
Bank Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
RAS, CAS, WE
DQM
Data Input/Output Mask
Data Input/Output
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
DQ0 ~ DQ7
VDD/VSS
VDDQ/VSSQ
NC
Power Supply/Ground
Data Output Power/Ground
No Connection
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 0.2/Oct.00
2
GM72V66841G
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 8 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
2Mx8 Bank3
CLK
Row
Pre
Decoders
Row active
2Mx8 Bank 2
2Mx8 Bank 1
CKE
CS
2Mx8 Bank 0
DQ0
DQ1
RAS
CAS
WE
Memory
Cell
Array
refresh
Column
Active
Column
Pre
Decoders
DQM
DQ6
DQ7
Y decoders
Column Add
Counter
Bank Select
A0
A1
Address
Registers
Burst
Counter
A11
BA0
BA1
CAS Latency
Pipe Line Control
Mode Registers
Data Out Control
Rev. 0.2/Oct.00
3
GM72V66841G
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
°C
Storage Temperature
TSTG
°C
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
V
VDD, VDDQ
IOS
V
mA
PD
1
W
Soldering Temperature × Time
TSOLDER
260 × 10
°C × Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Input High Voltage
Input Low Voltage
VDD, VDDQ
VIH
3.0
2.0
3.3
3.0
0
3.6
VDDQ + 2.0
0.8
V
V
V
1
1,2
1,3
VIL
VSSQ - 2.0
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 5.6V AC pulse width with £3ns of duration
3.VIL (min) is acceptable -2.0V AC pulse width with £3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
Note
AC Input High / Low Level Voltage
VIH / VIL
Vtrip
2.4/0.4
1.4
1
V
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
tR / tF
Voutref
CL
ns
V
Output Timing Measurement Reference Level
Output Load Capacitance for Access Time Measurement
1.4
50
pF
1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Rev. 0.2/Oct.00
4
GM72V66841G
CAPACITANCE (TA=25°C, f=1MHz)
Parameter
Pin
Symbol
Min
Max
Unit
Input capacitance
CLK
CI1
CI2
2
4
5
pF
pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM
2.5
Data input / output capacitance
DQ0 ~ DQ7
CI/O
2
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 W
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
-1
-1
2.4
-
1
1
uA
uA
V
1
2
ILO
VOH
VOL
-
IOH = -4mA
IOL = +4mA
0.4
V
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 0.2/Oct.00
5
GM72V66841G
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Speed
Parameter
Symbol
Test Condition
Unit Note
-6
-7
-K
-H
-P
-S
Burst length=1, One bank active
tRC ³ tRC(min), IOL=0mA
Operating Current
IDD1
90
85
85
85
80
80
mA
1
2
2
mA
mA
IDD2P
CKE £ VIL(max), tCK = min
CKE £ VIL(max), tCK = ¥
Precharge Standby Current
in Power Down Mode
IDD2PS
CKE ³ VIH(min), CS ³ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ³ VDD-0.2V or £ 0.2V
15
12
mA
mA
IDD2N
Precharge Standby Current
in Non Power Down Mode
CKE ³ VIH(min), tCK = ¥
Input signals are stable.
IDD2NS
IDD3P
CKE £ VIL(max), tCK = min
CKE £ VIL(max), tCK = ¥
6
5
mA
mA
Active Standby Current
in Power Down Mode
IDD3PS
CKE ³ VIH(min), CS ³ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ³ VDD-0.2V or £ 0.2V
IDD3N
30
20
mA
mA
Active Standby Current
in Non Power Down Mode
CKE ³ VIH(min), tCK = ¥
Input signals are stable.
IDD3NS
CL=3
150
NA
150
NA
150
150
120
120
mA
mA
mA
mA
uA
1
tCK ³ tCK(min), IOL=0mA
All banks active
Burst Mode Operating Current
Auto Refresh Current
IDD4
IDD5
IDD6
CL=2
120
tRRC ³ tRRC(min), All banks active
CKE £ 0.2V
160
1
2
3
4
Self Refresh Current
400
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.GM72V66841GT-7/K/H/P/S
4.GM72V66841GLT-7/K/H/P/S
Rev. 0.2/Oct.00
6
GM72V66841G
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-6
-7
-K
-H
-P
-S
Parameter
Symbol
Unit
Note
Min
6
Max
Min
7
Max
Min
7.5
7.5
2.5
2.5
-
Max
Min
7.5
10
Max
Min
10
10
3
Max
Min
10
12
3
Max
CAS Latency = 3
CAS Latency = 2
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System clock
cycle time
1000
1000
1000
1000
1000
1000
10
2.5
2.5
-
10
2.5
2.5
-
Clock high pulse width
Clock low pulse width
-
-
-
-
-
2.5
2.5
-
-
-
-
-
-
1
1
-
3
3
CAS Latency = 3
CAS Latency = 2
5.4
6
-
5.4
6
-
5.4
5.4
6
-
6
6
-
-
6
8
-
Access time from
clock
2
-
-
-
5.4
-
-
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
-
-
-
-
-
-
-
-
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
3
2
1
2
1
2
1
2
1
1
3
tDS
-
-
-
-
2
-
1
1
1
1
1
1
1
1
tDH
-
-
-
-
1
-
tAS
-
-
-
-
2
-
tAH
-
-
-
-
1
-
tCKS
tCKH
tCS
-
-
-
-
2
-
CKE hold time
-
-
-
-
1
-
Command setup time
Command hold time
-
-
-
-
2
-
tCH
-
-
-
-
1
-
CLK to data output in low Z-time
tOLZ
tOHZ3
tOHZ2
-
-
-
-
2
-
CAS Latency = 3
CAS Latency = 2
CLK to data output
in high Z-time
5.4
5.4
5.4
5.4
6
6
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 0.2/Oct.00
7
GM72V66841G
AC CHARACTERISTICS II
-6
-7
-K
-H
-P
-S
Parameter
Symbol
Unit
Note
Min
60
60
18
42
18
12
1
Max
Min
62
62
20
42
20
14
1
Max
Min
65
65
15
45
15
15
1
Max
Min
65
65
20
45
20
15
1
Max
Min
70
70
20
50
20
20
1
Max
Min
70
70
20
50
20
20
1
Max
Operation
Auto Refresh
tRC
-
-
-
-
-
-
ns
ns
RAS Cycle Time
tRRC
tRCD
tRAS
tRP
-
-
-
-
-
-
RAS to CAS Delay
RAS Active Time
-
-
-
-
-
-
ns
100K
120K
120K
120K
120K
120K
ns
RAS Precharge Time
-
-
-
-
-
-
-
-
-
-
-
-
ns
RAS to RAS Bank Active Delay
CAS to CAS Delay
tRRD
tCCD
tWTL
tDPL
ns
-
-
-
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ms
Write Command to Data-In Delay
Data-In to Precharge Command
Data-In to Active Command
DQM to Data-Out Hi-Z
0
-
0
-
0
-
0
-
0
-
0
-
2
-
1
-
1
-
1
-
1
-
1
-
5
-
4
-
4
-
4
-
3
-
3
-
tDAL
2
-
2
-
2
-
2
-
2
-
2
-
tDQZ
tDQM
tMRD
tPROZ3
tPROZ2
tPDE
tSRE
tREF
DQM to Data-In Mask
0
-
0
-
0
-
0
-
0
-
0
-
MRS to New Command
2
-
1
-
1
-
1
-
1
-
1
-
CAS Latency = 3
Precharge to Data
3
-
3
-
3
-
3
-
3
-
3
-
Output Hi-Z
CAS Latency = 2
2
-
2
-
2
-
2
-
2
-
2
-
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
64
-
64
-
64
-
64
-
64
-
64
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 0.2/Oct.00
8
GM72V66841G
DEVICE OPERATING OPTION TABLE
GM57V64820(L)T-6
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
166MHz(6ns)
143MHz(7ns)
133MHz(7.5ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
3CLKs
7CLKs
6CLKs
6CLKs
10CLKs
9CLKs
9CLKs
3CLKs
3CLKs
3CLKs
5.4ns
5.4ns
5.4ns
2.7ns
2.7ns
2.7ns
GM72V66841G(L)T-7
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
143MHz(7ns)
133MHz(7.5ns)
100MHz(10ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
5.4ns
6ns
2.7ns
2.7ns
3ns
GM72V66841G(L)T-K
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
2CLKs
3CLKs
2CLKs
2CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
8CLKs
9CLKs
7CLKs
2CLKs
3CLKs
2CLKs
5.4ns
6ns
2.7ns
3ns
6ns
3ns
GM72V66841G(L)T-H
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
6ns
2.7ns
3ns
6ns
3ns
GM72V66841G(L)T-P
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
GM72V66841G(L)T-S
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
3CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
Rev. 0.2/Oct.00
9
GM72V66841G
COMMAND TRUTH TABLE
A10/
AP
ADDR
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
Note
Mode Register Set
H
H
H
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
OP code
No Operation
X
X
X
X
X
X
X
Bank Active
L
RA
V
V
Read
L
H
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
H
H
L
X
V
X
X
L
L
H
H
L
L
H
H
H
H
H
X
L
X
V
X
X
X
X
X
DQM
Auto Refresh
Entry
H
L
L
L
L
L
H
H
X
H
X
H
X
H
X
V
L
Self Refresh1
Exit
H
L
X
H
X
H
X
H
X
V
X
H
X
H
X
H
X
V
X
X
X
L
H
L
H
L
X
X
X
H
L
Entry
Precharge
power down
H
L
Exit
H
H
L
Entry
Clock
Suspend
H
L
L
X
X
Exit
H
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don¢t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 0.2/Oct.00
10
GM72V66841G
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0.150(0.0059)
0.050(0.0020)
1.194(0.0470)
0.991(0.0390)
5deg
0deg
0.210(0.0083)
0.120(0.0047)
0.597(0.0235)
0.406(0.0160)
0.400(0.016)
0.80(0.0315)BSC
0.300(0.012)
Rev. 0.2/Oct.00
11
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