GMS36112-XXXD [HYNIX]
Microcontroller, 4-Bit, MROM, 4MHz, CMOS, PDSO20, 0.300 INCH, SOP-20;
| 型号： | GMS36112-XXXD |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Microcontroller, 4-Bit, MROM, 4MHz, CMOS, PDSO20, 0.300 INCH, SOP-20 微控制器 光电二极管 |
| 文件： | 总109页 (文件大小：813K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
JUNE.2001
Rev. 1.1
4-BIT SINGLE CHIP MICROCOMPUTERS
GMS36/37XXX(T) SERIES
USER`S MANUAL
• GMS36/37004(T)
• GMS36/37112(T)
• GMS36/37140(T)
Revision 1.1
Published by MCU Application Team in HYNIX Semiconductor Inc.
All Right Reserved.
Editor's E-Mail :
rhja@hynix.com
Additional information of this manual may be served by HYNIX Semiconductor Inc.Offices in
Korea or Distributors and Representative listed at address directory.
HYNIX Semiconductor Inc.reserves the right to make changes to any Information here at any
time without notice.
The information, diagrams, and other data in this manual are correct and reliable; however, HYNIX
Semiconductor Inc.is in no way responsible for any violations of patents or other rights of the third
party generated by the use of this manual.
Table of Contents
Table of Contents
Chapter 1 GMS36XXX
Description
Features
………...………………..……………………1-1
……………………………………………….1-1
……………………………………………….1-2
……………………………………………….1-3
……………………………………………….1-4
……………………………………………….1-5
……………………………………………….1-7
……………………………………………….1-7
……………………………………………….1-8
Block diagram
Pin assignment
Pin description
Pin circuit
Port operation
Optional features
Electrical characteristics
Chapter 2 GMS37XXX
Description
Features
………...………………..……………………2-1
……………………………………………….2-1
……………………………………………….2-2
……………………………………………….2-3
……………………………………………….2-4
……………………………………………….2-5
……………………………………………….2-7
……………………………………………….2-7
……………………………………………….2-8
Block diagram
Pin assignment
Pin description
Pin circuit
Port operation
Optional features
Electrical characteristics
Chapter 3 PACKAGE DIMENSIONS
Chapter 4 FUNCTIONAL DESCRIPTION
Program memory (ROM)
ROM address register
Data memory (RAM)
X-register (X)
Y-register (Y)
Accumulator (Acc)
……………………………………………….4-1
……………………………………………….4-2
……………………………………………….4-3
……………………………………………….4-3
……………………………………………….4-4
……………………………………………….4-4
Arithmetic and Logic Unit (ALU) ……………………………………………….4-4
State Counter (SC)
Clock generator
Pulse generator
Reset operation
Watch Dog Timer (WDT)
Stop operation
……………………………………………….4-5
……………………………………………….4-6
……………………………………………….4-7
……………………………………………….4-8
………………………………………………4-10
………………………………………………4-11
Table of Contents
Chapter 5 INSTRUCTION
Instruction format
Instruction table
Details of instruction system
………………...……………………………5-1
…………………...…………………………5-2
……………………...………………………5-4
Chapter 6 APPLICATION
Guideline for S/W
GMS36112 Circuit diagram
GMS37112 Circuit diagram
………………………...……………………6-1
…………………………...…………………6-2
………………………………...……………6-3
Truth Table for example program …………………………………...…………6-4
Output waveform of uPD6121G ……………………………………...………6-5
Example program-uPD6121G
………………………………………...……6-6
Reference to GMS36XXXT B/D …………………………...………………..6-12
Reference to GMS37XXXT B/D ……………………………...……………..6-13
Chapter 7 GMS36XXXT
Description
………...………………..……………………7-1
……………………………………………….7-1
……………………………………………….7-2
……………………………………………….7-3
……………………………………………….7-4
Features
Pin description
Stop operation
Electrical characteristics
Chapter 8 GMS37XXXT
Description
Features
Pin description
Stop operation
Electrical characteristics
………...………………..……………………8-1
……………………………………………….8-1
……………………………………………….8-2
……………………………………………….8-3
……………………………………………….8-4
Chapter 9 EPROM
Mode define
Port define for GMS36XXXT
Port define for GMS37XXXT
……………………………………………….9-1
……………………………………………….9-1
……………………………………………….9-2
AC/DC timing requirements for program / read mode
Program / verify timing diagrams in kHz version
Program / verify timing diagrams in MHz version
Caution when programming
...…………….9-3
……………....9-4
……………….9-8
…..………….9-14
GMS36XXX
1
2
3
4
5
6
7
8
9
GMS37XXX
PACKAGE DIMENSIONS
FUNCTIONAL DESCRIPTION
INSTRUCTION
APPLICATION
GMS36XXXT
GMS37XXXT
EPROM
Chapter 1. GMS36XXX
1. GMS36XXX
Description
The GMS36XXX series are remote control transmitter which uses CMOS technology.
This enables transmission code outputs of different configurations, multiple custom code
output, and double push key output for easy fabrication.
The GMS36XXX series are suitable for remote control of TV, VCR, FANS, Air-
conditioners, Audio Equipment, Toys, Games etc.
Features
Program memory : 1,024 bytes for GMS36004/112/140
•
•
•
•
•
Data memory : 32 4 bits
43 types of instruction set
3 levels of subroutine nesting
Operating frequency : 300kHz ~ 1MHz at kHz version
2.4MHz ~ 4MHz at MHz version
•
Instruction cycle : fOSC/6 at kHz version
fOSC/48 at MHz version
•
•
•
•
•
•
•
•
•
CMOS process (Single 3.0V power supply)
Stop mode (Through internal instruction)
Released stop mode by key input (Masked option)
Built in Power-on Reset circuit
Built in Low Voltage Detection circuit
Built in capacitor for ceramic oscillation circuit at kHZ version
Built in a watch dog timer (WDT)
Built in transistor for I.R LED Drive : IOL =210mA at VDD =3V and VO =0.3V
Low operating voltage: 2.0 ~ 3.6V (at 300kHz ~ 4MHz)
Table 1-1 GMS36XXX series members
Series
Program memory
Data memory
I/O ports
GMS36004
GMS36112
GMS36140
1,024
1,024
1,024
32
4
32
4
32
4
-
4
4
4
4
Input ports
4
Output ports
Package
6 (D0~D5)
6 (D0~D5)
10 (D0~D9)
16DIP/SOP
20DIP/SOP/SSOP
24Skinny DIP/SOP
1-1
Chapter 1. GMS36XXX
Block Diagram
VDD GND
24
1
Watchdog
timer
Power-on
Reset
ROM
10
3-level
Stack
Program counter
64word 16page
8bit
Low-Voltage
Detection
8
10
4
4
4
8
4
Instruction
Decoder
ALU
MUX
4
4
RAM
2
Control Signal
RAM
Word
Selector
16
16word x
Y-Reg
ST
X-Reg
2page x 4bit
ACC
4
10
4
D-Latch
OSC
R-Latch
Pulse
Generator
10
I.R. LED
Drive Tr.
4
4
4
22
PGND
2
3
6
7
8
9
10 11 12 13
R0 ~ R3
14 15 16 17 18 19 20 21
D0 ~ D9
5
4
23
REMOUT
OSC1 OSC2
K0 ~ K3
Fig 1-1 Block Diagram (In case of GMS36140)
1-2
Chapter 1. GMS36XXX
Pin Assignment
1
2
20
19
18
17
16
15
14
13
12
11
GND
OSC1
OSC2
VDD
1
2
3
4
5
6
7
8
16
VDD
GND
OSC1
OSC2
REMOUT
PGND
15 REMOUT
3
PGND
D5
14
13
12
4
K0
K1
K2
K3
R0
R1
R2
D5
D4
D3
D2
K0
K1
K2
K3
D0
5
D4
6
11 D3
7
D2
D1
10
9
8
D1
D0
R3
9
10
Fig 1-2 GMS36004 Pin Assignment
(16DIP/SOP)
Fig 1-3 GMS36112 Pin Assignment
(20DIP/SOP/SSOP)
1
2
24
23
GND
OSC1
OSC2
D9
VDD
REMOUT
3
22 PGND
21 D7
4
D8
5
20
19
18
17
16
15
D6
D5
D4
D3
D2
D1
6
K0
K1
K2
K3
7
8
9
10
11
12
R0
R1
14 D0
R3
R2
13
Fig 1-4 GMS36140 Pin Assignment
(24Skinny-DIP/SOP)
1-3
Chapter 1. GMS36XXX
Pin Description
Pin
I/O
Function
VDD
-
Connected to 2.0~ 3.6V power supply
GND
-
Connected to 0V power supply.
4-bit input port with built in pull-up resistor.
Input
K0 ~ K3
STOP mode is released by "L" input of each pin.(masked option)
Each can be set and reset independently.
D0 ~ D9
R0 ~ R3
Output
I/O
The output is the structure of N-channel-open-drain.
4-bit I/O port. (Input mode is set only when each of them output "H".)
In outputting, each can be set and reset independently(or at once.)
The output is in the form of C-MOS.
Pull-up resistor and STOP release mode can be respectively selected
as masked option for each pin. (It is released by ‘’L’’ input at STOP.)
Oscillator input. Input to the oscillator circuit and connection point for
ceramic resonator.
OSC1
Input
Internal capacitors available at kHz version.
A feedback resistor is internally connected between this pin and
OSC2.
Connect a resonator between this pin and OSC1.
OSC2
Output
Output
High current output port driving I.R. LED.
REMOUT
The output is in the form of N-channel-open-drain.
High current Tr. ground pin. (connected to GND)
PGND
-
High current output Tr. is connected between this pin and
REMOUT.
1-4
Chapter 1. GMS36XXX
Pin Circuit
Note
Pin
I/O
I/O circuit
pull-up
- CMOS output.
- "H" output at reset.
R0 ~ R3
I/O
(Option)
- Built in MOS Tr for
pull-up, about 140
.
pull-up
K0 ~ K3
I
- Built in MOS Tr for
pull-up, about 140
.
D0 ~ D9
- Open drain output.
- "L" output at reset.
O
REMOUT
O
REMOUT
RESET
- Open drain output.
- Output Tr. disable at
reset.
DATA
PGND
-
PGND
1-5
Chapter 1. GMS36XXX
Pin
I/O circuit
Note
I/O
STOP
- Built in feedback-
resistor about 1
Rd
OSC2
O
OSC1
- Built in damping-resistor
OSC2
[No resistor in MHz operation]
(Option)
- Built in resonance capacitor
at kHz version
- C1=C2 = 100pF 15%
[C1,C2 are not available
for MHz version]
OSC1
I
Rf
C2
C1
1-6
Chapter 1. GMS36XXX
Port Operation
Value of X-reg Value of Y-reg
Operation
SO : D(Y)
RO : D(Y)
1 (High-Z)
0
0 ~ 7
0 or 1
0 or 1
REMOUT port repeats ‘’L’’ and ‘’H’’ in pulse
frequency. (when PMR = 5, it is fixed at ‘’L’’ )
SO : REMOUT (PMR)
RO : REMOUT (PMR)
8
9
0
1 (High-Z)
SO : D0 ~ D9
RO : D0 ~ D9
1 (High-Z)
0
0 or 1
SO : R(Y-Ah)
RO : R(Y-Ah)
1
0
0 or 1
0 or 1
0 or 1
A ~ D
SO : R0 ~ R3
RO : R0 ~ R3
1
0
E
F
SO : D0 ~ D9
RO : D0 ~ D9
1 (High-Z), R0 ~ R3
0,
1
0
R0 ~ R3
SO : D(8)
RO : D(8)
1 (High-Z)
0
2 or 3
2 or 3
0
1
SO : D(9)
RO : D(9)
1 (High-Z)
0
Optional Features
The GMS36XXX series offer the following optional features.
Theses options are masked.
•
•
•
I/O terminals having pull-up resistor : R0 ~ R3
Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3.
Output form at STOP mode
L’’ or keep before stop mode.
D0 ~ D9 : ‘’
Theses options are offered default.
•
•
Ceramic oscillation circuit contained (or not contained)
[ This option is not available for MHz Ceramic oscillator. ]
Instruction cycle selection :
T = 48 / fOSC or 6 / fOSC
1-7
Chapter 1. GMS36XXX
Electrical Characteristics
Absolute maximum ratings (Ta = 25
Parameter
)
Symbol
Max. rating
Unit
Supply Voltage
VDD
PD
-0.3 ~ 5.0
700 *
V
Power dissipation
Storage temperature range
Input voltage
mW
Tstg
VIN
-55 ~ 125
-0.3 ~ VDD+0.3
-0.3 ~ VDD+0.3
V
V
Output voltage
VOUT
* Thermal derating above 25
: 6mW per degree
rise in temperature.
Recommended operating condition
Parameter
Supply Voltage
Symbol
Condition
Rating
Unit
VDD
300KHz ~ 4MHz
-
2.0 ~ 3.6
V
-20 ~ +70
Topr
Operating temperature
1-8
Chapter 1. GMS36XXX
Electrical characteristics (Ta=25 , VDD= 3V)
Limits
Condition
Parameter
Symbol
Unit
Min. Typ. Max.
VI = VDD , R having no Pull-up
Input H current
IIH
IIL
-
-1
70
70
0.3
2.1
-
-
-
1
-
uA
uA
Input L current
VI = GND, R having no Pull-up
VI = GND
K Pull-up Resistance
R Pull-up Resistance
Feedback Resistance
RPU1
RPU2
RFD
VIH1
VIL1
140
140
1.0
-
300
300
3.0
-
VI = GND, Output off
VOSC1= GND, VOSC2= GND
K, R Input H voltage
K, R Input L voltage
D, R Output L voltage
-
V
V
-
-
0.9
0.4
0.9
-
*1
IOL2 = 3mA
VOL2
-
0.15
0.4
2.5
210
-
V
I
OL3 = 40uA (kHz) , 150uA(MHz)
VOL3
VOH3
-
V
OSC2 Output L voltage
OSC2 Output H voltage
REMOUT Output L current
IOH3= -40uA (kHz), -150uA(MHz)
VOL1= 0.3V
2.1
170
-
V
*2
IOL1
250
1
mA
uA
uA
uA
mA
mA
V
OUT= VDD, Output off
IOLK1
IOLK2
ISTP
REMOUT leakage current
D, R Output leakage current
Current on STOP mode
VOUT= VDD, Output off
At STOP mode
fOSC= 455kHz
-
-
1
-
-
1
*3
Operating Supply current 1
Operating Supply current 2
IDD1
-
0.2
0.5
-
1.0
1.5
*3
fOSC= 4MHz
IDD2
-
System
fOSC/6
fOSC
fOSC
300
2.4
1000 kHz
MHz
kHz Version
colck
frequency
fOSC /48
-
4
MHz Version.
*1 Refer to
*2 Refer to
*3 IDD1, IDD2, is measured at RESET mode.
Fig.1-5 IOL2 vs. VOL2 Graph
Fig.1-6 OL1 vs. VOL1 Graph
I
1-9
Chapter 1. GMS36XXX
Fig 1-5. IOL2 vs. VOL2 Graph. ( D, R Port )
Fig 1-6. IOL1 vs. VOL1 Graph. ( REMOUT port)
1-10
GMS36XXX
1
2
3
4
5
6
7
8
9
GMS37XXX
PACKAGE DIMENSIONS
FUNCTIONAL DESCRIPTION
INSTRUCTION
APPLICATION
GMS36XXXT
GMS37XXXT
EPROM
Chapter 2. GMS37XXX
2. GMS37XXX
Description
The GMS37XXX series are remote control transmitter which uses CMOS technology.
This enables transmission code outputs of different configurations, multiple custom code
output, and double push key output for easy fabrication.
The GMS37XXX series are suitable for remote control of TV, VCR, FANS, Air-
conditioners, Audio Equipment, Toys, Games etc.
It is possible to structure the 8 x 7 key matrix for GMS37112, and the 4 x 7 key matrix
for GMS37004.
Features
Program memory : 1,024 bytes for GMS37004/112/140
•
•
•
•
•
Data memory : 32 4 bits
43 types of instruction set
3 levels of subroutine nesting
Operating frequency : 300kHz ~ 1MHz at kHz version
2.4MHz ~ 4MHz at MHz version
•
Instruction cycle : fOSC/6 at kHz version
fOSC/48 at MHz version
•
•
•
•
•
•
•
•
CMOS process (Single 3.0V power supply)
Stop mode (Through internal instruction)
Released stop mode by key input (Masked option)
Built in Power-on Reset circuit
Built in Low Voltage Detection circuit
Built in capacitor for ceramic oscillation circuit at kHZ version
Built in a watch dog timer (WDT)
Low operating voltage: 2.0 ~ 3.6V (at 300kHz ~ 4MHz)
Table 2-1 GMS37XXX series members
Series
Program memory
Data memory
I/O ports
GMS37004
GMS37112
GMS37140
1,024
1,024
1,024
32
4
32
4
32
4
-
4
4
4
4
Input ports
4
Output ports
Package
7 (D0~D6)
7 (D0~D6)
10 (D0~D9)
16DIP/SOP
20DIP/SOP/SSOP
24Skinny DIP/SOP
2-1
Chapter 2. GMS37XXX
Block Diagram
VDD GND
24
1
Watchdog
timer
Power-on
Reset
ROM
10
3-level
Stack
Program counter
64word 16page
8bit
Low-Voltage
Detection
8
10
4
4
4
8
4
Instruction
Decoder
ALU
MUX
4
4
RAM
2
Control Signal
RAM
Word
Selector
16
16word x
Y-Reg
ST
X-Reg
2page x 4bit
ACC
4
10
4
D-Latch
OSC
R-Latch
Pulse
Generator
10
4
4
4
22
NC
2
3
6
7
8
9
10 11 12 13
R0 ~ R3
14 15 16 17 18 19 20 21
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
5
4
23
REMOUT
OSC1 OSC2
K0 ~ K3
* NC : No connection
Fig 2-1 Block Diagram (In case of GMS37140)
2-2
Chapter 2. GMS37XXX
Pin Assignment
1
2
20
19
18
17
16
15
14
13
12
11
GND
OSC1
OSC2
VDD
GND
OSC1
OSC2
1
2
3
4
5
6
7
8
16
VDD
REMOUT
D6
15 REMOUT
3
D6
D5
D4
14
13
12
4
K0
K1
D5
D4
D3
D2
K0
K1
5
6
K2
K2
11 D3
7
K3/Vpp
R0
K3/Vpp
D0
D2
D1
10
9
8
D1
D0
R3
9
R1
R2
10
Fig 2-2 GMS37004 Pin Assignment
(16DIP/SOP)
Fig 2-3 GMS37112 Pin Assignment
(20DIP/SOP/SSOP)
1
2
24
23
GND
OSC1
OSC2
D9
VDD
REMOUT
3
22 NC
21 D7
4
D8
5
20
19
18
17
16
15
D6
D5
D4
D3
D2
D1
6
K0
K1
7
8
K2
9
K3/Vpp
10
11
12
R0
R1
14 D0
R3
R2
13
Fig 2-4 GMS37140 Pin Assignment
(24Skinny-DIP/SOP)
2-3
Chapter 2. GMS37XXX
Pin Description
Pin
VDD
GND
I/O
Function
Connected to 2.0~ 3.6V power supply
-
-
Connected to 0V power supply.
4-bit input port with built in pull-up resistor.
Input
K0 ~ K3
STOP mode is released by "L" input of each pin. ( masked option)
Each can be set and reset independently.
D0 ~ D9
R0 ~ R3
Output
I/O
The output is the structure of N-channel-open-drain.
4-bit I/O port. (Input mode is set only when each of them output "H".)
In outputting, each can be set and reset independently(or at once.)
The output is in the form of C-MOS.
Pull-up resistor and STOP release mode can be respectively selected
as masked option for each pin. (It is released by "L" input at STOP)
Oscillator input. Input to the oscillator circuit and connection point for
ceramic resonator.
OSC1
Input
Internal capacitors available at kHz version.
A feedback resistor is internally connected between this pin and OSC2.
OSC2
Output
Output
Connect a resonator between this pin and OSC1.
High current output port. The output is in the form of CMOS.
The state of large current on is "H".
REMOUT
2-4
Chapter 2. GMS37XXX
Pin Circuit
Pin
I/O circuit
Note
I/O
pull-up
- CMOS output.
- "H" output at reset.
R0 ~ R3
I/O
(Option)
- Built in MOS Tr for
pull-up, about 140
.
pull-up
K0 ~ K3
I
- Built in MOS Tr for
pull-up, about 140
.
- Open drain output.
- "L" output at reset.
O
D0 ~ D9
- CMOS output.
- "L" output at reset.
- High current output
source.
REMOUT
O
2-5
Chapter 2. GMS37XXX
Pin
I/O circuit
Note
I/O
STOP
- Built in feedback-
resistor about 1
Rd
OSC2
O
OSC1
- Built in damping-resistor
OSC2
[No resistor in MHz operation]
(Option)
- Built in resonance capacitor
at kHz version
- C1=C2 = 100pF 15%
[C1,C2 are not available
for MHz version]
OSC1
I
Rf
C2
C1
2-6
Chapter 2. GMS37XXX
Port operation
Value of X-reg Value of Y-reg
Operation
SO : D(Y)
RO : D(Y)
1 (High-Z)
0
0 ~ 7
0 or 1
0 or 1
0 or 1
REMOUT port repeats ‘’H’’ and ‘’L’’ in pulse
frequency. (when PMR = 5, it is fixed at ‘’H’’ )
SO : REMOUT (PMR)
RO : REMOUT (PMR)
8
9
1
0
SO : D0 ~ D9
RO : D0 ~ D9
1 (High-Z)
0
SO : R(Y-Ah)
RO : R(Y-Ah)
1
0
0 or 1
0 or 1
0 or 1
A ~ D
SO : R0 ~ R3
RO : R0 ~ R3
1
0
E
F
SO : D0 ~ D9
RO : D0 ~ D9
1 (High-Z), R0 ~ R3
0,
1
0
R0 ~ R3
SO : D(8)
RO : D(8)
1 (High-Z)
0
2 or 3
2 or 3
0
1
SO : D(9)
RO : D(9)
1 (High-Z)
0
Optional Features
The GMS37XXX series offer the following optional features.
Theses options are masked.
•
•
•
I/O terminals having pull-up resistor : R0 ~ R3
Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3.
Output form at STOP mode
‘’L’’ or keep before stop mode.
D0 ~ D9 :
Theses options are offered default.
•
•
Ceramic oscillation circuit contained (or not contained)
[ This option is not available for MHz Ceramic oscillator. ]
Instruction cycle selection :
T = 48 / fOSC or 6 / fOSC
2-7
Chapter 2. GMS37XXX
Electrical Characteristics
Absolute maximum ratings (Ta = 25
Parameter
)
Symbol
Max. rating
Unit
Supply Voltage
VDD
PD
-0.3 ~ 5.0
700 *
V
Power dissipation
Storage temperature range
Input voltage
mW
Tstg
VIN
-55 ~ 125
-0.3 ~ VDD+0.3
-0.3 ~ VDD+0.3
V
V
Output voltage
VOUT
* Thermal derating above 25
: 6mW per degree
rise in temperature.
Recommended operating condition
Parameter
Supply Voltage
Symbol
Condition
Rating
Unit
VDD
300KHz ~ 4MHz
-
2.0 ~ 3.6
V
-20 ~ +70
Topr
Operating temperature
2-8
Chapter 2. GMS37XXX
Electrical characteristics (Ta=25 , VDD= 3V)
Limits
Condition
Parameter
Symbol
Unit
Min. Typ. Max.
VI = VDD , R having no Pull-up
Input H current
IIH
IIL
-
-1
70
70
0.3
2.1
-
-
-
1
-
uA
uA
Input L current
VI = GND, R having no Pull-up
VI = GND
K Pull-up Resistance
R Pull-up Resistance
Feedback Resistance
RPU1
RPU2
RFD
VIH1
VIL1
140
140
1.0
-
300
300
3.0
-
VI = GND, Output off
VOSC1= GND, VOSC2= GND
K, R Input H voltage
K, R Input L voltage
D, R Output L voltage
-
V
V
-
-
0.9
0.4
0.9
-
*1
IOL2 = 3mA
VOL2
-
0.15
0.4
2.5
2.2
-15
-
V
I
OL3 = 40uA (kHz), 150uA (MHz)
VOL3
VOH3
-
V
OSC2 Output L voltage
OSC2 Output H voltage
REMOUT Output L current
IOH3= -40uA (kHz), -150uA (MHz)
VOL1= 0.4V
2.1
1
V
*2
IOL1
4
mA
mA
uA
uA
mA
mA
*3
V
OH1= 2V
-5
-
-30
1
REMOUT Output H current
D, R Output leakage current
Current on STOP mode
IOH1
VOUT= VDD, Output off
At STOP mode
fOSC= 455kHz
IOLK2
ISTP
-
-
1
*3
Operating Supply current 1
Operating Supply current 2
IDD1
-
0.2
0.5
-
1.0
1.5
*3
fOSC= 4MHz
IDD2
-
System
fOSC/6
fOSC
fOSC
300
2.4
1000 kHz
MHz
kHz Version
colck
frequency
fOSC /48
MHz Version.
-
4
*1 Refer to
Fig.2-5 IOL2 vs. VOL2 Graph
*2 Refer to
*3 Refer to
Fig.2-6
Fig.2-7
I
OL1 vs. VOL1 Graph
OH1 vs. VOH1 Graph
I
*4 IDD1, IDD2, is measured at RESET mode.
2-9
Chapter 2. GMS37XXX
Fig 2-5. IOL2 vs. VOL2 Graph. ( D, R Port )
Fig 2-6. IOL1 vs VOL1 Graph (REMOUT Port)
2-10
Chapter 2. GMS37XXX
Fig 2-7. IOH1 vs VOH1 Graph (REMOUT Port)
2-11
GMS36XXX
1
2
3
4
5
6
7
8
9
GMS37XXX
PACKAGE DIMENSIONS
FUNCTIONAL DESCRIPTION
INSTRUCTION
APPLICATION
GMS36XXXT
GMS37XXXT
EPROM
Chapter 3. PACKAGE DIMENSIONS
3. PACKAGE DIMENSIONS
The GMS36/37XXX series can be used the following package dimesions.
UNIT : INCH
Fig 3-1. 16PDIP (300MIL)
UNIT : INCH
Fig 3-2. 16SOP (150MIL) (* This type is not supported at OTP)
3-1
Chapter 3. PACKAGE DIMENSIONS
UNIT : INCH
Fig 3-3. 16SOP (300MIL)
UNIT : INCH
Fig 3-4. 20SSOP (150MIL)
3-2
Chapter 3. PACKAGE DIMENSIONS
UNIT : INCH
Fig 3-5. 20PDIP (300MIL)
UNIT : INCH
Fig 3-6. 20SOP (300MIL)
3-3
Chapter 3. PACKAGE DIMENSIONS
UNIT : INCH
Fig 3-7. 24Skinny-DIP (300MIL)
UNIT : INCH
Fig 3-8. 24SOP (300MIL)
3-4
GMS36XXX
1
2
3
4
5
6
7
8
9
GMS37XXX
PACKAGE DIMENSIONS
FUNCTIONAL DESCRIPTION
INSTRUCTION
APPLICATION
GMS36XXXT
GMS37XXXT
EPROM
Chapter 4. FUNCTIONAL DESCRIPTION
4. FUNCTIONAL DESCRIPTION
Program Memory (ROM)
The GMS36/37XXX series can incorporate maximum 1,024 words (64 words 16
pages 8bits) for program memory. Program counter PC (A0~A5) and page
address register (A6~A9) are used to address the whole area of program memory
having an instruction (8bits) to be next executed.
The program memory consists of 64 words on each page, and thus each page
can hold up to 64 steps of instructions.
The program memory is composed as shown below.
Program capacity (pages)
0
1
2
3
4
8
5
6
7
Page 0
Page 1
Page 2
Page 15
6
63
0
1
2
15
A0~A5
A6~A9
Program counter (PC)
6
Page address register (PA)
Page buffer (PB)
4
4
Stack register
(Level "1")
(Level "2")
(Level "3")
(SR)
(PSR)
Fig 4-1 Configuration of Program Memory
4-1
Chapter 4. FUNCTIONAL DESCRIPTION
ROM Address Register
The following registers are used to address the ROM.
• Page address register (PA) :
Holds ROM's page number (0 ~ Fh) to be addressed.
• Page buffer register (PB) :
Value of PB is loaded by an LPBI command when newly addressing a page.
Then it is shifted into the PA when rightly executing a branch instruction (BR)
and a subroutine call (CAL).
• Program counter (PC) :
Available for addressing word on each page.
• Stack register (SR) :
Stores returned-word address in the subroutine call mode.
(1) Page address register and page buffer register :
Address one of pages #0 to #15 in the ROM by the 4-bit binary counter.
Unlike the program counter, the page address register is usually unchanged so
that the program will repeat on the same page unless a page changing command
is issued. To change the page address, take two steps such as (1) writing in the
page buffer what page to jump (execution of LPBI) and (2) execution of BR or CAL,
because instruction code is of eight bits so that page and word can not be specified
at the same time.
In case a return instruction (RTN) is executed within the subroutine that has been
called in the other page, the page address will be changed at the same time.
(2) Program counter :
This 6-bit binary counter increments for each fetch to address a word in the
currently addressed page having an instruction to be next executed.
For easier programming, at turning on the power, the program counter is
reset to the zero location. The PA is also set to "0". Then the program
counter specifies the next ROM address in random sequence.
When BR, CAL or RTN instructions are decoded, the switches on each step
are turned off not to update the address. Then, for BR or CAL, address
data are taken in from the instruction operands (a0 to a5), or for RTN, and
address is fetched from stack register No. 1.
(3) Stack register :
This stack register provides two stages each for the program counter (6bits)
and the page address register (4bits) so that subroutine nesting can be
made on two levels.
4-2
Chapter 4. FUNCTIONAL DESCRIPTION
Data Memory (RAM)
Up to 32 nibbles (16 words 2pages 4bits) is incorporated for storing data.
The whole data memory area is indirectly specified by a data pointer (X,Y). Page
number is specified by zero bit of X register, and words in the page by 4 bits in
Y-register. Data memory is composed in 16 nibbles/page. Figure 2-2 shows the
configuration.
D0
D9 R0 R3 REMOUT
Data memory page (0~1)
Output port
0
1
2
3
Page 0
Page 1
15
4
0
1
a0~a3
Y-register (Y)
X-register (X)
Fig 4-2 Composition of Data Memory
X-register (X)
X-register is consist of 2bit, X0 is a data pointer of page in the RAM, X1 is only
used for selecting of D8 ~ D9 with value of Y-register
X1=0
D0
X1=1
D8
Y=0
Y=1
D1
D9
Table 4-1 Mapping table between X and Y register
4-3
Chapter 4. FUNCTIONAL DESCRIPTION
Y-register (Y)
Y-register has 4 bits. It operates as a data pointer or a general-purpose register.
Y-register specifies an address (a0~a3) in a page of data memory, as well as it
is used to specify an output port. Further it is used to specify a mode of carrier
signal outputted from the REMOUT port. It can also be treated as a general-
purpose register on a program.
Accumulator (ACC)
The 4-bit register for holding data and calculation results.
Arithmetic and Logic Unit (ALU)
In this unit, 4bits of adder/comparator are connected in parallel as it's main
components and they are combined with status latch and status logic (flag.)
(1) Operation circuit (ALU) :
The adder/comparator serves fundamentally for full addition and data
comparison. It executes subtraction by making a complement by processing
an inversed output of ACC (ACC+1)
(2) Status logic :
This is to bring an ST, or flag to control the flow of a program. It occurs when
a specified instruction is executed in three cases such as overflow or underflow
in operation and two inputs unequal.
4-4
Chapter 4. FUNCTIONAL DESCRIPTION
State Counter (SC)
A fundamental machine cycle timing chart is shown below. Every instruction is
one byte length. Its execution time is the same. Execution of one instruction
takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total).
Virtually these two cycles proceed simultaneously, and thus it is apparently
completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN
instructions is normal execution time since they change an addressing sequentially.
Therefore, the next instruction is prefetched so that its execution is completed
within the fetch cycle.
T2
T1
T3 T4 T5 T6 T1 T2 T3 T4 T5 T6
Fetch cycle N
Execute cycle N
Fetch cycle N-1
Execute cycle N-1
Phase
Phase
Phase
Machine
Cycle
Machine
Cycle
Fig. 4-3 Fundamental timing chart
4-5
Chapter 4. FUNCTIONAL DESCRIPTION
Clock Generator
The GMS36/37XXX series has an internal clock oscillator. The oscillator circuit is
designed to operate with an external ceramic resonator. Internal capacitors are
available at kHz version. Oscillator circuit is able to organize by connecting
ceramic resonator to outside.
* It is necessary to connect capacitor to outside in order to change ceramic resonator,
you must refer to a manufacturer`s resonator matching guide.
OSC1
OSC2
2
3
C1
C2
* All type have the built-in loading capacitors.
4-1
Chapter 4. FUNCTIONAL DESCRIPTION
Pulse Generator
The following frequency and duty ratio are selected for carrier signal outputted
from the REMOUT port depending on a PMR (Pulse Mode Register) value set in
a program.
T
T1
PMR
REMOUT signal
T=1/fPUL = 12/fOSC [96/fOSC], T1/T = 1/2
T=1/fPUL = 12/fOSC [96/fOSC], T1/T = 1/3
0
1
2
T=1/fPUL = 8/fOSC [64/fOSC],
T=1/fPUL = 8/fOSC [64/fOSC],
T1/T = 1/2
T1/T = 1/4
3
4
T=1/fPUL = 11/fOSC [88/fOSC], T1/T = 4/11
No Pulse (same to D0 ~ D9)
5
6
T=1/fPUL = 12/fOSC [96/fOSC], T1/T = 1/4
No pulse (same to D0 ~ D9)
7
* Default value is "0"
* [ ] means the value of "T", when Instruction cycle is fOSC/48 in MHz version
Table 4-2 PMR selection table
4-7
Chapter 4. FUNCTIONAL DESCRIPTION
Reset Operation
GMS36/37XXX has three reset sources. One is a built-in Power-on reset circuit, another
is a built-in Low VDD Detection circuit, the other is the overflow of Watch Dog Timer. (WDT)
All reset operations are internal in the GMS36/37XXX.
Built-in Power On Reset Circuit
GMS36/37XXX has a built-in Power-on reset circuit consisting of an about 1 Resistor
and a 3pF Capacitor. When the Power-on reset pulse occurs, system reset signal is
latched and WDT is cleared. After the overflow time of WDT (213 x System clock time)
system reset signal is released.
<GMS36/37XXX>
VCC
System
RESETB
treset
About 108msec at
fosc = 455kHz
Fig. 4-4 Power-On Reset Circuit and Timing Chart
4-8
Chapter 4. FUNCTIONAL DESCRIPTION
Built-in Low VDD Detection Circuit
GMS36/37XXX has a Low VDD detection circuit.
If VDD become Reset Voltage of Low VDD Detection circuit at active status, system
reset occur and WDT is cleared. After VDD is increased upper Reset Voltage again,
WDT is re-counted and if WDT is overflowed, system reset is released.
VDD
Reset Voltage
Internal
RESETB
About 108msec at fosc =455kHz
Fig. 4-5 Low Voltage Detection diagram
Fig. 4-6 Low Voltage vs Temperature
4-9
Chapter 4. FUNCTIONAL DESCRIPTION
Watch Dog Timer (WDT)
Watch dog timer is organized binary of 14 steps. The signal of fOSC/6 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
The overflow time is 6 2 13/fOSC (108.026ms at fOSC=455KHz.)
8 6 213/fOSC (108.026ms at fOSC = 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR), Power-on reset pulse or Low VDD detection pulse.
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted.
Binary counter(14 steps)
fOSC/6 or fOSC/48
RESET (edge-trigger)
CPU reset
Reset
by instruction
Power-On Reset
Low VDD Detection
Fig. 4-7 Block Diagram of Watch-dog Timer
4-10
Chapter 4. FUNCTIONAL DESCRIPTION
STOP Operation
Stop mode can be achieved by STOP instructions.
In stop mode :
1. Oscillator is stopped, the operating current is low.
2. Watch dog timer is reset, REMOUT output is disable
(High-Z at GMS36XXX(T) , “L” at GMS37XXX(T))
3. Part other than WDT and REMOUT output have a value before
come into stop mode.
* But the state of D0 ~ D9 output in stop mode is able to choose as masked option.
"L" output or same level before come into stop mode.
The Function to release stop mode is able to choose each bit of K or R input as masked option.
Stop mode is released when one of K or R input is going to "L".
1. State of D0 ~ D9 output and REMOUT output is return to state of before stop mode is
achieved.
2. After 210 {System clock time} for stable oscillating, first instruction start to operate.
3. In return to normal operation, WDT is counted from zero again.
But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction
is same to NOP instruction.
4-11
GMS36XXX
1
2
3
4
5
6
7
8
9
GMS37XXX
PACKAGE DIMENSIONS
FUNCTIONAL DESCRIPTION
INSTRUCTION
APPLICATION
GMS36XXXT
GMS37XXXT
EPROM
Chapter 5. INSTRUCTION
CHAPTER 5. INSTRUCTION
INSTRUCTION FORMAT
All of the 43 instruction in GMS36/37XXX(T) series is format in two fields of OP
code and operand which consist of eight bits. The following formats are available
with different types of operands.
*Format
All eight bits are for OP code without operand.
*Format
Two bits are for operand and six bits for OP code.
Two bits of operand are used for specifying bits of RAM and X-register (bit 1 and
bit 7 are fixed at 0 )
*Format
Four bits are for operand and the others are OP code.
Four bits of operand are used for specifying a constant loaded in RAM or Y-
register, a comparison value of compare command, or page addressing in ROM.
*Format
Six bits are for operand and the others are OP code.
Six bits of operand are used for word addressing in the ROM.
5-1
Chapter 5. INSTRUCTION
INSTRUCTION TABLE
The GMS36/37XXX(T) series provides the following 43 basic instructions.
Category Mnemonic
Function
ST*1
S
S
S
S
S
S
S
S
S
S
S
S
S
E
S
S
S
S
C
B
C
B
S
C
B
1
LAY
LYA
LAZ
A
Y
A
Y
A
0
Register to
Register
2
3
4
LMA
LMAIY
LYM
LAM
XMA
LYI i
LMIIY i
LXI n
SEM n
REM n
TM n
BR a
CAL a
RTN
LPBI i
AM
M(X,Y)
M(X,Y)
A
5
A, Y
M(X,Y)
M(X,Y)
Y+1
RAM to
Register
6
Y
A
A
Y
7
8
M(X,Y)
i
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
M(X,Y)
i, Y
Y+1
Immediate
X
n
M(n)
M(n)
1
RAM Bit
Manipulation
0
TEST M(n) = 1
if ST = 1 then Branch
if ST = 1 then Subroutine call
Return from Subroutine
ROM
Address
PB
A
i
A + M(X,Y)
M(X,Y) - A
M(X,Y) + 1
M(X,Y) - 1
A + 1
SM
A
IM
A
Arithmetic
DM
A
IA
A
IY
Y
Y + 1
DA
A
A - 1
5-2
Chapter 5. INSTRUCTION
Category Mnemonic
Function
ST*1
B
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DY
Y
A
A
Y - 1
Arithmetic
EORM
NEGA
ALEM
ALEI i
MNEZ
YNEA
YNEI i
KNEZ
RNEZ
LAK
A + M (X,Y)
A + 1
S
Z
TEST A M(X,Y)
TEST A
TEST M(X,Y)
E
i
E
0
N
Comparison
TEST Y
TEST Y
TEST K
TEST R
A
i
N
N
0
0
N
N
A
A
K
R
S
LAR
S
Input /
Output
SO
Output
Output
0 at GMS36XXX, 1 at GMS37XXX
1 at GMS36XXX, 0 at GMS37XXX
S
S
S
S
S
S
RO
WDTR
STOP
LPY
Watch Dog Timer Reset
Stop operation
Control
PMR
Y
NOP
No operation
Note) i = 0~f, n = 0~3, a = 6bit PC Address
*1 Column ST indicates conditions for changing status. Symbols have the following
meanings
S : On executing an instruction, status is unconditionally set.
C : Status is only set when carry or borrow has occurred in operation.
B : Status is only set when borrow has not occurred in operation.
E : Status is only set when equality is found in comparison.
N : Status is only set when equality is not found in comparison.
Z : Status is only set when the result is zero.
5-3
Chapter 5. INSTRUCTION
DETAILS OF INSTRUCTION SYSTEM
All 43 basic instructions of the GMS36/37XXX(T) Series are one by one described
in detail below.
Description Form
Each instruction is headlined with its mnemonic symbol according to the
instructions table given earlier.
Then, for quick reference, it is described with basic items as shown below. After
that, detailed comment follows.
• Items :
- Naming :
- Status :
- Format :
- Operand :
- Function
Full spelling of mnemonic symbol
Check of status function
Categorized into
to
Omitted for Format
5-4
Chapter 5. INSTRUCTION
(1) LAY
Naming :
Load Accumulator from Y-Register
Status :
Format :
Set
I
Function :
<Comment>
A
Y
Data of four bits in the Y-register is unconditionally transferred
to the accumulator. Data in the Y-register is left unchanged.
(2) LYA
Naming :
Status :
Format :
Load Y-register from Accumulator
Set
I
Function :
<Comment>
Y
A
Load Y-register from Accumulator
(3) LAZ
Naming :
Status :
Format :
Clear Accumulator
Set
I
Function :
<Comment>
A
0
Data in the accumulator is unconditionally reset to zero.
(4) LMA
Naming :
Status :
Format :
Load Memory from Accumulator
Set
I
Function :
<Comment>
M(X,Y)
A
Data of four bits from the accumulator is stored in the RAM
location addressed by the X-register and Y-register. Such data
is left unchanged.
(5) LMAIY
Naming :
Status :
Format :
Load Memory from Accumulator and Increment Y-Register
Set
I
Function :
<Comment>
M(X,Y)
A, Y
Y+1
Data of four bits from the accumulator is stored in the RAM
location addressed by the X-register and Y-register. Such data
is left unchanged.
5-5
Chapter 5. INSTRUCTION
(6) LYM
Naming :
Status :
Format :
Load Y-Register form Memory
Set
I
Function :
Y
M(X,Y)
<Comment>
Data from the RAM location addressed by the X-register and
Y-register is loaded into the Y-register. Data in the memory is
left unchanged.
(7) LAM
Naming :
Status :
Format :
Load Accumulator from Memory
Set
I
Function :
<Comment>
A
M(X,Y)
Data from the RAM location addressed by the X-register and
Y-register is loaded into the Y-register. Data in the memory is
left unchanged.
(8) XMA
Naming :
Status :
Format :
Exchanged Memory and Accumulator
Set
I
Function :
<Comment>
M(X,Y)
A
Data from the memory addressed by X-register and Y-register
is exchanged with data from the accumulator. For example,
this instruction is useful to fetch a memory word into the
accumulator for operation and store current data from the
accumulator into the RAM. The accumulator can be restored
by another XMA instruction.
(9) LYI i
Naming :
Status :
Load Y-Register from Immediate
Set
Format :
Operand :
Function :
<Purpose>
Constant 0
i
15
Y
i
To load a constant in Y-register. It is typically used to specify
Y-register in a particular RAM word address, to specify the
address of a selected output line, to set Y-register for
specifying a carrier signal outputted from OUT port, and to
initialize Y-register for loop control. The accumulator can be
restored by another XMA instruction.
<Comment>
Data of four bits from operand of instruction is transferred to
the Y-register.
5-6
Chapter 5. INSTRUCTION
(10) LMIIY i
Naming :
Status :
Load Memory from Immediate and Increment Y-Register
Set
Format :
Operand :
Function :
<Comment>
Constant 0
M(X,Y)
i
15
i, Y
Y + 1
Data of four bits from operand of instruction is stored into the
RAM location addressed by the X-register and Y-register.
Then data in the Y-register is incremented by one.
(11) LXI n
Naming :
Status :
Load X-Register from Immediate
Set
Format :
Operand :
Function :
<Comment>
X file address 0
n
3
X
n
A constant is loaded in X-register. It is used to set X-register in
an index of desired RAM page. Operand of 1 bit of command
is loaded in X-register.
(12) SEM n
Naming :
Status :
Set Memory Bit
Set
Format :
Operand :
Function :
<Comment>
Bit address 0
M(X,Y,n)
n
3
1
Depending on the selection in operand of operand, one of four
bits is set as logic 1 in the RAM memory addressed in
accordance with the data of the X-register and Y-register.
(13) REM n
Naming :
Status :
Reset Memory Bit
Set
Format :
Operand :
Function :
<Comment>
Bit address 0
M(X,Y,n)
n
3
0
Depending on the selection in operand of operand, one of four
bits is set as logic 0 in the RAM memory addressed in
accordance with the data of the X-register and Y-register.
5-7
Chapter 5. INSTRUCTION
(14) TM n
Naming :
Status :
Test Memory Bit
Comparison results to status
Format :
Operand :
Function :
Bit address 0
M(X,Y,n)
n
3
1?
ST
1 when M(X,Y,n)=1, ST
0 when M(X,Y,n)=0
<Purpose>
A test is made to find if the selected memory bit is logic. 1
Status is set depending on the result.
(15) BR a
Naming :
Status :
Branch on status 1
Conditional depending on the status
Format :
Operand :
Function :
Branch address a (Addr)
When ST =1 , PA
When ST = 0, PC
PB, PC
PC + 1, ST
a(Addr)
1
Note : PC indicates the next address in a fixed sequence that
is actually pseudo-random count.
<Purpose>
For some programs, normal sequential program execution can
be change.
A branch is conditionally implemented depending on the status
of results obtained by executing the previous instruction.
<Comment>
• Branch instruction is always conditional depending on the
status.
a. If the status is reset (logic 0), a branch instruction is not
rightly executed but the next instruction of the sequence is
executed.
b. If the status is set (logic 1), a branch instruction is executed
as follows.
• Branch is available in two types - short and long. The former
is for addressing in the current page and the latter for
addressing in the other page. Which type of branch to exeute
is decided according to the PB register. To execute a long
branch, data of the PB register should in advance be modified
to a desired page address through the LPBI instruction.
5-8
Chapter 5. INSTRUCTION
(16) CAL a
Naming :
Subroutine Call on status 1
Status :
Conditional depending on the status
Format :
Operand :
Function :
Subroutine code address a(Addr)
When ST =1 , PC
SR1
a(Addr)
PC + 1,
SR1
PA
PB
PA
PSR1
PSR2
PSR1
PSR2
PSR3
PB
SR2
SR3
SR2
When ST = 0 PC
PC + 1
PS ST
1
Note : PC actually has pseudo-random count against the next
instruction.
<Comment>
• In a program, control is allowed to be transferred to a mutual
subroutine. Since a call instruction preserves the return
address, it is possible to call the subroutine from different
locations in a program, and the subroutine can return control
accurately to the address that is preserved by the use of the
call return instruction (RTN).
Such calling is always conditional depending on the status.
a. If the status is reset, call is not executed.
b. If the status is set, call is rightly executed.
The subroutine stack (SR) of three levels enables a subroutine
to be manipulated on three levels. Besides, a long call (to call
another page) can be executed on any level.
• For a long call, an LPBI instruction should be executed before
the CAL. When LPBI is omitted (and when PA=PB), a short
call (calling in the same page) is executed.
5-9
Chapter 5. INSTRUCTION
(17) RTN
Naming :
Status :
Return from Subroutine
Set
Format :
Function :
PC
SR1
SR2
SR3
SR3
PA, PB
PSR1
PSR2
PSR3
ST
PSR1
PSR2
PSR3
PSR2
1
SR1
SR2
SR3
<Purpose>
Control is returned from the called subroutine to the calling
program.
<Comment>
Control is returned to its home routine by transferring to the PC
the data of the return address that has been saved in the stack
register (SR1).
At the same time, data of the page stack register (PSR1) is
transferred to the PA and PB.
(18) LPBI i
Naming :
Status :
Load Page Buffer Register from Immediate
Set
Format :
Operand :
Function :
<Purpose>
ROM page address 0
PB
A new ROM page address is loaded into the page buffer
register (PB).
i
15
i
This loading is necessary for a long branch or call instruction.
The PB register is loaded together with three bits from 4 bit
operand.
<Comment>
(19) AM
Naming :
Status :
Add Accumulator to Memory and Status 1 on Carry
Carry to status
Format :
Function :
A
M(X,Y)+A, ST
ST
1(when total>15),
0 (when total 15)
<Comment>
Data in the memory location addressed by the X and Y-register
is added to data of the accumulator. Results are stored in the
accumulator. Carry data as results is transferred to status.
When the total is more than 15, a carry is caused to put 1
in the status. Data in the memory is not changed.
5-10
Chapter 5. INSTRUCTION
(20) SM
Naming :
Subtract Accumulator to Memory and Status 1 Not Borrow
Carry to status
Status :
Format :
Function :
A
M(X,Y) - A
ST
ST
1(when A M(X,Y))
0(when A > M(X,Y))
<Comment>
Data of the accumulator is, through a 2`s complemental
addition, subtracted from the memory word addressed by the
Y-register. Results are stored in the accumulator. If data of
the accumulator is less than or equal to the memory word, the
status is set to indicate that a borrow is not caused.
If more than the memory word, a borrow occurs to reset the
status to 0 .
(21) IM
Naming :
Increment Memory and Status 1 on Carry
Carry to status
Status :
Format :
Function :
A
M(X,Y) + 1
ST
ST
1(when M(X,Y) 15)
0(when M(X,Y) < 15)
<Comment>
Data of the memory addressed by the X and Y-register is
fetched. Adding 1 to this word, results are stored in the
accumulator. Carry data as results is transferred to the status.
When the total is more than 15, the status is set. The memory
is left unchanged.
(22) DM
Naming :
Decrement Memory and Status 1 on Not Borrow
Carry to status
Status :
Format :
Function :
A
M(X,Y) - 1
ST
ST
1(when M(X,Y) 1)
0 (when M(X,Y) = 0)
<Comment>
Data of the memory addressed by the X and Y-register is
fetched, and one is subtracted from this word (addition of Fh)>
Results are stored in the accumulator. Carry data as results is
transferred to the status. If the data is more than or equal to
one, the status is set to indicate that no borrow is caused. The
memory is left unchanged.
5-11
Chapter 5. INSTRUCTION
(23) IA
Naming :
Status :
Format :
Increment Accumulator
Set
Function :
A
A+1
<Comment>
Data of the accumulator is incremented by one. Results are
returned to the accumulator.
A carry is not allowed to have effect upon the status.
(24) IY
Naming :
Status :
Increment Y-Register and Status 1 on Carry
Carry to status
Format :
Function :
Y
Y + 1
ST
ST
1 (when Y = 15)
0 (when Y < 15)
<Comment>
Data of the Y-register is incremented by one and results are
returned to the Y-register.
Carry data as results is transferred to the status. When the
total is more than 15, the status is set.
(25) DA
Naming :
Status :
Decrement Accumulator and Status 1 on Borrow
Carry to status
Format :
Function :
A
A - 1
ST
ST
1(when A 1)
0 (when A = 0)
<Comment>
Data of the accumulator is decremented by one. As a result
(by addition of Fh), if a borrow is caused, the status is reset to
0 by logic. If the data is more than one, no borrow occurs
and thus the status is set to 1 .
5-12
Chapter 5. INSTRUCTION
(26) DY
Naming :
Decrement Y-Register and Status 1 on Not Borrow
Carry to status
Status :
Format :
Function :
Y
Y -1
ST
ST
1 (when Y 1)
0 (when Y = 0)
<Purpose>
<Comment>
Data of the Y-register is decremented by one.
Data of the Y-register is decremented by one by addition of
minus 1 (Fh).
Carry data as results is transferred to the status. When the
results is equal to 15, the status is set to indicate that no
borrow has not occurred.
(27) EORM
Naming :
Status :
Exclusive or Memory and Accumulator
Set
Format :
Function :
<Comment>
A
M(X,Y) + A
Data of the accumulator is, through a Exclusive OR,
subtracted from the memory word addressed by X and Y-
register. Results are stored into the accumulator.
(28) NEGA
Naming :
Status :
Negate Accumulator and Status 1 on Zero
Carry to status
Format :
Function :
A
A + 1
ST
ST
1(when A = 0)
0 (when A != 0)
<Purpose>
<Comment>
The 2`s complement of a word in the accumulator is obtained.
The 2`s complement in the accumulator is calculated by adding
one to the 1`s complement in the accumulator. Results are
stored into the accumulator. Carry data is transferred to the
status. When data of the accumulator is zero, a carry is
caused to set the status to 1 .
5-13
Chapter 5. INSTRUCTION
(29) ALEM
Naming :
Status :
Accumulator Less Equal Memory
Carry to status
Format :
Function :
A
M(X,Y)
ST
ST
1 (when A M(X,Y))
0 (when A > M(X,Y))
<Comment>
Data of the accumulator is, through a complemental addition,
subtracted from data in the memory location addressed by the
X and Y-register. Carry data obtained is transferred to the
status. When the status is 1 , it indicates that the data of
the accumulator is less than or equal to the data of the
memory word. Neither of those data is not changed.
(30) ALEI
Naming :
Status :
Accumulator Less Equal Immediate
Carry to status
Format :
Function :
A
i
ST
ST
1 (when A i)
0 (when A > i)
<Purpose>
Data of the accumulator and the constant are arithmetically
compared.
<Comment>
Data of the accumulator is, through a complemental addition,
subtracted from the constant that exists in 4bit operand. Carry
data obtained is transferred to the status. The status is set
when the accumulator value is less than or equal to the
constant. Data of the accumulator is left unchanged.
(31) MNEZ
Naming :
Memory Not Equal Zero
Status :
Comparison results to status
Format :
Function :
M(X,Y)
0
ST
ST
1(when M(X,Y) 0)
0 (when M(X,Y) = 0)
<Purpose>
A memory word is compared with zero.
<Comment>
Data in the memory addressed by the X and Y-register is
logically compared with zero. Comparison data is thransferred
to the status. Unless it is zero, the status is set.
5-14
Chapter 5. INSTRUCTION
(32) YNEA
Naming :
Y-Register Not Equal Accumulator
Comparison results to status
Status :
Format :
Function :
Y
A
ST
ST
1 (when Y A)
0 (when Y = A)
<Purpose>
Data of Y-register and accumulator are compared to check if
they are not equal.
<Comment>
Data of the Y-register and accumulator are logically compared.
Results are transferred to the status. Unless they are equal,
the status is set.
(33) YNEI
Naming :
Status :
Y-Register Not Equal Immediate
Comparison results to status
Format :
Operand :
Function :
Constant 0
i
15
Y
i
ST
ST
1 (when Y i)
0 (when Y = i)
<Comment>
The constant of the Y-register is logically compared with 4bit
operand. Results are transferred to the status. Unless the
operand is equal to the constant, the status is set.
(34) KNEZ
Naming :
Status :
K Not Equal Zero
The status is set only when not equal
Format :
Function :
<Purpose>
<Comment>
When K 0, ST
A test is made to check if K is not zero.
Data on K are compared with zero. Results are transferred to
the status. For input data not equal to zero, the status is set.
1
(35) RNEZ
Naming :
Status :
R Not Equal Zero
The status is set only when not equal
Format :
Function :
<Purpose>
<Comment>
When R 0, ST
A test is made to check if R is not zero.
Data on R are compared with zero. Results are transferred to
the status. For input data not equal to zero, the status is set.
1
5-15
Chapter 5. INSTRUCTION
(36) LAK
Naming :
Status :
Load Accumulator from K
Set
Format :
Function :
A
K
<Comment>
Data on K are transferred to the accumulator
(37) LAR
Naming :
Status :
Load Accumulator from R
Set
Format :
Function :
<Comment>
A
R
Data on R are transferred to the accumulator
(38) SO
Naming :
Status :
Set Output Register Latch
Set
Format :
Function :
D(Y)
1
0
Y
7
REMOUT
REMOUT
D0~D9
0(PMR=5)
1(PMR=5)
1 (High-Z)
Y = 8 at GMS36XXX(T)
Y = 8 at GMS37XXX(T)
Y = 9
R(Y)
R
D0~D9, R
1
Ah
Y = Eh
Y = Fh
Y
Dh
1
1
<Purpose>
A single D output line is set to logic 1, if data of Y-register is
between 0 to 7.
Carrier frequency come out from REMOUT port, if data of
Y-register is 8.
All D output line is set to logic 1, if data of Y-register is 9.
It is no operation, if data of Y-register between 10 to 15.
When Y is between Ah and Dh, one of R output lines is set at
logic 1.
When Y is Eh, the output of R is set at logic 1.
When Y is Fh, the output D0~D9 and R are set at logic 1.
Data of Y-register is between 0 to 7, selects appropriate D
output.
<Comment>
Data of Y-register is 8, selects REMOUT port.
Data of Y-register is 9, selects all D port.
Data in Y-register, when between Ah and Dh, selects an
appropriate R output (R0~R3).
Data in Y-register, when it is Eh, selects all of R0~R3.
Data in Y-register, when it is Fh, selects all of D0~D9 and
R0~R3.
5-16
Chapter 5. INSTRUCTION
(39) RO
Naming :
Reset Output Register Latch
Set
Status :
Format :
Function :
D(Y)
0
0
Y
7
REMOUT
REMOUT
D0~D9
1
0
Y = 8 at GMS36XXX(T)
Y = 8 at GMS37XXX(T)
Y = 9
0
R(Y)
R
D0~D9, R
0
Ah
Y = Eh
Y = Fh
Y
Dh
0
0
<Purpose>
A single D output line is set to logic 0, if data of Y-register is
between 0 to 9.
REMOUT port is set to logic 0, if data of Y-register is 9.
All D output line is set to logic 0, if data of Y-register is 9.
When Y is between Ah and Dh, one of R output lines is set at
logic 0.
When Y is Eh, the output of R is set at logic 0
When Y is Fh, the output D0~D9 and R are set at logic 1.
Data of Y-register is between 0 to 7, selects appropriate D
output.
<Comment>
Data of Y-register is 8, selects REMOUT port.
Data of Y-register is 9, selects D port.
Data in Y-register, when between Ah and Dh, selects an
appropriate R output (R0~R3).
Data in Y-register, when it is Eh, selects all of R0~R3.
Data in Y-register, when it is Fh, selects all of D0~D9 and
R0~R3.
(40) WDTR
Naming :
Status :
Watch Dog Timer Reset
Set
Format :
Function :
<Purpose>
Reset Watch Dog Timer (WDT)
Normally, you should reset this counter before overflowed
counter for dc watch dog timer. this instruction controls this
reset signal.
5-17
Chapter 5. INSTRUCTION
(41) STOP
Naming :
Status :
STOP
Set
Format :
Function :
<Purpose>
Operate the stop function
Stopped oscillator, and little current.
(See 1-12 page, STOP function.)
(42) LPY
Naming :
Status :
Pulse Mode Set
Set
Format :
Function :
<Comment>
PMR
Y
Selects a pulse signal outputted from REMOUT port.
(43) NOP
Naming :
Status :
No Operation
Set
Format :
Function :
No operation
5-18
GMS36XXX
1
2
3
4
5
6
7
8
9
GMS37XXX
PACKAGE DIMENSIONS
FUNCTIONAL DESCRIPTION
INSTRUCTION
APPLICATION
GMS36XXXT
GMS37XXXT
EPROM
Chapter 6. Application
Guideline for S/W
1. All rams need to be initialized to zero in reset address for proper design.
2. Make the output ports `H` after reset.
3. Do not use WDTR instruction in subroutine.
4. Before reading the input port the waiting time should be more than 200uS.
5. To decrease current consumption, make the output port as high in normal routine except
for key scan strobe and STOP mode.
6. We recommend you do not use all 64 bytes in a page. You had better write ` BR $` in
unused area. This will help you prevent unusual operation of MCU.
7. Be careful not to use long call or branch (CALL,BL) with arithmetic manipulation.
If you want to use branch right after arithmetic manipulation, the long call or branch will be
against your intention.
ex)
LAR
; The value of R ports -> Accumulator
14 : S = 0
ALEI 14 ; A 14 : S = 1,
A
BL TRUE ; S is always 1 because BL is composed of LPBI and BR.
-------------- Fail
LAR
ALEI 14 ; A 14 : S = 1,
BR TRUE ; When S is 1 Branch will occur. Otherwise Branch will not occur and
LAK ; next instruction will be operated.
-------------- Right
; The value of R ports -> Accumulator
A
14 : S = 0
6-1
Chapter 6. Application
We recommend
alkaline battery
6-2
Chapter 6. Application
We recommend
alkaline battery
6-3
Chapter 6. Application
CUSTOM:04H
6-4
Chapter 6. Application
- Configuration of Flame
1st flame
Lead code
Custom code
Custom code
Data code
Data code
9ms
4.5ms
C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D5 D7
- Repeat code
0.56ms
9ms
2.25ms
- Bit Description
Bit
0
Bit 1
0.56ms
0.56ms
1.125ms
2.25ms
- Flame Interval : Tf
The transmitted waveform as long as a key is depressed
Tf=108mS
Tf=108mS
6-5
Chapter 6. Application
Example program - uPD6121G
6-6
Chapter 6. Application
6-7
Chapter 6. Application
6-8
Chapter 6. Application
6-9
Chapter 6. Application
6-10
Chapter 6. Application
6-11
Chapter 6. Application
6-12
Chapter 6. Application
6-13
GMS36XXX
1
2
3
4
5
6
7
8
9
GMS37XXX
PACKAGE DIMENSIONS
FUNCTIONAL DESCRIPTION
INSTRUCTION
APPLICATION
GMS36XXXT
GMS37XXXT
EPROM
Chapter 7.GMS36XXXT
CHAPTER 7. GMS36XXXT
Description
The GMS36XXXT series are remote control transmitter which uses CMOS technology
and the EPROM version.
This enables transmission code outputs of different configurations, multiple custom code
output and double push key output for easy fabrication.
The GMS36XXXT series are suitable for remote control of TV, VCR, FANS, Air-conditioners,
Audio Equipment, Toys, Games etc.
Features
•
Program memory : 1,024 bytes for GMS36/004T/112T/140T
Data memory : 32 4 bits
•
•
•
•
43 types of instruction set
3 levels of subroutine nesting
Operating frequency : 300kHz ~ 1MHz at kHz version
2.4MHz ~ 4MHz at MHz version
•
Instruction cycle :
fOSC/6 at kHz version
fOSC/48 at MHz version
•
•
•
•
•
•
•
•
•
CMOS process (Single 3.0V power supply)
Stop mode (Through internal instruction)
Released stop mode by key input
Built in Power-on Reset circuit
Built in Low Voltage Detection circuit
Built in capacitor for ceramic oscillation circuit at kHz version
Built in a watch dog timer (WDT)
Built in transistor for I.R LED Drive : IOL =190mA at VDD =3V and VO =0.3V
Low operating voltage: 2.2 ~ 3.6V (at 300kHz ~ 4MHz)
Table 7-1 GMS36XXXT series members
Series
Program memory
Data memory
I/O ports
GMS36004T
GMS36112T
GMS36140T
1,024
1,024
1,024
32
4
32
4
32
4
-
4
4
4
4
Input ports
4
Output ports
Package
6 (D0~D5)
6 (D0~D5)
10 (D0~D9)
16DIP/SOP
20DIP/SOP/SSOP
24Skinny DIP/SOP
7-1
Chapter 7. GMS36XXXT
Pin Description
Pin
I/O
Function
VDD
-
Connected to 2.2~ 3.6V power supply
GND
-
Connected to 0V power supply.
4-bit input port with built in pull-up resistor.
STOP mode is released by "L" input of each pin.
Especially, K3 is the input pin for VPP.
Input
K0 ~ K3
For programming K3 pin receives 12.5V(programming voltage).
Each can be set and reset independently.
D0 ~ D9
R0 ~ R3
Output
I/O
The output is the structure of N-channel-open-drain.
4-bit I/O port. (Input mode is set only when each of them output
"H".)
In outputting, each can be set and reset independently(or at once.)
The output is in the form of C-MOS.
STOP mode is released by "L" input of each pin.
Oscillator input. Input to the oscillator circuit and connection point for
ceramic resonator.
OSC1
Input
Internal capacitors available at kHz version.
A feedback resistor is internally connected between this pin and
OSC2.
Connect a resonator between this pin and OSC1.
OSC2
Output
Output
High current output port driving I.R. LED.
REMOUT
The output is in the form of N-channel-open-drain.
High current Tr. ground pin. (connected to GND)
PGND
-
High current output Tr. is connected between this pin and
REMOUT.
7-2
Chapter 7. GMS36XXXT
STOP Operation
Stop mode can be achieved by STOP instructions.
In stop mode :
1. Oscillator is stopped, the operating current is low.
2. Watch dog timer is reset, D0~D3 output is "L"and REMOUT output is "H" (Output
Tr. is off.)
3. Part other than WDT, D0~D3 output and REMOUT output have a value before
come into stop mode.
Stop mode is released when one of K or R input is going to "L".
1. State of D0~D3 output and REMOUT output is return to state of before stop mode
is achieved.
2. After 210 System clock time for stable oscillating, first instruction start to operate.
3. In return to normal operation, WDT is counted from zero again.
But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction
is same to NOP instruction.
7-3
Chapter 7. GMS36XXXT
Electrical Characteristics
Absolute maximum ratings (Ta = 25 )
Parameter
Symbol
Max. rating
Unit
Supply Voltage
VDD
VPP
PD
-0.3 ~ 5.0
-0.3 ~ 13.5
700 *
V
V
Programming Voltage
Power dissipation
Storage temperature range
Input voltage
mW
Tstg
VIN
-55 ~ 125
-0.3 ~ VDD+0.3
-0.3 ~ VDD+0.3
V
V
Output voltage
VOUT
* Thermal derating above 25
: 6mW per degree
rise in temperature.
Recommended operating condition
Parameter
Symbol
Condition
Rating
Unit
Supply Voltage
VDD
300kHz ~ 4MHz
-
2.2 ~ 3.6
V
Operating temperature
Topr
-20 ~ +70
7-4
Chapter 7. GMS36XXXT
Electrical characteristics (Ta=25 , VDD= 3V)
Limits
Parameter
Symbol
Unit
Condition
Min. Typ. Max.
1
uA
VI=VDD
IIH
-
-
Input H current
RPU1
RPU2
VI=GND
K Pull-up Resistance
R Pull-up Resistance
300
300
3.0
-
70
70
140
140
VI=GND, Output off
RFD
VIH1
VIL1
Feedback Resistance
VOSC1=GND, VOSC2=VDD
0.3
2.1
1.0
-
V
V
V
V
-
-
K, R input H voltage
K, R input L voltage
0.9
0.4
-
-
-
*1
VOL2
0.15
0.4
IOL2=3mA
D. R output L voltage
OSC2 output L voltage
IOL3=40uA (455kHz)
-
VOL3
VOH3
0.9
-
= 150uA (4MHz)
IOH3= -40uA (455kHz)
OSC2 output H voltage
2.1
2.5
V
= -150uA (4MHz)
230
mA
VOL1=0.3V
150
190
*2
REMOUT output L current
IOL1
300
1
mA
uA
VOL1=0.4V
200
-
250
-
IOLK1
IOLK2
VOUT=VDD, Output off
REMOUT leakage current
D, R output leakage current
1
uA
-
-
VOUT=VDD, Output off
1
uA
mA
mA
At STOP mode
fOSC=455KHz
fOSC=4MHz
ISTP
-
-
-
-
Current on STOP mode
*3
1.5
3.0
IDD1
0.8
1.0
Operating supply current 1
Operating supply current 2
*3
IDD2
fOSC/6
1000
4
kHz
kHz version
MHz version
fOSC
fOSC
300
2.4
-
-
System
clock
frequency
MHz
fOSC/48
*1 Refer to
*2 Refer to
Fig.7-1 IOL2 vs. VOL2 Graph
Fig.7-2 IOL1 vs. VOL1 Graph
*3 IDD1, IDD2, is measured at RESET mode.
7-5
Chapter 7. GMS36XXXT
Fig 7-1. IOL2 vs. VOL2 Graph. ( D, R Port )
Fig 7-2. IOL1 vs. VOL1 Graph. ( REMOUT port)
7-6
GMS36XXX
1
2
3
4
5
6
7
8
9
GMS37XXX
PACKAGE DIMENSIONS
FUNCTIONAL DESCRIPTION
INSTRUCTION
APPLICATION
GMS36XXXT
GMS37XXXT
EPROM
Chapter 8. GMS37XXXT
CHAPTER 8. GMS37XXXT
Description
The GMS37XXXT series are remote control transmitter which uses CMOS
technology and the EPROM version.
This enables transmission code outputs of different configurations, multiple
custom code output, and double push key output for easy fabrication.
The GMS37XXXT series are suitable for remote control of TV, VCR, FANS, Air-
conditioners, Audio Equipment, Toys, Games etc.
It is possible to structure the 8 x 7 key matrix for GMS37112T, and the 4 x 7 key
matrix for GMS37004T.
Features
•
•
•
•
•
Program memory
: 1,024 bytes for GMS37004T/112T/140T
Data memory : 32 4 bits
43 types of instruction set
3 levels of subroutine nesting
Operating frequency : 300kHz ~ 1MHz at kHz version
2.4MHz ~ 4MHz at MHz version
•
Instruction cycle :
fOSC/6 at kHz version
fOSC/48 at MHz version
•
•
•
•
•
•
•
•
CMOS process (Single 3.0V power supply)
Stop mode (Through internal instruction)
Released stop mode by key input
Built in Power-on Reset circuit
Built in Low Voltage Detection circuit
Built in capacitor for ceramic oscillation circuit at kHz version
Built in a watch dog timer (WDT)
Low operating voltage : 2.2 ~ 3.6V (at 300kHz ~ 4MHz)
Table 8-1 GMS37XXXT series members
Series
Program memory
Data memory
I/O ports
GMS37004T
GMS37112T
GMS37140T
1,024
1,024
1,024
32
4
32
4
32
4
-
4
4
4
4
Input ports
4
Output ports
Package
7 (D0~D6)
7 (D0~D6)
10 (D0~D9)
16DIP/SOP
20DIP/SOP/SSOP
24Skinny DIP/SOP
8-1
Chapter 8. GMS37XXXT
Pin Description
Pin
I/O
Function
VDD
-
Connected to 2.2~ 3.6V power supply
GND
-
Connected to 0V power supply.
4-bit input port with built in pull-up resistor.
STOP mode is released by "L" input of each pin.
Especially, K3 is the input pin for VPP.
Input
K0 ~ K3
For programming K3 pin receives 12.5V(programming voltage).
Each can be set and reset independently.
D0 ~ D9
R0 ~ R3
Output
I/O
The output is the structure of N-channel-open-drain.
4-bit I/O port. (Input mode is set only when each of them output
"H".)
In outputting, each can be set and reset independently(or at once.)
The output is in the form of C-MOS.
STOP mode is released by "L" input of each pin.
Oscillator input. Input to the oscillator circuit and connection point for
ceramic resonator.
OSC1
Input
Internal capacitors available at kHz version.
A feedback resistor is internally connected between this pin and
OSC2.
Connect a resonator between this pin and OSC1.
OSC2
Output
Output
High current output port
The output is in the form of C-MOS.
The state of large current on is “ H “
REMOUT
8-2
Chapter 8. GMS37XXXT
STOP Operation
Stop mode can be achieved by STOP instructions.
In stop mode :
1. Oscillator is stopped, the operating current is low.
2. Watch dog timer is reset, D0~D3 output is "L"and REMOUT output is ”L"
3. Part other than WDT, D0~D3 output and REMOUT output have a value before
come into stop mode.
Stop mode is released when one of K or R input is going to "L".
1. State of D0~D3 output and REMOUT output is return to state of before stop mode
is achieved.
2. After 210 System clock time for stable oscillating, first instruction start to operate.
3. In return to normal operation, WDT is counted from zero again.
But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction
is same to NOP instruction.
8-3
Chapter 8. GMS37XXXT
Electrical Characteristics
Absolute maximum ratings (Ta = 25 )
Parameter
Symbol
Max. rating
Unit
Supply Voltage
VDD
VPP
PD
-0.3 ~ 5.0
-0.3 ~ 13.5
700 *
V
V
Programming Voltage
Power dissipation
Storage temperature range
Input voltage
mW
Tstg
VIN
-55 ~ 125
-0.3 ~ VDD+0.3
-0.3 ~ VDD+0.3
V
V
Output voltage
VOUT
* Thermal derating above 25
: 6mW per degree
rise in temperature.
Recommended operating condition
Parameter
Symbol
Condition
Rating
Unit
Supply Voltage
VDD
300kHz ~ 4MHz
-
2.2 ~ 3.6
V
Operating temperature
Topr
-20 ~ +70
8-4
Chapter 8. GMS37XXXT
Electrical characteristics (Ta=25 , VDD= 3V)
Limits
Parameter
Symbol
Unit
Condition
Min. Typ. Max.
1
uA
VI=VDD
IIH
-
-
Input H current
RPU1
RPU2
VI=GND
K Pull-up Resistance
R Pull-up Resistance
300
300
3.0
-
70
70
140
140
1.0
-
VI=GND, Output off
RFD
VIH1
VIL1
Feedback Resistance
VOSC1=GND, VOSC2=VDD
-
0.3
2.1
V
V
V
K, R input H voltage
K, R input L voltage
0.9
0.4
-
-
-
-
*1
IOL2=3mA
VOL2
0.15
D. R output L voltage
OSC2 output L voltage
0.9
-
IOL3=40uA (455kHz)
VOL3
VOH3
-
0.4
2.5
V
V
=150uA (4MHz)
IOH3= -40uA (455kHz)
= -150uA (4Mhz)
2.1
OSC2 output H voltage
*2
REMOUT output L current
REMOUT output H current
IOL1
4
mA
mA
VOL1=0.4V
1
2.2
-15
*3
-30
IOH1
-5
VOH1=2V
D, R output leakage
current
IOLK2
ISTP
1
uA
-
-
VOUT=VDD, Output off
1
uA
mA
mA
At STOP mode
fOSC=455KHz
fOSC=4MHz
-
-
-
-
Current on STOP mode
Operating supply current 1
Operating supply current 2
*4
1.5
3.0
IDD1
0.8
1.0
*4
IDD2
fOSC/6
1000
4
kHz
kHz version
MHz version
fOSC
fOSC
300
2.4
-
-
System
clock
frequency
MHz
fOSC/48
*1 Refer to Fig.8-1 < IOL2 vs. VOL2 Graph>
*2 Refer to Fig.8-2 < IOL1 vs. VOL1 Graph>
*3 Refer to Fig.8-3 < IOH1 vs. VOH1 Graph>
*4 IDD1, IDD2, is measured at RESET mode.
8-5
Chapter 8. GMS37XXXT
Fig 8-1. IOL2 vs. VOL2 Graph. ( D, R, OD6 Port )
Fig 8-2. IOL1 vs VOL1 Graph (REMOUT Port)
8-6
Chapter 8. GMS37XXXT
Fig 8-3. IOH1 vs VOH1 Graph (REMOUT Port)
8-7
GMS36XXX
1
2
3
4
5
6
7
8
9
GMS37XXX
PACKAGE DIMENSIONS
FUNCTIONAL DESCRIPTION
INSTRUCTION
APPLICATION
GMS36XXXT
GMS37XXXT
EPROM
Chapter 9. EPROM
CHAPTER 9. EPROM
MODE Define
Item
Device operation
Exact User pgm
Mode setting
K3~ K0 = 0 ~ 3V
K1~0=01/10
Vcc=3V
User mode
Address in, Data out
Vcc=5.5V
EPROM read mode
Address in, Data in
Data out
Vcc=5.5V
1Byte PGM Write & Verify
K1~0=01/10
K2 = Vcc
K2 = 0V
K3 =12.5V
Lock bit write
K1~0=01/00
K1~0=01/01
Lock bit Write mode
Lock bit Read mode
Vcc=5.5V,
(Default : unlock)
Lock bit out (to D5 port)
System reset before
all test
Reset mode
-
-
* Mode setting (K1~0=01/10) means the serial input by 2bits.
Port Define for GMS36XXXT
9-1
Chapter 9. EPROM
Port Define for GMS37XXXT
9-2
Chapter 9. EPROM
AC / DC Timing Requirements for Program / Read Mode (Ta = 25
)
9-3
Chapter 9. EPROM
Program / Verify Timing Diagrams In kHz Version.
1) EPROM Write & Verify Mode (1Byte)
#. Note :
1. Internal system is reset at VPP = 12.5V and K2=`Low`
2. The reset release (K2=`High`) must be set within OSC1 = `Low` state.
(From this time, OSC1 clock is counted.)
3. The Data will be inputted from the 19th rising edge of OSC1.
4. If not written during 10 times repeats (120us), repeat the 5 times until all is written.
5. For device verify. If you set Lock bit, output data is always `0F`h.
9-4
Chapter 9. EPROM
2) EPROM Read Mode (1Byte)
#. Note :
1. Internal system is reset at VPP = 12.5V and K2=`Low`
2. The reset release (K2=`High`) must be set within OSC1 = `Low` state.
(From this time, OSC1 clock is counted.)
3. The Data will be inputted from the 19th rising edge of OSC1.
4. For device verify. If you set Lock bit, output data is always `0F`h.
9-5
Chapter 9. EPROM
3) Lock Bit Write Mode
#. Note :
1. Internal system is reset at VPP = 12.5V and K2=`Low`
2. The reset release (K2=`High`) must be set within OSC1 = `Low` state.
(From this time, OSC1 clock is counted.)
3. If not written during 10 times repeats (120us), repeat the 5 times until all is written.
9-6
Chapter 9. EPROM
4) Lock Bit Read Mode
#. Note :
1. Internal system is reset at VPP = 12.5V and K2=`Low`
2. The reset release (K2=`High`) must be set within OSC1 = `Low` state.
(From this time, OSC1 clock is counted.)
3. Lock data is outputted from D5 port.
If you set Lock bit, the output data of D5 is always `H`.
9-7
Chapter 9. EPROM
Program / Verify Timing Diagrams In MHz Version.
1) EPROM Write & Verify Mode (1Byte)
#. Note :
1. Internal system is reset at VPP = 12.5V and K2=`Low`
2. OSC1 is made of a block of 8 x Tp clock.
3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck.
4. If not written during 10 times repeats (120us), repeat the 5 times until all is written.
5. For device verify. If you set Lock bit, output data is always `0F`h.
9-8
Chapter 9. EPROM
- Continue -
9-9
Chapter 9. EPROM
2) EPROM Read Mode
#. Note :
1. Internal system is reset at VPP = 12.5V and K2=`Low`
2. OSC1 is made of a block of 8 x Tp clock.
3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck.
4. For device verify. If you set Lock bit, output data is always `0F`h.
9-10
Chapter 9. EPROM
- Continue -
9-11
Chapter 9. EPROM
3) Lock Bit Write Mode
#. Note :
1. Internal system is reset at VPP = 12.5V and K2=`Low`
2. OSC1 is made of a block of 8 x Tp clock.
3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck.
4. If not written during 10 times repeats(120us), repeat the 5 times until all is written.
9-12
Chapter 9. EPROM
4) Lock Bit Read Mode
#. Note :
1. Internal system is reset at VPP = 12.5V and K2=`Low`
2. OSC1 is made of a block of 8 x Tp clock.
3. From this time when the reset is released (K2=`High`) , OSC1 clock is counted by 1-bolck.
4. Lock data is outputted from D5 port.
If you set Lock bit, the output data of D5 is always `H`.
9-13
Chapter 9. EPROM
Caution when programming
Writing should be done at the defined voltage and timing. In case of EPROM mode, programming
voltage is 12.5V. More than defined voltage can give device so great damage to destroy it.
Before writing you had better ascertain the characteristics of socket and socket adapter of EPROM
writer. It can happen to write error when you touch socket adapter or device. We recommend below
flow to improve reliability after writing.
Timing Flowchart for Eprom Program / Verify.
9-14
Chapter 9. EPROM
Timing Flowchart for Lock Bit Program / Verify.
9-15
MASK ORDER & VERIFICATION SHEET
GMS3
-R
1. Customer Information
Company Name
Tel:
Fax:
Name & Signature
Order Date
2. Device Information
E-Mail
(
)
16 SOP (150mil)
16 SOP (300mil)
File Name
Package
Mask Data
16 DIP
20 DIP
20 SOP
24 SOP
20 SSOP
24 DIP
. RHX
. DMP
Check Sum
@27C256
3. Mask Option
Inclusion of
Pull-up
Register
Port R0* R1* R2* R3*
Y/N
Port K0 K1 K2 K3 R0* R1* R2* R3*
Y/N
Release of
Stop mode
Status of
D port while
Stop mode
System
Clock
Selection
Inclusion of
condensor
for Osc.
Port D0 D1 D2 D3 D4 D5 D6 D7**D8**D9**
a/b
focs / 6
Y/N
fosc / 48
1. Don’t use WDTR instruction in subroutine.
2. Use Br $ at start (except 0 page ) , end and
unused address in every page.
4. If you use fosc/6, we recommend inclusion of condensor and
fosc/48, no inclusion of condensor
3. a: State of “ L” forcibly, b: Remain the state just before
stop instruction. You must select “a” option when you use
Dport as key application.
* : Marked port is not available for GMS36/37004
** : Marked port is not available for GMS36/37004/112
5. D6 port is available for GMS37004/112 but
not available for GMS36004/112
4. Marking Specification
Standard Marking
User Marking
HYNIX
User LOGO
R
YWW
R
YWW
5. Delivery Schedule
Date
Quantity
Confirmation
.
.
.
.
Mask Sample
Risk Order
pcs
pcs
6. ROM CODE Verification
HYNIX Semiconductor Inc. write in below
Verification Date :
Customer write in below
Approval Date :
.
.
Please confirm our verification data.
I agree with your verification data and confirm
you to make mask set.
Check Sum :
TEL :82-431-270-4078 FAX :82-431-270-4075
@27c256
TEL :
FAX :
Company Name :
Name &
Signature
HYNIX Semiconductor Inc.
MCU APPLICATION TEAM
Section Name
Signature
:
:
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