GMS90C320Q40中文资料_数据手册_规格书

HYNIX SEMICONDUCTOR INC.

8-BIT SINGLE-CHIP MICROCONTROLLERS

GMS90C320

User’s Manual (Ver. 1.2)

REVISION HISTORY

VERSION 1.2 (Oct. 2000) This book

Correct the pin number of 44-MQFP package type on page 6.

VERSION 1.1 (Oct. 1999) Before version

Version 1.2

Published by

MCU Application Team

Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Repre-

sentatives listed at address directory.

Hynix semiconductor reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconductor is in no

way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

GMS90C320

Device Naming Structure

H(G)MS90X320 XXXX

Frequency

Blank: 24MHz

40:

40MHz

50:

50MHz

Package Type

Blank: 40PDIP

PL:

Q:

44PLCC

44MQFP

Enhanced ROM-less version

Operating Voltage

C: Normal voltage

L: Low voltage

OCT. 2000 Ver 1.2

GMS90C320

GMS90C320 ordering information

Operating

Device Name

Voltage (V)

ROM size

(bytes)

RAM size

(bytes)

Operating max.

Frequency (MHz)

Package Type

40PDIP

GMS90C320 40

GMS90C320 PL40

GMS90C320 Q40

4.25~5.5

ROM-less

256

40

50

24

44PLCC

44MQFP

GMS90C320 50

GMS90C320 PL50

GMS90C320 Q50

40PDIP

44PLCC

44MQFP

GMS90L320

GMS90L320 PL

GMS90L320 Q

40PDIP

44PLCC

44MQFP

2.7~5.5

OCT. 2000 Ver 1.2

GMS90C320

GMS90C320/L320

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

ROM-less Version for 90C52

Operating

Frequency (MHz)

Operating Voltage (V)

Device Name

ROM

RAM

4.25~5.5

2.7~5.5

GMS90C320

GMS90L320

ROM-less

256 × 8bit

40/50

24

Features

• Fully compatible to standard MCS-51 microcontroller

• Versions for 40/50 MHz operating frequency

• Low voltage version for 24MHz operating frequency

• 256 bytes of on-chip data RAM

• 64K external program memory space

• 64K external data memory space

• Four 8-bit ports

• Three 16-bit Timers/Counters (Timer 2 with up/down counter feature)

• USART

• Six interrupt sources, two priority levels

• Power saving Idle and power down mode

• 2.7Volt low voltage version available

• P-DIP-40, P-LCC-44, P-MQFP-44 package

RAM

I/O

PORT0

256 x 8

PORT1

T0

8-BIT

CPU

T2

USART

T1

I/O

PORT2

PORT3

ROM-less

The GMS90C320 described in this document is compatible with the standard 80C32 can be used for all present standard

80C32 applications.

OCT. 2000 Ver 1.2

1

GMS90C320

44-PLCC Pin Configuration

(top view)

(P-LCC-44)

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

P1.5

7

39

38

37

36

35

34

33

32

31

30

29

P1.6

P1.7

8

9

RESET

RxD/P3.0

N.C.

10

11

12

13

14

15

16

17

N.C.

ALE

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

2

OCT. 2000 Ver 1.2

GMS90C320

40-PDIP Pin Configuration

(top view)

(P-DIP-40)

T2/P1.0

T2EX/P1.1

P1.2

1

2

V_CC

40

P0.0/AD0

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

3

P1.3

4

5

P1.4

6

P1.5

7

P1.6

8

P1.7

9

RESET

RxD/P3.0

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

WR/P3.6

RD/P3.7

XTAL2

XTAL1

V_SS

10

11

12

13

14

15

16

17

18

19

20

ALE

PSEN

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P2.0/A8

OCT. 2000 Ver 1.2

3

GMS90C320

44-PLCC Pin Configuration

(top view)

(P-MQFP-44)

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

P1.5

P1.6

1

2

33

32

31

30

29

28

27

26

25

24

23

P1.7

3

RESET

RxD/P3.0

N.C.

4

5

N.C.

6

ALE

7

TxD/P3.1

INT0/P3.2

INT1/P3.3

T0/P3.4

T1/P3.5

PSEN

8

P2.7/A15

P2.6/A14

P2.5/A13

9

10

11

4

OCT. 2000 Ver 1.2

GMS90C320

V_CCV_SS

Port 0

8-bit Digital I/O

XTAL1

XTAL2

Port 1

8-bit Digital I/O

RESET

Port 2

8-bit Digital I/O

EA

ALE

Port 3

8-bit Digital I/O

PSEN

Logic Symbol

OCT. 2000 Ver 1.2

5

GMS90C320

Pin Definitions and functions

Pin Number

Input/

Symbol

Function

P-MQFP-

44

Output

P-LCC-44

P-DIP-40

P1.0-P1.7

2-9

1-8

40-44,

1-3

I/O

Port1

is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins

that have 1s written to them are pulled high by the internal pull-up

resistors and can be used as inputs. As inputs, port 1 pins that are

externally pulled low will source current because of the pulls-ups

(I_IL, in the DC characteristics). Pins P1.0 and P1.1 also. Port 1

also receives the low-order address byte during program memory

verification. Port1 also serves alternate functions of Timer 2.

2

3

1

2

40

41

P1.0/T2: Timer/counter 2 external count input

P1.1/T2EX: Timer/counter 2 trigger input

P3.0-P3.7

11,13-

19

10-17

5, 7-

13

I/O

Port 3

is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins

that have 1s written to them are pulled high by the internal pull-up

resistors, and in that state they can be used as inputs. As inputs,

port 3 pins being externally pulled low will source current (I_IL, in

the DC characteristics) because of internal pulls-up resistors. Port

3 also serves the special features of the 80C51 family, as listed

below.

11

13

10

11

5

7

P3.0/RxD

receiver data input (asynchronous) or data input

output (synchronous) of the serial interface 0

P3.1 / TxD

transmitter data output (asynchronous) or clock

output (synchronous) of the serial interface 0

14

15

16

17

18

12

13

14

15

16

8

P3.2 / INT0 interrupt 0 input / timer 0 gate control

P3.3 / INT1 interrupt 1 input / timer 1 gate control

9

10

11

12

P3.4 / T0

P3.5 / T1

P3.6 / WR

counter 0 input

counter 1 input

the write control signal latches the data byte from

port 0 into the external data memory

19

20

21

17

18

19

13

14

15

P3.7 / RD

the read control signal enables the external data

memory to port 0

XTAL2

XTAL1

O

I

XTAL2

Output of the inverting oscillator amplifier

XTAL1

Input to the inverting oscillator amplifier and input to the internal

clock generator circuits.

To drive the device from an external clock source, XTAL1 should

be driven, while XTAL2 is left unconnected. There are no require-

ments on the duty cycle of the external clock signal, since the

input to the internal clocking circuitry is divided down by a divide-

by-two flip-flop. Minimum and maximum high and low times as

well as rise fall times specified in the AC characteristics must be

observed.

6

OCT. 2000 Ver 1.2

GMS90C320

Pin Number

P-DIP-40

Input/

Output

Symbol

Function

P-MQFP-

44

P-LCC-44

P2.0-P2.7

24-31

21-28

18-25

I/O

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal

pull-up resistors and can be used as inputs. As inputs, port 2 pins

that are externally pulled low will source current because of the

pulls-ups (I_IL, in the DC characteristics). Port 2 emits the high-

order address byte during fetches from external program memory

and during accesses to external data memory that use 16-bit

addresses (MOVX @DPTR). In this application it uses strong

internal pull-ups when emitting 1s. During accesses to external

data memory that use 8-bit addresses (MOVX @Ri), port 2 emits

the contents of the P2 special function register.

PSEN

32

29

26

O

The Program Store Enable

The read strobe to external program memory when the device is

executing code from the external program memory. PSEN is acti-

vated twice each machine cycle, except that two PSEN activation

are skipped during each access to external data memory. PSEN

is not activated during fetches from internal program memory.

RESET

ALE

10

33

9

4

I

RESET

A high level on this pin for two machine cycles while the oscillator

is running resets the device. An internal diffused resistor to V_SS

permits power-on reset using only an external capacitor to V_CC

.

30

27

O

The Address Latch Enable

Output pulse for latching the low byte of the address during an

access to external memory. In normal operation, ALE is emitted

at a constant rate of 1/6 the oscillator frequency, and can be used

for external timing or clocking. Note that one ALE pulse is skipped

during each access to external data memory.

EA

35

31

29

I

External Access Enable

EA must be external held low to enable the device to fetch code

from external program memory locations 0000_Hto FFFF_H. If EA is

held high, the device executes from internal program memory

unless the program counter contains an address greater than its

internal memory size.

P0.0-P0.7

43-36

39-32

37-30

I/O

Port 0

Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that

have 1s written to them float and can be used as high-impedance

inputs. Port 0 is also the multiplexed low-order address and data

bus during accesses to external program and data memory. In

this application it uses strong internal pull-ups when emitting 1s.

Port 0 also outputs the code bytes during program verification in

the GMS97C5x. External pull-up resistors are required during

program verification.

V_SS

V_{C C}

22

44

20

40

16

38

-

Circuit ground potential

Supply terminal for all operating modes

No connection

N.C.

1,12,

23,34

6,17,

28,39

-

OCT. 2000 Ver 1.2

7

GMS90C320

Function Description

The GMS90 series is fully compatible to the standard 8051 microcontroller family.

It is compatible with the standard 80C32. While maintaining all architectural and operational characteristics of the standard

80C32, the GMS90C320 incorporates some enhancements in the Timer 2 unit.

Figure 1 shows a block diagram of the GMS90C320

RAM

256 x 8

XTAL1

OSC & Timing

XTAL2

CPU

Timer 0

RESET

Port 0

8-bit Digital I/O

Port 0

Port 1

Port 2

Port 3

ALE

Timer 1

Port 1

8-bit Digital I/O

PSEN

EA

Timer 2

Port 2

8-bit Digital I/O

Interrupt Unit

Serial Channel

Port 3

8-bit Digital I/O

Figure 1 Block Diagram of the GMS90C320

8

OCT. 2000 Ver 1.2

GMS90C320

CPU

The GMS90C320 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD

arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set con-

sisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are

executed in 1.0µs.

Special Function Register PSW

MSB

7

LSB

0

Bit No.

6

5

4

3

2

1

Addr. D0_H

CY

AC

F0

RS1

RS2

OV

F1

P

PSW

Bit

Function

CY

AC

F0

Carry Flag

Auxiliary Carry Flag (for BCD operation)

General Purpose Flag

Register Bank select control bits

Bank 0 selected, data address 00_H-07_H

Bank 1 selected, data address 08_H-0F_H

Bank 2 selected, data address 10_H-17_H

Bank 3 selected, data address 18_H-1F_H

RS1

RS0

0

1

0

1

0

1

OV

F1

P

Overflow Flag

General Purpose Flag

Parity Flag

Set/cleared by hardware each instruction cycle to indicate an odd/

even number of “one” bits in the accumulator, i.e. even parity.

Reset value of PSW is 00_{H .}

OCT. 2000 Ver 1.2

9

GMS90C320

Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside in the special function register

area.

The 27 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other

on-chip peripherals. There are also 128 directly addressable bits within the SFR area.

All SFRs are listed in Table 1, Table 2, and Table 3.

In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the

functional blocks of the GMS90C320. Table 3 illustrates the contents of the SFRs.

Table 1

Special Function Registers in Numeric Order of their Addresses

Contents after

Reset

Contents after

Reset

Address

Register

Address

Register

FF_H

07_H

00_H

FF_H

80_H

81_H

82_H

83_H

84_H

85_H

86_H

87_H

A0_H

A1_H

A2_H

A3_H

A4_H

A5_H

A6_H

A7_H

P0¹⁾

SP

DPL

P2¹⁾

_H2)

XX

reserved

2)

XX_H

2)

DPH

_H2)

XX

reserved

PCON

_B2)

0XXX0000

_B2)

0X000000

88_H

89_H

8A_H

8B_H

8C_H

8D_H

8E_H

8F_H

00_H

A8_H

A9_H

AA_H

AB_H

AC_H

AD_H

AE_H

AF_H

TCON¹⁾

TMOD

TL0

TL1

TH0

TH1

reserved

IE¹⁾

_H2)

XX

reserved

2)

XX_H

2)

XX_H

2)

XX_H

P1¹⁾

FF_H

90_H

91_H

92_H

93_H

94_H

95_H

96_H

97_H

FF_H

00_H

B0_H

B1_H

B2_H

B3_H

B4_H

B5_H

B6_H

B7_H

P3¹⁾

_H2)

XX

reserved

2)

XX_H

2)

XX_H

2)

_B2)

XX000000

00_H

98_H

99_H

9A_H

9B_H

9C_H

9D_H

9E_H

9F_H

B8_H

B9_H

BA_H

BB_H

BC_H

BD_H

BE_H

BF_H

SCON¹⁾

SBUF

IP¹⁾

_H2)

XX

_H2)

XX

reserved

2)

XX_H

reserved

XX_H

2)

1)

2)

: Bit-addressable Special Function Register

: X means that the value is indeterminate and the location is reserved

10

OCT. 2000 Ver 1.2

GMS90C320

Table 1

Special Function Registers in numeric order of their addresses (cont’d)

Contents after

Reset

Address

Register

Address

Register

Reset

2)

C0_H

C1_H

C2_H

C3_H

C4_H

C5_H

C6_H

C7_H

XX_H

E0_H

E1_H

E2_H

E3_H

E4_H

E5_H

E6_H

E7_H

00_H

reserved

ACC¹⁾

2)

XX_H

reserved

2)

XX_H

2)

C8_H

C9_H

CA_H

CB_H

CC_H

CD_H

CE_H

CF_H

00_H

XXXXXXX0_B

00_H

E8_H

E9_H

EA_H

EB_H

EC_H

ED_H

EE_H

EF_H

XX_H

T2CON¹⁾

T2MOD

RC2L

RC2H

TL2

TH2

reserved

2)

00_H

2)

XX_H

2)

XX_H

D0_H

D1_H

D2_H

D3_H

D4_H

D5_H

D6_H

D7_H

00_H

F0_H

F1_H

F2_H

F3_H

F4_H

F5_H

F6_H

F7_H

00_H

PSW¹⁾

B¹⁾

2)

XX_H

reserved

2)

XX_H

2)

XX_H

2)

D8_H

D9_H

DA_H

DB_H

DC_H

DD_H

DE_H

DF_H

XX_H

F8_H

F9_H

FA_H

FB_H

FC_H

FD_H

FE_H

FF_H

XX_H

reserved

2)

1)

2)

: Bit-addressable Special Function Register

: X means that the value is indeterminate and the location is reserved

OCT. 2000 Ver 1.2

11

GMS90C320

Table 2

Special Function Registers - Functional Blocks

Content

after Reset

Block

Symbol

Name

Address

1)

CPU

ACC

B

DPH

DPL

PSW

SP

Accumulator

B-Register

Data Pointer, High Byte

Data Pointer, Low Byte

Program Status Word Register

Stack Pointer

E0_H

F0_H

83_H

82_H

D0_H

00_H

07_H

1)

81_H

1)

2)

Interrupt System

Ports

IE

IP

Interrupt Enable Register

Interrupt Priority Register

A8_H

B8_H

0X000000_B

XX000000_B

2)

1)

P0

P1

P2

P3

Port 0

Port 1

Port 2

Port 3

80_H

90_H

A0_H

B0_H

FF_H

1)

2)

Serial Channels

Timer 0 / Timer 1

PCON

SBUF

SCON

Power Control Register

Serial Channel Buffer Register

Serial Channel 0 Control Register

87_H

99_H

98_H

0XXX0000_B

3)

XX_H

00_H

1)

TCON

TH0

TH1

TL0

TL1

Timer 0/1 Control Register

Timer 0, High Byte

Timer 1, High Byte

Timer 0, Low Byte

Timer 1, Low Byte

Timer Mode Register

88_H

00_H

8C_H

8D_H

8A_H

8B_H

89_H

TMOD

1)

Timer 2

T2CON

T2MOD

RC2H

RC2L

TH2

Timer 2 Control Register

Timer 2 Mode Register

Timer 2 Reload Capture Register, High Byte

Timer 2 Reload Capture Register, Low Byte

Timer 2, High Byte

C8_H

C9_H

00_H

XXXXXXX0_B

2)

CB_H

CA_H

CD_H

CC_H

00_H

TL2

Timer 2, Low Byte

2)

Power Saving

Modes

PCON

Power Control Register

87_H

0XXX0000_B

1)

2)

3)

Bit-addressable Special Function Registers

This special function register is listed repeatedly since some bits of it also belong to other functional blocks

X means that the value is indeterminate and the location is reserved

12

OCT. 2000 Ver 1.2

GMS90C320

Table 3

Contents of SFRs, SFRs in Numeric Order

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

80_H

Register

P0

81_H

82_H

83_H

87_H

88_H

89_H

8A_H

8B_H

8C_H

8D_H

90_H

98_H

99_H

A0_H

A8_H

B0_H

B8_H

C8_H

C9_H

SP

DPL

DPH

PCON

TCON

TMOD

TL0

SMOD

TF1

-

GF1

IE1

GF0

IT1

PDE

IE0

IDLE

IT0

TR1

C/T

TF0

M1

TR0

M0

GATE

C/T

M1

M0

TL1

TH0

TH1

P1

SCON

SBUF

P2

SM0

EA

SM1

SM2

ET2

REN

TB8

RB8

EX1

TI

RI

IE

-

ES

PS

ET1

PT1

ET0

EX0

P3

IP

-

TF2

-

EXF2

-

PT2

RCLK

-

PX1

TR2

-

PT0

C/T2

-

PX0

T2CON

T2MOD

TCLK EXEN2

CP/RL2

DCEN

-

SFR bit and byte addressable

SFR not bit addressable

-

This bit location is reserved.

OCT. 2000 Ver 1.2

13

GMS90C320

Table 3

Contents of SFRs, SFRs in Numeric Order (cont’d)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

CA_H

Register

RC2L

CB_H

CC_H

CD_H

D0_H

E0_H

F0_H

RC2H

TL2

TH2

PSW

ACC

B

CY

AC

F0

RS1

RS0

OV

F1

P

SFR bit and byte addressable

SFR not bit addressable

-

This bit location is reserved.

14

OCT. 2000 Ver 1.2

GMS90C320

Timer / Counter 0 and 1

Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:

Table 4

Timer/Counter 0 and 1 Operating Modes

TMOD

Input Clock

Mode

Description

External

(Max.)

GATE

C/T

M1

M0

Internal

0

1

2

3

8-bit timer/counter with a

divide-by-32 prescaler

ƒ_OSC

-------------------

12 × 32

ƒ_OSC

-------------------

24 × 32

X

0

16-bit timer/counter

ƒ_OSC

---------------

12

ƒ_OSC

---------------

24

X

0

1

0

8-bit timer/counter with 8-bit

autoreload

ƒ_OSC

---------------

12

ƒ_OSC

---------------

24

Timer/counter 0 used as one

8-bit timer/counter and one 8-

bit timer

ƒ_OSC

---------------

12

ƒ_OSC

---------------

24

X

1

Timer 1 stops

In the “timer” function (C/T = “0”) the register is incremented every machine cycle. Therefore the count rate is ƒ_OSC⁄ 12 .

In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin

(P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is ƒ_OSC⁄ 24 . External inputs

INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements.

Figure 2 illustrates the input clock logic.

f_OSC

ƒ_OSC⁄ 12

÷12

C/T

TMOD

0

Timer 0/1

Input Clock

P3.4/T0

P3.5/T1

max. f_OSC/24

1

Control

TR 0/1

TCON

GATE

TMOD

P3.2/INT0

P3.3/INT1

Figure 2 Timer/Counter 0 and 1 Input Clock Logic

OCT. 2000 Ver 1.2

15

GMS90C320

Timer 2

Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which

is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5.

Table 5

Timer/Counter 2 Operating Modes

T2CON

Input Clock

T2MO

D

DECN

T2CON P1.1

Mode

Remarks

RxCLK

or

TxCLK

CP/

External

EXEN

T2EX

TR2

Internal

(P1.0/T2)

RL2

16-bit Auto-

reload

0

1

0

1

0

1

X

↓

0

1

reload upon overflow

reload trigger (falling edge)

Down counting

ƒ_OSC

---------------

12

ƒ_OSC

24

---------------

max.

Up counting

16-bit

Capture

0

1

X

0

1

X

16-bit Timer/Counter (only

up-counting)

capture

ƒ_OSC

---------------

12

ƒ_OSC

---------------

24

↓

TH1, TL2 → RC2H, RC2L

Baud Rate

Generator

1

X

1

X

0

1

X

no overflow interrupt request

(TF2)

extra external interrupt

(“Timer 2”)

ƒ_OSC

---------------

12

ƒ_OSC

---------------

24

↓

off

X

0

X

Timer 2 stops

-

1Note: ↓ =

falling edge

16

OCT. 2000 Ver 1.2

GMS90C320

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated

in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.

Table 6

USART Operating Modes

SCON

Mode

0

Baudrate

Description

SM0

SM1

0

Serial data enters and exits through RxD.

TxD outputs the shift clock.

8-bit are transmitted/received (LSB first)

ƒ_OSC

---------------

12

1

2

3

0

1

0

1

Timer 1/2 overflow rate

8-bit UART

10 bits are transmitted (through TxD) or

received (RxD)

9-bit UART

11 bits are transmitted (through TxD) or

received (RxD)

ƒ_OSC

---------------

32

ƒ_OSC

---------------

64

or

Timer 1/2 overflow rate

9-bit UART

Like mode 2 except the variable baud rate

Table 7

Formulas for Calculating Baud rates

Baud Rate

derived from

Interface Mode

Baud rate

Oscillator

0

ƒ_OSC

---------------

12

2

× ƒ

64

SMOD

2

OSC

------------------------------------------

Timer 1 (16-bit timer)

(8-bit timer with 8-bit autore-

load)

1, 3

SMOD

× timer 1 overflow raet

2

--------------------------------------------------------------------------------

32

1, 3

× ƒ

SMOD

2

×

OSC

----------------------------------------------------------

× (

)

32 12 256 – TH1

Timer 2

ƒ_OSC

------------------------------------------------------------------------------

× [ )]

– (

32 65536 RC2H,RC2L

OCT. 2000 Ver 1.2

17

GMS90C320

Interrupt System

The GMS90C320 provides 6 interrupt sources with two priority levels. Figure 3 gives a general overview of the interrupt

sources and illustrates the request and control flags.

High Priority

Low Priority

Timer 0 Overflow

TF0

TCON.5

ET0

IE.1

PT0

IP.1

Timer 1 Overflow

TF1

TCON.7

ET1

IE.3

PT1

IP.3

Timer 2 Overflow

TF2

T2CON.7

P1.1/

T2EX

EXF2

T2CON.6

ET2

IE.5

PT2

IP.5

EXEN2

T2CON.3

RI

SCON.0

USART

TI

SCON.1

ES

PS

IE.4

IP.4

P3.2/

INT0

IE0

TCON.1

EX0

IE.0

IT0

PX0

IP.0

TCON.0

P3.3/

INT1

IE1

TCON.3

EX1

IE.2

EA

PX1

IP.2

IT1

IE.7

TCON.2

Figure 3

Interrupt Request Sources

18

OCT. 2000 Ver 1.2

GMS90C320

Table 8

Interrupt Sources and their Corresponding Interrupt Vectors

Source (Request Flags)

Vector

Vector Address

IE0

TF0

IE1

TF1

RI+TI

TF2+EXF2

External interrupt 0

Timer 0 interrupt

External interrupt 1

Timer 1 interrupt

Serial port interrupt

Timer 2 interrupt

0003_H

000B_H

0013_H

001B_H

0023_H

002B_H

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-

priority interrupt cannot be interrupted by any other interrupt source.

If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of

the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within

each priority level there is a second priority structure determined by the polling sequence as shown in Table 9.

Table 9

Interrupt Priority-Within-Level

Interrupt Source

External interrupt 0

Priority

IE0

High

TF0

IE1

TF1

RI+TI

TF2+EXF2

Timer 0 interrupt

External interrupt 1

Timer 1 interrupt

Serial port interrupt

Timer 2 interrupt

↓

Low

OCT. 2000 Ver 1.2

19

GMS90C320

Power Saving Modes

Two power down modes are available, the Idle Mode and Power Down Mode.

The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down

mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview

of the power saving modes.

Table 10

Power Saving Modes Overview

Mode

Entering Instruction

Example

Leaving by

Remarks

Idle mode

ORL PCON,#01H

- enabled interrupt

- Hardware Reset

CPU is gated off

CPU status registers maintain

their data.

Peripherals are active

Power-Down

Mode

ORL PCON,#02H

Hardware Reset

Oscillator is stopped, contents of

on-chip RAM and SFR’s are main-

tained (leaving Power Down Mode

means redefinition of SFR con-

tents).

In the Power Down mode of operation, V_{C C}can be reduced to minimize power consumption. It must be ensured, however,

that V_{C C}is not reduced before the Power Down mode is invoked, and that V_{C C}is restored to its normal operating level, before

the Power Down mode is terminated. The reset signal that terminates the Power Down Mode also restarts the oscillator. The

reset should not be activated before V_{C C}is restored to its normal operating level and must be held active long enough to allow

the oscillator to restart and stabilize (similar to power-on reset).

20

OCT. 2000 Ver 1.2

GMS90C320

Absolute Maximum Ratings

Ambient temperature under bias (T_A) .......................................................................................................-40 to + 85°C

Storage temperature (T_{S T})..........................................................................................................................-65 to + 150°C

Voltage on V_{C C}pins with respect to ground (V_{S S}).....................................................................................-0.5 V to 6.5 V

Voltage on any pin with respect to ground (V_SS).......................................................................................-0.5 to V_{C C}+ 0.5 V

Input current on any pin during overload condition..................................................................................-10 mA to + 10 mA

Absolute sum of all input currents during overload condition..................................................................| 100 mA |

Power dissipation.......................................................................................................................................TBD

Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is

a stress rating only and functional operation of the device at these or any other conditions above those indicated in the oper-

ational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may

affect device reliability. During overload conditions (V_IN> V_{C C}or V_IN< V_SS) the Voltage on V_CCpins with respect to ground (V_SS

)

must not exceed the values defined by the absolute maximum ratings.

OCT. 2000 Ver 1.2

21

GMS90C320

DC Characteristics

DC Characteristics for GMS90C320

V_{C C}= 5V + 10%, -15%; V_{S S}=0V; T_A= 0°C to 70°C

Limit Values

Max.

Parameter

Input low voltage

Symbol

Unit

Test Conditions

Min.

V_IL

0.2V_CC- 0.1

-0.5

V

-

(except EA, RESET)

Input low voltage (EA)

Input low voltage (RESET)

V_IL1

V_IL2

0.2V_CC- 0.3

0.2V_CC+ 0.1

-0.5

V

-

Input high voltage (except

XTAL1, EA, RESET)

V_IH

V_IH1

V_IH2

0.2V_CC+ 0.9

0.7V_CC

V_CC+ 0.5

V

-

Input high voltage to XTAL1

-

Input high voltage to EA,

RESET

0.6V_CC

Output low voltage

(ports 1, 2, 3)

I_{O L}= 100µA

I

_{O L}= 1.6mA¹⁾

I_{O L}= 3.5mA

0.3

0.45

1.0

V_{O L}

-

V

Output low voltage

(port 0, ALE, PSEN)

I_{O L}= 200µA

0.3

0.45

1.0

V_{O L1}

I

_{O L}= 3.2mA¹⁾

V

I_{O L}= 7.0mA

Output high voltage

(ports 1, 2, 3)

I_{O H}= -80µA

I_{O H}= -10µA

2.4

0.9V_CC

V_{O H}

-

Output high voltage

(port 0 in external bus mode,

ALE, PSEN)

I_{O H}= -800µA²⁾

I_{O H}= -80µA²⁾

2.4

0.9V_CC

V_{O H1}

Logic 0 input current

(ports 1, 2, 3)

I_IL

V_IN= 0.45V

V_IN= 2.0V

-10

-65

-50

µA

Logical 1-to-0 transition cur-

rent (ports 1, 2, 3)

I_TL

-650

Input leakage current

(port 0, EA)

I_LI

0.45 < V_IN< V_CC

-

±1

µA

Pin capacitance

C_IO

f_C=1MHz, T_A= 25°C

10

pF

Power supply current:

Active mode, 12MHz³⁾

Idle mode, 12MHz³⁾

Active mode, 24 MHz³⁾

Idle mode, 24MHz³⁾

Active mode, 40 MHz³⁾

Idle mode, 40 MHz³⁾

Active mode, 50 MHz³⁾

Idle mode, 50 MHz³⁾

Power Down Mode³⁾

I_CC

I_PD

-

16

7.5

26

V_{C C}= 5V⁴⁾

V_{C C}= 5V⁵⁾

V_{C C}= 5V⁴⁾

V_{C C}= 5V⁵⁾

V_{C C}= 5V⁴⁾

V_{C C}= 5V⁵⁾

V_{C C}= 5V⁴⁾

V_{C C}= 5V⁵⁾

V_{C C}= 5.5V⁶⁾

mA

µA

13.5

44

18

55

22.5

50

22

OCT. 2000 Ver 1.2

GMS90C320

1)

Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_{O L}of ALE and port 3. The

noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions

during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE line may

exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-

trigger strobe input.

2)

3)

Capacitive loading on ports 0 and 2 may cause the V_OHon ALE and PSEN to momentarily fall below the 0.9V_{C C}specification

when the address lines are stabilizing.

I_CC

at other frequencies is given by:

m ax

active mode: I_{C C}= 1.0 × ƒ_{O SC}+ 3.16

idle mode: I_{C C}= 0.37 × ƒ_{O SC}+ 3.63

where ƒ_{O SC}is the oscillator frequency in MHz. I_CCvalues are given in mA and measured at V_{C C}= 5V.

4)

I_CC(active mode) is measured with:

XTAL1 driven with t_CLCH, t_CHCL= 5ns, V_IL= V_SS+ 0.5V, V_IH= V_CC- 0.5V; XTAL2 = N.C.;

EA = Port 0 = RESET = V_CC; all other pins are disconnected. I_{C C}would be slightly higher if a crystal oscillator is used (appr.

1mA).

5)

6)

I_CC(Idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with t_CLCH, t_CHCL= 5ns, V_IL= V_SS+ 0.5V, V_IH= V_CC- 0.5V; XTAL2 = N.C.;

RESET = EA = V_SS; Port0 = V_CC; all other pins are disconnected;

I_PD(Power Down Mode) is measured under following conditions:

EA = Port 0 = V_CC; RESET = V_SS; XTAL2 = N.C.; XTAL1 = V_SS; all other pins are disconnected.

OCT. 2000 Ver 1.2

23

GMS90C320

DC Characteristics for GMS90L320

V_{C C}= 3.3V + 0.3V, -0.6V; V_{S S}=0V; T_A= 0°C to 70°C

Limit Values

Max.

Parameter

Input low voltage

Symbol

Unit

Test Conditions

Min.

-0.5

2.0

V_IL

V_IH

0.8

V

-

Input high voltage

V_CC+ 0.5

Output low voltage

(ports 1, 2, 3)

I_OL= 1.6mA¹⁾

I_OL= 100µA¹⁾

0.45

0.30

V_{O L}

V_{O L1}

V_{O H}

-

V

Output low voltage

(port 0, ALE, PSEN)

I_OL= 3.2mA¹⁾

I_OL= 200µA¹⁾

0.45

0.30

Output high voltage

(ports 1, 2, 3)

I_OH= -20µA

I_OH= -10µA

2.0

0.9V_CC

-

Output high voltage

(port 0 in external bus mode, ALE,

PSEN)

I_OH= -800µA²⁾

I_OH= -80µA²⁾

2.0

0.9V_CC

V_{O H1}

V

Logic 0 input current

(ports 1, 2, 3)

I_IL

I_TL

I_LI

V_IN= 0.45V

-1

-25

-

-50

-250

±1

µA

pF

Logical 1-to-0 transition current

(ports 1, 2, 3)

V_IN= 2.0V

Input leakage current

(port 0, EA)

0.45 < V_IN< V_CC

Pin capacitance

f_C= 1MHz

T_A= 25°C

C_IO

-

10

Power supply current:

Active mode, 16 MHz³⁾

Idle mode, 16MHz³⁾

Active mode, 24MHz³⁾

Idle mode, 24MHz³⁾

Power Down Mode³⁾

I_CC

I_PD

-

V_{C C}= 3.3V⁴⁾

V_{C C}= 3.3V⁵⁾

V_{C C}= 3.3V⁴⁾

V_{C C}= 3.3V⁵⁾

V_{C C}= 3.6V⁶⁾

10

5.25

16

8.25

10

mA

µA

24

OCT. 2000 Ver 1.2

GMS90C320

AC Characteristics

Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a ‘t’ (stand for time). The other characters, depending on

their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters

and what they stand for.

A: Address

T: Time

C: Clock

V: Valid

D: Input Data

W: WR signal

X: No longer a valid logic level

Z: Float

H: Logic level HIGH

I: Instruction (program memory contents)

L: Logic level LOW, or ALE

P: PSEN

For example,

Q: Output Data

R: RD signal

t_AVLL= Time from Address Valid to ALE Low

t_LLPL= Time from ALE Low to PSEN Low

OCT. 2000 Ver 1.2

25

GMS90C320

AC Characteristics for 12MHz version

V_CC= 5V:

V_CC= 5V + 10%, −15%; V_SS= 0V; T_A= 0°C to 70°C

(C_Lfor port 0. ALE and PSEN outputs = 100pF; C_Lfor all other outputs = 80pF)

V_CC= 3.3V:

Variable clock:

V_CC= 3.3V + 0.3V, −0.6V; V_SS= 0V; T_A= 0°C to 70°C

(C_Lfor port 0. ALE and PSEN outputs = 50pF; C_Lfor all other outputs = 50pF)

Vcc = 5V: 1/t_{CLC L}= 3.5 MHz to 12 MHz

Vcc = 3.3V: 1/t_{C LCL}= 1 MHz to 12 MHz

External Program Memory Characteristics

Variable Oscillator

1/t_CLCL= 3.5 to 12MHz

12 MHz Oscillator

Parameter

Symbol

Unit

Min.

127

43

-

Max.

Min.

Max.

t_LHLL

t_AVLL

t_LLAX

t_LLIV

-

2t_CLCL-40

-

ALE pulse width

ns

-

t_CLCL-40

-

Address setup to ALE

-

t_CLCL-40

-

Address hold after ALE

ALE low to valid instruction in

ALE to PSEN

233

-

4t_{CLC L}-100

t_LLPL

58

215

-

t_CLCL-25

-

t_PLPH

t_PLIV

t_PXIX

-

150

-

3t_CLCL-35

-

PSEN pulse width

-

3t_{CLC L}-100

PSEN to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address valid after PSEN

Address to valid instruction in

Address float to PSEN

0

-

1)

t_PXIZ

t_PXAV

t_AVIV

t_AZPL

-

63

-

t_CLCL-8

-

t_{CLC L}-20

1)

75

-

302

-

5t_{CLC L}-115

-

-10

1)

Interfacing the GMS90C320 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage

to port 0 Drivers.

26

OCT. 2000 Ver 1.2

GMS90C320

AC Characteristics for 12MHz version

External Data Memory Characteristics

Variable Oscillator

1/t_CLCL= 3.5 to 12MHz

12 MHz Oscillator

Parameter

Symbol

Unit

Min.

400

127

-

Max.

Min.

Max.

t_RLRH

t_{W LW H}

t_LLAX2

t_RLDV

t_{RHD X}

t_{RHD Z}

t_{LLD V}

-

6t_CLCL-100

-

RD pulse width

ns

-

6t_CLCL-100

-

WR pulse width

2t_{C LC L}-40

-

Address hold after ALE

RD to valid data in

252

-

5t_CLCL-165

0

-

Data hold after RD

-

97

517

585

300

-

2t_CLCL-70

Data float after RD

-

8t_CLCL-150

ALE to valid data in

t_{AVD V}

t_{LLW L}

t_{AVW L}

t_{W HLH}

t_{Q VW X}

t_{Q VW H}

t_{W HQ X}

t_RLAZ

-

9t_CLCL-165

Address to valid data in

ALE to WR or RD

200

203

43

33

433

33

-

3t_{C LC L}-50

4t_CLCL-130

t_CLCL-40

t_CLCL-50

7t_CLCL-150

t_CLCL-50

-

3t_{CLC L}+50

-

Address valid to WR or RD

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

123

-

t_{C LC L}+40

-

0

Address float after RD

Advance Information (12MHz)

External Clock Drive

Variable Oscillator

(Freq. = 3.5 to 12MHz)

Parameter

Symbol

Unit

Min.

Max.

Oscillator period (V_{C C}=5V)

Oscillator period (V_{C C}=3.3V)

t_CLCL

83.3

285.7

1

ns

t_{CHC X}

t_CLCX

t_CLCH

t_{CHC L}

20

-

t_{C LCL}- t_{C LC X}

t_{C LC L}- t_{CH CX}

20

ns

High time

Low time

Rise time

Fall time

-

20

OCT. 2000 Ver 1.2

27

GMS90C320

AC Characteristics for 16MHz version

V_CC= 5V:

V_CC= 5V + 10%, −15%; V_SS= 0V; T_A= 0°C to 70°C

(C_Lfor port 0. ALE and PSEN outputs = 100pF; C_Lfor all other outputs = 80pF)

V_CC= 3.3V:

Variable clock:

V_CC= 3.3V + 0.3V, −0.6V; V_SS= 0V; T_A= 0°C to 70°C

(C_Lfor port 0. ALE and PSEN outputs = 50pF; C_Lfor all other outputs = 50pF)

Vcc = 5V: 1/t_{CLC L}= 3.5 MHz to 16 MHz

Vcc = 3.3V: 1/t_{C LCL}= 1 MHz to 16 MHz

External Program Memory Characteristics

Variable Oscillator

1/t_CLCL= 3.5 to 16MHz

16 MHz Oscillator

Parameter

Symbol

Unit

Min.

85

23

43

-

Max.

Min.

Max.

t_LHLL

t_AVLL

t_LLAX

t_LLIV

-

2t_{C LC L}-40

-

ALE pulse width

ns

-

t_CLCL-40

-

Address setup to ALE

-

150

-

t_CLCL-40

-

Address hold after ALE

ALE low to valid instruction in

ALE to PSEN

-

4t_CLCL-100

t_LLPL

38

153

-

t_CLCL-25

-

t_PLPH

t_PLIV

t_PXIX

-

3t_{C LC L}-35

-

PSEN pulse width

88

-

3t_CLCL-100

PSEN to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address valid after PSEN

Address to valid instruction in

Address float to PSEN

0

-

1)

t_PXIZ

t_PXAV

t_AVIV

t_AZPL

-

43

-

t_{C LC L}-8

-

t_CLCL-20

1)

55

-

198

-

5t_CLCL-115

-

-10

1)

Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible. This limited bus contention will not cause

any damage to port 0 Drivers.

28

OCT. 2000 Ver 1.2

GMS90C320

AC Characteristics for 16MHz

External Data Memory Characteristics

Variable Oscillator

1/t_CLCL= 3.5 to 16MHz

16 MHz Oscillator

Parameter

Symbol

Unit

Min.

275

127

-

Max.

Min.

Max.

t_RLRH

t_{W LW H}

t_LLAX2

t_RLDV

t_{RHD X}

t_{RHD Z}

t_{LLD V}

-

6t_CLCL-100

-

RD pulse width

ns

-

6t_CLCL-100

-

WR pulse width

2t_{C LC L}-40

-

Address hold after ALE

RD to valid data in

183

-

5t_CLCL-130

0

-

Data hold after RD

-

75

350

398

238

-

2t_CLCL-50

Data float after RD

-

8t_CLCL-150

ALE to valid data in

t_{AVD V}

t_{LLW L}

t_{AVW L}

t_{W HLH}

t_{Q VW X}

t_{Q VW H}

t_{W HQ X}

t_RLAZ

-

9t_CLCL-165

Address to valid data in

ALE to WR or RD

138

120

28

13

288

23

-

3t_CLCL−50

4t_CLCL-130

3t_{CLC L}+50

-

Address valid to WR or RD

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

97

-

t

_CLCL−35

_CLCL−50

t_{C LC L}+35

t

-

7t_CLCL-150

-

t

_CLCL−40

-

0

-

0

Address float after RD

Advance Information (16MHz)

External Clock Drive

Variable Oscillator

(Freq. = 3.5 to 16MHz)

Parameter

Symbol

Unit

Min.

Max.

t_CLCL

t_{CHC X}

t_CLCX

t_CLCH

t_{CHC L}

62.5

17

-

285.7

Oscillator period

High time

ns

t_{C LCL}- t_{C LC X}

t_{C LC L}- t_{CH CX}

17

Low time

Rise time

-

17

Fall time

OCT. 2000 Ver 1.2

29

GMS90C320

AC Characteristics for 24MHz version

V_CC= 5V:

V_CC= 5V + 10%, −15%; V_SS= 0V; T_A= 0°C to 70°C

(C_Lfor port 0. ALE and PSEN outputs = 100pF; C_Lfor all other outputs = 80pF)

V_CC= 3.3V:

Variable clock:

V_CC= 3.3V + 0.3V, −0.6V; V_SS= 0V; T_A= 0°C to 70°C

(C_Lfor port 0. ALE and PSEN outputs = 50pF; C_Lfor all other outputs = 50pF)

Vcc = 5V: 1/t_{CLC L}= 3.5 MHz to 24 MHz

Vcc = 3.3V: 1/t_{C LCL}= 1 MHz to 24 MHz

External Program Memory Characteristics

Variable Oscillator

1/t_CLCL= 3.5 to 24MHz

24 MHz Oscillator

Parameter

Symbol

Unit

Min.

43

17

-

Max.

Min.

Max.

t_LHLL

t_AVLL

t_LLAX

t_LLIV

-

2t_{C LC L}-40

-

ALE pulse width

ns

-

t_CLCL-25

-

Address setup to ALE

t_CLCL-25

-

Address hold after ALE

ALE low to valid instruction in

ALE to PSEN

80

-

4t_CLCL-87

t_LLPL

22

95

-

t_CLCL-20

-

t_PLPH

t_PLIV

t_PXIX

-

3t_{C LC L}-30

-

PSEN pulse width

60

-

3t_CLCL-65

PSEN to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address valid after PSEN

Address to valid instruction in

Address float to PSEN

0

-

1)

t_PXIZ

t_PXAV

t_AVIV

t_AZPL

-

32

-

t_{C LC L}-5

-

t_CLCL-10

1)

37

-

148

-

5t_CLCL-60

-

-10

1)

Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible. This limited bus contention will not cause

any damage to port 0 Drivers.

30

OCT. 2000 Ver 1.2

GMS90C320

AC Characteristics for 24MHz

External Data Memory Characteristics

Variable Oscillator

1/t_CLCL= 3.5 to 24MHz

24 MHz Oscillator

Parameter

Symbol

Unit

Min.

180

56

-

Max.

Min.

Max.

t_RLRH

t_{W LW H}

t_LLAX2

t_RLDV

t_{RHD X}

t_{RHD Z}

t_{LLD V}

-

6t_{C LC L}-70

-

RD pulse width

ns

-

6t_{C LC L}-70

-

WR pulse width

2t_{C LC L}-27

-

Address hold after ALE

RD to valid data in

118

-

5t_CLCL-90

0

-

Data hold after RD

-

63

200

220

175

-

2t_CLCL-20

Data float after RD

-

8t_CLCL-133

ALE to valid data in

t_{AVD V}

t_{LLW L}

t_{AVW L}

t_{W HLH}

t_{Q VW X}

t_{Q VW H}

t_{W HQ X}

t_RLAZ

-

9t_CLCL-155

Address to valid data in

ALE to WR or RD

75

67

17

5

3t_{C LC L}-50

4t_{C LC L}-97

t_CLCL-25

t_CLCL-37

7t_CLCL-122

t_CLCL-27

-

3t_{CLC L}+50

-

Address valid to WR or RD

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

67

-

t_{C LC L}+25

-

170

15

-

0

Address float after RD

Advance Information (24MHz)

External Clock Drive

Table 11.

Variable Oscillator

(Freq. = 3.5 to 24MHz)

Parameter

Symbol

Unit

Min.

Max.

t_CLCL

t_{CHC X}

t_CLCX

t_CLCH

t_{CHC L}

41.7

12

-

285.7

Oscillator period

High time

ns

t_{C LCL}- t_{C LCX}

t_{C LC L}- t_{CH CX}

12

Low time

Rise time

-

12

Fall time

OCT. 2000 Ver 1.2

31

GMS90C320

AC Characteristics for 40MHz version

V_{C C}= 5V + 10%, − 15%; V_SS= 0V; T_A= 0°C to 70°C

(C_Lfor port 0. ALE and PSEN outputs = 100pF; C_Lfor all other outputs = 80pF)

External Program Memory Characteristics

Variable Oscillator

1/t_CLCL= 3.5 to 40MHz

40 MHz Oscillator

Parameter

Symbol

Unit

Min.

35

10

-

Max.

Min.

Max.

t_LHLL

t_AVLL

t_LLAX

t_LLIV

-

2t_CLCL−15

-

ALE pulse width

ns

t

_CLCL−15

-

Address setup to ALE

-

t

-

Address hold after ALE

ALE low to valid instruction in

ALE to PSEN

55

-

4t_CLCL−45

t_LLPL

10

60

-

t

_CLCL−15

-

t_PLPH

t_PLIV

t_PXIX

-

3t_CLCL−15

-

PSEN pulse width

25

-

0

-

3t_CLCL−50

PSEN to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address valid after PSEN

Address to valid instruction in

Address float to PSEN

0

-

1)

t_PXIZ

t_PXAV

t_AVIV

t_AZPL

-

15

-

t

_{CLC L}−10

1)

20

-

t

_CLCL−5

-

65

-

5t_CLCL−60

-5

-

1)

Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage

to port 0 Drivers.

32

OCT. 2000 Ver 1.2

GMS90C320

AC Characteristics for 40MHz

External Data Memory Characteristics

Variable Clock

1/t_CLCL= 3.5 to 40MHz

at 40 MHz Clock

Parameter

Symbol

Unit

Min.

120

10

-

Max.

Min.

Max.

t_RLRH

t_{W LW H}

t_LLAX2

t_RLDV

t_{RHD X}

t_{RHD Z}

t_{LLD V}

-

6t_{C LC L}-30

-

RD pulse width

ns

6t_{C LC L}-30

-

WR pulse width

-

t_CLCL-15

-

Address hold after ALE

RD to valid data in

75

-

5t_CLCL-50

0

-

Data hold after RD

-

38

150

90

-

2t_CLCL-12

Data float after RD

-

8t_CLCL-50

ALE to valid data in

t_{AVD V}

t_{LLW L}

t_{AVW L}

t_{W HLH}

t_{Q VW X}

t_{Q VW H}

t_{W HQ X}

t_RLAZ

-

9t_CLCL-75

Address to valid data in

ALE to WR or RD

60

70

10

5

3t_{C LC L}-15

4t_{C LC L}-30

t_CLCL-15

t_CLCL-20

7t_{C LC L}-50

t_CLCL-20

-

3t_{CLC L}+15

-

Address valid to WR or RD

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

40

-

t_{C LC L}+15

-

125

5

-

0

Address float after RD

Advance Information (40MHz)

External Clock Drive

Variable Oscillator

(Freq. = 3.5 to 40MHz)

Parameter

Symbol

Unit

Min.

Max.

t_CLCL

t_{CHC X}

t_CLCX

t_CLCH

t_{CHC L}

25

10

-

285.7

Oscillator period

High time

ns

t_{C LCL}- t_{C LC X}

t_{C LC L}- t_{CH CX}

10

Low time

Rise time

-

10

Fall time

OCT. 2000 Ver 1.2

33

GMS90C320

AC Characteristics for 50MHz version

V_{C C}= 5V + 10%, − 15%; V_SS= 0V; T_A= 0°C to 70°C

(C_Lfor port 0. ALE and PSEN outputs = 100pF; C_Lfor all other outputs = 80pF)

Variable Clock : V_{C C}= 5V, 1/ t_{C LCL}= 3.5MHz to 50 MHz

External Program Memory Characteristics

Variable Oscillator

1/t_CLCL= 3.5 to 50MHz

50 MHz Oscillator

Parameter

Symbol

Unit

Min.

25

5

Max.

Min.

Max.

t_LHLL

t_AVLL

t_LLAX

t_LLIV

-

2t_CLCL−15

-

ALE pulse width

ns

t

_CLCL−15

-

Address setup to ALE

5

-

t

-

Address hold after ALE

ALE low to valid instruction in

ALE to PSEN

-

40

-

4t_CLCL−40

t_LLPL

5

t

_CLCL−15

-

t_PLPH

t_PLIV

t_PXIX

45

-

3t_CLCL−15

-

PSEN pulse width

20

-

0

-

3t_CLCL−40

PSEN to valid instruction in

Input instruction hold after PSEN

Input instruction float after PSEN

Address valid after PSEN

Address to valid instruction in

Address float to PSEN

0

-

1)

t_PXIZ

t_PXAV

t_AVIV

t_AZPL

-

10

-

t

_{CLC L}−10

1)

15

-

t

_CLCL−5

-

45

-

5t_CLCL−55

-5

-

1)

Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage

to port 0 Drivers.

34

OCT. 2000 Ver 1.2

GMS90C320

AC Characteristics for 50MHz

External Data Memory Characteristics

Variable Clock

1/t_CLCL= 3.5 to 50MHz

at 50 MHz Clock

Parameter

Symbol

Unit

Min.

90

25

-

Max.

Min.

Max.

t_RLRH

t_{W LW H}

t_LLAX2

t_RLDV

t_{RHD X}

t_{RHD Z}

t_{LLD V}

-

6t_{C LC L}-30

-

RD pulse width

ns

6t_{C LC L}-30

-

WR pulse width

-

2t_{C LC L}-15

-

Address hold after ALE

RD to valid data in

60

-

5t_CLCL-40

0

-

Data hold after RD

-

28

120

125

75

-

2t_CLCL-12

Data float after RD

-

8t_CLCL-40

ALE to valid data in

t_{AVD V}

t_{LLW L}

t_{AVW L}

t_{W HLH}

t_{Q VW X}

t_{Q VW H}

t_{W HQ X}

t_RLAZ

-

9t_CLCL-55

Address to valid data in

ALE to WR or RD

45

50

5

3t_{C LC L}-15

4t_{C LC L}-30

t_CLCL-15

7t_{C LC L}-40

t_CLCL-15

-

3t_{CLC L}+15

-

Address valid to WR or RD

WR or RD high to ALE high

Data valid to WR transition

Data setup before WR

Data hold after WR

35

-

t_{C LC L}+15

5

-

100

5

-

0

Address float after RD

Advance Information (50MHz)

External Clock Drive

Variable Oscillator

(Freq. = 3.5 to 50MHz)

Parameter

Symbol

Unit

Min.

Max.

t_CLCL

t_{CHC X}

t_CLCX

t_CLCH

t_{CHC L}

20

10

-

285.7

Oscillator period

High time

ns

t_{C LCL}- t_{C LC X}

t_{C LC L}- t_{CH CX}

10

Low time

Rise time

-

10

Fall time

OCT. 2000 Ver 1.2

35

GMS90C320

t_LHLL

ALE

t_LLPL

t_AVLL

t_PLPH

t_LLIV

t_PLIV

PSEN

t_PXAV

t_PXIZ

t_PXIX

t_AZPL

t_LLAX

INSTR.

IN

A0-A7

PORT 0

PORT 2

t_AVIV

A8-A15

Figure 4 External Program Memory Read Cycle

36

OCT. 2000 Ver 1.2

GMS90C320

ALE

t_LHLL

t_{W HLH}

PSEN

RD

t_LLDV

t_{LLW L}

t_{RLR H}

t_RHDZ

t_AVLL

t_{RLD V}

t_RLAZ

t_LLAX2

t_{R HDX}

DATA IN

A0-A7 from

RI or DPL

A0-A7 from PCL

INSTR. IN

PORT 0

PORT 2

t_{AVW L}

t_AVDV

P2.0-P2.7 or A8-A15 from DPH

A8-A15 from PCH

Figure 5 External Data Memory Read Cycle

ALE

t_LHLL

t_{W HLH}

PSEN

WR

t_{LLW L}

t_{W LW H}

t_{QVW X}

t_AVLL

t_{W HQX}

t_LLAX

t_{QVW H}

A0-A7 from

RI or DPL

A0-A7 from PCL

DATA OUT

INSTR. IN

PORT 0

PORT 2

t_{AVW L}

P2.0-P2.7 or A8-A15 from DPH

A8-A15 from PCH

Figure 6 External Data Memory Write Cycle

OCT. 2000 Ver 1.2

37

GMS90C320

V

_{C C}−0.5V

0.2V_CC+ 0.9

Test Points

0.2V_{C C}− 0.1

0.45V

AC Inputs during testing are driven at V_CC−0.5V for a logic ‘1’ and 0.45V for a logic ‘0’.

Timing measurements are made a V_{IH m in}for a logic ‘1’ and V_{ILm ax}for a logic ‘0’.

Figure 7 AC Testing: Input, Output Waveforms

V_LOAD+ 0.1

V_OH− 0.1

Timing Reference Points

0.2V_CC− 0.1

V_LOAD

V_LOAD− 0.1

V_OL+ 0.1

For timing purposes a port pin is no longer floating when a 100mV change from load voltage

occurs and begins to float when a 100mV change from the loaded V_{O H}/ V_{O L}level occurs.

I_{O L}/ I_{O H}≥ 20mA.

Figure 8 Float Waveforms

t_{CLC L}

V

_CC−0.5V

0.7 V_CC

0.2 V_CC−0.1

0.45V

t_{CLC X}

t_{C HCX}

t_CLCH

t_{CH CL}

Figure 9 External Clock Cycle

38

OCT. 2000 Ver 1.2

GMS90C320

OSCILLATOR CIRCUIT

CRYSTAL OSCILLATOR MODE

DRIVING FROM EXTERNAL SOURCE

C2

C1

N.C.

XTAL2

P-LCC-44/Pin 20

P-DIP-40/Pin 18

M-QFP-44/Pin 14

P-LCC-44/Pin 20

P-DIP-40/Pin 18

M-QFP-44/Pin 14

External Oscillator

Signal

XTAL1

P-LCC-44/Pin 21

P-DIP-40/Pin 19

M-QFP-44/Pin 15

P-LCC-44/Pin 21

P-DIP-40/Pin 19

M-QFP-44/Pin 15

C1, C2 = 30pF ±10pF for Crystals

For Ceramic Resonators, contact resonator manufacturer.

Figure 10 Recommended Oscillator Circuits

Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic

resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external

components.

OCT. 2000 Ver 1.2

39

GMS90C320

Plastic Package P-LCC-44

(Plastic Leaded Chip-Carrier)

44PLCC

UNIT: INCH

0.695

0.685

min. 0.020

0.656

0.650

0.012

0.0075

0.050 BSC

0.120

0.090

0.180

0.165

40

OCT. 2000 Ver 1.2

GMS90C320

Plastic Package P-DIP-40

(Plastic Dual in-Line Package)

40DIP

UNIT: INCH

2.075

2.045

0.600 BSC

0.550

0.530

0.022

0.015

0.065

0.045

0.100 BSC

0-15°

OCT. 2000 Ver 1.2

41

GMS90C320

Plastic Package P-MQFP-44

(Plastic Metric Quad Flat Package)

P-MQFP-44

13.45

12.95

10.10

9.90

UNIT: MM

0-7°

SEE DETAIL “A”

1.03

0.73

2.35 max.

1.60

REF

0.45

0.30

0.80 BSC

DETAIL “A”

42

OCT. 2000 Ver 1.2

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	METRIC, PLASTIC, QFP-44	针数：	44
Reach Compliance Code：	compliant	ECCN代码：	3A991.A.2
HTS代码：	8542.31.00.01	风险等级：	5.82
具有ADC：	NO	地址总线宽度：	16
位大小：	8	CPU系列：	8051
最大时钟频率：	40 MHz	DAC 通道：	NO
DMA 通道：	NO	外部数据总线宽度：	8
JESD-30 代码：	S-PQFP-G44	长度：	10 mm
I/O 线路数量：	32	端子数量：	44
最高工作温度：	70 °C	最低工作温度：
PWM 通道：	NO	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP44,.5SQ,32
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	5 V	认证状态：	Not Qualified
RAM（字节）：	256	ROM（单词）：	0
座面最大高度：	2.35 mm	速度：	40 MHz
子类别：	Microcontrollers	最大压摆率：	44 mA
最大供电电压：	5.5 V	最小供电电压：	4.25 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	10 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER	Base Number Matches：	1

型号	制造商	描述	价格	文档
GMS90C320Q50	HYNIX	HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS	获取价格
GMS90C3X	HYNIX	HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS	获取价格
GMS90C51	HYNIX	8-BIT SINGLE-CHIP MICROCONTROLLERS	获取价格
GMS90C51-GBXXX24	HYNIX	Microcontroller, 8-Bit, MROM, 24MHz, CMOS, PDIP40, PLASTIC, DIP-40	获取价格
GMS90C51-GBXXX40	HYNIX	Microcontroller, 8-Bit, MROM, 40MHz, CMOS, PDIP40, PLASTIC, DIP-40	获取价格
GMS90C51-GBXXXPL12	HYNIX	Microcontroller, 8-Bit, MROM, 12MHz, CMOS, PQCC44, PLASTIC, LCC-44	获取价格
GMS90C51-GBXXXPL24	HYNIX	Microcontroller, 8-Bit, MROM, 24MHz, CMOS, PQCC44, PLASTIC, LCC-44	获取价格
GMS90C51-GBXXXPL40	HYNIX	Microcontroller, 8-Bit, MROM, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44	获取价格
GMS90C51-GBXXXQ12	HYNIX	Microcontroller, 8-Bit, MROM, 12MHz, CMOS, PQFP44, METRIC, PLASTIC, QFP-44	获取价格
GMS90C51-GBXXXQ40	HYNIX	Microcontroller, 8-Bit, MROM, 40MHz, CMOS, PQFP44, METRIC, PLASTIC, QFP-44	获取价格

GMS90C320Q40

GMS90C320Q40 概述

GMS90C320Q40 规格参数

GMS90C320Q40 数据手册

GMS90C320Q40 相关器件

GMS90C320Q40 相关文章

热门型号