GMS97C56PL [HYNIX]
Microcontroller, 8-Bit, OTPROM, 24MHz, CMOS, PQCC44, PLASTIC, LCC-44;
| 型号： | GMS97C56PL |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Microcontroller, 8-Bit, OTPROM, 24MHz, CMOS, PQCC44, PLASTIC, LCC-44 可编程只读存储器 微控制器 |
| 文件： | 总59页 (文件大小：724K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYUNDAI MICRO ELECTRONICS
8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS90C3X
GMS90C5X
GMS97C5X
User’s Manual (Ver. 3.1a)
ꢀ ꢁ ꢂ ꢃ ꢄ ꢅ ꢆ
MicroElectronics
Semiconductor Group of Hyundai Electronics Industrial Co., Ltd.
Version 3.1a
Published by
MCU Application Team
1999 HYUNDAI MicroElectronics All right reserved.
Additional information of this manual may be served by HYUNDAI MicroElectronics offices in Korea or Dis-
tributors and Representatives listed at address directory.
HYUNDAI MicroElectronics reserves the right to make changes to any information here in at any time without
notice.
The information, diagrams and other data in this manual are correct and reliable; however, HYUNDAI Micro-
Electronics is in no way responsible for any violations of patents or other rights of the third party generated by
the use of this manual.
GMS90 Series
HYUNDAI MicroElectronics
Device Naming Structure
GMS90X5X - GBXXX XX XX
Frequency
Blank: 12MHz
16:
24:
40:
16MHz
24MHz
40MHz
Package Type
Blank: 40PDIP
PL:
Q:
44PLCC
44MQFP
ROM Code serial No.
ROM size
1: 4k bytes
2: 8k bytes
4: 16k bytes
6: 24k bytes
8: 32k bytes
Operating Voltage
C: 4.25~5.5V
L: 2.7~3.6V
GMS97X5X X XX
Package Type
Blank: 40PDIP
PL:
Q:
44PLCC
44MQFP
Frequency
Blank: 12/24(5V),12MHz(3V)
H:
33MHz
ROM size
1: 4k bytes
2: 8k bytes
4: 16k bytes
6: 24k bytes
8: 32k bytes
Operating Voltage
C: 4.25~5.5V
L: 2.7~3.6V
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
GMS90 Series Selection Guide
ROM size
(bytes)
Operating
Voltage
RAM size
(bytes)
Operating
Device Name
Frequency
(V)
(MHz)
MASK
ROM-less
OTP
128
256
GMS90C31
GMS90C32
12/24/40
12/24/40
4K
8K
16K
24K
32K
-
-
-
-
-
128
256
256
256
256
GMS90C51
GMS90C52
GMS90C54
GMS90C56
GMS90C58
12/24/40
12/24/40
12/24/40
12/24/40
12/24/40
-
-
-
-
-
-
-
-
-
-
4K
4K
8K
8K
16K
16K
24K
24K
32K
32K
128
128
256
256
256
256
256
256
256
256
GMS97C51
GMS97C51H
GMS97C52
GMS97C52H
GMS97C54
GMS97C54H
GMS97C56
GMS97C56H
GMS97C58
GMS97C58H
12/24
33
12/24
33
12/24
33
12/24
33
4.25~5.5
12/24
33
128
256
GMS90L31
GMS90L32
12/16
12/16
ROM-less
4K
8K
16K
24K
32K
-
-
-
-
-
128
256
256
256
256
GMS90L51
GMS90L52
GMS90L54
GMS90L56
GMS90L58
12/16
12/16
12/16
12/16
12/16
2.7~3.6
-
-
-
-
-
4K
8K
16K
24K
32K
128
256
256
256
256
GMS97L51
GMS97L52
GMS97L54
GMS97L56
GMS97L58
12
12
12
12
12
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
GMS90C31/51, 97C51
GMS90L31/51, 97L51 (Low voltage versions)
• Fully compatible to standard MCS-51 microcontroller
• Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
• 4K × 8 (EP)ROM
• 128 × 8 RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Two 16-bit Timers / Counters
• USART
• Five interrupt sources, two priority levels
• Power saving Idle and power down mode
• Quick pulse programming algorithm (in the OTP devices)
• 2-level program memory lock (in the OTP devices)
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
RAM
I/O
PORT 0
128 × 8
T 0
T 1
I/O
I/O
I/O
PORT 1
PORT 2
PORT 3
8-BIT
USART
CPU
ROM / EPROM
4K × 8
Oct. 2000 Ver 3.1a
1
HYUNDAI MicroElectronics
GMS90 Series
GMS90C32/52, 97C52
GMS90L32/52, 97L52 (Low voltage versions)
• Fully compatible to standard MCS-51 microcontroller
• Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
• 8K × 8 (EP)ROM
• 256 × 8 RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Three 16-bit Timers / Counters (Timer2 with up/down counter feature)
• USART
• Six interrupt sources, two priority levels
• Power saving Idle and power down mode
• Quick pulse programming algorithm (in the OTP devices)
• 2-level program memory lock (in the OTP devices)
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
RAM
I/O
PORT 0
256 × 8
T 0
T 1
I/O
I/O
I/O
PORT 1
PORT 2
PORT 3
8-BIT
USART
CPU
T 2
ROM / EPROM
8K × 8
2
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
GMS90C54/56/58, 97C54/56/58
GMS90L54/56/58, 97L54/56/58 (Low voltage versions)
• Fully compatible to standard MCS-51 microcontroller
• Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”)
• 16K/24K/32K bytes (EP)ROM
• 256 × 8 RAM
• 64K external program memory space
• 64K external data memory space
• Four 8-bit ports
• Three 16-bit Timers / Counters (Timer2 with up/down counter feature)
• USART
• One clock output port
• Programmable ALE pin enable / disable
• Six interrupt sources, two priority levels
• Power saving Idle and power down mode
• Quick pulse programming algorithm (in the OTP devices)
• 2-level program memory lock (in the OTP devices)
• 2.7Volt low voltage version available
• P-DIP-40, P-LCC-44, P-MQFP-44 package
Block Diagram
RAM
I/O
PORT 0
256 × 8
T 0
T 1
I/O
I/O
PORT 1
PORT 2
8-BIT
USART
CPU
T 2
ROM / EPROM
GMS9XX54: 16K × 8
GMS9XX56: 24K × 8
GMS9XX58: 32K × 8
I/O
PORT 3
Oct. 2000 Ver 3.1a
3
HYUNDAI MicroElectronics
GMS90 Series
PIN CONFIGURATION
44-PLCC Pin Configuration (top view)
INDEX
CORNER
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
P1.5
P1.6
39
38
37
36
7
8
P1.7
9
RESET
10
EA / V
PP
RxD / P3.0
N.C.*
35
34
33
32
31
30
29
11
12
13
14
15
16
17
N.C.*
ALE / PROG
PSEN
TxD / P3.1
INT0 / P3.2
INT1 / P3.3
T0 / P3.4
T1 / P3.5
P2.7 / A15
P2.6 / A14
P2.5 / A13
N.C.: Do not connect.
4
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
40-PDIP Pin Configuration (top view)
V
T2 / P1.0
T2EX / P1.1
P1.2
CC
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P0.0 / AD0
P0.1 / AD1
P0.2 / AD2
P0.3 / AD3
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
3
P1.3
4
P1.4
5
P1.5
6
P1.6
7
P1.7
8
RESET
RxD / P3.0
TxD / P3.1
INT0 / P3.2
INT1 / P3.3
T0 / P3.4
T1 / P3.5
WR / P3.6
RD / P3.7
XTAL2
9
EA / V
PP
10
11
12
13
14
15
16
17
18
19
20
ALE / PROG
PSEN
P2.7 / A15
P2.6 / A14
P2.5 / A13
P2.4 / A12
P2.3 / A11
P2.2 / A10
P2.1 / A9
P2.0 / A8
XTAL1
V
SS
Oct. 2000 Ver 3.1a
5
HYUNDAI MicroElectronics
GMS90 Series
44-MQFP Pin Configuration (top view)
P1.5
P1.6
33
32
31
30
P0.4 / AD4
P0.5 / AD5
P0.6 / AD6
P0.7 / AD7
1
2
3
4
P1.7
RESET
RxD / P3.0
N.C.*
5
6
29
28
27
26
25
24
23
EA / V
N.C.*
PP
TxD / P3.1
INT0 / P3.2
INT1 / P3.3
T0 / P3.4
T1 / P3.5
ALE / PROG
PSEN
7
8
P2.7 / A15
P2.6 / A14
P2.5 / A13
9
10
11
N.C.: Do not connect.
6
Oct. 2000 Ver 3.1a
GMS90 Series
Logic Symbol
HYUNDAI MicroElectronics
VCC VSS
XTAL1
XTAL2
Port 0
8-bit Digital I/O
Port 1
8-bit Digital I/O
RESET
Port 2
8-bit Digital I/O
EA/VPP
ALE/PROG
PSEN
Port 3
8-bit Digital I/O
Oct. 2000 Ver 3.1a
7
HYUNDAI MicroElectronics
GMS90 Series
PIN DEFINITIONS AND FUNCTIONS
Pin Number
Input/
Symbol
Function
PLCC-
44
PDIP-
40
MQFP-
44
Output
Port1
P1.0-P1.7
2-9
1-8
40-44,
1-3
I/O
Port 1 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 1 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics). Pins P1.0
and P1.1 also. Port1 also receives the low-order
address byte during program memory verification.
Port1 also serves alternate functions of Timer 2.
2
3
1
2
40
41
P1.0 / T2 :
Timer/counter 2 external count input
P1.1 / T2EX : Timer/counter 2 trigger input
In GMS9XC54/56/58:
2
1
40
P1.0 / T2, Clock Out : Timer/counter 2 external count
input, Clock Out
Port 3
P3.0-P3.7
11,
10-17
5, 7-13
I/O
13-19
Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 3 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics). Port 3 also
serves the special features of the 80C51 family, as
listed below.
11
13
10
11
5
7
P3.0 / RxD receiver data input (asynchronous) or
data input output(synchronous) of serial
interface 0
P3.1 / TxD transmitter data output (asynchronous)
or clock output (synchronous) of the
serial interface 0
14
15
16
17
18
12
13
14
15
16
8
9
10
11
12
P3.2 /INT0 interrupt 0 input/timer 0 gate control
P3.3 / INT1
P3.4 /T0
interrupt 1 input/timer 1 gate control
counter 0 input
P3.5 /T1
counter 1 input
P3.6 / WR
the write control signal latches the data
byte from port 0 into the external data
memory
19
20
17
18
13
14
P3.7 /RD
the read control signal enables the
external data memory to port 0
XTAL2
XTAL2
O
Output of the inverting oscillator amplifier.
8
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
Pin Number
Input/
Symbol
Function
PLCC-
44
PDIP-
40
MQFP-
44
Output
XTAL1
XTAL1
21
19
15
I
Input to the inverting oscillator amplifier and input to
the internal clock generator circuits.To drive the
device from an external clock source, XTAL1 should
be driven, while XTAL2 is left unconnected. There are
no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking
circuitry is divided down by a divide-by-two flip-flop.
Minimum and maximum high and low times as well as
rise fall times specified in the AC characteristics must
be observed.
Port 2
P2.0-P2.7
24-31
21-28
18-25
I/O
Port 2 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 2 pins that have 1s written to them are
pulled high by the internal pull-up resistors and can be
used as inputs. As inputs, port 2 pins that are
externally pulled low will source current because of
the pulls-ups (IIL, in the DC characteristics).Port 2
emits the high-order address byte during fetches from
external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses
(MOVX @Ri), port 2 emits the contents of the P2
special function register.
The Program Store Enable
PSEN
32
29
26
O
The read strobe to external program memory when
the device is executing code from the external
program memory. PSEN is activated twice each
machine cycle, except that two PSEN activations are
skipped during each access to external data memory.
PSEN is not activated during fetches from internal
program memory.
RESET
RESET
10
9
4
I
A high level on this pin for two machine cycles while
the oscillator is running resets the device. An internal
diffused resistor to VSS permits power-on reset using
only an external capacitor to VCC
.
Oct. 2000 Ver 3.1a
9
HYUNDAI MicroElectronics
GMS90 Series
Pin Number
Symbol
Input/
Output
Function
PLCC-
44
PDIP-
40
MQFP-
44
The Address Latch Enable / Program pulse
Output pulse for latching the low byte of the address
during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped
during each access to external data memory. This pin
is also the program pulse input (PROG) during
EPROM programming.
ALE /
PROG
33
30
27
O
In GMS9XC54/56/58:
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With this bit set, the pin is
weakly pulled high. The ALE disable feature will be
terminated by reset. Setting the ALE-disable bit has
no affect if the microcontroller is in external execution
mode.
EA / VPP
35
31
29
I
External Access Enable / Program Supply Voltage
EA must be external held low to enable the device to
fetch code from external program memory locations
0000H to FFFFH. If EA is held high, the device
executes from internal program memory unless the
program counter contains an address greater than its
internal memory size. This pin also receives the
12.75V programming supply voltage (VPP) during
EPROM programming.
Note;
however, that if any of the Lock bits are
programmed, EA will be internally
latched on reset.
Port 0
P0.0-P0.7
36-43
32-39
30-37
I/O
Port 0 is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1s written to them float and can
be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and
data memory. In this application it uses strong internal
pull-ups when emitting 1s. Port 0 also outputs the
code bytes during program verification in the
GMS97X5X. External pull-up resistors are required
during program verification.
VSS
VCC
N.C.
22
44
20
40
-
16
38
-
-
-
Circuit ground potential
Supply terminal
No connection
for all operating modes
1,12
23,34
6,17
28,39
10
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
FUNCTIONAL DESCRIPTION
The GMS90 series is fully compatible to the standard 8051 microcontroller family.
It is compatible with the general 8051 family. While maintaining all architectural and operational characteristics
of the general 8051 family.
Figure 1 shows a block diagram of the GMS90 series
ROM/EPROM
RAM
XTAL1
XTAL2
4K/8K/16K
24K/32K
OSC & TIMING
128/256×8
CPU
Timer 0
RESET
EA/V
PP
Port 0
8-bit Digit. I/O
Port 0
Port 1
ALE/PROG
PSEN
Timer 1
Port 1
8-bit Digit. I/O
Timer 2
Port 2
8-bit Digit. I/O
Port 2
Port 3
Interrupt Unit
Serial Channel
Port 3
8-bit Digit. I/O
Figure 1. Block Diagram of the GMS90 series
Oct. 2000 Ver 3.1a
11
HYUNDAI MicroElectronics
GMS90 Series
CPU
The GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for
binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results
from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12
MHz crystal, 58% of the instructions are executed in 1.0µs (40MHz: 300ns).
Special Function Register PSW
LSB
0
MSB
7
Bit No.
6
5
4
3
2
1
Addr. D0
H
PSW
CY AC F0 RS1 RS0 OV F1
P
Bit
Function
Carry Flag
CY
AC
F0
Auxiliary Carry Flag
(for BCD operations)
General Purpose Flag
Register Bank select control bits
RS1
RS0
0
0
1
1
0
1
0
1
Bank 0 selected, data address 00H - 07H
Bank 1 selected, data address 08H - 0FH
Bank 2 selected, data address 10H - 17H
Bank 3 selected, data address 18H - 1FH
Overflow Flag
OV
F1
P
General Purpose Flag
Parity Flag
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
Reset value of PSW is 00H.
12
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
SPECIAL FUNCTION REGISTERS
All registers, except the program counter and the four general purpose register banks, reside in the special func-
tion register area.
The 28 special function registers (SFR) include pointers and registers that provide an interface between the CPU
and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area.
All SFRs are listed in Table 1, Table 1, and Table 3.
In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which
refer to the functional blocks of the GMS90 series. Table 3 illustrates the contents of the SFRs.
Table 1. Special Function Registers in Numeric Order of their Addresses
Contents after
Reset
Contentsafter
Reset
Address
Register
Address
Register
P0 1)
SP
DPL
P1 1)
80H
81H
82H
83H
84H
85H
86H
87H
FFH
07H
00H
00H
XXH 2)
XXH 2)
XXH 2)
90H
91H
92H
93H
94H
95H
96H
97H
FFH
00H
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
DPH
reserved
reserved
reserved
PCON
2)
0XX0000B
TCON 1)
TMOD
TL0
TL1
TH0
SCON 1)
SBUF
88H
89H
8AH
8BH
8CH
8DH
00H
00H
00H
00H
00H
00H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
reserved
reserved
reserved
reserved
reserved
reserved
TH1
8EH 3)
8FH
☞
3)
3)
☞
reserved
XXH 2)
1) Bit-addressable Special Function Register.
2) X means that the value is indeterminate and the location is reserved.
3) The GMS9XX54/56/58 have the AUXR0 register at address 8E .
H
GMS9XX51/52
GMS9XX54/56/58
8EH
2)
2)
XXXXXXXXB
8EH
reserved
AUXR0
XXXXXXX0B
Oct. 2000 Ver 3.1a
13
HYUNDAI MicroElectronics
GMS90 Series
Table 1. Special Function Registers in Numeric Order of their Addresses
Contents after
(cont’d)
Contentsafter
Reset
Address
Register
Address
Register
Reset
P2 1)
T2CON 1)
T2MOD
RC2L
RC2H
TL2
TH2
reserved
reserved
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
FFH
C8H
00H
3)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
C9H 3)
CAH
CBH
CCH
CDH
CEH
CFH
☞
00H
00H
00H
00H
XXH 2)
XXH 2)
IE 1)
0X000000B 2)
XXH 2)
PSW 1)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
00H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
P3 1)
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
FFH
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
IP 1)
XX000000B 2)
XXH 2)
ACC 1)
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
XXH
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
14
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
Table 1. Special Function Registers in Numeric Order of their Addresses
Contents after
(cont’d)
Contentsafter
Reset
Address
Register
Address
Register
Reset
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
B 1)
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
FCH
FDH
FEH
FFH
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
00H
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
XXH 2)
reserved
reserved
reserved
reserved
reserved
reserved
reserved
1) Bit-addressable Special Function Register.
2) X means that the value is indeterminate and the location is reserved.
3) Address C9 is configured as below.
H
GMS9XX51/52
GMS9XX54/56/58
2)
2)
C9H
reserved
XXXXXXX0B
C9H
T2MOD
XXXXXX00B
Oct. 2000 Ver 3.1a
15
HYUNDAI MicroElectronics
GMS90 Series
Table 2. Special Function Registers - Functional Blocks
Contents
after Reset
Block
Symbol
Name
Address
E0H 1)
F0H 1)
83H
82H
D0H 1)
81H
CPU
ACC
B
DPH
DPL
PSW
SP
Accumulator
B-Register
00H
00H
00H
00H
00H
07H
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer
A8H 1)
B8H 1)
0X000000B 2)
XX000000B 2)
Interrupt System IE
IP
Interrupt Enable Register
Interrupt Priority Register
80H 1)
90H 1)
A0H 1)
B0H 1)
Ports
P0
P1
P2
P3
Port 0
Port 1
Port 2
Port 3
FFH
FFH
FFH
FFH
PCON 3)
SBUF
SCON
0XXX0000B 2)
XXH 2)
Serial Channels
Power Control Register
Serial Channel Buffer Reg.
Serial Channel 0 Control Reg.
87H
99H
98H 1)
00H
88H 1)
8CH
8DH
8AH
8BH
89H
Timer 0/ Timer 1 TCON
Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register
00H
00H
00H
00H
00H
00H
TH0
TH1
TL0
TL1
TMOD
C8H 1)
C9H
CBH
CAH
CDH
CCH
8EH
Timer 2
T2CON
T2MOD
RC2H
RC2L
TH2
TL2
AUXR0 4)
Timer 2 Control Register
Timer 2 Mode Register
Timer 2 Reload Capture Reg., High Byte
Timer 2 Reload Capture Reg., Low Byte
Timer 2, High Byte
00H
00H
00H
00H
00H
00H
Timer 2, Low Byte
Aux. Register 0
XXXXXXX0B 2)
3)
0XXX0000B 2)
Power
Modes
Saving
Power Control Register
87H
PCON
1) Bit-addressable Special Function register
2) X means that the value is indeterminate and the location is reserved
3) This special function register is listed repeatedly since some bit of it also belong to other functional blocks
4) The AUXR0 is in the GMS9XX54/56/58 only.
16
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
Table 3. Contents of SFRs, SFRs in Numeric Order
Address
Register
Bit 7
6
5
4
3
2
1
0
80H
P0
81H
82H
83H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
SP
DPL
DPH
PCON
TCON
TMOD
TL0
SM OD
TF1
-
-
-
GF1
IE1
GF0
IT1
PDE
IE0
M1
IDLE
IT0
TR1
C/T
TF0
M1
TR0
MT
GATE
GATE
C/T
M0
TL1
TH0
TH1
AUXR0 †
P1
A0 †
RI
-
-
-
-
-
-
-
90H
98H
99H
A0H
A8H
B0H
B8H
SCON
SBUF
P2
SM0
SM1
SM2
REN
TB8
RB8
TI
IE
EA
-
-
-
ET2
PT2
ES
PS
ET1
PT1
EX1
PX1
ET0
PT0
EX0
PX0
P3
IP
† indicates resident in the GMS9XX54/56/58, not in 9XX51/52.
SFR bit and byte addressable
SFR not bit addressable
- : this bit location is reserved
Oct. 2000 Ver 3.1a
17
HYUNDAI MicroElectronics
GMS90 Series
Table 3. Contents of SFRs, SFRs in Numeric Order
(cont’d)
Address
Register
Bit 7
6
5
4
3
2
1
0
C8H
T2CON
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
†
C9H
T2MOD
-
-
-
-
-
-
DCEN
T2OE
CAH
CBH
CCH
CDH
D0H
E0H
F0H
RC2L
RC2H
TL2
TH2
PSW
ACC
B
CY
AC
F0
RS1
RS0
OV
F1
P
† indicates resident in the GMS9XX54/56/58, not in 9XX51/52.
†
A0
8EH
A0 : ALE Signal Disable bit
0 : Enable ALE Signal (Generated ALE Signal)
1 : Disable ALE Signal (Not Generated ALE Signal)
†
T2OE
C9H
T2OE : Timer2 Output Enable bit
0 : Disable Timer2 Output
1 : Enable Timer2 Output
SFR bit and byte addressable
SFR not bit addressable
- : this bit location is reserved
18
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
TIMER / COUNTER 0 AND 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
Table 4. Timer/Counter 0 and 1 Operating Modes
TMOD
Input Clock
Mode
Description
Gate
X
C/T
X
M1
0
M0
0
internal
external (Max.)
8-bit timer/counter with a
divide-by-32 prescaler
f
OSC ÷(12×32)
fOSC ÷(24×32)
0
1
2
f
f
OSC ÷12
OSC ÷12
f
f
OSC ÷24
OSC ÷24
16-bit timer/counter
X
X
0
1
8-bit timer/counter with
8-bit auto-reload
X
X
1
0
Timer/counter 0 used as
one 8-bit timer/counter and
one 8-bit timer Timer 1
stops
f
OSC ÷12
f
OSC ÷24
3
X
X
1
1
In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is
OSC/12.
f
In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding exter-
nal input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate
is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate
pulse width measurements. Figure 2 illustrates the input clock logic.
f
÷
12
OSC
f
÷ 12
OSC
C/T
TMOD
0
Timer 0/1
Input Clock
P3.4/T0
P3.5/T1
1
Max. f
/24
OSC
TR0 / 1
TCON
&
Gate
=1
TMOD
≥1
P3.2 / INT0
P3.3 / INT1
Figure 2. Timer/Counter 0 and 1 Input Clock Logic
Oct. 2000 Ver 3.1a
19
HYUNDAI MicroElectronics
GMS90 Series
TIMER 2
Timer 2 is a 16-bit timer/Counter with an up/down count feature. It can operate either as timer or as an event
counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5.
Table 5. Timer/Counter 2 Operating Modes
T2MO
T2CON
T2CON
Input Clock
D
P1.1/
T2EX
Mode
Remarks
RCLKor
TCLK
external
CP/RL2
TR2
DCEN EXEN2
internal
(P1.0/T2)
16-bit Auto-
Reload
0
0
0
1
0
0
0
1
X
reload upon over-
flow
reload trigger (fall-
ing edge)
Max.
OSC ÷24
0
1
↓
f
OSC ÷ 12
f
0
0
0
0
1
1
1
1
X
X
0
1
Down counting
Up counting
16-bit
Capture
0
1
1
X
0
X
16 bit Timer/ Coun-
ter (only up-count-
ing)
Max.
OSC ÷ 24
f
f
OSC ÷ 12
f
0
1
1
1
1
X
X
1
0
↓
capture TH2,TL2
→ RC2H,RC2L
Baud Rate
Generator
X
X
no overflow
interrupt request
(TF2)
Max.
OSC ÷ 24
OSC ÷ 12
f
1
X
X
1
0
X
X
1
↓
extra external inter-
rupt ("Timer 2")
Off
X
X
X
Timer 2 stops
-
-
Note: ↓ =
falling edge
20
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
SERIAL INTERFACE (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes)
as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.
Table 6. USART Operating Modes
SCON
Mode
Baudrate
Description
SM0
SM1
Serial data enters and exits through RxD.
TxD outputs the shift clock. 8-bit are transmit-
ted/received (LSB first)
f
--O----S----C--
0
1
0
0
12
8-bit UART
10 bits are transmitted (through TxD) or
received (RxD)
0
1
Timer 1/2 overflow rate
9-bit UART
f
fOSC
--O----S----C--
------------
2
3
1
1
0
1
or
11 bits are transmitted (TxD) or received (RxD)
32
64
9-bit UART
Like mode 2 except the variable baud rate
Timer 1/2 overflow rate
Table 7. Formulas for Calculating Baud rates
Baud Rate
Interface Mode
derived from
Baudrate
fOSC
0
------------
12
Oscillator
2SMOD
64
2
------------------
× fOSC
2SMOD
------------------
32
1,3
× (Timer 1 overflow)
Timer 1 (16-bit timer)
(8-bit timer with
8-bit auto reload)
2SMOD
f
------------------ ---------------------O----S----C---------------------
1,3
×
32
12 × [256 – (TH1)]
fOSC
Timer 2
1,3
---------------------------------------------------------------------------------
32 × [65536 – (RC2H, RC2L)]
Oct. 2000 Ver 3.1a
21
HYUNDAI MicroElectronics
GMS90 Series
INTERRUPT SYSTEM
The GMS90 series provides 5 (4K bytes ROM version) or 6 (above 8K bytes ROM version) interrupt sources
with two priority levels. Figure 3 gives a general overview of the interrupt sources and illustrates the request and
control flags.
High
Priority
Timer 0 Overflow
Timer 1 Overflow
TF0
Low
Priority
TCON.5
ET0
IE.1
PT0
IP.1
TF1
TCON.7
ET1
IE.3
PT1
IP.3
Timer 2 Overflow
TF2
≥1
≥1
T2CON.7
P1.1/
T2EX
EXF2
ET2
IE.5
PT2
IP.5
T2CON.6
EXEN2
T2CON.3
RI
SCON.0
UART
TI
ES
PS
SCON.1
IE.4
IP.4
P3.2/
INT0
IE0
TCON.1
EX0
IE.0
PX0
IP.0
IT0
TCON.0
P3.3/
INT1
IE1
TCON.3
EA
IT1
EX1
IE.2
PX1
IP.2
IE.7
TCON.2
: Low level triggered
: Falling edge triggered
Figure 3. Interrupt Request Sources
22
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
Table 8. Interrupt Sources and their Corresponding Interrupt Vectors
Source (Request Flags)
RESET
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
Vectors
Vector Address
RESET
0000H
0003H
000BH
0013H
001BH
0023H
002BH
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial port interrupt
Timer 2 interrupt
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority in-
terrupt. A high-priority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is serviced.
If requests of the same priority are received simultaneously, an internal polling sequence determines which re-
quest is serviced. Thus within each priority level there is a second priority structure determined by the polling
sequence as shown in Table 9.
Table 9. Interrupt Priority-Within-Level
Interrupt Source
Priority
External Interrupt 0
IE0
High
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
Serial Channel
TF0
IE1
TF1
RI + TI
TF2 + EXF2
↓
↓
↓
↓
Low
Timer 2 Interrupt
Oct. 2000 Ver 3.1a
23
HYUNDAI MicroElectronics
GMS90 Series
Power Saving Modes
Two power down modes are available, the Idle Mode and Power Down Mode.
The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If
the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence.
Table 10 gives a general overview of the power saving modes.
Table 10. Power Saving Modes Overview
Entering
Instruction
Example
Mode
Leaving by
Remarks
Idle mode
ORL PCON, #01H
- Enabled interrupt
- Hardware Reset
CPU is gated off
CPU status registers maintain their
data.
Peripherals are active
Power-Down mode
ORL PCON, #02H
Hardware Reset
Oscillator is stopped, contents of on-
chip RAM and SFR’s are maintained
(leaving Power Down Mode means
redefinition of SFR contents).
In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured,
however, that VCC is not reduced before the Power Down mode is invoked, and that VCC is restored to its normal
operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down
mode also restarts the oscillator. The reset should not be activated before VCC is restored to its normal operating
level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on
reset).
24
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Ambient temperature under bias (TA)...................................................................................... -40 to + 85 °C
Storage temperature (TST)...................................................................................................... -65 to + 150 °C
Voltage on VCC pins with respect to ground (VSS) ................................................................. -0.5V to 6.5V
Voltage on any pin with respect to ground (VSS) ..........................................................-0.5V to VCC + 0.5V
Input current on any pin during overload condition............................................................-15mA to +15mA
Absolute sum of all input currents during overload condition...........................................................|100mA|
Power dissipation ....................................................................................................................................1.5W
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the de-
vice. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS
)
the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maxi-
mum ratings.
Oct. 2000 Ver 3.1a
25
HYUNDAI MicroElectronics
GMS90 Series
DC Characteristics
DC Characteristics for GMS90C31/32, GMS90C51/52/54/56/58
VCC= 5V + 10%, -15%; VSS=0V; TA= 0°C to 70°C
Limit Values
Max.
Parameter
Symbol
Unit
Test Conditions
Min.
Input low voltage
(except EA, RESET)
VIL
0.2VCC - 0.1
-0.5
V
-
Input low voltage (EA)
VIL1
VIL2
0.2VCC - 0.3
0.2VCC + 0.1
-0.5
-0.5
V
V
-
-
Input low voltage (RESET)
Input high voltage (except
XTAL1, EA, RESET)
VIH
VIH1
VIH2
0.2VCC + 0.9
0.7VCC
VCC + 0.5
VCC + 0.5
VCC + 0.5
V
V
V
-
-
-
Input high voltage to XTAL1
Input high voltage to EA,
RESET
0.6VCC
Output low voltage
(ports 1, 2, 3)
OL= 1.6mA 1)
OL= 3.2mA 1)
VOL
VOL1
VOH
-
-
0.45
0.45
-
V
V
V
I
I
Output low voltage
(port 0, ALE, PSEN)
Output high voltage
(ports 1, 2, 3)
IOH= -80µA
IOH= -10µA
2.4
0.9VCC
Output high voltage
(port 0 in external bus
mode, ALE, PSEN)
IOH= -800µA 2)
IOH= -80µA 2)
2.4
0.9VCC
VOH1
-
V
Logic 0 input current
(ports 1, 2, 3)
IIL
ITL
ILI
VIN= 0.45V
-10
-65
-
-50
-650
±1
µA
µA
µA
pF
Logical 1-to-0 transition cur-
rent (ports 1, 2, 3)
VIN= 2.0V
Input leakage current
(port 0, EA)
0.45 < VIN < VCC
Pin capacitance
fC= 1MHz
TA= 25°C
CIO
-
10
Power supply current:
Active mode, 12MHz 3)
Idle mode, 12MHz 3)
Active mode, 24 MHz 3)
Idle mode, 24MHz 3)
Active mode, 40 MHz 3)
Idle mode, 40 MHz 3)
Power Down Mode 3)
VCC= 5V 4)
VCC= 5V 5)
VCC= 5V 4)
VCC= 5V 5)
VCC= 5V 4)
VCC= 5V 5)
VCC= 5V 6)
ICC
ICC
ICC
ICC
ICC
ICC
IPD
-
-
-
-
-
-
-
21
mA
mA
mA
mA
mA
mA
µA
4.8
36.2
8.2
58.5
12.5
50
26
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V of ALE and port 3.
OL
The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 tran-
sitions during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE
line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with
a schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specifica-
OH
CC
tion when the address lines are stabilizing.
3) I Max at other frequencies is given by:
CC
active mode: I = 1.27 × f
+ 5.73
CC
OSC
idle mode:
where f
I
= 0.28 × f
+ 1.45 (except OTP devices)
CC
OSC
is the oscillator frequency in MHz. I values are given in mA and measured at V = 5V.
OSC
CC
CC
4) I (active mode) is measured with:
CC
XTAL1 driven with t
, t
= 5ns, V = V + 0.5V, V = V - 0.5V; XTAL2 = N.C.;
CLCH CHCL IL SS IH CC
EA = Port0 = RESET = V ; all other pins are disconnected. I would be slightly higher if a crystal oscillator is used (appr.
CC
CC
1mA).
5) I (Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
CC
XTAL1 driven with t
, t
= 5ns, V = V + 0.5V, V = V - 0.5V; XTAL2 = N.C.;
CLCH CHCL IL SS IH CC
RESET = EA = V ; Port0 = V ; all other pins are disconnected;
SS
CC
6) I (Power Down Mode) is measured under following conditions:
PD
EA = Port0 = V ; RESET = V ; XTAL2 = N.C.; XTAL1 = V ; all other pins are disconnected.
CC
SS
SS
Oct. 2000 Ver 3.1a
27
HYUNDAI MicroElectronics
GMS90 Series
DC Characteristics for GMS97C51/52/54/56/58 (H)
VCC= 5V + 10%, -15%; VSS=0V; TA= 0°C to 70°C
Limit Values
Max.
Parameter
Symbol
Unit
Test Conditions
Min.
Input low voltage
(except EA, RESET)
VIL
0.2VCC - 0.1
-0.5
V
-
Input low voltage (EA)
VIL1
VIL2
0.2VCC - 0.3
0.2VCC + 0.1
-0.5
-0.5
V
V
-
-
Input low voltage (RESET)
Input high voltage (except
XTAL1, EA, RESET)
VIH
VIH1
VIH2
0.2VCC + 0.9
0.7VCC
VCC + 0.5
VCC + 0.5
VCC + 0.5
V
V
V
-
-
-
Input high voltage to XTAL1
Input high voltage to EA,
RESET
0.6VCC
Output low voltage
(ports 1, 2, 3)
OL= 1.6mA 1)
VOL
VOL1
VOH
-
-
0.45
0.45
-
V
V
V
I
Output low voltage
(port 0, ALE, PSEN)
IOL= 3.2mA 1)
Output high voltage
(ports 1, 2, 3)
IOH= -80µA
IOH= -10µA
2.4
0.9VCC
Output high voltage
(port 0 in external bus
mode, ALE, PSEN)
IOH= -800µA 2)
IOH= -80µA 2)
2.4
0.9VCC
VOH1
-
V
Logic 0 input current
(ports 1, 2, 3)
IIL
ITL
ILI
VIN= 0.45V
-10
-65
-
-50
-650
±1
µA
µA
µA
pF
Logical 1-to-0 transition cur-
rent (ports 1, 2, 3)
VIN= 2.0V
Input leakage current
(port 0, EA)
0.45 < VIN < VCC
Pin capacitance
fC= 1MHz
TA= 25°C
CIO
-
10
Power supply current:
Active mode, 12MHz 3)
Idle mode, 12MHz 3)
Active mode, 24 MHz 3)
Idle mode, 24MHz 3)
Active mode, 33 MHz 3)
Idle mode, 33 MHz 3)
Power Down Mode 3)
VCC= 5V 4)
VCC= 5V 5)
VCC= 5V 4)
VCC= 5V 5)
VCC= 5V 4)
VCC= 5V 5)
VCC= 5V 6)
ICC
ICC
ICC
ICC
ICC
ICC
IPD
-
-
-
-
-
-
-
21
mA
mA
mA
mA
mA
mA
µA
4.8
36.2
8.2
45
10
50
28
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
DC Characteristics for GMS90L31/32, GMS90L51/52/54/56/58
VCC= 3.3V + 0.3V, -0.6V; VSS=0V; TA= 0°C to 70°C
Limit Values
Max.
Parameter
Symbol
Unit
Test Conditions
Min.
-0.5
2.0
Input low voltage
Input high voltage
VIL
0.8
V
V
-
VIH
VCC + 0.5
-
OL= 1.6mA 1)
Output low voltage
(ports 1, 2, 3)
I
0.45
0.30
VOL
-
-
V
IOL= 100µA 1)
IOL= 3.2mA 1)
IOL= 200µA 1)
Output low voltage
(port 0, ALE, PSEN)
0.45
0.30
VOL1
V
V
Output high voltage
(ports 1, 2, 3)
IOH= -20µA
IOH= -10µA
2.0
0.9VCC
VOH
-
-
Output high voltage
(port 0 in external bus
mode, ALE, PSEN)
IOH= -800µA 2)
IOH= -80µA 2)
2.0
0.9VCC
VOH1
V
Logic 0 input current
(ports 1, 2, 3)
IIL
ITL
ILI
VIN= 0.45V
-1
-25
-
-50
-250
±1
µA
µA
µA
pF
Logical 1-to-0 transition cur-
rent (ports 1, 2, 3)
VIN= 2.0V
Input leakage current
(port 0, EA)
0.45 < VIN < VCC
Pin capacitance
fC= 1MHz
TA= 25°C
CIO
-
10
Power supply current:
Active mode, 16 MHz 3)
Idle mode, 16MHz 3)
Power Down Mode 3)
VCC= 3.6V 4)
VCC= 2.6V 5)
VCC=2~ 5.5V 6)
ICC
ICC
IPD
-
-
-
mA
mA
µA
15
5
10
Oct. 2000 Ver 3.1a
29
HYUNDAI MicroElectronics
GMS90 Series
DC Characteristics for GMS97L51/52/54/56/58
VCC= 3.3V + 0.3V, -0.6V; VSS=0V; TA= 0°C to 70°C
Limit Values
Parameter
Symbol
Unit
Test Conditions
Min.
-0.5
2.0
max.
Input low voltage
Input high voltage
VIL
VIH
0.8
V
V
-
VCC + 0.5
-
OL= 1.6mA 1)
Output low voltage
(ports 1, 2, 3)
I
0.45
0.30
VOL
-
-
V
IOL= 100µA 1)
IOL= 3.2mA 1)
IOL= 200µA 1)
Output low voltage
(port 0, ALE, PSEN)
0.45
0.30
VOL1
V
V
Output high voltage
(ports 1, 2, 3)
IOH= -20µA
IOH= -10µA
2.0
0.9VCC
VOH
-
-
Output high voltage
(port 0 in external bus
mode, ALE, PSEN)
IOH= -800µA 2)
IOH= -80µA 2)
2.0
0.9VCC
VOH1
V
Logic 0 input current
(ports 1, 2, 3)
IIL
ITL
ILI
VIN= 0.45V
-1
-25
-
-50
-250
±1
µA
µA
µA
pF
Logical 1-to-0 transition cur-
rent (ports 1, 2, 3)
VIN= 2.0V
Input leakage current
(port 0, EA)
0.45 < VIN < VCC
Pin capacitance
fC= 1MHz
TA= 25°C
CIO
-
10
Power supply current:
Active mode, 12MHz 3)
Idle mode, 12MHz 3)
Power Down Mode 3)
VCC= 3.6V 4)
VCC= 2.6V 5)
VCC=2~ 5.5V 6)
ICC
ICC
IPD
-
-
-
15
5
mA
mA
µA
10
30
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
AC Characteristics
Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a ‘t’ (stand for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.
A: Address
T: Time
C: Clock
V: Valid
D: Input Data
W: WR signal
X: No longer a valid logic level
Z: Float
H: Logic level HIGH
I: Instruction (program memory contents)
L: Logic level LOW, or ALE
P: PSEN
For example,
Q: Output Data
t
AVLL = Time from Address Valid to ALE Low
R: RD signal
tLLPL = Time from ALE Low to PSEN Low
AC Characteristics for GMS90 series (12MHz version)
VCC= 5V :
VCC= 5V + 10%, − 15%; VSS= 0V; TA= 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
V
CC= 3.3V :
VCC= 3.3V + 0.3V, − 0.6V; VSS= 0V; TA= 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF)
Variable clock :
Vcc = 5V : 1/tCLCL = 3.5 MHz to 12 MHz
Vcc = 3.3V : 1/tCLCL = 1 MHz to 12 MHz
External Program Memory Characteristics
Variable Oscillator
1/tCLCL = 3.5 to 12MHz
12 MHz Oscillator
Parameter
Symbol
Unit
Min.
127
43
30
-
Max.
Min.
Max.
tLHLL
-
2tCLCL-40
-
ALE pulse width
ns
ns
ns
ns
ns
ns
ns
ns
tAVLL
tLLAX
tLLIV
-
tCLCL-40
-
Address setup to ALE
-
233
-
tCLCL-53
-
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
-
4tCLCL-100
tLLPL
tPLPH
tPLIV
tPXIX
58
215
-
tCLCL-25
-
-
3tCLCL-35
-
PSEN pulse width
150
-
-
0
-
3tCLCL-100
-
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
0
†
-
63
tCLCL-20
ns
ns
tPXIZ
†
75
-
tCLCL-8
-
Address valid after PSEN
tPXAV
Oct. 2000 Ver 3.1a
31
HYUNDAI MicroElectronics
GMS90 Series
Variable Oscillator
1/tCLCL = 3.5 to 12MHz
12 MHz Oscillator
Parameter
Symbol
Unit
Min.
Max.
302
-
Min.
Max.
tAVIV
tAZPL
-
-
5tCLCL-115
-
Address to valid instruction in
Address float to PSEN
ns
ns
0
0
†
Interfacing the GMS90 series to devices with float times up to 75 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
32
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
AC Characteristics for GMS90 series (12MHz)
External Data Memory Characteristics
Variable Oscillator
1/tCLCL = 3.5 to 12MHz
12 MHz Oscillator
Parameter
Symbol
Unit
Min.
400
400
53
-
Max.
Min.
Max.
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
-
6tCLCL-100
-
RD pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
6tCLCL-100
-
WR pulse width
tCLCL-30
-
Address hold after ALE
RD to valid data in
252
-
-
5tCLCL-165
0
0
-
Data hold after RD
-
97
517
585
300
-
-
2tCLCL-70
Data float after RD
-
-
8tCLCL-150
ALE to valid data in
Address to valid data in
ALE to WR or RD
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
-
-
9tCLCL-165
200
203
43
33
433
33
-
3tCLCL-50
4tCLCL-130
tCLCL-40
tCLCL-50
7tCLCL-150
tCLCL-50
-
3tCLCL+50
-
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
123
-
tCLCL+40
-
-
-
-
-
0
0
Advance Information (12MHz)
External Clock Drive
Variable Oscillator
(Freq. = 3.5 to 12MHz)
Parameter
Symbol
Unit
Min.
Max.
Oscillator period (VCC=5V)
Oscillator period (VCC=3.3V)
tCLCL
tCLCL
83.3
83.3
285.7
1
ns
tCHCX
tCLCX
tCLCH
tCHCL
20
20
-
tCLCL - tCLCX
ns
ns
ns
ns
High time
Low time
Rise time
Fall time
tCLCL - tCHCX
20
20
-
Oct. 2000 Ver 3.1a
33
HYUNDAI MicroElectronics
GMS90 Series
AC Characteristics for GMS90 series (16MHz version)
VCC= 3.3V + 0.3V, −0.6V; VSS= 0V; TA= 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF)
External Program Memory Characteristics
16 MHz Oscillator
Variable Oscillator
1/tCLCL = 3.5 to 16MHz
Parameter
Symbol
Unit
Min.
85
23
23
-
Max.
Min.
Max.
tLHLL
-
2tCLCL-40
-
ALE pulse width
ns
ns
ns
ns
ns
ns
ns
ns
tAVLL
tLLAX
tLLIV
-
-
tCLCL-40
-
Address setup to ALE
tCLCL-40
-
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
150
-
-
4tCLCL-100
tLLPL
tPLPH
tPLIV
tPXIX
38
153
-
tCLCL-25
-
-
3tCLCL-35
-
PSEN pulse width
88
-
-
0
-
3tCLCL-100
-
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
0
†
-
43
tCLCL-20
ns
ns
tPXIZ
†
55
-
tCLCL-8
-
Address valid after PSEN
Address to valid instruction in
Address float to PSEN
tPXAV
tAVIV
tAZPL
-
198
-
-
5tCLCL-115
-
ns
ns
0
0
†
Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
34
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
AC Characteristics for GMS90 series (16MHz)
External Data Memory Characteristics
Variable Oscillator
1/tCLCL = 3.5 to 16MHz
16 MHz Oscillator
Parameter
Symbol
Unit
Min.
275
275
23
-
Max.
Min.
Max.
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
-
6tCLCL-100
-
RD pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
6tCLCL-100
-
WR pulse width
tCLCL-40
-
Address hold after ALE
RD to valid data in
183
-
-
5tCLCL-130
0
0
-
Data hold after RD
-
75
350
398
238
-
-
2tCLCL-50
Data float after RD
-
-
8tCLCL-150
ALE to valid data in
Address to valid data in
ALE to WR or RD
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
-
-
9tCLCL-165
138
120
28
13
288
23
-
3tCLCL−50
4tCLCL-130
3tCLCL+50
-
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
97
-
t
t
CLCL−35
CLCL−50
tCLCL+35
-
-
-
7tCLCL-150
-
t
CLCL−40
-
0
-
0
Advance Information (16MHz)
External Clock Drive
Variable Oscillator
(Freq. = 3.5 to 16MHz)
Parameter
Symbol
Unit
Min.
Max.
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
62.5
17
17
-
285.7
tCLCL - tCLCX
tCLCL - tCHCX
17
Oscillator period
High time
ns
ns
ns
ns
ns
Low time
Rise time
-
17
Fall time
Oct. 2000 Ver 3.1a
35
HYUNDAI MicroElectronics
GMS90 Series
AC Characteristics for GMS90 series (24MHz version)
VCC= 5V + 10%, −15%; VSS= 0V; TA= 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
External Program Memory Characteristics
24 MHz Oscillator
Variable Oscillator
1/tCLCL = 3.5 to 24MHz
Parameter
Symbol
Unit
Min.
43
17
17
-
Max.
Min.
Max.
tLHLL
-
-
2tCLCL-40
-
ALE pulse width
ns
ns
ns
ns
ns
ns
ns
ns
tAVLL
tLLAX
tLLIV
tCLCL-25
-
Address setup to ALE
-
tCLCL-25
-
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
80
-
-
4tCLCL-87
tLLPL
tPLPH
tPLIV
tPXIX
22
95
-
tCLCL-20
-
-
3tCLCL-30
-
PSEN pulse width
60
-
-
0
-
3tCLCL-65
-
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
0
†
-
32
tCLCL-10
ns
ns
tPXIZ
†
37
-
tCLCL-5
-
Address valid after PSEN
Address to valid instruction in
Address float to PSEN
tPXAV
tAVIV
tAZPL
-
148
-
-
5tCLCL-60
-
ns
ns
0
0
†
Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
36
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
AC Characteristics for GMS90 series (24MHz)
External Data Memory Characteristics
Variable Oscillator
1/tCLCL = 3.5 to 24MHz
24 MHz Oscillator
Parameter
Symbol
Unit
Min.
180
180
15
-
Max.
Min.
Max.
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
-
6tCLCL-70
-
RD pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
6tCLCL-70
-
WR pulse width
tCLCL-27
-
Address hold after ALE
RD to valid data in
118
-
-
5tCLCL-90
0
0
-
Data hold after RD
-
63
200
220
175
-
-
-
2tCLCL-20
Data float after RD
-
8tCLCL-133
ALE to valid data in
Address to valid data in
ALE to WR or RD
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
-
-
9tCLCL-155
75
67
17
5
3tCLCL-50
4tCLCL-97
tCLCL-25
tCLCL-37
7tCLCL-122
tCLCL-27
-
3tCLCL+50
-
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
67
-
tCLCL+25
-
-
170
15
-
-
-
-
0
0
Advance Information (24MHz)
External Clock Drive
Variable Oscillator
(Freq. = 3.5 to 24MHz)
Parameter
Symbol
Unit
Min.
Max.
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
41.7
12
12
-
285.7
tCLCL - tCLCX
tCLCL - tCHCX
12
Oscillator period
High time
ns
ns
ns
ns
ns
Low time
Rise time
-
12
Fall time
Oct. 2000 Ver 3.1a
37
HYUNDAI MicroElectronics
GMS90 Series
AC Characteristics for GMS90 series (33MHz version)
VCC= 5V + 10%, −15%; VSS= 0V; TA= 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
External Program Memory Characteristics
33 MHz Oscillator
Variable Oscillator
1/tCLCL = 3.5 to 33MHz
Parameter
Symbol
Unit
Min.
40
10
10
-
Max.
Min.
Max.
tLHLL
-
-
2tCLCL-20
-
ALE pulse width
ns
ns
ns
ns
ns
ns
ns
ns
tAVLL
tLLAX
tLLIV
tCLCL-20
-
Address setup to ALE
-
tCLCL-20
-
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
56
-
-
4tCLCL-65
tLLPL
tPLPH
tPLIV
tPXIX
15
80
-
tCLCL-15
-
-
3tCLCL-20
-
PSEN pulse width
35
-
-
0
-
3tCLCL-55
-
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
0
†
-
20
tCLCL-10
ns
ns
tPXIZ
†
25
-
tCLCL-5
-
Address valid after PSEN
Address to valid instruction in
Address float to PSEN
tPXAV
tAVIV
tAZPL
-
91
-
-
5tCLCL-60
-
ns
ns
0
0
†
Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
38
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
AC Characteristics for GMS90 series (33MHz)
External Data Memory Characteristics
Variable Oscillator
1/tCLCL = 3.5 to 33MHz
33 MHz Oscillator
Parameter
Symbol
Unit
Min.
132
132
10
-
Max.
Min.
Max.
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
-
-
6tCLCL-50
-
RD pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6tCLCL-50
-
WR pulse width
-
tCLCL-20
-
Address hold after ALE
RD to valid data in
81
-
-
5tCLCL-70
0
0
-
Data hold after RD
-
46
153
183
111
-
-
2tCLCL-15
Data float after RD
-
-
8tCLCL-90
ALE to valid data in
Address to valid data in
ALE to WR or RD
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
-
-
9tCLCL-90
71
66
10
5
3tCLCL-20
4tCLCL-55
tCLCL-20
tCLCL-25
7tCLCL-70
tCLCL-20
-
3tCLCL+20
-
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
40
-
tCLCL+20
-
-
142
10
-
-
-
-
0
0
Advance Information (33MHz)
External Clock Drive
Variable Oscillator
(Freq. = 3.5 to 24MHz)
Parameter
Symbol
Unit
Min.
Max.
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
30.3
11.5
11.5
-
285.7
Oscillator period
High time
ns
ns
ns
ns
ns
tCLCL - tCLCX
tCLCL - tCHCX
Low time
5
5
Rise time
-
Fall time
Oct. 2000 Ver 3.1a
39
HYUNDAI MicroElectronics
GMS90 Series
AC Characteristics for GMS90 series (40MHz version)
VCC= 5V + 10%, − 15%; VSS= 0V; TA= 0°C to 70°C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
External Program Memory Characteristics
40 MHz Oscillator
Variable Oscillator
1/tCLCL = 3.5 to 40MHz
Parameter
Symbol
Unit
Min.
35
10
10
-
Max.
Min.
Max.
tLHLL
-
-
2tCLCL−15
-
ALE pulse width
ns
ns
ns
ns
ns
ns
ns
ns
tAVLL
tLLAX
tLLIV
t
t
CLCL−15
CLCL−15
-
-
Address setup to ALE
-
-
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
55
-
4tCLCL−45
tLLPL
tPLPH
tPLIV
tPXIX
10
60
-
t
CLCL−15
-
-
3tCLCL−15
-
PSEN pulse width
25
-
-
0
-
3tCLCL−50
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
0
-
†
-
15
t
CLCL−10
ns
ns
tPXIZ
†
20
-
t
CLCL−5
-
Address valid after PSEN
Address to valid instruction in
Address float to PSEN
tPXAV
tAVIV
tAZPL
-
65
-
-
5tCLCL−60
ns
ns
5
5
-
†
Interfacing the GMS90 series to devices with float times up to 20 ns is permissible. This limited bus contention will not cause
any damage to port 0 Drivers.
40
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
AC Characteristics for GMS90 series (40MHz)
External Data Memory Characteristics
Variable Clock
1/tCLCL = 3.5 to 40MHz
at 40 MHz Clock
Parameter
Symbol
Unit
Min.
120
120
10
-
Max.
Min.
Max.
tRLRH
tWLWH
tLLAX2
tRLDV
tRHDX
tRHDZ
tLLDV
-
-
6tCLCL-30
-
RD pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6tCLCL-30
-
WR pulse width
-
tCLCL-15
-
Address hold after ALE
RD to valid data in
75
-
-
5tCLCL-50
0
0
-
Data hold after RD
-
38
150
150
90
-
-
2tCLCL-12
Data float after RD
-
-
8tCLCL-50
ALE to valid data in
Address to valid data in
ALE to WR or RD
tAVDV
tLLWL
tAVWL
tWHLH
tQVWX
tQVWH
tWHQX
tRLAZ
-
-
9tCLCL-75
60
70
10
5
3tCLCL-15
4tCLCL-30
tCLCL-15
tCLCL-20
7tCLCL-50
tCLCL-20
-
3tCLCL+15
-
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
40
-
tCLCL+15
-
-
125
5
-
-
-
-
0
0
Advance Information (40MHz)
External Clock Drive
Variable Oscillator
(Freq. = 3.5 to 40MHz)
Parameter
Symbol
Unit
Min.
Max.
tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
25
10
10
-
285.7
tCLCL - tCLCX
tCLCL - tCHCX
10
Oscillator period
High time
ns
ns
ns
ns
ns
Low time
Rise time
-
10
Fall time
Oct. 2000 Ver 3.1a
41
HYUNDAI MicroElectronics
GMS90 Series
t
LHLL
ALE
t
LLPL
t
t
PLPH
AVLL
t
LLIV
t
PLIV
PSEN
t
t
PXAV
PXIZ
t
AZPL
t
LLAX
t
PXIX
INSTR.
IN
A0-A7
A0-A7
PORT 0
PORT 2
t
AVIV
A8-A15
A8-A15
Figure 4. External Program Memory Read Cycle
42
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
ALE
t
LHLL
t
WHLH
PSEN
RD
t
LLDV
t
t
RLRH
LLWL
t
RHDZ
t
AVLL
t
RLDV
t
t
LLAX2
t
RHDX
DATA IN
RLAZ
A0-A7 from
RI or DPL
A0-A7 from PCL
INSTR. IN
PORT 0
PORT 2
t
AVWL
t
AVDV
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 5. External Data Memory Read Cycle
ALE
t
LHLL
t
WHLH
PSEN
WR
t
t
WLWH
LLWL
t
QVWX
t
t
WHQX
AVLL
t
LLAX2
t
QVWH
A0-A7 from
RI or DPL
A0-A7 from PCL
DATA OUT
INSTR. IN
PORT 0
PORT 2
t
AVWL
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 6. External Data Memory Write Cycle
Oct. 2000 Ver 3.1a
43
HYUNDAI MicroElectronics
GMS90 Series
V
−0.5V
CC
0.2V + 0.9
CC
Test Points
0.2V − 0.1
CC
0.45V
AC Inputs during testing are driven at VCC−0.5V for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made a VIHmin for a logic ‘1’ and VILmax for a logic ‘0’.
Figure 7. AC Testing: Input, Output Waveforms
V
+ 0.1
− 0.1
V
− 0.1
+ 0.1
LOAD
OH
Timing Reference Points
0.2V − 0.1
V
LOAD
CC
V
V
OL
LOAD
For timing purposes a port pin is no longer floating when a 100mV change from load voltage
occurs and begins to float when a 100mV change from the loaded VOH / VOL level occurs.
IOL / IOH ≥ 20mA.
Figure 8. Float Waveforms
t
CLCL
V
−0.5V
CC
0.7 V
CC
0.2 V −0.1
CC
0.45V
t
t
CLCX
CHCX
t
CLCH
t
CHCL
Figure 9. External Clock Cycle
44
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
OSCILLATOR CIRCUIT
CRYSTAL OSCILLATOR MODE
DRIVING FROM EXTERNAL SOURCE
C2
C1
N.C.
XTAL2
XTAL2
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
P-LCC-44/Pin 20
P-DIP-40/Pin 18
M-QFP-44/Pin 14
External Oscillator
Signal
XTAL1
XTAL1
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
P-LCC-44/Pin 21
P-DIP-40/Pin 19
M-QFP-44/Pin 15
C1, C2 = 30pF ±10pF for Crystals
For Ceramic Resonators, contact resonator manufacturer.
Figure 10. Recommended Oscillator Circuits
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal
and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for ap-
propriate values of external components.
Oct. 2000 Ver 3.1a
45
HYUNDAI MicroElectronics
GMS90 Series
OTP ROM Verification Characteristics
ROM Verification Mode 1
Limit Values
Max.
Parameter
Symbol
Unit
Min.
tAVQV
tCLCL
tEHQZ
1/tCLCL
-
-
48tCLCL
48tCLCL
48tCLCL
6
Address to valid data
ENABLE to valid data
Data float after ENABLE
Oscillator frequency
ns
0
4
MHz
P1.0-P1.7
P2.0-P2.4
Address
t
AVQV
Data Out
PORT 0
t
ELQV
t
EHQZ
P2.7
ENABLE
P1.0-P1.7 = A0-A7
P2.0-P2.5 = A8-A13
P3.4 = A14
Input:
Address:
Data:
P2.6-P2.7, PSEN = VSS
ALE = VIH
EA, RESET = VIH2
P0.0-P0.7 = D0-D7
Figure 11. OTP ROM Verification Mode 1
46
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
EPROM CHARACTERISTICS
The GMS97C5X, 97L5X are programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It dif-
fers from older methods in the value used for VPP (programming supply voltage) and in the width and number
of the ALE/PROG pulses. The GMS97C5X, 97L5X contains two signature bytes that can be read and used by
an EPROM programming system to identify the device. The signature bytes identify the device as an manufac-
tured by HME. Table 11 shows the logic levels for reading the signature byte, and for programming the program
memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figure 12 and Figure 13. Figure 14 show the circuit configuration for normal pro-
gram memory verification.
Reading the Signature Bytes :
The GMS97X51/52 signature bytes in locations 030H and 031H, the GMS97X54/56/58 signature bytes in loca-
tions 05EH and 07CH. To read these bytes follow the procedure for EPROM verify, except that P3.6 and P3.7
need to be pulled to a logic low.
The values are:
Device
Location
Contents
Remarks
GMS97X51
30H
31H
E0H
73H
Manufacturer ID
Device ID
GMS97X52
GMS97X54
GMS97X56
GMS97X58
30H
31H
E0H
71H
Manufacturer ID
Device ID
5EH
7CH
E0H
54H
Manufacturer ID
Device ID
5EH
7CH
E0H
56H
Manufacturer ID
Device ID
5EH
7CH
E0H
58H
Manufacturer ID
Device ID
Quick-pulse programming
The setup for microcontroller quick-pulse programming is shown in Figure 13. Note that the GMS97C5X,
97L5X is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device
is executing internal address and program data transfers.
The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 12. The
code byte to be programmed into that location is applied to port 0, RST, PSENand pins of port 2 and 3 in Table
11 are held at the "Program Code Data" levels indicated in Table 11. The ALE/PROGis pulsed low 25 times(10
times for 97X54/56/58) as shown Figure 13.
To program the encryption table, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence for
addresses 0 through 1FH(3FH for 97X54/56/58), using the "Program Encryption Table" levels. Do not forget
that after the encryption table is programmed, verification cycles will produce only encrypted data.
To program the security bits, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence using the
"Pgm Security Bit" levels after one security bit is programmed, further programming of the code memory and
Oct. 2000 Ver 3.1a
47
HYUNDAI MicroElectronics
GMS90 Series
encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/VPP pin
must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch
above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free
glitches and overshoot.
+5V
V
CC
P1
A0-A7
PROGRAM DATA
+12.75V
P0
P2.0
-P2.5
A8-A13
EA/V
PP
P3.4
A14
1
1
1
RST
P3.6
P3.7
☞NOTE
ALE/PROG
0
1
PSEN
P2.7
XTAL2
XTAL1
4~6MHz
P2.6
1
V
SS
NOTE:
GMS97X51/52:
100µs × 25 pulses to GND
GMS97X54/56/58: 100µs × 10 pulses to GND
Figure 12. Programming Configuration
Program Verification
If security bit 2 has not been programmed, the on-chip program memory can be read out for program verifica-
tion. The address of the program memory location to be read is applied to ports 1 and 2 as shown in Figure 15.
The other pins are held at the "Verify Code Data" levels indicated in Table 11. The contents of the address lo-
cation will be emitted on port 0 for this operation. If the encryption table has been programmed, the data pre-
sented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will
have to know the encryption table contents in order to correctly decode the verification data. The encryption
table itself cannot be read out.
48
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
Program Memory Lock Bits
Lock Bit Protection Modes
The two-level Program Lock system consists of 2
Lock bits and a 32-byte (64-byte for GMS97X54/
56/58) Encryption Array which are used to protect
the program memory against software piracy.
Mode LB1 LB2
Protection Type
1
2
U
P
U
U
No program lock features
Further programming of the
EPROM is disabled
Encryption Array:
3
P
P
Same as mode 2, also verify is
disabled
Within the EPROM array are 32 bytes (64 bytes
for GMS97X54/56/58) of Encryption Array that
are initially unprogrammed (all 1s). Every time
that a byte is addressed during a verify, address
U: unprogrammed, P: programmed
lines are used to select a byte of the Encryption array. This byte is then exclusive-NORed (XNOR) with the code
byte, creating an Encrypted Verify byte.
The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, unmodified
form, It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be pro-
grammed as well.
Program / Verify algorithms
Any algorithm in agreement with the conditions listed in Table 11, and which satisfies the timing specifications
is suitable.
Table 11. EPROM programming modes
EA/
VPP
ALE/
PROG
MODE
RST
PSEN
P2.7
P2.6
P3.7
P3.6
Read Signature
1
1
1
1
1
1
0
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
0
0
1
1
0
1
0
VPP
1
Program Code Data
Verify Code Data
VPP
VPP
VPP
Program encryption table
Program security bit 1
Program security bit 2
Notes:
1. “0” = Valid low for that pin, "1" = valid high for that pin.
2. VPP = 12.75V ± 0.25V
3. VCC = 5V ± 10% during programming and verification.
4. ALE/PROG receives 25 (10 for GMS97X54/56/58) programming pulses while VPP is held at 12.75V.
Each programming pulse is low for 100us (± 10us) and high for a minimum of 10µs.
Oct. 2000 Ver 3.1a
49
HYUNDAI MicroElectronics
GMS90 Series
25 PULSES
In the GMS97X51/52
ALE/PROG
Min. 10µs
100µs ±10
100µs ±10
Enlarged View
10 PULSES
In the GMS97X54/56/58
ALE/PROG
Figure 13. PROG Waveform
+5V
V
CC
P1
10kΩ
A0-A7
P2.0
-P2.5
PROGRAM DATA
P0
A8-A13
A14
P3.4
EA/V
1
PP
1
1
1
RST
P3.6
P3.7
1
0
0
ALE/PROG
PSEN
P2.7
XTAL2
XTAL1
4~6MHz
1
P2.6
V
SS
Figure 14. Program Verification
50
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
EPROM Programming and Verification Characteristics
TA= 21°C to 27°C, VCC= 5V + 10%, − 15%; VSS=0V;
Limit Values
Parameter
Symbol
Unit
Min.
Max.
VPP
IPP
12.5
13.0
V
Programming supply voltage
Programming supply current
Oscillator frequency
-
50
mA
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGL
tAVQV
tELQV
tEHQZ
tGHGL
4
6
MHz
48tCLCL
-
-
-
Address setup to PROG low
Address hold after PROG
Data setup to PROG
48tCLCL
-
48tCLCL
-
-
48tCLCL
-
-
Data hold after PROG
P2.7 (ENABLE) high to VPP
VPP setup to PROG
48tCLCL
-
-
10
10
90
-
-
-
µs
µs
µs
-
VPP hold after PROG
110
PROG width
48tCLCL
48tCLCL
48tCLCL
-
Address to data valid
-
-
ENABLE low to data valid
Data float after ENABLE
PROG high to PROG low
0
-
10
µs
PROGRAMMING
VERIFICATION
P1.0-P1.7
P2.0-P2.5
P3.4
ADDRESS
ADDRESS
DATA OUT
t
AVQV
PORT 0
DATA IN
t
DVGL
t
GHDX
25 or 10
PULSES
t
t
AVGL
GHAX
ALE/PROG
t
t
SHGL
GHGL
t
GHSL
tG LG L
V
PP
EA/V
PP
TTL HIGH
TTL HIGH
TTL HIGH
t
ELQV
t
t
EHQZ
EHSH
P2.7
(ENABLE)
Figure 15. EPROM Programming and Verification
Oct. 2000 Ver 3.1a
51
HYUNDAI MicroElectronics
GMS90 Series
Plastic Package P-LCC-44
(Plastic Leaded Chip-Carrier)
44PLCC
UNIT: INCH
0.695
0.685
min. 0.020
0.656
0.650
0.012
0.0075
0.050 BSC
0.120
0.090
0.180
0.165
52
Oct. 2000 Ver 3.1a
GMS90 Series
HYUNDAI MicroElectronics
Plastic Package P-DIP-40
(Plastic Dual in-Line Package)
40DIP
UNIT: INCH
2.075
2.045
0.600 BSC
0.550
0.530
0.022
0.015
0.065
0.045
0.100 BSC
0-15°
Oct. 2000 Ver 3.1a
53
HYUNDAI MicroElectronics
GMS90 Series
Plastic Package P-MPQF-44
(Plastic Metric Quad Flat Package)
44MQFP
13.45
12.95
UNIT: MM
10.10
9.90
0-7°
SEE DETAIL "A"
1.03
0.73
2.35 max.
1.60
REF
0.45
0.30
0.80 BSC
DETAIL "A"
54
Oct. 2000 Ver 3.1a
MASK ORDER & VERIFICATION SHEET
GMS90X5X-GB
Customer should write inside thick line box.
1. Customer Information
2. Device Information
Package
ROM size
Vol. / Freq.
12MHz
Company Name
44MQFP
44PLCC
40PDIP
4K
Application
8K
5V
3V
24MHz
40MHz
12MHz
16MHz
YYYY
M M
DD
16K
24K
32K
Order Date
Tel:
Fax:
Name &
Signature:
ROM: 4K,8K
ROM: 16,24,32K
ROM Protection
Without
Normal
Super
File Name: (
.HEX)
Check Sum:
Internet
Chollian
Hitel
3. Marking Specification
(Please check mark into
)
40PDIP or 44PLCC
44MQFP
HME
GMS90
HME
5
90
➀
ROM size
1: 4K
2: 8K
➁
➀
C: 5V
L: 3V
5
-GB
➁
-GB
➁
➀
4: 16K
6: 24K
8: 32K
YYW W
KOREA
YYW W
KOREA
SIEMENS ’92
SIEMENS ’92
Customer’s part number
4. Delivery Schedule
Quantity
Date
LG Confirmation
YYYY
MM
DD
DD
pcs
pcs
Customer Sample
Risk Order
YYYY
MM
5. ROM Code Verification
This box is written after “5.Verification”.
YYYY
MM
DD
YYYY
MM
DD
Verification Date:
Approval Date:
Please confirm our verification data.
I agree with your verification data and confirm you to
m ake m ask set.
Check Sum:
Fax:
Tel:
Fax:
Tel:
Name &
Signature:
Name &
Signature:
HYUNDAI MicroElectronics
相关型号：
©2020 ICPDF网 联系我们和版权申明