H5MS1222EFP-J3E_技术文档

128Mbit MOBILE DDR SDRAM based on 1M x 4Bank x32 I/O

Specification of

128M (4Mx32bit) Mobile DDR SDRAM

Memory Cell Array

- Organized as 4banks of 1,048,576 x32

This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for

use of circuits described. No patent licenses are implied.

Rev 1.0 / Jun. 2008

1

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Document Title

128MBit (4Bank x 1M x 32bits) MOBILE DDR SDRAM

Revision History

Revision No.

History

Draft Date

Remark

0.1

- Initial Draft

Sep. 2007

Preliminary

- Define

IDD specification

0.2

0.3

0.4

1.0

Feb. 2008

May. 2008

Jun. 2008

Preliminary

- Correct

tREFi specification

- Modify

IDD values

-. Modify

IDD Values(p22,p23) , AC Characteristics(p.24)

Rev 1.0 / Jun. 2008

2

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

FEATURES SUMMARY

●Mobile DDR SDRAM

●MODE RERISTER SET, EXTENDED MODE REGIS-

TER SET and STATUS REGISTER READ

- Keep to the JEDEC Standard regulation

(Low Power DDR SDRAM)

- Double data rate architecture: two data transfer per

clock cycle

●Mobile DDR SDRAM INTERFACE

- x32 bus width: HY5MS5B2ALFP

- Multiplexed Address (Row address and Column ad-

dress)

●CAS LATENCY

- Programmable CAS latency 2 or 3 supported

●BURST LENGTH

●SUPPLY VOLTAGE

- Programmable burst length 2 / 4 / 8 with both sequen-

tial and interleave mode

- 1.8V device: VDD and VDDQ = 1.7V to 1.95V

●MEMORY CELL ARRAY

●AUTO PRECHARGE

- 128Mbit (x32 device) = 1M x 4Bank x 32 I/O

- Option for each burst access

●DATA STROBE

●AUTO REFRESH AND SELF REFRESH MODE

- x32 device: DQS0 ~ DQS3

- Bidirectional, data strobe (DQS) is transmitted and re-

ceived with data, to be used in capturing data at the

receiver

●CLOCK STOP MODE

- Clock stop mode is a feature supported by Mobile DDR

SDRAM.

- Data and data mask referenced to both edges of DQS

- Keep to the JEDEC Standard regulation

●LOW POWER FEATURES

●INITIALIZING THE MOBILE DDR SDRAM

- Occurring at device power up or interruption of device

power

- PASR (Partial Array Self Refresh)

- AUTO TCSR (Temperature Compensated Self Refresh)

- DS (Drive Strength)

- DPD (Deep Power Down): DPD is an optional feature,

so please contact Hynix office for the DPD feature

●PACKAGE

- HY5MS5B2ALFP: 90 Ball Lead free FBGA

●INPUT CLOCK

- Differential clock inputs (CK, CK)

●Data MASK

- DM0 ~ DM3: Input mask signals for write data

- DM masks write data-in at the both rising and

falling edges of the data strobe

Rev 1.0 / Jun. 2008

3

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

DESCRIPTION

The Hynix H5MS1222EFP Series is 134,217,728-bit CMOS Low Power Double Data Rate Synchronous DRAM (Mobile

DDR SDRAM), ideally suited for mobile applications which use the battery such as PDAs, 2.5G and 3G cellular phones

with internet access and multimedia capabilities, mini-notebook, hand-held PCs. It is organized as 4banks of 1,048,576

x32.

The HYNIX H5MS1222EFP series uses a double-data-rate architecture to achieve high-speed operation. The double

data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data per clock

cycle at the I/O pins.

The Hynix H5MS1222EFP Series offers fully synchronous operations referenced to both rising and falling edges of the

clock. While all address and control inputs are latched on the rising edges of the CK (Mobile DDR SDRAM operates

from a differential clock: the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK),

data, data strobe and data mask inputs are sampled on both rising and falling edges of it (Input data is registered on

both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK). The data

paths are internally pipelined and 2-bit prefetched to achieve high bandwidth. All input voltage levels are compatible

with LVCMOS.

Read and write accesses to the Low Power DDR SDRAM (Mobile DDR SDRAM) are burst oriented; accesses start at a

selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with

the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits reg-

istered coincident with the ACTIVE command are used to select the bank and the row to be accessed. The address bits

registered coincident with the READ or WRITE command are used to select the bank and the starting column location

for the burst access.

The Low Power DDR SDRAM (Mobile DDR SDRAM) provides for programmable read or write bursts of 2, 4 or 8 loca-

tions. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end

of the burst access.

As with standard SDRAM, the pipelined and multibank architecture of Low Power DDR SDRAM (Mobile DDR SDRAM)

allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation

times.

The Low Power DDR SDRAM (Mobile DDR SDRAM) also provides for special programmable Self Refresh options which

are Partial Array Self Refresh (full, half, quarter and 1/8 and 1/16 array) and Temperature Compensated Self Refresh.

A burst of Read or Write cycles in progress can be interrupted and replaced by a new burst Read or Write command on

any cycle (this pipelined design is not restricted by a 2N rule). Only Read bursts in progress with auto precharge disa-

bled can be terminated by a burst terminate command. Burst Terminate command is undefined and should not be

used for Read with Autoprecharge enabled and for Write bursts.

Rev 1.0 / Jun. 2008

4

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

The Hynix H5MS1222EFP series has the special Low Power function of Auto TCSR (Temperature Compensated Self

Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implemented, it enables

to automatically adjust refresh rate according to temperature without external EMRS command.

Deep Power Down Mode is an additional operating mode for Low Power DDR SDRAM (Mobile DDR SDRAM). This mode

can achieve maximum power reduction by removing power to the memory array within Low Power DDR SDRAM

(Mobile DDR SDRAM). By using this feature, the system can cut off almost all DRAM power without adding the cost of

a power switch and giving up mother-board power-line layout flexibility.

All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).

The Hynix H5MS1222EFP series is available in the following package:

- 90Ball FBGA [size: 8mm x 13mm, t=1.0mm max]

128Mb Mobile DDR SDRAM ORDERING INFORMATION

Package

Part Number

Clock Frequency

Organization

Interface

Temp.

H5MS1222EFP-Q3E 185MHz(CL3) / 83MHz(CL2)

H5MS1222EFP-J3E 166MHz(CL3) / 83MHz(CL2)

H5MS1222EFP-K3E 133MHz(CL3) / 83MHz(CL2)

H5MS1222EFP-L3E 100MHz(CL3) / 66MHz(CL2)

H5MS1222EFP-Q3M 185MHz(CL3) / 83MHz(CL2)

H5MS1222EFP-J3M 166MHz(CL3) / 83MHz(CL2)

H5MS1222EFP-K3M 133MHz(CL3) / 83MHz(CL2)

H5MS1222EFP-L3M 100MHz(CL3) / 66MHz(CL2)

Extended

Temp. :-25^oC

~ 85^oC

90Ball Lead

Free

4banks x 1Mb x 32

LVCMOS

Mobile Temp.

: -30^oC ~

85^oC

90Ball Lead

Free

Rev 1.0 / Jun. 2008

5

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

INFORMATION for Hynix KNOWN GOOD DIE

With the advent of Multi-Chip package (MCP), Package on Package (PoP) and System in a Package (SiP) applications,

customer demand for Known Good Die (KGD) has increased.

Requirements for smaller form factors and higher memory densities are fueling the need for Wafer-level memory solu-

tions due to their superior flexibility. Hynix Known Good Die (KGD) products can be used in packaging technologies

such as systems-in-a-package (SIP) and multi-chip package (MCP) to reduce the board area required, making them

ideal for hand-held PCs, and many other portable digital applications.

Hynix Mobile SDRAM will be able to continue its constant effort of enabling the advanced package products of all appli-

cation customers.

- Please Contact Hynix Office for Hynix KGD product availability and informations.

Rev 1.0 / Jun. 2008

6

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

90Ball FBGA ASSIGNMENT

1

2

3

4

5

6

7

8

9

VSS DQ31 VSSQ

VDDQ DQ29 DQ30

VSSQ DQ27 DQ28

VDDQ DQ25 DQ26

VSSQ DQS3 DQ24

VDDQ DQ16 VDD

DQ17 DQ18 VSSQ

DQ19 DQ20 VDDQ

DQ21 DQ22 VSSQ

DQ23 DQS2 VDDQ

A

B

C

D

E

F

VDD

CKE

A9

DM3

CK

NC

/CK

NC

A8

NC

DM2

VSS

/WE /CAS /RAS

G

H

J

A11

A7

/CS

A10

A2

BA0

A0

BA1

A1

Top view

A6

A4

DM1

A5

DM0

A3

K

L

VSSQ DQS1 DQ8

VDDQ DQ9 DQ10

VSSQ DQ11 DQ12

VDDQ DQ13 DQ14

VSS DQ15 VSSQ

DQ7 DQS0 VDDQ

DQ5

DQ3

DQ1

DQ6 VSSQ

DQ4 VDDQ

DQ2 VSSQ

M

N

P

VDDQ DQ0

VDD

R

Rev 1.0 / Jun. 2008

7

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Mobile DDR SDRAM PIN DESCRIPTIONS

SYMBOL

TYPE

DESCRIPTION

Clock: CK and CK are differential clock inputs. All address and control input signals are

CK, CK

INPUT sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read)

data is referenced to the crossings of CK and CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, device

input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN

INPUT and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in

any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is

achieved asynchronously.

CKE

CS

Chip Select: CS enables (registered LOW) and disables (registered HIGH) the command

decoder. All commands are masked when CS is registered HIGH. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the command

INPUT

code.

RAS, CAS, WE INPUT Command Inputs: RAS, CAS and WE (along with CS) define the command being entered

Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or

BA0, BA1

INPUT PRECHARGE command is being applied. BA0 and BA1 also determine which mode register

is to be loaded during a MODE REGISTER SET command (MRS, EMRS or SRR).

Address inputs: Provide the row address for ACTIVE commands, and the column address

and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the

memory array in the respective bank. The address inputs also provide the op-code during

a MODE REGISTER SET command. A10 sampled during a PRECHARGE command deter-

mines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH).

A0 ~ A11

INPUT

If only one bank is to be precharged, the bank is selected by BA0, BA1.

For 128Mb (x32), Row Address: A0 ~ A11, Column Address: A0 ~ A7

Auto-precharge flag: A10

DQ0 ~ DQ31

DM0 ~ DM3

I/O

Data Bus: data input / output pin

Input Data Mask: DM is an input mask signal for write data. Input data is masked when

DM is sampled. HIGH along with that input data during a WRITE access. DM is sampled

on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ

INPUT and DQS loading.

For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data

on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, and DM3 corresponds to the

data on DQ24-DQ31.

Data Strobe: Output with read data, input with write data. Edge-aligned with read data,

center-aligned with write data. Used to capture write data. For x32 device, DQS0 corre-

sponds to the data on DQ0-DQ7, DQS1 corresponds to the data on DQ8-DQ15, DQS2 cor-

responds to the data on DQ16-DQ23, and DQS3 corresponds to the data on DQ24-DQ31.

DQS0 ~ DQS3

I/O

VDD

VSS

SUPPLY Power supply

SUPPLY Ground

VDDQ

VSSQ

NC

SUPPLY I/O Power supply

SUPPLY I/O Ground

-

No Connect: No internal electrical connection is present.

Rev 1.0 / Jun. 2008

8

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

FUNCTIONAL BLOCK DIAGRAM

1Mbit x 4banks x 32 I/O Mobile DDR SDRAM

PASR

Extended

Self refresh

Mode

Write Data Register

32

logic & timer

Register

2-bit Prefetch Unit

DS

64

Internal Row

Counter

1Mx32 Bank3

1Mx32 Bank2

1Mx32 Bank1

1Mx32 Bank0

/CLK

CLK

CKE

/CS

Row

Pre

Decoder

Row Active

DQ0

Refresh

/RAS

Memory

Cell

64

32

Array

/CAS

/WE

Column Active

Column

Pre

Decoder

DQ31

DM0

~DM3

Column decoders

Column Add

Counter

DQS0

~

Bank Select

DQS3

Address

Register

A0

A1

Burst

Counter

Data Strobe

Transmitter

Data Strobe

Receiver

DS

CAS

Latency

A11

BA1

BA0

Mode Register

Data Out Control

Rev 1.0 / Jun. 2008

9

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

REGISTER DEFINITION I

Mode Register Set (MRS) for Mobile DDR SDRAM

BA1

BA0

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

0

CAS Latency

BT

Burst Length

Burst Type

A3

0

Burst Type

Sequential

Interleave

1

CAS Latency

Burst Length

A6

0

A5

0

A4

0

CAS Latency

R e s e r v e d

2

Burst Length

A2

A1

A0

A3 = 0

A3=1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

2

Reserved

2

0

1

0

1

3

4

1

0

Reserved

R e s e r v e d

Reserved

8

1

0

1

Reserved

1

0

1

Rev 1.0 / Jun. 2008

10

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

REGISTER DEFINITION II

Extended Mode Register Set (EMRS) for Mobile DDR SDRAM

BA1

BA0

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

1

0

DS

0

PASR

DS (Drive Strength)

Drive

Strength

A6

A5

0

1

0

1

0

1

Full

Half (Default)

Quarter

Octant

PASR (Partial Array Self Refresh)

A2

0

A1

0

A0 Self Refresh Coverage

0

1

0

1

0

All Banks (Default)

Half of Total Bank (BA1=0)

0

1

Quarter of Total Bank (BA1=BA0=0)

0

1

Reserved

1

0

One Eighth of Total Bank

(BA1 = BA0 = Row Address MSB=0)

1

0

1

One Sixteenth of Total Bank

(BA1 = BA0 = Row Address 2 MSBs=0)

1

0

1

Reserved

Rev 1.0 / Jun. 2008

11

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

REGISTER DEFINITION III

Status Register (SR) for Mobile DDR SDRAM

BA1

BA0

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

0

1

0

DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Density

0

-

DW

1

Refresh Rate

X

Revision Identification

X¹⁾X¹⁾X¹⁾X¹⁾

Manufacturers Identification

0

1

0

X

0

1

0

Refresh Rate

DQ10 DQ9 DQ8 Refresh Rate

DW (Device Width)

0

1

0

1

0

1

x

0

1

0

1

0

1

4²⁾

4

DQ11 Device Width

2

0

1

16 bits

32 bits

1

0.5

0.25

0.25³⁾

Density

DQ15 DQ14 DQ13 Density

0

1

0

1

0

1

0

1

0

1

0

1

0

1

128

256

Manufacturers Identification

DQ3 DQ2 DQ1 DQ0 Manufacturer

512

1024

Reserved

0

1

0

Hynix

Reserved or

other companies

x

Note)

1. The revision number starts at ‘0000’ and increments by ‘0001’ each time a change in the manufacturer’s specification, IBIS, or

process occurs.

2. Low temperature out of range.

3. High temperature out of range - no refresh rate can guarantee functionality.

4. The refresh rate multiplier is based on the memory’s temperature sensor.

5. Required average periodic refresh interval = tREFI * multiplier.

6. Status Register is only for Read.

7. To read out Status Register values, BA[1:0] set to 01b and A[11:0] set to all 0 with MRS command followed by Read command

with that BA[1:0] and A[11:0] are Don’t care.

Rev 1.0 / Jun. 2008

12

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

COMMAND TRUTH TABLE

Function

CS

RAS

CAS

WE

BA A10/AP ADDR Note

DESELECT (NOP)

H

L

X

H

L

X

H

L

X

H

X

V

X

2

NO OPERATION (NOP)

ACTIVE (Select Bank and activate Row)

READ (Select bank and column and start read burst)

READ with AP (Read Burst with Autoprecharge)

Row

L

Row

Col

H

L

H

3

WRITE (Select bank and column and start write

burst)

L

H

L

V

L

Col

WRITE with AP (Write Burst with Autoprecharge)

BURST TERMINATE or enter DEEP POWER DOWN

PRECHARGE (Deactivate Row in selected bank)

PRECHARGE ALL (Deactivate rows in all Banks)

AUTO REFRESH or enter SELF REFRESH

MODE REGISTER SET

L

H

L

H

L

H

L

V

X

V

X

V

H

X

L

Col

X

3

4, 5

6

X

L

H

X

6

L

X

7,8,9

10

L

Op code

DM TRUTH TABLE

Function

Write Enable

DM

L

DQ

Note

11

Valid

X

Write Inhibit

H

11

Note:

1. All states and sequences not shown are illegal or reserved.

2. DESLECT and NOP are functionally interchangeable.

3. Autoprecharge is non-persistent. A10 High enables Autoprecharge, while A10 Low disables Autoprecharge

4. Burst Terminate applies to only Read bursts with auto precharge disabled. This command is undefined and should not be used for

Read with Autoprecharge enabled, and for Write bursts.

5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low.

6. If A10 is low, bank address determines which bank is to be precharged. If A10 is high, all banks are precharged and BA0-BA1 are

don't care.

7. This command is AUTO REFRESH if CKE is High, and SELF REFRESH if CKE is low.

8. All address inputs and I/O are ''don't care'' except for CKE. Internal refresh counters control Bank and Row addressing.

9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command.

10. BA0 and BA1 value select among MRS, EMRS and SRR.

11. Used to mask write data, provided coincident with the corresponding data.

12. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN.

Rev 1.0 / Jun. 2008

13

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

CKE TRUTH TABLE

COMMANDn

ACTIONn

CKEn-1

CKEn

Current State

Power Down

Self Refresh

Note

L

X

Maintain Power Down

Maintain Self Refresh

Maintain Deep Power

Down

L

Deep Power Down

X

L

H

Power Down

Self Refresh

NOP or DESELECT

Exit Power Down

Exit Self Refresh

5,6,9

5,7,10

5,8

Deep Power Down

Exit Deep Power Down

Precharge Power

Down Entry

H

L

All Banks Idle

NOP or DESELECT

5

Active Power Down

Entry

H

L

Bank(s) Active

All Banks Idle

NOP or DESELECT

AUTO REFRESH

Self Refresh entry

Enter Deep Power

Down

L

BURST TERMINATE

See the other Truth Tables

H

Note:

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

2. Current state is the state of LP DDR immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is the result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. DESELECT and NOP are functionally interchangeable.

6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued.

7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued.

8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional Description.

9. The clock must toggle at least one time during the tXP period.

10. The clock must toggle at least once during the tXSR time.

Rev 1.0 / Jun. 2008

14

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

CURRENT STATE BANKn TRUTH TABLE (COMMAND TO BANK n)

Command

CS RAS CAS WE

Current State

Action

Notes

Description

H

L

X

H

L

X

H

L

X

H

L

DESELECT (NOP)

NOP

Continue previous Operation

Select and activate row

Any

ACTIVE

L

AUTO REFRESH

MODE REGISTER SET

PRECHARGE

READ

Auto refresh

10

Idle

L

Mode register set

L

H

L

H

L

No action if bank is idle

H

L

Select Column & start read burst

Select Column & start write burst

Deactivate Row in bank (or banks)

Row Active

L

WRITE

H

L

PRECHARGE

4

Truncate Read &

start new Read burst

L

H

L

H

L

READ

5,6

Read

Truncate Read &

start new Write burst

WRITE

5,6,13

(without Auto

recharge)

L

H

L

PRECHARGE

Truncate Read, start Precharge

Burst terminate

H

BURST TERMINATE

11

Truncate Write &

start new Read burst

L

H

L

H

READ

5,6,12

Write

(without Auto

precharge)

Truncate Write &

start new Write burst

L

H

L

WRITE

5,6

12

H

PRECHARGE

Truncate Write, start Precharge

Note:

1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh

or Power Down.

2. DESELECT and NOP are functionally interchangeable.

3. All states and sequences not shown are illegal or reserved.

4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging.

5. A command other than NOP should not be issued to the same bank while a READ or WRITE Burst with auto precharge is enabled.

6. The new Read or Write command could be auto precharge enabled or auto precharge disabled.

Rev 1.0 / Jun. 2008

15

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

7. Current State Definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met.

No data bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.

Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.

8. The following states must not be interrupted by a command issued to the same bank.

DESELECT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring

during these states. Allowable commands to the other bank are determined by its current state and Truth Table3,

and according to Truth Table 4.

Precharging: Starts with the registration of a PRECHARGE command and ends when tRP is met.

Once tRP is met, the bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met.

Once tRCD is met, the bank will be in the ''row active'' state.

Read with AP Enabled: Starts with the registration of the READ command with AUTO PRECHARGE enabled and ends

when tRP has been met. Once tRP has been met, the bank will be in the idle state.

Write with AP Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends

when tRP has been met. Once tRP is met, the bank will be in the idle state.

9. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied

to each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met.

Once tRFC is met, the LP DDR will be in an ''all banks idle'' state.

Accessing Mode Register: Starts with registration of a MODE REGISTER SET command and ends when tMRD has been met.

Once tMRD is met, the LP DDR will be in an ''all banks idle'' state.

Precharging All: Starts with the registration of a PRECHARGE ALL command and ends when tRP is met.

Once tRP is met, the bank will be in the idle state.

10. Not bank-specific; requires that all banks are idle and no bursts are in progress.

11. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank.

12. Requires appropriate DM masking.

13. A WRITE command may be applied after the completion of the READ burst; otherwise, a Burst terminate must be used to end

the READ prior to asserting a WRITE command.

Rev 1.0 / Jun. 2008

16

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

CURRENT STATE BANKn TRUTH TABLE (COMMAND TO BANK m)

Command

CS RAS CAS WE

Current State

Action

Notes

Description

H

L

X

L

X

H

X

L

X

H

X

H

L

X

H

X

H

L

DESELECT (NOP)

NOP

Continue previous Operation

Any command allowed to bank m

Activate Row

Any

Idle

ANY

ACTIVE

READ

Row Activating,

Active, or Pre-

charging

H

L

Start READ burst

Start WRITE burst

Precharge

8

L

WRITE

H

L

PRECHARGE

ACTIVE

READ

L

H

L

Activate Row

Read with Auto

Precharge dis-

abled

H

L

Start READ burst

Start WRITE burst

Precharge

8

L

WRITE

8,10

H

L

PRECHARGE

ACTIVE

READ

L

H

L

Activate Row

Write with Auto

precharge dis-

abled

H

L

Start READ burst

Start WRITE burst

Precharge

8,9

8

L

WRITE

H

L

PRECHARGE

ACTIVE

READ

L

H

L

Activate Row

H

L

Start READ burst

Start WRITE burst

Precharge

5,8

Read with Auto

Precharge

L

WRITE

5,8,10

H

L

PRECHARGE

ACTIVE

READ

L

H

L

Activate Row

H

L

Start READ burst

Start WRITE burst

Precharge

5,8

Write with Auto

precharge

L

WRITE

H

L

PRECHARGE

Rev 1.0 / Jun. 2008

17

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Note:

1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was

Self Refresh or Power Down.

2. DESELECT and NOP are functionally interchangeable.

3. All states and sequences not shown are illegal or reserved.

4. Current State Definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and

no register accesses are in progress.

Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.

Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated or been terminated.

5. Read with AP enabled and Write with AP enabled: The read with Autoprecharge enabled or Write with Autoprecharge

enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the

precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the

earliest possible PRECHARGE command that still accesses all the data in the burst. For Write with Auto precharge, the

precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts

with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period,

of the Read with Autoprecharge enabled or Write with Autoprecharge enabled states, ACTIVE, PRECHARGE, READ, and

WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands

to the other banks may be applied. In either case, all other related limitations apply (e.g. contention between READ data

and WRITE data must be avoided).

6. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle.

7. A BURST TERMINATE command cannot be issued to another bank;

it applies to the bank represented by the current state only.

8. READs or WRITEs listed in the Command column include READs and WRITEs with AUTO PRECHARGE enabled and

READs and WRITEs with AUTO PRECHARGE disabled.

9. Requires appropriate DM masking.

10. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command

must be issued to end the READ prior to asserting a WRITE command.

Rev 1.0 / Jun. 2008

18

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

ABSOLUTE MAXIMUM RATING

Parameter

Symbol

TC

Rating

-25 ~ 85

-30 ~ 85

Unit

^oC

Operating Case Temperature¹⁾

^oC

V

mA

W

Storage Temperature

TSTG

-55 ~ 150

-0.3 ~ VDDQ+0.3

-0.3 ~ 2.7

50

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Voltage on VDDQ relative to VSS

Short Circuit Output Current

Power Dissipation

VIN, VOUT

VDD

VDDQ

IOS

PD

0.7

Note1, H5MS1222EFP-XXE Series : Extended Temp. : -25^oC ~ 85^oC, H5MS1222EFP-XXM Series : Mobile Temp. : -30^oC ~ 85^oC

AC and DC OPERATING CONDITIONS

OPERATING CONDITION

Parameter

Supply Voltage

I/O Supply Voltage

Symbol

VDD

Min

1.7

Typ

1.8

Max

1.95

Unit

V

Note

1

VDDQ

CLOCK INPUTS (CK, CK)

Parameter

DC Input Voltage

DC Input Differential Voltage

AC Input Differential Voltage

AC Differential Crosspoint Voltage

Symbol

VIN

Min

-0.3

0.4*VDDQ

0.6*VDDQ

0.4*VDDQ

Max

Unit

Note

VDDQ+0.3

VDDQ+0.6

0.6*VDDQ

V

VID(DC)

VID(AC)

VIX

2

3

Address And Command Inputs (A0~An, BA0, BA1, CKE, CS, RAS, CAS, WE)

Parameter

Input High Voltage

Input Low Voltage

Symbol

VIH

Min

0.8*VDDQ

-0.3

Max

VDDQ+0.3

0.2*VDDQ

Unit

V

Note

VIL

Data Inputs (DQ, DM, DQS)

Parameter

DC Input High Voltage

DC Input Low Voltage

AC Input High Voltage

AC Input Low Voltage

Symbol

VIHD(DC)

VILD(DC)

VIHD(AC)

VILD(AC)

Min

0.7*VDDQ

-0.3

0.8*VDDQ

-0.3

Max

Unit

VDDQ+0.3

0.3*VDDQ

VDDQ+0.3

0.2*VDDQ

V

Data Outputs (DQ, DQS)

Parameter

DC Output High Voltage (IOH = -0.1mA)

DC Output Low Voltage (IOL = 0.1mA)

Symbol

VOH

Min

0.9*VDDQ

-

Max

-

0.1*VDDQ

Unit

V

Note

VOL

Rev 1.0 / Jun. 2008

19

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Leakage Current

Parameter

Symbol

Min

Max

Unit

Note

Input Leakage Current

Output Leakage Current

ILI

-1

-1.5

1

1.5

uA

4

5

ILO

Note:

1. All voltages are referenced to VSS = 0V and VSSQ must be same potential and VDDQ must not exceed the level of VDD.

2. VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on CK.

3. The value of VIX is expected to be 0.5*VDDQ and must track variations in the DC level of the same.

4. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V.

5. DOUT is disabled. VOUT= 0 to 1.95V.

AC OPERATING TEST CONDITION

Parameter

AC Input High/Low Level Voltage

Input Timing Measurement Reference Level Voltage

Input Rise/Fall Time

Output Timing Measurement Reference Level Voltage

Output Load Capacitance for Access Time Measurement

Symbol

VIH / VIL

Vtrip

Value

0.8*VDDQ/0.2*VDDQ

0.5*VDDQ

Unit

V

ns

V

pF

Note

tR / tF

Voutref

CL

1

0.5*VDDQ

1

Note: 1. The circuit shown on the right represents the timing

load used in defining the relevant timing parameters of

the part. It is not intended to be either a precise repre-

sentation of the typical system environment nor a depic-

tion of the actual load presented by a production tester.

System designers will use IBIS or other simulation tools

to correlate the timing reference load to system environ-

ment. Manufacturers will correlate to their production

(generally a coaxial transmission line terminated at the

tester electronics). For the half strength driver with a

nominal 10pF load parameters tAC and tQH are

ZO=50Ω

O utput

Test Load for Full Drive Strength Buffer

(20 pF)

Test Load for Half Drive Strength Buffer

(10 pF)

expected to be in the same range. However, these

parameters are not subject to production test but are

estimated by design and characterization. Use of IBIS or other simulation tools for system design validation is suggested.

Input / Output Capacitance

Speed

Parameter

Symbol

Unit

Note

Min

Max

Input capacitance, CK, CK

Input capacitance delta, CK, CK

Input capacitance, all other input-only pins

Input capacitance delta, all other input-only pins

Input/output capacitance, DQ, DM, DQS

Input/output capacitance delta, DQ, DM, DQS

CCK

CDCK

CI

CDI

CIO

1.5

-

1.5

-

2.0

-

3.5

0.25

3.0

0.5

4.5

pF

4

CDIO

0.5

Note:

1. These values are guaranteed by design and are tested on a sample base only.

2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads.

3. Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer. VDD,

VDDQ are applied and all other pins (except the pin under test) floating. DQ's should be in high impedance state. This may be

achieved by pulling CKE to low level.

4. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This

is required to match signal propagation times of DQ, DQS and DM in the system.

Rev 1.0 / Jun. 2008

20

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Mobile DDR OUTPUT SLEW RATE CHARACTERRISTICS

Parameter

Min

0.7

0.3

0.7

Max

2.5

1.0

Unit

V/ns

-

Note

1, 2

3

Pull-up and Pull-Down Slew Rate for Full Strength Driver

Pull-up and Pull-Down Slew Rate for Half Strength Driver

Output Slew Rate Matching ratio (Pull-up to Pull-down)

1.4

Note:

1. Measured with a test load of 20pF connected to VSSQ

2. Output slew rate for rising edge is measured between VILD(DC) to VIHD(AC) and for falling edge between VIHD(DC) to VILD(AC)

3. The ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature

and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process

variation.

Mobile DDR AC OVERSHOOT / UNDERSHOOT SPECIFICATION

Parameter

Maximum peak amplitude allowed for overshoot

Specification

0.5V

Maximum peak amplitude allowed for undershoot

0.5V

The area between overshoot signal and VDD must be less than or equal to

The area between undershoot signal and GND must be less than or equal to

3V-ns

Note:

1. This specification is intended for devices with no clamp protection and is guaranteed by design.

2.5V

Overshoot

2.0V

1.5V

1.0V

0.5V

0.0V

-0.5V

VDD

Max. Amplitude = 0.5V

Max. Area = 3V-ns

VSS

Undershoot

Time (ns)

Rev 1.0 / Jun. 2008

21

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

DC CHARACTERISTICS

Max

Parameter

Symbol

Test Condition

Unit Note

DDR DDR DDR

333

266

200

tRC = tRC(min); tCK = tCK(min); CKE is HIGH; CS is

HIGH between valid commands; address inputs are

SWITCHING; data bus inputs are STABLE

Operating one bank

active-precharge current

IDD0

50

45

40

mA

1

all banks idle; CKE is LOW; CS is HIGH; tCK =

IDD2P tCK(min); address and control inputs are SWITCH-

ING; data bus inputs are STABLE

Precharge power-down

standby current

0.3

5

Precharge power-down

standby current

with clock stop

all banks idle; CKE is LOW; CS is HIGH; CK = LOW;

IDD2PS CK = HIGH; address and control inputs are SWITCH-

ING; data bus inputs are STABLE

mA

all banks idle; CKE is HIGH; CS is HIGH, tCK =

IDD2N tCK(min); address and control inputs are SWITCH-

ING; data bus inputs are STABLE

Precharge non power-down

standby current

Precharge non power-down

standby current

with clock stop

all banks idle; CKE is HIGH; CS is HIGH; CK = LOW;

IDD2NS CK = HIGH; address and control inputs are SWITCH-

ING; data bus inputs are STABLE

3

one bank active; CKE is LOW; CS is HIGH; tCK =

IDD3P tCK(min); address and control inputs are SWITCH-

ING; data bus inputs are STABLE

Active power-down

standby current

2

1.2

10

8

mA

Active power-down

standby current

with clock stop

one bank active; CKE is LOW; CS is HIGH; CK =

IDD3PS LOW; CK = HIGH; address and control inputs are

SWITCHING; data bus inputs are STABLE

one bank active; CKE is HIGH; CS is HIGH; tCK =

IDD3N tCK(min); address and control inputs are SWITCH-

ING; data bus inputs are STABLE

Active non power-down

standby current

mA

Active non power-down

standby current

with clock stop

one bank active; CKE is HIGH; CS is HIGH; CK =

IDD3NS LOW; CK = HIGH; address and control inputs are

SWITCHING; data bus inputs are STABLE

one bank active; BL=4; CL=3; tCK = tCK(min);

Operating burst r

ead current

continuous read bursts; IOUT=0mA; address inputs

are SWITCHING, 50% data change each burst trans-

fer

IDD4R

120

110

100

85

80

mA

1

one bank active; BL=4; tCK=tCK(min); continuous

IDD4W write bursts; address inputs are SWITCHING; 50%

data change each burst transfer

Operating burst

write current

90

mA

tRC=tRFC(min); tCK=tCK(min); burst refresh; CKE

IDD5 is HIGH; address and control inputs are SWITCH-

ING; data bus inputs are STABLE

Auto Refresh Current

CKE is LOW; CK=LOW; CK=HIGH;

Extended Mode Register set to all 0's; address and

control inputs are STABLE; data bus inputs are STA-

BLE

Self Refresh Current

IDD6

See Next Page

10

uA

2

4

Deep Power Down Current

IDD8

Address, control and data bus inputs are STABLE

Rev 1.0 / Jun. 2008

22

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Note:

1. IDD specifications are tested after the device is properly initialized.

2. Input slew rate is 1V/ns.

3. Definitions for IDD:

LOW is defined as VIN ≤ 0.1 * VDDQ

HIGH is defined as VIN ≥ 0.9 * VDDQ

STABLE is defined as inputs stable at a HIGH or LOW level

SWITCHING is defined as

- address and command: inputs changing between HIGH and LOW once per two clock cycles

- data bus inputs: DQ changing between HIGH and LOW once per clock cycle

DM and DQS are STABLE

4. Please contact Hynix office for more information and ability for DPD operation. Deep Power Down operation is a hynix optional

function.

5. IDD values are for full operating range of voltage and temperature.

DC CHARACTERISTICS - IDD6

Memory Array

2 Banks

125

Temp.

(^oC)

Unit

4 Banks

135

1 Bank

120

45

85

uA

250

185

170

Note:

1. VDD / VDDQ = 1.8V

2. Related numerical values in this 45^oC are examples for reference sample value only.

3. With a on-chip temperature sensor, auto temperature compensated self refresh will automatically adjust the interval of self-refresh

operation according to case temperature variations.

Rev 1.0 / Jun. 2008

23

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

AC CHARACTERISTICS (AC operating conditions unless otherwise noted) (Sheet 1 of 2)

DDR333

DDR266

DDR200

Parameter

Symbol

Unit Note

Min

Max

5.0

Min

Max

6.0

Min

Max

6.0

DQ Output Access Time (from CK, CK)

DQS Output Access Time (from CK, CK)

Clock High-level Width

2.0

ns

tAC

tDQSCK

tCH

5.0

6.0

0.45

0.55

0.45

0.55

0.45

0.55

tCK

Clock Low-level Width

tCL

tCL,

tCH

(Min)

tCL,

tCH

(Min)

tCL,

tCH

(Min)

Clock Half Period

-

ns

1,2

3

tHP

CL = 3

System Clock Cycle Time

CL = 2

6.0

12

7.5

12

-

10

15

-

ns

tCK3

tCK2

tDS

DQ and DM Input Setup Time

0.6

1.6

1.1

2.2

1.0

0.8

2.0

1.3

2.6

1.0

0.8

2.0

1.3

3.0

1.0

4,5,6

7

DQ and DM Input Hold Time

tDH

DQ and DM Input Pulse Width

-

tDIPW

tIS

Address and Control Input Setup Time

Address and Control Input Hold Time

Address and Control Input Pulse Width

DQ & DQS Low-impedance time from CK, CK

DQ & DQS High-impedance time from CK, CK

DQS - DQ Skew

6,8,9

7

tIH

-

tIPW

tLZ

-

10

5.0

0.5

6.0

0.6

6.0

0.65

10

tHZ

11

tDQSQ

tHP -

tQHS

tHP -

tQHS

tHP -

tQHS

DQ / DQS output hold time from DQS

tQH

ns

2

Data Hold Skew Factor

0.65

1.25

0.75

1.25

1.0

ns

tQHS

Write Command to 1st DQS Latching Transition

DQS Input High-Level Width

0.75

0.4

0.2

0.75

0.4

0.2

0.75

0.35

0.2

1.25

tCK

tDQSS

tDQSH

tDQSL

tDSS

DQS Input Low-Level Width

DQS Falling Edge of CK Setup Time

DQS Falling Edge Hold Time from CK

tDSH

0.2

Rev 1.0 / Jun. 2008

24

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

AC CHARACTERISTICS (AC operating conditions unless otherwise noted) (Sheet 2 of 2)

DDR333

DDR266

DDR200

Parameter

Symbol

Unit Note

Min

Max

Min

Max

Min

Max

MODE REGISTER SET Command Period

MRS(SRR) to Read Command Period

2

-

2

-

2

-

tCK

tMRD

tSRR

Minimum Time between Status Register Read to

Next Valid Command

CL+1

-

CL+1

-

CL+1

-

tCK

tSRC

Write Preamble Setup Time

Write Postamble

0

0.4

0.25

0.9

0.5

0.4

42

-

0.6

-

0

0.4

0.25

0.9

0.5

0.4

45

-

0.6

-

0

-

0.6

-

ns

tCK

ns

12

13

tWPRES

tWPST

tWPRE

tRPRE

tRPST

tRAS

0.4

0.25

0.9

0.5

0.4

50

Write Preamble

1.1

0.6

70,000

-

1.1

0.6

70,000

-

1.1

0.6

70,000

-

14

CL = 3

Read Preamble

CL = 2

Read Postamble

ACTIVE to PRECHARGE Command Period

ACTIVE to ACTIVE Command Period

60

75

80

ns

tRC

AUTO REFRESH to ACTIVE/AUTO REFRESH

Command Period

tRFC

80

-

80

-

80

-

ns

ACTIVE to READ or WRITE Delay

18

12

15

-

22.5

15

-

30

15

-

ns

15

tRCD

tRP

PRECHARGE Command Period

ACTIVE Bank A to ACTIVE Bank B Delay

WRITE Recovery Time

tRRD

tWR

ns

15

ns

Auto Precharge Write Recovery + Precharge Time

Internal Write to Read Command Delay

Self Refresh Exit to next valid Command Delay

(tWR/tCK) + (tRP/tCK)

tCK

ns

16

tDAL

tWTR

tXSR

1

-

1

-

1

-

120

tIS +

1CLK

tIS +

1CLK

tIS +

1CLK

Exit Power Down to next valid Command Delay

-

ns

tXP

CKE min. Pulse Width (High and Low)

Average Periodic Refresh Interval

Refresh Period

tCKE

tREFI

tREF

1

-

1

-

1

-

tCK

us

15.6

64

15.6

64

15.6

64

17

-

ms

Rev 1.0 / Jun. 2008

25

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Note:

1. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device

(i.e. this value can be greater than the minimum specification limits for tCL and tCH)

2. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).

tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition

followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output

pattern effects, and p-channel to n-channel variation of the output drivers.

3. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes.

4. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to

VIL(AC) for falling input signals.

5. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions

through the DC region must be monotonic.

6. Input slew rate ≥ 1.0 V/ns.

7. These parameters guarantee device timing but they are not necessarily tested on each device.

8. The transition time for address and command inputs is measured between VIH and VIL.

9. A CK/CK differential slew rate of 2.0 V/ns is assumed for this parameter.

10. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a

specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

11. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any

given cycle.

12. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid

transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in

progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH,

LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

13. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system

performance (bus turnaround) will degrade accordingly.

14. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the

system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).

15. Speed bin (CL-tRCD-tRP) = 3-3-3

16. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms above, if not already an integer, round to the next higher integer.

17. A maximum of eight Refresh commands can be posted to any given Low Power DDR SDRAM (Mobile DDR SDRAM), meaning that

the maximum absolute interval between any Refresh command and the next Refresh command is 8*tREFI.

Rev 1.0 / Jun. 2008

26

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Mobile DDR SDRAM OPERATION

State Diagram

ACT :

Active

DEEP

POWER

DOWN

DPDSX

Power

applied

POWER

ON

BST :

Burst

CKEL :

Enter Power-Down

PCG.

ALL

BANKS

DPDS

CKEH :

Exit Power-Down

SELF

REFRESH

DPDS :

Enter Deep

Power-Down

(E)MRS

SET

SRR

REFS

REFSX

MRS,

READ

EMRS

DPDSX :

Exit Deep Power-

DownEMRS

SRR

IDLE

ALL BANK

PCG.

EMRS :

Ext. Mode Reg.

Set

CKEL

CKEH

REFA

MRS :

Mode Register Set

PCG.

POWER

DOWN

AUTO

REFRESH

ACT

PRE :

Precharge

ACTIVE

POWER

DOWN

BURST

STOP

PREALL :

Precharge All

Banks

CKEL

CKEH

REFA

Auto Refresh

:

ROW

ACTIVE

BST

WRITE

READ

REFS :

Enter Self Refresh

REFSX :

Exit Self Refresh

WRITE

READ

WRITE

READ

READ :

Read w/o Auto

Precharge

WRITEA

READA

WRITEA

READA

READA :

Read with Auto

Precharge

READ A

WRITE A

PRE

WRITE :

PRE

Write w/o Auto

Precharge

WRITEA :

Write with Auto

Precharge

ALL

SRR :

Status Register

COMMAND Input

Read

AUTOMATIC

Sequence

Rev 1.0 / Jun. 2008

27

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

DESELECT

The DESELECT function (CS = High) prevents new commands from being executed by the Mobile DDR SDRAM. The

Mobile DDR SDRAM is effectively deselected. Operations already in progress are not affected.

NO OPERATION

The NO OPERATION (NOP) command is used to perform a NOP to a Mobile DDR SDRAM that is selected (CS = Low).

This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are

not affected. (see to next figure)

ACTIVE

The Active command is used to activate a row in a particular bank for a subsequent Read or Write access. The value of

the BA0,BA1 inputs selects the bank, and the address provided on A0-A11 (or the highest address bit) selects the row.

(see to next figure)

Before any READ or WRITE commands can be issued to a bank within the Mobile DDR SDRAM, a row in that bank

must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be acti-

vated.

The row remains active until a PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) com-

mand is issued to the bank.

A PRECHARGE (or READ with AUTO PRECHARGE or WRITE with AUTO PRECHARGE) command must be issued before

opening a different row in the same bank.

CLK

CKE

(High)

CS

RAS

CAS

WE

RA

BA

A0~A11

Row Address

Bank Address

BA0, BA1

Don't Care

NOP Command

ACTIVE Command

Rev 1.0 / Jun. 2008

28

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Once a row is Open (with an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the

tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to

determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered.

A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row

has been closed (precharge). The minimum time interval between successive ACTIVE commands to the same bank is

defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in

a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to differ-

ent banks is defined by tRRD.

/CLK

CLK

Bank A

ACT

Write A

With A/P

Bank B

ACT

Bank A

ACT

Command

Address

NOP

Bank A

Row

Bank A

Col

Bank B

Row

Bank A

Row

tRRD

tRCD

tRC

Don't Care

Once a row is Open(with an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the

tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to

determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered.

Rev 1.0 / Jun. 2008

29

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

READ / WRITE COMMAND

The READ command is used to initiate a Burst Read to an active row. The value of BA0 and BA1 selects the bank and

address inputs select the starting column location.

The value of A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being

accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open

for subsequent access. The valid data-out elements will be available CAS latency after the READ command is issued.

The Mobile DDR drives the DQS during read operations. The initial low state of the DQS is known as the read preamble

and the last data-out element is coincident with the read postamble. DQS is edge-aligned with read data. Upon com-

pletion of a burst, assuming no new READ commands have been initiated, the I/O's will go high-Z.

The WRITE command is used to initiate a Burst Write access to an active row. The value of BA0, BA1 selects the bank

and address inputs select the starting column location.

The value of A10 determines whether or not auto precharge is used.If auto precharge is selected, the row being

accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open

for subsequent access. Input data appearing on the data bus, is written to the memory array subject to the DM input

logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be

written to the memory; if the DM signal is registered high, the corresponding data-inputs will be ignored, and a write

will not be executed to that byte/column location. The memory controller drives the DQS during write operations. The

initial low state of the DQS is known as the write preamble and the low state following the last data-in element is write

postamble. Upon completion of a burst, assuming no new commands have been initiated, the I/O's will stay high-Z

and any additional input data will be ignored.

CLK

CKE

(High)

CS

RAS

CAS

WE

A0~A7

CA

BA

CA

BA

A0~A7

High to enable

Auto Precharge

A10

Low to disable

Auto Precharge

BA0, BA1

Don't Care

Read Command

Write Command

READ / WRITE COMMAND

Rev 1.0 / Jun. 2008

30

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

READ

The basic Read timing parameters for DQ are shown next figure (Basic Read Timing Parameters). They apply to all

Read operations. During Read bursts, DQS is driven by the Mobile DDR SDRAM along with the output data. The initial

Low state of the DQS is known as the read preamble; the Low state coincident with last data-out element is known as

the read postamble.

tCK

tCH

tCL

/CLK

CLK

tDQSCK

tACmax

tRPST

tHZ

tRPRE

DQS

DQ

tDQSQmax

tAC

tLZ

tQH

Don

tQH

Don+1 Don+2 Don+3

tQH

tDQSCK

tRPST

tDQSCK

tACmin

tRPRE

DQS

DQ

tDQSQ max

tHZ

tAC

tLZ

Don

tQH

Don+1 Don+2 Don+3

tQH

Don't Care

1) Do n : Data Out from column n

2) All DQ are vaild tAC after the CK edge

All DQ are vaild tDQSQ after the DQS edge, regardless of tAC

Basic Read Timing Parameters

Rev 1.0 / Jun. 2008

31

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

The first data-out element is edge aligned with the first rising edge of DQS and the successive data-out elements are

edge aligned to successive edges of DQS. This is shown in next figure with a CAS latency of 2 and 3.

Upon completion of a read burst, assuming no other READ command has been initiated, the DQ will go to High-Z.

/CLK

CLK

Command

Address

DQS

READ

NOP

BA,

Col n

CL =2

DQ

Don

CL =3

DQS

DQ

Don

Don't Care

1) Don : Data out from column n

2) BA, Col n = Bank A, Column n

3) Burst Length = 4; 3 subseqnent elements of Data Out appear in the programmed order following Do n

4) Shown with nominal tAC, tDQSCK and tDQSQ

Read Burst Showing CAS Latency

Rev 1.0 / Jun. 2008

32

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

READ to READ

Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the

new burst follows either the last element of a completed burst or the last desired element of a longer burst that is

being truncated. The new READ command should be issued X cycles after the first READ command, where X equals

the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture).

/CLK

CLK

Command

Address

DQS

READ

NOP

READ

NOP

BA,

Col n

BA,

Col b

CL =2

DQ

Don

Dob

CL =3

DQS

DQ

Don

Dob

Don't Care

1) Don (or b): Data out from column n (or column b)

2) BA, Col n (b) = Bank A, Column n (b)

3) Burst Length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first)

4) Read bursts are to an active row in any bank

5) Shown with nominal tAC, tDQSCK and tDQSQ

Consecutive Read Bursts

A READ command can be initiated on any clock cycle following a previous READ command. Non-consecutive Reads are

shown in the first figure of next page. Random read accesses within a page or pages can be performed as shown in

second figure of next page.

Rev 1.0 / Jun. 2008

33

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

/CLK

CLK

READ

N O P

READ

N O P

Com m and

Address

BA,

Col n

BA,

Col b

CL = 2

D Q S

D Q

D on

D ob

CL = 3

D Q S

D Q

D on

D on't Care

1) D on (or b): D ata out from colum n n (or colum n b)

2) BA, Col n (b) = Bank A, Colum n n (b)

3) Burst Length = 4; 3 subsequent elem ents of D ata O ut appear in the program m ed order follow ing D o n (b)

4) Show n w ith nom inal tAC, tD Q SCK and tD Q SQ

Non-Consecutive Read Bursts

/C LK

C LK

R E A D

N O P

C o m m a n d

A d d re ss

B A ,

C o l g

B A ,

C o l n

B A ,

C o l x

B A ,

C o l b

C L = 2

D Q S

D Q

D o x

D o x'

D o b

D o g '

D o n

D o n '

D o b '

D o g

C L = 3

D Q S

D Q

D o x

D o b

D o b '

D o n

D o n '

D o x'

D o n 't C a re

1 ) D o n , e tc: D a ta o u t fro m co lu m n n , e tc

n ', x', e tc : D a ta O u t e le m e n ts, a cco d in g to th e p ro g ra m m d b u rst o rd e r

B a n k A , C o lu m n

3 ) B u rst L e n g th 2 , 4 o r 8 in ca se s sh o w n (if b u rst o f 4 o r 8 , th e b u rst is in te rru p te d )

4 ) R e a d a re to a ctive ro w s in a n y b a n ks

2 ) B A , C o l n

=

n

=

Random Read Bursts

Rev 1.0 / Jun. 2008

34

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

READ BURST TERMINATE

Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is

equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ com-

mand where X equals the desired data-out element pairs.

/CLK

CLK

BURST

Terminate

READ

NOP

Command

Address

BA,

Col n

CL =2

DQS

DQ

CL =3

DQS

DQ

Don't Care

1) Don : Data out from column n

2) BA, Col n = Bank A, Column n

3) Cases shown are bursts of 4 or 8 terminated after 2 data elements

4) Shown with nominal tAC, tDQSCK and tDQSQ

Terminating a Read Burst

Rev 1.0 / Jun. 2008

35

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

READ to WRITE

Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If trun-

cation is necessary, the BURST TERMINATE command must be used, as shown in next fig. for the case of nominal

tDQSS.

/CLK

CLK

NOP

READ

BST

NOP

WRITE

NOP

Command

Address

BA,

Col b

BA,

Col n

CL =2

tDQSS

DQS

DQ

Don

DI b

Command

Address

READ

BST

NOP

WRITE

NOP

BA,

Col n

BA,

Col b

CL =3

DQS

Don

DI b

DQ

DM

Don't Care

1) DO n = Data Out from column n; DI b = Data In to column b

2) Burst length = 4 or 8 in the cases shown; if the burst length is 2, the BST command can be ommitted

3) Shown with nominal tAC, tDQSCK and tDQSQ

Read to Write

Rev 1.0 / Jun. 2008

36

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

READ to PRECHARGE

A Read burst may be followed by or truncated with a PRECHARGE command to the same bank (provided Auto Pre-

charge was not activated). The PRECHARGE command should be issued X cycles after the READ command, where X

equal the number of desired data-out element pairs.

Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.

Note that part of the row precharge time is hidden during the access of the last data-out elements.In the case of a

Read being executed to completion, a PRECHARGE command issued at the optimum time (as described above) pro-

vides the same operation that would result from Read burst with Auto Precharge enabled.

The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at

the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to

truncate bursts.

/CLK

CLK

READ

NOP

PRE

NOP

ACT

Command

Address

BA,

Col n

Bank

A or All)

BA,

Row

(

CL =2

tRP

DQS

DQ

Don

CL =3

DQS

DQ

Don

Don't Care

1) DO n = Data Out from column n

2) Cases shown are either uninterrupted burst of 4, or interrupted bursts of 8

3) Shown with nominal tAC, tDQSCK and tDQSQ

4) Precharge may be applied at (BL / 2) tCK after the READ command.

5) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks.

6) The ACTIVE command may be applied if tRC has been met.

READ to PRECHARGE

Rev 1.0 / Jun. 2008

37

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Write

Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing

coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory;

if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to

that byte / column location.

Basic Write timing parameters for DQ are shown in Figure; they apply to all Write operations.

tCH

tCK

tCL

/CLK

CLK

tDSH

tDQSH

tDSH

Case 1:

tDQSS = min

tDQSS

tWPST

DQS

tWPRE

tDS tDH

tDQSL

tWPRES

DI n

DQ, DM

tDSS

tWPST

tDQSS

tDQSH tDSS

Case 2:

tDQSS = max

DQS

tWPRES

tDQSL

tWPRE

tDS tDH

DQ, DM

DI n

Don't Care

1) DI n: Data in for column n

2) 3 subsequent elements of Data in are applied in the programmed order following DI n

3) tDQSS : each rising edge of DQS must fall within the +/-25 (percentage) window of the corresponding positive clock edge

Basic Write Timing Parameters

During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the

WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of

DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS

following the last data-in element is called the write postamble.

The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a rel-

atively wide range - from 75% to 125% of a clock cycle. Next fig. shows the two extremes of tDQSS for a burst of 4.

Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain high-Z and any

additional input data will be ignored.

Rev 1.0 / Jun. 2008

38

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

/CLK

CLK

Command

WRITE

NOP

BA,

Col b

Address

DQS

tDQSSmin

DQ

DM

tDQSSmax

DQS

DQ

DM

Don't Care

1) DI b = Data In to column b

2) 3 subsequent elements of Data In are applied in the programmed order following DI b

3) A non-interrupted burst of 4 is shown

4) A10 is low with the WRITE command (Auto Precharge is disabled)

Write Burst (min. and max. tDQSS)

Rev 1.0 / Jun. 2008

39

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

WRITE to WRITE

Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case,

a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of

the clock following the previous WRITE command.The first data-in element from the new burst is applied after either

the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The

new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of

desired data-in element pairs.

/CLK

CLK

Command

Address

DQS

WRITE

NOP

WRITE

NOP

BA,

Col b

BA,

Col n

tDQSSmin

DI

b

DI

n

DQ

DM

tDQSSmax

DQS

DQ

DI

b

DI

n

DM

Don't Care

1) DI b (n) = Data In to column b (column n)

2) 3 subsequent elements of Data In are applied in the programmed order following DI b.

3 subsequent elements of Data In are applied in the programmed order following DI n.

3) Non-interrupted bursts of 4 are shown.

4) Each WRITE command may be to any active bank

Concatenated Write Bursts

Rev 1.0 / Jun. 2008

40

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

/CLK

CLK

WRITE

NOP

WRITE

NOP

Command

Address

DQS

BA,

Col b

BA,

Col n

tDQSSmax

DI

b

DI

n

DQ

DM

Don't Care

1) DI b (n) = Data In to column b (or column n).

2) 3 subsequent elements of Data In are applied in the programmed order following DI b.

3 subsequent elements of Data In are applied in the programmed order following DI n.

3) Non-interrupted bursts of 4 are shown.

4) Each WRITE command may be to any active bank and may be to the same or different devices.

Non-Concatenated Write Bursts

/CLK

CLK

WRITE

NOP

Command

BA,

Col b

BA,

Col x

BA,

Col n

BA,

Col a

BA,

Col g

Address

DQS

tDQSSmax

Di

b

Di

b'

Di

x

Di

x'

Di

n

Di

n'

Di

a

Di

a'

DQ

DM

Don't Care

1) DI b etc. = Data In to column b, etc.

; b', etc. = the next Data In following DI b, etc. according to the programmed burst order

2) Programmed burst length = 2, 4 or 8 in cases shown. If burst of 4 or 8, burst would be truncated.

3) Each WRITE command may be to any active bank and may be to the same or different devices.

Random Write Cycles

Rev 1.0 / Jun. 2008

41

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

WRITE to READ

Data for any Write burst may be followed by a subsequent READ command. To follow a Write without truncating the

write burst, tWTR should be met as shown in Figure.

/CLK

CLK

Command

Address

DQS

WRITE

NOP

READ

NOP

BA,

Col b

BA,

Col n

tWTR

CL=3

tDQSSmax

Di

b

DQ

DM

Don't Care

1) DI b = Data In to column b . 3 subsequent elements of Data In are applied in the programmed order following DI b.

2) A non-interrupted burst of 4 is shown.

3) tWTR is referenced from the positive clock edge after the last Data In pair.

4) A10 is LOW with the WRITE command (Auto Precharge is disabled)

5) The READ and WRITE commands are to the same device but not necessarily to the same bank.

Data for any Write burst may be truncated by a subsequent READ command as shown in Figure. Note that the only

data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in

must be masked with DM.

Rev 1.0 / Jun. 2008

42

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

/CLK

CLK

Command

WRITE

NOP

READ

NOP

BA,

Col b

BA,

Col n

Address

DQS

tWTR

CL=3

tDQSSmax

DI

b

Don

DQ

DM

Don't Care

1) DI b = Data In to column b. DO n = Data Out from column n.

2) An interrupted burst of 4 is shown, 2 data elements are written.

3 subsequent elements of Data In are applied in the programmed order following DI b.

3) tWTR is referenced from the positive clock edge after the last Data In pair.

4) A10 is LOW with the WRITE command (Auto Precharge is disabled)

5) The READ and WRITE commands are to the same device but not necessarily to the same bank.

Interrupting Write to Read

Rev 1.0 / Jun. 2008

43

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

WRITE to PRECHARGE

Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto

Precharge was not activated). To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in

Fig.

/CLK

CLK

Command

WRITE

NOP

PRE

BA,

Col b

BA

Address

DQS

(A or All)

tDQSSmax

tWR

DI

b

DQ

DM

Don't Care

1) DI b (n) = Data In to column b (column n)

3 subsequent elements of Data In are applied in the programmed order following DI b.

2) A non-interrupted bursts of 4 are shown.

3) tWR is referenced from the positive clock edge after the last Data In pair.

4) A10 is LOW with the WRITE command (Auto Precharge is disabled)

Non-Interrupting Write to Precharge

Rev 1.0 / Jun. 2008

44

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in Figure.

Note that only data-in pairs that are registered prior to the tWR period are written to the internal array, and any subse-

quent data-in should be masked with DM, as shown in next Fig. Following the PRECHARGE command, a subsequent

command to the same bank cannot be issued until tRP is met.

/CLK

CLK

WRITE

NOP

PRE

NOP

Command

Address

DQS

BA,

Col b

BA

(A or All)

tDQSSmax

tWR

*2

DI

b

DQ

DM

*1

Don't Care

1) DI b = Data In to column b .

2) An interrupted burst of 4 or 8 is shown, 2 data elements are written.

3) tWR is referenced from the positive clock edge after the last desired Data In pair.

4) A10 is LOW with the WRITE command (Auto Precharge is disabled)

5) *1 = can be Don't Care for programmed burst length of 4

6) *2 = for programmed burst length of 4, DQS becomes Don't Care at this point

Interrupting Write to Precharge

Rev 1.0 / Jun. 2008

45

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

BURST TERMINATE

The BURST TERMINATE command is used to truncate read bursts (with auto precharge disabled). The most recently

registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation sec-

tion of this datasheet. Note the BURST TERMINATE command is not bank specific. This command should not be used

to terminate write bursts.

CLK

CKE

(High)

CS

RAS

CAS

WE

A0~A11

Don't Care

BA0, BA1

BURST TERMINATE COMMAND

Rev 1.0 / Jun. 2008

46

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.

Another command to the same bank (or banks) being precharged must not be issued until the precharge time (tRP) is

completed.

If one bank is to be precharged, the particular bank address needs to be specified. If all banks are to be precharged,

A10 should be set high along with the PRECHARGE command. If A10 is high, BA0 and BA1 are ignored. A PRECHARGE

command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the

process of precharging.

CLK

CKE

(High)

A10 defines the precharge

mode when a precharge

command, a read command

or a write command is

issued.

CS

RAS

If A10=Highwhena

precharge command is

issued, all banks are

precharged.

CAS

WE

If A10 = Low when a

precharge command is

issued, onlythebankthat is

selectedbyBA1/BA0is

precharged.

A0~A9,

A11

If A10=Highwhenreador

write command, auto-

precharge function is

enabled.

A10

While A10 = Low, auto-

precharge function is

disabled.

BA0, BA1

BA

Bank Address

Don't Care

PRECHARGE command

AUTO PRECHARGE

Auto Precharge is a feature which performs the same individual bank precharge function as described above, but with-

out requiring an explicit command.

This is accomplished by using A10 (A10=high), to enable auto precharge in conjunction with a specific Read or Write

command. This precharges the bank/row after the Read or Write burst is complete.

Auto precharge is non persistent, so it should be enabled with a Read or Write command each time auto precharge is

desired. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst.

The user must not issue another command to the same bank until the precharge time (tRP) is completed.

Rev 1.0 / Jun. 2008

47

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

AUTO REFRESH AND SELF REFRESH

Mobile DDR devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two

ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode:

- AUTO REFRESH.

This command is used during normal operation of the Mobile DDR. It is non persistent, so must be issued each time a

refresh is required. The refresh addressing is generated by the internal refresh controller.The Mobile DDR requires

AUTO REFRESH commands at an average periodic interval of tREFI.

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh

interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given Mobile DDR, and the

maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8*tREFI.

-SELF REFRESH.

This state retains data in the Mobile DDR, even if the rest of the system is powered down (even without external clock-

ing). Note refresh interval timing while in Self Refresh mode is scheduled internally in the Mobile DDR and may vary

and may not meet tREFI time.

''Don't Care'' except CKE, which must remain low. An internal refresh cycle is scheduled on Self Refresh entry. The pro-

cedure for exiting Self Refresh mode requires a series of commands. First clock must be stable before CKE going high.

NOP commands should be issued for the duration of the refresh exit time (tXSR), because time is required for the com-

pletion of any internal refresh in progress.

The use of SELF REFRESH mode introduces the possibility that an internally timed event can be missed when CKE is

raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra AUTO REFRESH command is recom-

mended. In the self refresh mode, two additional power-saving options exist. They are Temperature Compensated Self

Refresh and Partial Array Self Refresh and are described in the Extended Mode Register section.

The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM

operates refresh cycle asynchronously.

The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled (Low). The Mobile DDR

can accomplish an special Self Refresh operation by the specific modes (PASR) programmed in extended mode regis-

ters. The Mobile DDR can control the refresh rate automatically by the temperature value of Auto TCSR (Temperature

Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of

PASR (Partial Array Self Refresh). The Mobile DDR can reduce the self refresh current(IDD6) by using these two

modes.

Rev 1.0 / Jun. 2008

48

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

CLK

CKE

(High)

CS

RAS

CAS

WE

A0~A11

BA0, BA1

Don't Care

Auto Refresh Command

Self Refresh Command

Rev 1.0 / Jun. 2008

49

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

/CLK

CLK

tRP

tRFC

tXSR

tRFC

CKE

Command

PRE

NOP

ARF

NOP

ARF

NOP

ACT

BA A

Row n

Address

Pre

All

A10(AP)

DQ

Row n

High-Z

Enter

Self Refresh

Mode

Exit

Self Refresh

Mode

Any Command

(Auto Refresh

Recommended)

Cont't Care

SELF REFRESH ENTRY AND EXIT

Rev 1.0 / Jun. 2008

50

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

MODE REGISTER SET

The Mode Register and the Extended Mode Register are loaded via the address bits. BA0 and BA1 are used to select

among the Mode Register, the Extended Mode Register and Status Register. See the Mode Register description in the

register definition section. The MODE REGISTER SET command can only be issued when all banks are idle and no

bursts are in progress, and a subsequent executable command cannot be issued until tMRD is met.

CLK

CKE

(High)

CS

RAS

CAS

W E

A0~A11

Code

Don't Care

BA0, BA1

MODE REGISTER SET COMMAND

/CLK

CLK

MRS

NOP

tMRD

Valid

Command

Address

Code

Don't Care

Code = Mode Register / Extended Mode Register selection

(BA0, BA1) and op-code (A0 - An)

tMRD DEFINITION

Rev 1.0 / Jun. 2008

51

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Mode Register

The mode register contains the specific mode of operation of the Mobile DDR SDRAM. This register includes the selec-

tion of a burst length(2, 4 or 8), a cas latency(2 or 3), a burst type. The mode register set must be done before any

activate command after the power up sequence. Any contents of the mode register be altered by re-programming the

mode register through the execution of mode register set command.

0

1

2

3

4

5

6

CLK

Mode

Register

Set

Precharge

All Bank

Command

(any)

CMD

tCK

tRP

2 CLKmin

Mode Register Set

BURST LENGTH

Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as

shown in Page10. The burst length determines the maximum number of column locations that can be accessed for a

given READ or WRITE command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the

interleaved burst types.

BURST TYPE

Accesses within a given burst may be programmed to be either sequential or interleaved.

CAS LATENCY

The CAS latency is the delay between the registration of a READ command and the availability of the first piece of out-

put data. If a READ command is registered at a clock edge n and the latency is 3 clocks, the first data element will be

valid at n + 2tCK + tAC. If a READ command is registered at a clock edge n and the latency is 2 clocks, the first data

element will be valid at n + tCK + tAC.

Rev 1.0 / Jun. 2008

52

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Extended Mode Register

The Extended Mode Register contains the specific features of self refresh operation of the Mobile DDR SDRAM.

The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA1=1 and BA0=0) and

will retain the stored information until it is reprogrammed, the device is put in Deep Power-Down mode, or the device

loses power. The Extended Mode Register should be loaded when all Banks are idle and no bursts are in progress, and

subsequent operation should only be initiated after tMRD. Violating these requirements will result in unspecified opera-

tion.

The Extended Mode Register is written by asserting low on CS, RAS, CAS, WE and high on BA0. The state of address

pins A0 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode regis-

ter. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the con-

troller must wait the specified time before initiating any subsequent operation. Violating either of these requirements

will result in unspecified operation.

This register includes the selection of partial array to be refreshed (full array, half array, quarter array, etc.). The

extended mode register set must be done before any activate command after the power up sequence. Any contents of

the mode register be altered by re-programming the mode register through the execution of extended mode register

set command.

PARTIAL ARRAY SELF REFRESH (PASR)

With PASR, the self refresh may be restricted to a variable portion of the total array. The whole array (default), 1/2

array, 1/4 array, 1/8 array or 1/16 array could be selected.

DRIVE STRENGTH (DS)

The drive strength could be set to full or half via address bits A5 and A6. The half drive strength is intended for lighter

loads or point-to-point environments.

Rev 1.0 / Jun. 2008

53

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Status Register Read

The Status Register contains the specific die information such as density, device type, data bus width, refresh rate,

revision ID and manufacturers. The Status Register is only for READ. Below figure is Status Register Read Timing Dia-

gram.

To read out the Status Register values, BA[1:0] set to 01b and A[11:0] set to all 0 with MRS command followed by

Read command with that BA[1:0] and A[11:0] are Don’t care.

tSRC

tCK

tRP

tSRR

CLK

CMD

NOP

READ

NOP

CMD

NOP

MRS

NOP

PRE All or PRE

01

0

BA[1:0]

Add

CL = 3

DQS

Register

Value Out

DQ[15:0]

Don’t care

Note)

1. SRR can only be issued after power-up sequence is complete.

2. SRR can only be issued with all banks precharged.

3. SRR CL is unchanged from value in the mode register.

4. SRR BL is fixed at 2.

5. tSRR = 2 CLK (min)

6. tSRC = CL + 1. (min time between READ to next valid command)

7. No commands other than NOP and DESELECT are allowed between the SRR and the READ.

Rev 1.0 / Jun. 2008

54

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

POWER DOWN

Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in

progress. If power down occurs when all banks are idle, it is Precharge Power Down.

If Power down occurs when one or more banks are Active, it is referred to as Active power down. The device cannot

stay in this mode for longer than the refresh requirements of the device, without losing data. The power down state is

exited by setting CKE high while issuing a Device Deselect or NOP command.

A valid command can be issued after tXP. For Clock stop during power down mode, please refer to the Clock Stop sub-

section in Operation section of this datasheet.

NOTE: This case shows CKE low coincident with NO OPERATION.

Alternately POWER DOWN entry can be achieved with CKE low coincident with Device DESELECT.

DEEP POWER DOWN

The Deep Power Down (DPD) mode enables very low standby currents. All internal voltage generators inside the

Mobile DDR SDRAM are stopped and all memory data is lost in this mode.

All the information in the Mode Register and the Extended Mode Register is lost. Next Figure, DEEP POWER DOWN

COMMAND shows the DEEP POWER DOWN command All banks must be in idle state with no activity on the data bus

prior to entering the DPD mode. While in this state, CKE must be held in a constant low state.

To exit the DPD mode, CKE is taken high after the clock is stable and NOP command must be maintained for at least

200 us. After 200 us a complete re-initialization routing is required following steps 4 through 11 as defined in POWER-

UP and INITIALIZATION SEQUENCES. DPD is an optional feature, so please contact Hynix office for DPD feature.

CLK

CKE

CS

RAS

CAS

WE

A0~A11

BA0, BA1

Don't Care

POWER-DOWN ENTRY COMMAND

DEEP POWER DOWN ENTRY COMMAND

Rev 1.0 / Jun. 2008

55

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Mobile DDR SDRAM Deep Power Down Entry and Exit

Before entering deep power down the DRAM must be in an all banks idle state with no activity on the data bus. Upon

entering deep power down all data will be lost. While in deep power down CKE must be held in a constant low state.

Upon exiting deep power down NOP command must be maintained for 200us. After 200us a complete initialization

routine is required following steps 4 through 11 as defined in POWER-UP and INITIALIZATION SEQUENCES.

T0

T1

Ta0¹

Ta¹

Tb¹

CK

tCK

tCH

tIS tIH

tCL

CKE

COM

ADD

DQS

DQ

tIS

DPD⁴

NOP

VALID⁵

tIS

tIH

VALID

DM

tRP²

T=200us³

Deep Power Down Mode

Exit Deep Power Down Mode

DON'T CARE

Mobile DDR SDRAM Deep Power-Down Entry and Exit

Note:

1. Clock must be stable before exiting deep power down mode. That is, the clock must be cycling within specifications by Ta0.

2. Device must be in the all banks idle state prior to entering Deep Power Down mode.

3. 200us is required before any command can be applied upon exiting DPD.

4. DPD = Deep Power Down command.

5. Upon exiting Deep Power Down a precharge all command must be issued followed by two auto refresh commands and a load

mode register sequence.

Rev 1.0 / Jun. 2008

56

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

CAS LATENCY DEFINITION

CAS latency definition of Mobile DDR SDRAM must be must be loaded when all banks are idle, and the controller must

wait the specified time before initiating the subsequent operation.

CAS latency definition: with CL = 3 the first data element is valid at (2 * tCK + tAC) after the clock at which the READ

command was registered (See Figure 2)

T0

T1

T2

T2n

T3

T3n

T4

T4n

T5

T5n

T6

CK

Read

NOP

CMD

CL = 3

tDQSCK

tRPRE

tRPST

tLZ

DQS

tDQSQ

tAC

tLZ

All DQ values,

collectively²

T2

T2n

T3

T3n

T4

T4n

T5

T5n

CAS LATENCY DEFINITION

NOTE

1. DQ transitioning after DQS transition define tDQSQ window.

2. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.

3. tAC is the DQ output window relative to CK, and is the long term component of DQ skew.

Rev 1.0 / Jun. 2008

57

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

Clock Stop Mode

Clock stop mode is a feature supported by Mobile DDR SDRAM devices. It reduces clock-related power consumption

during idle periods of the device.

Conditions: the Mobile DDR SDRAM supports clock stop in case:

● The last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has

executed to completion, including any data-out during read bursts; the number of required clock pulses per access

command depends on the device's AC timing parameters and the clock frequency;

● The related timing condition (tRCD, tWR, tRP, tRFC, tMRD) has been met;

● CKE is held HIGH.

When all conditions have been met, the device is either in ''idle'' or ''row active'' state, and clock stop mode may be

entered with CK held LOW and CK held HIGH. Clock stop mode is exited when the clock is restarted. NOPs command

have to be issued for at least one clock cycle before the next access command may be applied. Additional clock pulses

might be required depending on the system characteristics.

Figure1 illustrates the clock stop mode:

● Initially the device is in clock stop mode;

● The clock is restarted with the rising edge of T0 and a NOP on the command inputs;

● With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock

stop as soon as this access command has completed;

● Tn is the last clock pulse required by the access command latched with T1.

● The timing condition of this access command is met with the completion of Tn; therefore Tn is the last clock pulse

required by this command and the clock is then stopped.

Tn

T0

T1

T2

CK

CKE

Timing Condition

CMD

ADD

NOP

CMD

Valid

NOP

(High-Z)

Valid

DQ,

DQS

Exit Clock

Stop Mode

Enter Clock

Stop Mode

Clock

Stopped

Don't Care

Command

Clock Stop Mode

Rev 1.0 / Jun. 2008

58

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

1,2)

Data mask

Mobile DDR SDRAM uses a DQ write mask enable signal (DM) which masks write data.

Data masking is only available in the write cycle for Mobile DDR SDRAM. Data masking is available during write, but

data masking during read is not available.

DM command masks burst write data with reference to data strobe signal and it is not related with read data. DM com-

mand can be initiated at both the rising edge and the falling edge of the DQS. DM latency for write operation is zero.

For x32 data I/O, Mobile DDR SDRAM is equipped with DM0, DM1, DM2 and DM3 which control DQ0~DQ7,

DQ8~DQ15, DQ16~DQ23 and DQ24~DQ31 respectively.

Note:

1) Mobile SDR SDRAM can mask both read and write data, but the read mask is not supported by Mobile DDR SDRAM.

2) Differences in Functions and Specifications (next table)

Item

Mobile DDR SDRAM

Mobile SDR SDRAM

Data mask

Write mask only

Write mask/Read mask

CK

WRITE

CMD

tDQSS

tDS

tDH

DM

tDQSL

tDQSH

Hi-Z

DQS

Data

Masking

Data

Masking

Hi-Z

DQ

D0

D1

D3

D0

D1

D3

Data Masking (Write cycle: BL=4)

Rev 1.0 / Jun. 2008

59

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

POWER-UP AND INITIALIZATION SEQUENCES

Mobile DDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other thank

those specified may result in undefined operation. If there is any interruption to the device power, the initialization

routine should be followed. The steps to be followed for device initialization are listed below.

●Step1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up simulta-

neously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are from

the same power source. Also assert and hold CLOCK ENABLE (CKE) to a LVCMOS logic high level.

●Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply stable

clock.

●Step 3: There must be at least 200us of valid clocks before any command may be given to the DRAM. During this

time NOP or DESELECT commands must be issued on the command bus.

●Step 4: Issue a PRECHARGE ALL command.

●Step 5: Provide NOPs or DESELECT commands for at least tRP time.

●Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Issue

the second AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time.

Note as part of the initialization sequence there must be two auto refresh commands issued. The typical

flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.

●Step 7: Using the MRS command, load the base mode register. Set the desired operating modes.

●Step 8: Provide NOPs or DESELECT commands for at least tMRD time.

●Step 9: Using the MRS command, program the extended mode register for the desired operating modes. Note the

order of the base and extended mode register programming is not important.

●Step 10: Provide NOP or DESELCT commands for at least tMRD time.

●Step 11: The DRAM has been properly initialized and is ready for any valid command.

Rev 1.0 / Jun. 2008

60

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

The Initialization flow sequence is below.

VDD

VDDQ

T=200usec

tCK

tRFC

tRP

tMRD

/CLK

CLK

tCH

tCL

CKE

NOP

PRE

ARF

MRS

ACT

CMD

tIS tIH

CODE

RA

BA

ADDR

A10

tIS tIH

ALL

BANKS

CODE

tIS tIH

BA0,

BA1

BA0=L

BA1=L

BA0=L

BA1=H

DM

High-Z

DQ,

DQS

VDD/VDDQ

Powered up

CLOCK stable

Load

Extended

Mode

Load

Mode

Register

Precharge

All

Auto

Refresh

Auto

Refresh

Register

DON'T CARE

Initialization Waveform Sequence

Rev 1.0 / Jun. 2008

61

Mobile DDR SDRAM 128Mbit (4M x 32bit)

H5MS1222EFP Series

PACKAGE INFORMATION

2

90 Ball 0.8mm pitch 8mm FBGA [8.0 x 13.0 mm , t=1.0mm max]

A1 INDEX MARK

8.00 Typ.

0.8

0.8Typ.

Unit [mm]

0.90.

0.80 Typ.

Bottom

View

0.45

+/- 0.05

0.34

+/- 0.05

0.90

0.80

6.40 Typ.

1.00 max

Rev 1.0 / Jun. 2008

62


型号：	H5MS1222EFP-J3E
厂家：	HYNIX SEMICONDUCTOR
描述：	128Mbit MOBILE DDR SDRAM based on 1M x 4Bank x32 I/O 128Mbit的移动DDR SDRAM的基础上1M X 4Bank X32的I / O 存储内存集成电路动态存储器双倍数据速率时钟
文件：	总62页 (文件大小：1782K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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