HM18TS402 [HYNIX]
Liquid Crystal Driver, 402-Segment, CMOS;
| 型号： | HM18TS402 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Liquid Crystal Driver, 402-Segment, CMOS 驱动 接口集成电路 |
| 文件： | 总24页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM18TS402
HM18TS402
402Ch. , 64 Gray Scale Color
TFT LCD SOURCE DRIVER
- 1-
Preliminary
HM18TS402
1. OVERVIEW
The HM18TS402 is a 402 channel output, ultra low power, signal source (column ) driver for a TFT LCD panel. This
device has a digital-to-analog converter using 5 external reference voltages to display 262,144 colors.
2. FEATURES
l
l
l
l
l
18-bit( RGB x 6bit ) parallel color data inputs
402 outputs to driving liquid crystal panel
Support 2-,8-,16- and 64-gray scale modes selection
5 external reference voltages to support gamma correction
Maximum 10MHz operation
l
l
Digital supply voltage, DVDD, 2.5 ~ 3.3 V
Analog supply voltage, AVDD, 5.0±0.5V
l
l
CMOS technology
Support cascade connection
- 2-
Preliminary
HM18TS402
3. BLOCK DIAGRAM
U/D
DI/O
CPH
POL
Shift Register
Sam pling Register
Hold Register
DO/I
XIN0~5
XOR
Operation
YIN0~5
ZIN0~5
LOAD
Mode
Control
GS1~2
PS1~2
Level Shifter
PS Control
IX
Data ControlCircuit
OutputSwitch Circuit
OP AMP
V0~4
AVDD
DVDD
AVSS
DVSS
TESTB1~2
X01
Z01
X134
Z134
Y01
Y134
- 3-
Preliminary
HM18TS402
4. TERMINAL FUNCTIONS
Terminal
I/O
FUNCTION
LCD panel driving terminal.
Name
X01 ~ X134
Y01 ~ Y134
Z01 ~ Z134
LCD Panel
Drive
O
Chip Enable
Data enable terminal.
Input for the start of data transfer and output for the end of data transfer.
U/D terminal controls as followings.
U/D= “H”, DI/O : input
DO/I : output
DI/O
DO/I
U/D= “L”, DO/I : input
I/O
DI/O : output
Case of input: If “H” is received on the rising edge of CPH, the internal
circuits come into data receivable status from stand-by status. Data input
starts to enter from next rising edge of CPH in sequence.
Case of output: Output gives Enable signal to next stage driver. After
making “H” level, the internal circuits comes into stand-by status.
Shift Direction U/D controls the direction in which the data is loaded into the input
register.
U/D
CPH
POL
I
I
I
U/D = “H”, X01~Z01,X02~Z02,X03~Z03……
U/D = “L”, X134~Z134,X133~Z133,X132~Z132……
This terminal uses DC level as “H” or “L” level
Clock
The clock synchronizes the 18-bit (three 6-bit channels) data sampling, and
synchronizes the internal control logic of the HM18TS402. All data are
loaded and moved on at rising edge of CPH.
Data Polarity
Data polarity switching terminal
POL= “H” : Reverse data
POL= “L” : Non-reverse data
Data bus and this signal are operated and the result is obtained
synchronously at the CPH rising edge.
Bias
Controls the bias current.
If IX voltage increases, the amp bias current also increases, and if IX
voltage decreases, then the amp bias current also decreases.
In the production, this terminal is inhibited.
IX
I
- 4-
Preliminary
HM18TS402
Power Save
Power Save
Power saving mode(1)
PS1
I
PS1= “H”: Normal operation
PS1= “L” : Turn off the OP AMP
Power saving mode(2)
PS2
I
I
I
PS2= “H”: Normal operation
PS2= “L” : Turn off the bias circuit of OP AMP
In normal operation, these terminals are tied to DVDD
Reference voltage for g correction of DAC circuit.
VSS£V0£V1£V2£V3£V4£AVDD
VSS£V4£V3£V2£V1£V0£AVDD
TESTB1/2
V0 ~ 4
Test pin
g - Correction
Voltage
Load Pulse
LOAD pulse transfers the data from sampling register to hold register.
The transfer happens after loading the 6bit data into sampling register for all
corresponding channels. Then output buffer outputs analog voltage
corresponding to data as soon.
LOAD
I
I
XIN0~5
YIN0~5
ZIN0~5
Data Input
Data inputs consist of 6-bit word s for three each channels (18bits) for color
input data.
At the rising edge of CPH, each 6-bit data for three adjacent channels
are loaded in parallel.
Data width pin Control the data bus width ( select the display mode )
Control the valid data bit number , then decide the valid color number of
display.
If GS1=GS2=1, V0 and V4 is disconnected from Gamma correction resistor
ladder, so there is no current in resistor ladder.
Setting
Color
Valid bus
number
Gray scale
number
GS1/GS2
I
number
GS1 GS2
262,144
0
0
1
1
0
1
0
1
6 bit
4bit
3bit
1bit
64 gray-scale
16 gray-scale
8 gray-scale
2 gray-scale
4,096
512
8
AVDD
DVDD
AVSS
DVSS
I
I
I
I
Analog Power Power supply for analog block.
Digital Power
Analog GND
Digital GND
Power supply for digital block.
Analog circuit ground.
Digital circuit ground.
- 5-
Preliminary
HM18TS402
5. FUNCTIONAL DESCRIPTIONS
5.1 Data Input
DI/O,DO/I = “H” is loaded into the address shift register on the rising edge of CPH(n).
18bit(6bit x X,Y,Z) data are loaded into sampling register on the rising edge of CPH(n+1).
When LOAD = ”H” after the rising edge of CPH(n+134), the data in each sampling register
are transferred to hold register andthe HM18TS402 outputs analog voltage signal through output buffer.
5.2 Extension of Output
By cascade connection of this device, Enlargement of driving data is available and as a result
it can be used to a larger size screen.
(1) U/D= “L”
DI/O pin of the former chip is connected toDO/Ipin of the next chip.
The other input pins except DI/O and DO/I is connected commonly to each device.
(2) U/D= “H”
DO/I pin of the former chip is connected toDI/O pin of the next chip.
The other input pins except DO/I and DI/O is connected commonly to each device.
5.3 Gray-Scale Data Bus Relationship
The relationship between GS1/2, gray-scale number and color number.
Mode setting
Gray-scale
Data bus
Display
color
262,144
4,096
512
Valid gray -scale data bus
GS1
GS2
nIN5
nIN4
nIN3
nIN2
nIN1
nIN0
0
0
1
1
0
1
0
1
6 bit mode
4 bit mode
3 bit mode
1 bit mode
Valid
Valid
L/H
L/H
L/H
L/H
L/H
L/H
Valid
L/H
L/H
L/H
8
Valid
L/H
- 6-
Preliminary
HM18TS402
g
5.4
- Correction Reference Voltage Circuit
g - correction reference voltage circuit consists of arrays of 13, 20, 21 series-connected resistor.
The reference voltage is fed to OP AMP for impedance conversion and is used as gray-scale voltage of
internal circuit.
Source Driver
V0
V1
R0
R1
External
V2
V3
V4
Voltage source
for reference
voltage
R2
R3
5.5 Input Data Value and Output Voltage
Output voltage is determined by input data value and 5 reference voltage (V0 ~ V4).
And the relationship between input data value and output voltage is as follows.
(1) Reference voltage input for g - Correction (V0 ~ V4)
This external voltage is reference voltage extracted from panel characteristics.
(2) Contents of image data
MSB
LSB
wIN5
wIN4
wIN3
wIN2
wIN1
wIN0
** w in wIN5 ~ 0 is one of X,Y,Z.
g
l
- CorrectionVoltage
Gray-scale Data
00H~13H
Description
Division into equal 20 voltage output between V0~V1
Division into equal 21 voltage output between V1~V2
Division into equal 13 voltage output between V2~V3
Division into equal 13 voltage output between V3~V4
14H~28H
29H~35H
36H~3FH
- 7-
Preliminary
HM18TS402
l Relation with Input Data & Output Voltage( 6bit mode )
Data
D
5
D4 D3 D2 D1 D0 Output Voltage
Data D5 D4 D3 D2 D1 D0 Output Voltage
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
V0
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
V2+(V1-V2) x 9/21
V2+(V1-V2) x 8/21
V2+(V1-V2) x 7/21
V2+(V1-V2) x 6/21
V2+(V1-V2) x 5/21
V2+(V1-V2) x 4/21
V2+(V1-V2) x 3/21
V2+(V1-V2) x 2/21
V2+(V1-V2) x 1/21
V2
0
V1+(V0-V1) x19/20
V1+(V0-V1) x18/20
V1+(V0-V1) x17/20
V1+(V0-V1) x16/20
V1+(V0-V1) x15/20
V1+(V0-V1) x14/20
V1+(V0-V1) x13/20
V1+(V0-V1) x12/20
V1+(V0-V1) x11/20
V1+(V0-V1) x10/20
0
0
0
0
0
0
0
0
0
V3+(V2-V3)
12/13
x
0BH
0CH
0
0
0
0
1
1
0
1
1
0
1
0
V1+(V0-V1) x9/20
V1+(V0-V1) x8/20
2BH
2CH
1
1
0
0
1
1
0
1
1
0
1
0
V3+(V2-V3)
11/13
x
x
V3+(V2-V3)
10/13
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
V1+(V0-V1) x7/20
V1+(V0-V1) x6/20
V1+(V0-V1) x5/20
V1+(V0-V1) x4/20
V1+(V0-V1) x3/20
V1+(V0-V1) x2/20
V1+(V0-V1) x1/20
V1
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
V3+(V2-V3) x 9/13
V3+(V2-V3) x 8/13
V3+(V2-V3) x 7/13
V3+(V2-V3) x 6/13
V3+(V2-V3) x 5/13
V3+(V2-V3) x 4/13
V3+(V2-V3) x 3/13
V3+(V2-V3) x 2/13
V3+(V2-V3) x 1/13
V3
V2+(V1-V2) x 20/21
V2+(V1-V2) x 19/21
V2+(V1-V2) x 18/21
V4+(V3-V4)
12/13
x
18H
19H
0
0
1
1
1
1
0
0
0
0
0
1
V2+(V1-V2) x 17/21
V2+(V1-V2) x 16/21
38H
39H
1
1
1
1
1
1
0
0
0
0
0
1
V4+(V3-V4)
11/13
x
x
V4+(V3-V4)
10/13
1AH
1BH
1CH
1DH
1EH
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
V2+(V1-V2) x 15/21
V2+(V1-V2) x 14/21
V2+(V1-V2) x 13/21
V2+(V1-V2) x 12/21
V2+(V1-V2) x 11/21
3AH
3BH
3CH
3DH
3EH
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
V4+(V3-V4) x 9/13
V4+(V3-V4) x 8/13
V4+(V3-V4) x 7/13
V4+(V3-V4) x 6/13
V4+(V3-V4) x 5/13
- 8-
Preliminary
HM18TS402
1FH
0
1
1
1
1
1
V2+(V1-V2) x 10/21
3FH
1
1
1
1
1
1
V4
- 9-
Preliminary
HM18TS402
l Relation with Input Data & Output Voltage( 4bit mode )
Data
D5 D4 D3 D2 Output Voltage
Data
D5 D4 D3 D2 Output Voltage
00H
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V0
08H
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V2+(V1-V2) x 7/21
01H
02H
03H
04H
05H
06H
07H
V1+(V0-V1) x16/20
V1+(V0-V1) x12/20
V1+(V0-V1) x8/20
V1+(V0-V1) x3/20
V2+(V1-V2) x 20/21
V2+(V1-V2) x 16/21
V2+(V1-V2) x 12/21
09H
0AH
0BH
0CH
0DH
0EH
0FH
V2+(V1-V2) x 3/21
V3+(V2-V3) x 12/13
V3+(V2-V3) x 8/13
V3+(V2-V3) x 3/13
V4+(V3-V4) x 12/13
V4+(V3-V4) x 8/13
V4
l Relation with Input Data & Output Voltage( 3bit mode )
Data
D5 D4 D3 Output Voltage
00H
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V0
01H
02H
03H
04H
05H
06H
07H
V1+(V0-V1) x11/20
V1+(V0-V1) x2/20
V2+(V1-V2) x14/21
V2+(V1-V2) x5/21
V3+(V2-V3) x 9/13
V3
V4
l Relation with Input Data & Output Voltage( 1bit mode )
Data
00H
01H
D5 Output Voltage
0
1
V0
V4
5.6 Correction Resistor Ratio( R0=44kΩ )
R0
R1
R2
R3
1.00
1.00
0.61
1.91
5.7 Power Save Function
This driver controls the OP AMP current using PS1, PS2 terminals.
These control signals are not synchronized with CPH.
5.8 Bias Current Adjustment Circuit
This driver includes IX terminal which provides DC level of bias circuit.
If DC level increases, bias current also increases, and if DC level decreases, bias current also decreases.
- 10 -
Preliminary
HM18TS402
Timing Diagram (1)
DI/O,DO/I
(input)
0
1
2
3
133
134
CPH
*1
XIN0~5
YIN0~5
ZIN0~5
X01/X134 X02/X133 X03/X132
Y01/Y134 Y02/Y133 Y03/Y132
Z01/Z134 Z02/Z133 Z03/Z132
X133/X02
Y133/Y02
Z133/Z02
X134/X01
Y134/Y01
Z134/Z01
X01/X134
Y01/Y134
Z01/Z134
DI/O,DO/I
(output)
*1 X01 : U/D = “H”
X134 : U/D = “L”
Timing Diagram (2)
0
1
2
3
4
133 134 135
0
1
2
3
4
CPH
DI/O,DO/I
(input)
DI/O,DO/I
(output)
First
data
Last
data
First
data
DATA BUS
LOAD
X01~X134
Y01~Y134
Z01~Z134
Hi-Z
- 11 -
Preliminary
HM18TS402
Timing Diagram (3)
Ex) Data vs. POL terminal relationship
0
1
2
3
CPH
DI/O,DO/I
(input)
wIN0
wIN1
wIN2
wIN3
wIN4
wIN5
POL
w=X,Y,Z
Obtained Data
wIN0
wIN1
wIN2
wIN3
wIN4
wIN5
w=X,Y,Z
- 12 -
Preliminary
HM18TS402
6. ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage Range
Symbol
DVDD
AVDD
VIND
Value
Unit
V
Digital
Analog
Digital
Analog
-0.3 ~ 6.0
-0.3 ~ 6.0
V
-0.3 ~ DVDD +0.3
-0.3 ~ AVDD +0.3
-0.3 ~ AVDD +0.3
-0.3 ~ DVDD +0.3
-0.3 ~ AVDD +0.3
-20 ~ 75
V
Input Voltage Range
Output Voltage Range
VINA
V
Gamma Correction Voltage
V0~V4
V
I/O
V
out1
V
OUT
V
out2
V
℃
℃
Operating Temp.range
Storage Temp. Range
Topr
Tstg
-55 ~ 125
Stresses beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions beyond those
indicated in the “Recommended Operating Conditions” section of this specification is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
- 13 -
Preliminary
HM18TS402
7. ELECTRICAL CHARACTERISTICS
DC Characteristics
(Typical is the case of AVDD=5V, DVDD=3V, Ta=25°C)
Parameter
Operating Voltage
Gamma Voltage
Input Current
Symbol
DVDD
AVDD
V0~V4
IIL
Condition
Min
2.5
Typ
Max
3.3
Unit
V
Terminal
DVDD
4.5
5.5
V
AVDD
V0~V4
Note 3
V
L
H
L
H
L
H
1
1
uA
uA
V
Note1
IIH
VIL
0.3DVDD
DVDD
0.5
Input Voltage
Note2
VIH
0.7DVDD
V
VOL
IOL= 0.1mA
0
V
Output Voltage
DI/O,DO/I
VOH
IOH=-0.1mA
DVDD-0.5
DVDD
AVDD-0.1
AVDD
10
V
Output Voltage
Range
VOUT1 VG1~VG62
VOUT2 VG0,VG63
0.1
0
V
X01~X134
Y01~Y134
Z01~Z134
V
Output Offset
VDO
fCPH
CL=30pF,
-10
mV
MHz
Operating Freq.
10
CPH
X01~X134
Y01~Y134
Z01~Z134
Output Load
Capacitance
pF/
pin
CL
30
AIDD1
AIDD2
AIDD3
AIDD4
Note 5
Note 6
Note 7
Note 8
1050
300
150
45
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
uA
Current
AVDD
DVDD
Consumption(1)
AIDDP1 Note 10
AIDDP2 Note 11
45
1
AIDDS
DIDD1
DIDD2
DIDD3
DIDD4
DIDDS
Note 9
Note 5
Note 6
Note 7
Note 8
Note 9
900
600
400
300
100
1
Current
Consumption(2)
Note 1. XIN0~5, YIN0~5, ZIN0~5, DI/O, DO/I, CPH, LOAD, PS1, PS2, GS1, GS2, U/D, TESTB1/2
Note 2. XIN0~5, YIN0~5, ZIN0~5, DI/O, DO/I, CPH, LOAD, PS1, PS2, GS1, GS2, U/D, TESTB1/2
Note 3. V0£V1£V2£V3£V4£ or V4£V3£V2£V1£V0
Note 4. AVDD=5.5V, fCPH=10MHz, 1H=64us, DI/O=”L”
Note 5. DVDD=3.3V, AVDD=5.5V, fCPH=10MHz, 1H=64us, no load, cross-hatch pattern, 6bit mode
Note 6. DVDD=3.3V, AVDD=5.5V, fCPH=10MHz, 1H=64us, no load, cross-hatch pattern 6bit mode
Note 7. DVDD=3.3V, AVDD=5.5V, fCPH=10MHz, 1H=64us, no load, cross-hatch pattern 6bit mode
Note 8. DVDD=3.3V, AVDD=5.5V, fCPH=10MHz, 1H=64us, no load, cross-hatch pattern 6bit mode
Note 9. DVDD=3.3V, AVDD=5.5V, fCPH=10MHz, 1H=64us, no load, 6bit mode, DI/O=”L”
Note 10. DVDD=3.3V, AVDD=5.5V, fCPH=10MHz, 1H=64us, no load, 6bit mode, PS1=”L”
Note 11. DVDD=3.3V, AVDD=5.5V, fCPH=10MHz, 1H=64us, no load, 6bit mode, PS2=”L”
- 14 -
Preliminary
HM18TS402
AC Characteristics (1)
(Typical is the case of AVDD=5V, DVDD=3V, Ta=25°C)
Parameter
CPH pulse width, H
CPH pulse width, L
Enable setup time
Enable hold time
Data setup time
Data hold time
Symbol
tCWH
tCWL
tsDI
Condition
Min
8
Typ
Max
Unit
ns
ns
8
10
2
ns
thDI
ns
tsDD
6
ns
thDD
2
ns
LOAD setup time
LOAD hold time
LOAD “H” time
tsLD
1
CPH
CPH
ns
thLD
1
tLWH
TpdDO1
TpdDO2
tpdDX
TpdDX2
200
10
10
Output delay time
1
2
3
4
CL=10pF
CL=10pF
20
20
4
ns
ns
1 ch. (note 12,13)
402 ch. (note 12,13)
us
30
us
Note 12. Test Circuit
Output terminal load
Output
Test
Terminal
Terminal
30kOhm
30pF
Vcom
* Vcomis 5Vp -p square-wave.
* Output delay time is specified as the time that output voltage enters within output offset.
Note 13. The load which internal amp drives is modeled as follows
Internal
Test
Amp output
Termi nal
30kOhm/n
30pF x n
(n = 0~402)
- 15 -
Preliminary
HM18TS402
tCWH
tCWL
70%
70%
30%
70%
30%
70%
30%
CPH
30%
TpdDO1
TpdDO2
DI/O,DO/I
(input)
70%
30%
tLWH
thLD
70%
tsLD
70%
30%
LOAD
tsDI
70%
tpdDX/tpdDX2
thDI
DI/O,DO/I
(output)
70%
X01~X134
Y01~Y134
Z01~Z134
Hi-Z
tsD
thDD
VIH
VIH
VIL
wIN0~5
w=X,Y,Z
Valid
Data
Valid
Data
Invalid
Data
VIL
AC Characteristics (2)
Parameter
PS2-PS1 time at rising
Symbol
Condition
Min
Typ
Max
Unit
ta
tb
tc
t1
t2
2
5
1
us
us
us
us
us
Return time to display region
PS1-PS2 time at falling
PS1- current moving time
PS2- current moving time
1
1
2
2
Video Display Time
No display region
Display region
No display region
VIH
PS2
VIL
ta
tb
tc
(Bias current)
VIH
PS1
VIL
(Amp)
- 16 -
Preliminary
HM18TS402
Current
AIDDP1
AIDDP2
t1
t2
PS1 = H ® L
PS2 = H ® L
- 17 -
Preliminary
HM18TS402
8.PAD Layout
AVDD
AVSS
DI/O
XIN0
XIN1
XIN2
XIN3
XIN4
XIN5
YIN0
YIN1
YIN2
YIN3
YIN4
YIN5
PS1
DUM M Y
PS2
IX
V0
V1
V2
V3
V4
POL
GS1
GS2
DVSS
TESTB2
DVDD
TESTB1
CPH
LO AD
U/D
ZIN0
ZIN1
ZIN2
ZIN3
ZIN4
ZIN5
DO/I
AVSS
AVDD
- 18 -
Preliminary
HM18TS402
No.
1
PAD
AVDD
X
Y
No.
PAD
X
Y
No.
PAD
X
Y
-8797.5
-8702.5
-8607.5
-8512.5
-8417.5
-8322.5
-8227.5
-8052.5
-7957.5
-7862.5
-7767.5
-7672.5
-7577.5
-7482.5
-7270
-855
34 dum m y
35 ZIN1
-5415
-5270
-5200
-5130
-5015
-4870
-4800
-4730
-4615
-4470
-4400
-4330
-4215
-4070
-4000
-3930
-3815
-3670
-3600
-3530
-3415
-3265
-3205
-2995
-2895
-2795
-2585
-2525
-2315
-2215
-2115
-1900
-1830
-855
67 GS2
68 dum m y
69 GS1
70 GS1
71 GS1
72 dum m y
73 POL
74 POL
75 V4
-1760
-1645
-1500
-1430
-1360
-1245
-1045
-985
-775
-675
-575
-395
-295
-195
-15
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
2
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVSS
AVSS
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
3
36 ZIN1
4
37 ZIN1
5
38 dum m y
39 ZIN0
6
7
40 ZIN0
8
41 ZIN0
9
42 dum m y
43 U/D
10 AVSS
11 AVSS
12 AVSS
13 AVSS
14 AVSS
15 DO/I
16 DO/I
17 DO/I
18 dum m y
19 ZIN5
20 ZIN5
21 ZIN5
22 dum m y
23 ZIN4
24 ZIN4
25 ZIN4
26 dum m y
27 ZIN3
28 ZIN3
29 ZIN3
30 dum m y
31 ZIN2
32 ZIN2
33 ZIN2
76 V4
44 U/D
77 V4
45 U/D
78 V3
46 dum m y
47 LOAD
48 LOAD
49 LOAD
50 dum m y
51 CPH
79 V3
80 V3
81 V2
-7200
82 V2
85
-7130
83 V2
185
-7015
84 V1
365
-6870
52 CPH
85 V1
465
-6800
53 CPH
86 V1
565
-6730
54 dum m y
55 TESTB1
56 TESTB1
57 DVDD
58 DVDD
59 DVDD
60 TESTB2
61 TESTB2
62 DVSS
63 DVSS
64 DVSS
65 GS2
87 V0
745
-6615
88 V0
845
-6470
89 V0
945
-6400
90 IX
1155
1215
1410
1480
1550
1665
1810
1880
1950
2065
-6330
91 IX
-6215
92 PS2
93 PS2
94 PS2
95 dum m y
96 PS1
97 PS1
98 PS1
99 dum m y
-6070
-6000
-5930
-5815
-5670
-5600
-5530
66 GS2
- 19 -
Preliminary
HM18TS402
No.
PAD
X
Y
No.
PAD
X
Y
No.
PAD
X
Y
100 YIN5
101 YIN5
2210
2280
-855
133 XIN3
134 XIN3
5480
5550
-855 166 AM BUM P
-855 167 AM M ETA
L
8800
8800
750
825
-855
102 YIN5
103 dum m y
104 YIN4
105 YIN4
106 YIN4
107 dum m y
108 YIN3
109 YIN3
110 YIN3
111 dum m y
112 YIN2
113 YIN2
114 YIN2
115 dum m y
116 YIN1
117 YIN1
118 YIN1
119 dum m y
120 YIN0
121 YIN0
122 YIN0
123 dum m y
124 XIN5
125 XIN5
126 XIN5
127 dummy
128 XIN4
129 XIN4
130 XIN4
131 dum m y
132 XIN3
2350
2465
2610
2680
2750
2865
3010
3080
3150
3265
3410
3480
3550
3665
3810
3880
3950
4065
4210
4280
4350
4465
4610
4680
4750
4865
5010
5080
5150
5265
5410
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
-855
135 dum m y
136 XIN2
137 XIN2
138 XIN2
139 dum m y
140 XIN1
141 XIN1
142 XIN1
143 dum m y
144 XIN0
145 XIN0
146 XIN0
147 dummy
148 DI/O
5665
5810
5880
5950
6065
6210
6280
6350
6465
6610
6680
6750
6865
7010
7080
7150
7265
-855 168 X1
8621.5
8578.5
8535.5
8492.5
8449.5
8406.5
8363.5
8320.5
8277.5
8234.5
8191.5
8148.5
8105.5
8062.5
8019.5
7976.5
7933.5
7890.5
7847.5
7804.5
7761.5
7718.5
7675.5
7632.5
7589.5
7546.5
7503.5
7460.5
7417.5
7374.5
7331.5
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
-855 169 Y1
-855 170 Z1
-855 171 X2
-855 172 Y2
-855 173 Z2
-855 174 X3
-855 175 Y3
-855 176 Z3
-855 177 X4
-855 178 Y4
-855 179 Z4
-855 180 X5
-855 181 Y5
-855 182 Z5
-855 183 X6
-855 184 Y6
-855 185 Z6
-855 186 X7
-855 187 Y7
-855 188 Z7
-855 189 X8
-855 190 Y8
-855 191 Z8
-855 192 X9
-855 193 Y9
-855 194 Z9
-855 195 X10
-855 196 Y10
-855 197 Z10
-855 198 X11
149 DI/O
150 DI/O
151 dum m y
152 AVSS
153 AVSS
154 AVSS
155 AVSS
156 AVSS
157 AVSS
158 AVSS
159 AVDD
160 AVDD
161 AVDD
162 AVDD
163 AVDD
164 AVDD
165 AVDD
7482.5
7577.5
7672.5
7767.5
7862.5
7957.5
8052.5
8227.5
8322.5
8417.5
8512.5
8607.5
8702.5
8797.5
- 20 -
Preliminary
HM18TS402
No.
PAD
X
Y
No.
PAD
X
Y
No.
PAD
X
Y
199 Y11
200 Z11
201 X12
202 Y12
203 Z12
204 X13
205 Y13
206 Z13
207 X14
208 Y14
209 Z14
210 X15
211 Y15
212 Z15
213 X16
214 Y16
215 Z16
216 X17
217 Y17
218 Z17
219 X18
220 Y18
221 Z18
222 X19
223 Y19
224 Z19
225 X20
226 Y20
227 Z20
228 X21
229 Y21
230 Z21
231 X22
7288.5
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
232 Y22
233 Z22
234 X23
235 Y23
236 Z23
237 X24
238 Y24
239 Z24
240 X25
241 Y25
242 Z25
243 X26
244 Y26
245 Z26
246 X27
247 Y27
248 Z27
249 X28
250 Y28
251 Z28
252 X29
253 Y29
254 Z29
255 X30
256 Y30
257 Z30
258 X31
259 Y31
260 Z31
261 X32
262 Y32
263 Z32
264 X33
5869.5
858 265 Y33
718 266 Z33
858 267 X34
718 268 Y34
858 269 Z34
718 270 X35
858 271 Y35
718 272 Z35
858 273 X36
718 274 Y36
858 275 Z36
718 276 X37
858 277 Y37
718 278 Z37
858 279 X38
718 280 Y38
858 281 Z38
718 282 X39
858 283 Y39
718 284 Z39
858 285 X40
718 286 Y40
858 287 Z40
718 288 X41
858 289 Y41
718 290 Z41
858 291 X42
718 292 Y42
858 293 Z42
718 294 X43
858 295 Y43
718 296 Z43
858 297 X44
4450.5
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
7245.5
7202.5
7159.5
7116.5
7073.5
7030.5
6987.5
6944.5
6901.5
6858.5
6815.5
6772.5
6729.5
6686.5
6643.5
6600.5
6557.5
6514.5
6471.5
6428.5
6385.5
6342.5
6299.5
6256.5
6213.5
6170.5
6127.5
6084.5
6041.5
5998.5
5955.5
5912.5
5826.5
5783.5
5740.5
5697.5
5654.5
5611.5
5568.5
5525.5
5482.5
5439.5
5396.5
5353.5
5310.5
5267.5
5224.5
5181.5
5138.5
5095.5
5052.5
5009.5
4966.5
4923.5
4880.5
4837.5
4794.5
4751.5
4708.5
4665.5
4622.5
4579.5
4536.5
4493.5
4407.5
4364.5
4321.5
4278.5
4235.5
4192.5
4149.5
4106.5
4063.5
4020.5
3977.5
3934.5
3891.5
3848.5
3805.5
3762.5
3719.5
3676.5
3633.5
3590.5
3547.5
3504.5
3461.5
3418.5
3375.5
3332.5
3289.5
3246.5
3203.5
3160.5
3117.5
3074.5
No.
PAD
X
Y
No.
PAD
X
Y
No.
PAD
X
Y
- 21 -
Preliminary
HM18TS402
298 Y44
299 Z44
300 X45
301 Y45
302 Z45
303 X46
304 Y46
305 Z46
306 X47
307 Y47
308 Z47
309 X48
310 Y48
311 Z48
312 X49
313 Y49
314 Z49
315 X50
316 Y50
317 Z50
318 X51
319 Y51
320 Z51
321 X52
322 Y52
323 Z52
324 X53
325 Y53
326 Z53
327 X54
328 Y54
329 Z54
330 X55
3031.5
2988.5
2945.5
2902.5
2859.5
2816.5
2773.5
2730.5
2687.5
2644.5
2601.5
2558.5
2515.5
2472.5
2429.5
2386.5
2343.5
2300.5
2257.5
2214.5
2171.5
2128.5
2085.5
2042.5
1999.5
1956.5
1913.5
1870.5
1827.5
1784.5
1741.5
1698.5
1655.5
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
331 Y55
332 Z55
333 X56
334 Y56
335 Z56
336 X57
337 Y57
338 Z57
339 X58
340 Y58
341 Z58
342 X59
343 Y59
344 Z59
345 X60
346 Y60
347 Z60
348 X61
349 Y61
350 Z61
351 X62
352 Y62
353 Z62
354 X63
355 Y63
356 Z63
357 X64
358 Y64
359 Z64
360 X65
361 Y65
362 Z65
363 X66
1612.5
1569.5
1526.5
1483.5
1440.5
1397.5
1354.5
1311.5
1268.5
1225.5
1182.5
1139.5
1096.5
1053.5
1010.5
967.5
718 364 Y66
858 365 Z66
718 366 X67
858 367 Y67
718 368 Z67
858 369 X68
718 370 Y68
858 371 Z68
718 372 X69
858 373 Y69
718 374 Z69
858 375 X70
718 376 Y70
858 377 Z70
718 378 X71
858 379 Y71
718 380 Z71
858 381 X72
718 382 Y72
858 383 Z72
718 384 X73
858 385 Y73
718 386 Z73
858 387 X74
718 388 Y74
858 389 Z74
718 390 X75
858 391 Y75
718 392 Z75
858 393 X76
718 394 Y76
858 395 Z76
718 396 X77
193.5
150.5
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
107.5
64.5
21.5
-21.5
-64.5
-107.5
-150.5
-193.5
-236.5
-279.5
-322.5
-365.5
-408.5
-451.5
-494.5
-537.5
-580.5
-623.5
-666.5
-709.5
-752.5
-795.5
-838.5
-881.5
-924.5
-967.5
-1010.5
-1053.5
-1096.5
-1139.5
-1182.5
924.5
881.5
838.5
795.5
752.5
709.5
666.5
623.5
580.5
537.5
494.5
451.5
408.5
365.5
322.5
279.5
236.5
No.
PAD
X
Y
No.
PAD
X
Y
No.
PAD
X
Y
397 Y77
-1225.5
718
430 Y88
-2644.5
858 463 Y99
-4063.5
718
- 22 -
Preliminary
HM18TS402
398 Z77
399 X78
400 Y78
401 Z78
402 X79
403 Y79
404 Z79
405 X80
406 Y80
407 Z80
408 X81
409 Y81
410 Z81
411 X82
412 Y82
413 Z82
414 X83
415 Y83
416 Z83
417 X84
418 Y84
419 Z84
420 X85
421 Y85
422 Z85
423 X86
424 Y86
425 Z86
426 X87
427 Y87
428 Z87
429 X88
-1268.5
-1311.5
-1354.5
-1397.5
-1440.5
-1483.5
-1526.5
-1569.5
-1612.5
-1655.5
-1698.5
-1741.5
-1784.5
-1827.5
-1870.5
-1913.5
-1956.5
-1999.5
-2042.5
-2085.5
-2128.5
-2171.5
-2214.5
-2257.5
-2300.5
-2343.5
-2386.5
-2429.5
-2472.5
-2515.5
-2558.5
-2601.5
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
431 Z88
432 X89
433 Y89
434 Z89
435 X90
436 Y90
437 Z90
438 X91
439 Y91
440 Z91
441 X92
442 Y92
443 Z92
444 X93
445 Y93
446 Z93
447 X94
448 Y94
449 Z94
450 X95
451 Y95
452 Z95
453 X96
454 Y96
455 Z96
456 X97
457 Y97
458 Z97
459 X98
460 Y98
461 Z98
462 X99
-2687.5
-2730.5
-2773.5
-2816.5
-2859.5
-2902.5
-2945.5
-2988.5
-3031.5
-3074.5
-3117.5
-3160.5
-3203.5
-3246.5
-3289.5
-3332.5
-3375.5
-3418.5
-3461.5
-3504.5
-3547.5
-3590.5
-3633.5
-3676.5
-3719.5
-3762.5
-3805.5
-3848.5
-3891.5
-3934.5
-3977.5
-4020.5
718 464 Z99
858 465 X100
718 466 Y100
858 467 Z100
718 468 X101
858 469 Y101
718 470 Z101
858 471 X102
718 472 Y102
858 473 Z102
718 474 X103
858 475 Y103
718 476 Z103
858 477 X104
718 478 Y104
858 479 Z104
718 480 X105
858 481 Y105
718 482 Z105
858 483 X106
718 484 Y106
858 485 Z106
718 486 X107
858 487 Y107
718 488 Z107
858 489 X108
718 490 Y108
858 491 Z108
718 492 X109
858 493 Y109
718 494 Z109
858 495 X110
-4106.5
-4149.5
-4192.5
-4235.5
-4278.5
-4321.5
-4364.5
-4407.5
-4450.5
-4493.5
-4536.5
-4579.5
-4622.5
-4665.5
-4708.5
-4751.5
-4794.5
-4837.5
-4880.5
-4923.5
-4966.5
-5009.5
-5052.5
-5095.5
-5138.5
-5181.5
-5224.5
-5267.5
-5310.5
-5353.5
-5396.5
-5439.5
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
No.
PAD
X
Y
No.
PAD
X
Y
No.
PAD
X
Y
496 Y110
497 Z110
-5482.5
-5525.5
858
718
528 X121
529 Y121
-6858.5
-6901.5
858 560 Z131
718 561 X132
-8234.5
-8277.5
858
718
- 23 -
Preliminary
HM18TS402
498 X111
499 Y111
500 Z111
501 X112
502 Y112
503 Z112
504 X113
505 Y113
506 Z113
507 X114
-5568.5
-5611.5
-5654.5
-5697.5
-5740.5
-5783.5
-5826.5
-5869.5
-5912.5
-5955.5
858
718
858
718
858
718
858
718
858
718
530 Z121
531 X122
532 Y122
533 Z122
534 X123
535 Y123
536 Z123
537 X124
538 Y124
539 Z124
-6944.5
-6987.5
-7030.5
-7073.5
-7116.5
-7159.5
-7202.5
-7245.5
-7288.5
-7331.5
858 562 Y132
718 563 Z132
858 564 X133
718 565 Y133
858 566 Z133
718 567 X134
858 568 Y134
718 569 Z134
858 570 AM BUM P
-8320.5
-8363.5
-8406.5
-8449.5
-8492.5
-8535.5
-8578.5
-8621.5
-8800
858
718
858
718
858
718
858
718
750
825
718 571 AM M ETA
-8800
L
508 Y114
509 Z114
510 X115
511 Y115
512 Z115
513 X116
514 Y116
515 Z116
516 X117
517 Y117
518 Z117
519 X118
520 Y118
521 Z118
522 X119
523 Y119
524 Z119
525 X120
526 Y120
527 Z120
-5998.5
-6041.5
-6084.5
-6127.5
-6170.5
-6213.5
-6256.5
-6299.5
-6342.5
-6385.5
-6428.5
-6471.5
-6514.5
-6557.5
-6600.5
-6643.5
-6686.5
-6729.5
-6772.5
-6815.5
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
540 X125
541 Y125
542 Z125
543 X126
544 Y126
545 Z126
546 X127
547 Y127
548 Z127
549 X128
550 Y128
551 Z128
552 X129
553 Y129
554 Z129
555 X130
556 Y130
557 Z130
558 X131
559 Y131
-7374.5
-7417.5
-7460.5
-7503.5
-7546.5
-7589.5
-7632.5
-7675.5
-7718.5
-7761.5
-7804.5
-7847.5
-7890.5
-7933.5
-7976.5
-8019.5
-8062.5
-8105.5
-8148.5
-8191.5
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
858
718
- 24 -
Preliminary
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