HM6C5332 [HYNIX]
HM6C5332 - 1.2GHz/250MHz Dual Frequency Synthesizer; HM6C5332 - 的1.2GHz / 250MHz的双通道频率合成器
| 型号： | HM6C5332 |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | HM6C5332 - 1.2GHz/250MHz Dual Frequency Synthesizer |
| 文件： | 总10页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
HM6C5332
HM6C5332 – 1.2GHz/250MHz Dual Frequency Synthesizer
Features
Description
Full CMOS RF frequency synthesizer
The HM6C5332 of full CMOS monolithic, dual frequency
synthesizer is to be used as a local oscillator for RF and IF
of a dual conversion transceiver. It is fabricated using
Hyundai’s standard CMOS process.
ꢀ
Low Current Consumption
ꢀ
Selectable Powersave Mode
ꢀ
Dual Modulus Prescaler
ꢀ
Selectable Charge Pump High Z State
2.7V to 3.6V Operation
Small Out Line 20 Pin TSSOP Package
24 Pin LGA(Leadless Grid Array) Package
HM6C5332 contains dual modulus prescalers. A 64/65 or
a 128/129 prescaler can be selected for RF synthesizer
and a 8/9 or 16/17 prescaler can be selected for IF
synthesizer. Using digital phase locked loop technique,
HM6C5332 provides the tuning voltage for voltage
controlled oscillators to generate very stable low noise RF
& IF local oscillator signals. Serial data is transferred into
the HM6C5332 via three wire interface (Data, Enable,
Clock). Supply voltage can range from 2.7 to 3.6 V.
HM6C5332 features very low current consumption; 3.2mA
at 3.0V.
ꢀ
ꢀ
ꢀ
Applications
Portable Wireless Communications
Cordless and Cellular Telephone Systems
Wireless Local Area Networks(WLANs)
Cable TV Tuners(CATV)
Other Wireless Communication Systems
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
HM6C5332 is available in a 20-pin TSSOP package and
24-pin LGA (Leadless Grid Array) package
Functional Block Diagram
ꢇꢈ
fIN IF
ꢙꢏꢎꢑꢒꢗꢜꢎꢏ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢕꢆꢊꢋꢌꢍꢅꢎꢏ
ꢙꢖꢗꢑꢎ
DO IF
ꢊꢖꢗꢏꢘꢎꢆꢙꢌꢚꢛ
ꢊꢋꢚꢛ
ꢓ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢉꢆꢊꢋꢌꢍꢅꢎꢏ
ꢈꢋꢌꢅ
!ꢋꢒ ꢆꢞꢎꢅꢎꢒꢅ
#$%
ꢐꢑꢒꢓꢀꢁ
ꢐꢑꢒꢓ
ꢀꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆꢉꢈ
ꢉꢆꢊꢋꢌꢍꢅꢎꢏ
ꢙꢖꢗꢑꢎ
ꢊꢋꢚꢛ
ꢓ
DO RF
ꢊꢖꢗꢏꢘꢎꢆꢙꢌꢚꢛ
ꢀꢔꢂꢃꢄꢅꢆꢉꢈ
ꢕꢆꢊꢋꢌꢍꢅꢎꢏ
ꢊꢜꢋꢒ
ꢞꢗꢅꢗ
!"
ꢝꢝꢂꢃꢄꢅ
ꢉꢈ
ꢙꢏꢎꢑꢒꢗꢜꢎꢏ
fIN RF
ꢞꢗꢅꢗꢆꢉꢎꢘꢄꢑꢅꢎꢏ
ꢀ
PRELIMINARY
Pin Assignment
Leadless Grid Array Package
Thin Shrink Small Outline Package ™
Pin Description
Pin No.
HM6C5332
24-pin LGA
Package
Pin No.
HM6C5332
20-pin TSSOP
Package
PIN
I/O
Description
NAME
Power supply voltage input for RF analog and RF digital circuits. Input may
range from 2.7V to 3.6V. VDDRF must equal VDDIF. Bypass capacitors
should be placed as close as possible to this pin and be connected directly
to the ground plane.
24
1
VDDRF
-
2
3
2
3
VPPRF
DoRF
-
Power Supply for RF charge pump. Must be ≥ VDDRF.
Internal RF charge pump output. For connection to a loop filter for driving
the input of an external VCO.
O
4
5
4
5
VSRFD
finRF
-
I
Ground for RF digital circuitry.
RF prescaler input. Small signal input from the VCO.
This pin is to provide a bypass capacitor to the internal voltage supply and
bypass capacitor must be placed between this pin and RF analog GND(Pin
7). With a slight performance degradation, this pin may be NC.
Ground for RF analog circuitry.
6
6
VIRF
-
7
8
7
8
VSRFA
OSCin
VSS
-
I
Oscillator input. The input has a VDDRF/2 input threshold and can be
driven from an external CMOS or TTL logic gate.
10
11
9
-
Ground for data interface, FoLD, and oscillator circuits.
Multiplexed output of the RF/IF programmable or reference dividers, and
RF/IF lock detect signals. CMOS output(See Programmable Modes)
High impedance CMOS Clock input. Data for the various counters is
clocked in on the rising edge, into the 22-bit shift register.
Binary serial data input. Data entered MSB first. The last two bits are the
control bits. High impedance CMOS input.
10
FoLD
O
12
14
11
12
Clock
Data
I
I
Load enable high impedance CMOS input. When LE goes HIGH, data
stored in the shift register is loaded into one of the 4 appropriate
latches(control bit dependent).
15
13
LE
I
ꢁ
PRELIMINARY
Pin No.
HM6C5332
24-pin LGA
Package
Pin No.
HM6C5332
20-pin TSSOP
Package
PIN
I/O
Description
NAME
16
17
14
15
VSIFA
VIIF
-
-
Ground for IF analog circuitry.
This pin is to provide a bypass capacitor to the internal voltage supply and
bypass capacitor must be placed between this pin and IF analog GND(Pin
14). With a slight performance degradation, this pin may be NC.
IF prescaler input. Small signal input from the VCO.
18
19
20
16
17
18
finIF
VSIFD
DoIF
I
-
Ground for IF digital circuitry.
O
Internal IF charge pump output. For connection to a loop filter for driving
the input of an external VCO.
22
23
19
20
VPPIF
VDDIF
-
-
Power Supply for IF charge pump. Must be ≥ VDDIF.
Power supply voltage input for IF analog, IF digital, data interface, FoLD,
and oscillator circuits. Input may range from 2.7V to 3.6V. VDDIF must
equal VDDRF. Bypass capacitors should be placed as close as possible to
this pin and be connected directly to the ground plane.
No Connect
1,9,13,21
X
NC
-
Block Diagram
FoLD
ꢌꢒꢜꢄ
ꢇꢒꢉ%ꢆꢎꢗꢄꢗꢉꢄ
"ꢜꢖꢄꢃ(ꢖꢗ*ꢗꢑ
ꢀ+ꢆꢆꢆꢆꢆ,+
ꢀ+ꢆꢆꢆꢆꢆ,+
)ꢌꢆ
ꢇꢒꢉ%
&
ꢅꢊꢈ'ꢗꢆ
ꢎꢗꢄꢗꢉꢄꢒꢑ
ꢋꢌꢆ
ꢇꢒꢉ%
&
)ꢌ
ꢛꢊꢈꢑꢓꢗꢆꢅꢜꢔ(
ꢋꢌ
ꢛꢊꢈꢑꢓꢗꢆꢅꢜꢔ(
DoIF
DoRF
ꢅꢊꢈ'ꢗꢆ
ꢎꢗꢄꢗꢉꢄꢒꢑ
ꢞ ꢈꢖꢖꢒ
ꢛꢒꢝꢄꢑꢒꢖ
ꢞ ꢈꢖꢖꢒ
ꢛꢒꢝꢄꢑꢒꢖ
ꢅꢑꢒꢓꢑꢈꢔꢔꢈꢕꢖꢗ
ꢀ!ꢁꢂꢃꢄꢆꢙ)ꢌꢚ
ꢏꢁꢛꢒꢜꢝꢄꢗꢑ
ꢅꢑꢒꢓꢑꢈꢔꢔꢈꢕꢖꢗ
ꢀꢘꢁꢂꢃꢄꢆꢙꢋꢌꢚ
ꢏꢁꢛꢒꢜꢝꢄꢗꢑ
)ꢌꢆꢅꢑꢗ'ꢉꢈꢖꢗꢑ
finRF
ꢋꢌꢆꢃꢝ(ꢜꢄꢆꢕꢜ$$ꢗꢑ
ꢋꢌꢆꢅꢑꢗ'ꢉꢈꢖꢗꢑ
finIF
ꢙ)ꢌꢚꢆꢀ!ꢁꢂꢃꢄ
ꢏꢁꢇꢈꢄꢉꢊ
ꢀꢁꢂꢃꢄ
ꢅꢐꢆꢇꢈꢄꢉꢊ
ꢀꢁꢂꢃꢄꢆ)ꢌꢆ
ꢅꢍꢎꢏ
ꢀꢁꢂꢃꢄꢆꢋꢌꢆ
ꢅꢍꢎꢏ
ꢀꢁꢂꢃꢄ
ꢅꢀꢆꢇꢈꢄꢉꢊ
ꢙꢋꢌꢚꢆꢀꢘꢁꢂꢃꢄ
ꢏꢁꢇꢈꢄꢉꢊ
!ꢁꢂꢃꢄꢆ"ꢒ#ꢗꢆ
ꢇꢈꢄꢉꢊ
ꢀ!ꢁꢂꢃꢄꢆꢋꢌꢆ
ꢋꢀꢆꢇꢈꢄꢉꢊ
ꢇꢈꢄꢉꢊ
ꢎꢗꢉꢒ#ꢗ
LE
ꢅꢑꢒꢓꢑꢈꢔꢔꢈꢕꢖꢗꢆꢀ!ꢁꢂꢃꢄ
ꢙꢋꢀꢚꢆꢋꢗ$ꢗꢑꢗꢝꢉꢗꢆꢛꢒꢜꢝꢄꢗꢑ
OSCin
ꢐꢁꢂꢃꢄꢆ
ꢛꢒꢝꢄꢑꢒꢖꢆ
ꢇꢈꢄꢉꢊ
Data
Clock
ꢅꢑꢒꢓꢑꢈꢔꢔꢈꢕꢖꢗꢆꢀ!ꢁꢂꢃꢄ
ꢙꢋꢐꢚꢆꢋꢗ$ꢗꢑꢗꢝꢉꢗꢆꢛꢒꢜꢝꢄꢗꢑ
ꢐꢐꢁꢂꢃꢄꢆꢞꢊꢃ$ꢄꢆꢋꢗꢓꢃ'ꢄꢗꢑ
!ꢁꢂꢃꢄꢆ"ꢒ#ꢗꢆ
ꢇꢈꢄꢉꢊ
ꢀ!ꢁꢂꢃꢄꢆꢋꢌꢆ
ꢋꢐꢆꢇꢈꢄꢉꢊ
ꢂ
PRELIMINARY
Absolute Maximum Ratings
Operating Conditions
Power Supply Voltage
Power Supply Voltage
VDD
-0.3V to +4.2V
-0.3V to +4.2V
VDD
2.7V to 3.6V
VDD to 3.6V
-40°C to 85°C
VPP
VPP
Voltage on Any Pin
Operating Temperature(TA)
with GND = 0V (VI)
-0.3V to +4.2V
-65°C to +150°C
260°C
Storage Temperature Range (TS)
Lead Temperature (solder 4 sec.) (TL)
Thermal Resistance(Typical) θJA (°C/W)
TSSOP Package
130°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Other conditions
above those indicated in the operational sections of this specification are not implied.
Electrical Characteristics
VDD = 3.0V, -40°C < TA < 85°C, Except as Specified
Symbol
Conditions
Units
Min
Typ
Max
Parameter
VDD=2.7V to 3.6V,
RF
IF
2.2
1.0
mA
mA
f
Φ= 10KHz
VDD=2.7V to 3.6V,
Φ= 10KHz
IDD
Power Supply Current
4.1
f
IDD-PWDN
fINRF
fINIF
fOSC
fΦ
Powerdown Current
Operating Frequency
Operating Frequency
Oscillator Frequency.
VDD=3.0V
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
10
µA
GHz
MHz
MHz
MHz
dBm
dBm
VPP
V
0.5
50
1.2
250
4
40
Maximum Phase Detector Freq.
RF Input Sensitivity
10
-
PfINRF
PfINIF
VOSC
VIH
VDD=2.7V to 3.6V
VDD=2.7V to 3.6V
OSCIN
-10
-10
0.5
0.8 VDD
-
0
IF Input Sensitivity
0
Oscillator Sensitivity
-
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Oscillator Input Current
Oscillator Input Current
High-Level Output Voltage
Low-Level Output Voltage
Data Clock Setup Time
Data Clock Hold Time
*
-
VIL
*
0.2 VDD
V
IIH
VIH =VDD=3.6V*
VIL =0V, VDD=3.6V*
VIH =VDD=3.6V
-1.0
-1.0
-
1.0
µA
IIL
1.0
µA
IIH
100
µA
IIL
VIL =0V, VDD=3.6V
IOH = -500 µA
-100
VDD-0.4
-
-
µA
VOH
VOL
t CS
-
V
0.4
IOL = 500 µA
V
ns
ꢅꢆ
ꢅꢆ
ꢅꢆ
ꢅꢆ
ꢅꢆ
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
50
-
ꢄ
-
-
-
-
t CH
10
t CWH
Clock Pulse Width High
Clock Pulse Width Low
Clock to Load Enable Setup Time
Load Enable Pulse Width
50
t CWL
t ES
50
50
t EW
50
* Clock, Data and LE. Does not include fINRF, fINIF and OSCIN.
ꢃ
PRELIMINARY
Functional Description
The simplified block diagram below shows the 22-bit data
register, two 15-bit R Counters and the 15-bit and 18-bit N
Counters (intermediate latches are not shown). The data
stream is clocked (on the rising edge of Clock) into the
DATA input, MSB first. The last two bits are the Control
Bits. The DATA is transferred into the counters as follows:
CONTROL BITS
C1
C2
0
1
0
1
DATA LOCATION
IF R Counter
RF R Counter
IF N Counter
0
0
1
1
RF N Counter
ꢇꢈ
fIN IF
ꢙꢏꢎꢑꢒꢗꢜꢎꢏ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢕꢆꢊꢋꢌꢍꢅꢎꢏ
ꢙꢖꢗꢑꢎ
DO IF
ꢀꢀꢁꢂ
DO RF
ꢊꢖꢗꢏꢘꢎꢆꢙꢌꢚꢛ
ꢊꢋꢚꢛ
ꢓ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈ
ꢉꢆꢊꢋꢌꢍꢅꢎꢏ
ꢈꢋꢌꢅ
!ꢋꢒ ꢆꢞꢎꢅꢎꢒꢅ
#$%
ꢐꢑꢒꢓꢀꢁ
ꢐꢑꢒꢓ
ꢀꢁꢂꢃꢄꢅꢆꢉꢈ
ꢉꢆꢊꢋꢌꢍꢅꢎꢏ
ꢙꢖꢗꢑꢎ
ꢊꢋꢚꢛ
ꢓ
ꢊꢖꢗꢏꢘꢎꢆꢙꢌꢚꢛ
ꢀꢔꢂꢃꢄꢅꢆꢉꢈ
ꢕꢆꢊꢋꢌꢍꢅꢎꢏ
ꢊꢜꢋꢒ
ꢞꢗꢅꢗ
!"
ꢝꢝꢂꢃꢄꢅ
ꢉꢈ
ꢙꢏꢎꢑꢒꢗꢜꢎꢏ
fIN RF
ꢞꢗꢅꢗꢆꢉꢎꢘꢄꢑꢅꢎꢏ
Programmable Reference Dividers (IF and RF R Counters)
If the Control Bits are 00 or 01 (00 for IF and 01 for RF) data is transferred from the 22bit shift register into a latch which
sets the 15-bit R Counter. Serial data format is shown below.
ꢀꢁꢂ
ꢃꢁꢂ
ꢀꢁ ꢀꢂ
ꢃ
ꢁ
ꢃ
ꢂ
ꢃ
ꢄ
ꢃ
ꢅ
ꢃ
ꢆ
ꢃ
ꢇ
ꢃ
ꢈ
ꢃ
ꢉ
ꢃ
ꢊ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢃ
ꢁꢋ
ꢁꢁ
ꢁꢂ
ꢁꢄ
ꢁꢅ
ꢁꢆ
ꢁꢇ
ꢁꢈ
ꢁꢉ
ꢁꢊ
ꢂꢋ
ꢌꢀꢍꢎꢏꢐꢍꢑꢒꢓꢔꢏꢕꢖ
ꢗꢐꢍꢘꢐꢙꢚꢒꢛꢍꢜꢝꢕ
ꢀꢁꢂꢁꢃꢄꢅꢆꢇꢈꢁꢉꢅꢉꢊꢅꢈꢋꢄꢅꢆꢄꢊꢄꢆꢄꢌꢍꢄꢅꢃꢁꢂꢁꢃꢄꢆꢎꢅꢏ
15-Bit Programmable Reference Divider Ratio (R Counter)
DIVIDE
RATIO
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
4
•
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NOTES:
1. Divide ratios less than 3 are prohibited.
2. Divide ratio: 3 to 32767.
3. R1 to R15: These bits select the divide ratio of the programmable reference divider.
4. Data is shifted in MSB first.
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢈ
ꢇ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
PRELIMINARY
Programmable Divide (N Counter)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the
Control Bits are 10 or 11 (10 for IF counter and 11 for RF counter) data is transferred from the 22-bit shift register into a 4-
bit or 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter),
MSB first. Serial data format is shown below. For the IF N counter bits 5, 6, and 7 are don’t care bits. The RF N counter
does not have don’t care bits.
ꢀꢁꢂ
ꢃꢁꢂ
ꢀꢁ ꢀꢂ
ꢞ
ꢁ
ꢞ
ꢂ
ꢞ
ꢄ
ꢞ
ꢅ
ꢞ
ꢆ
ꢞ
ꢇ
ꢞ
ꢈ
ꢞ
ꢉ
ꢞ
ꢊ
ꢞ
ꢞ
ꢞ
ꢞ
ꢞ
ꢞ
ꢞ
ꢞ
ꢞ
ꢞ
ꢞ
ꢁꢋ
ꢁꢁ
ꢁꢂ
ꢁꢄ
ꢁꢅ
ꢁꢆ
ꢁꢇ
ꢁꢈ
ꢁꢉ
ꢁꢊ
ꢂꢋ
ꢌꢀꢍꢎꢏꢐꢍꢑꢒꢓꢔꢏꢕꢖ
ꢗꢐꢍꢘꢐꢙꢚ
ꢔ!ꢔꢜꢝꢒꢐꢙꢏꢔꢍꢒꢍ"ꢒꢏ#ꢝꢒ$ꢐꢍꢘꢐꢙꢚꢚꢙꢓꢑꢝꢒꢜꢔ!ꢔꢜꢝꢐ%ꢒꢞ
7-Bit Swallow Counter Divide Ratio (A Counter)
RF
IF
DIVIDE
N
7
N
6
N
5
N
4
N
3
N
2
N
1
DIVIDE
N
7
N
N
5
N
N
3
N
2
N
1
RATIO A
RATIO A
6
X
X
•
4
0
0
•
0
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
0
1
X
X
•
X
X
•
0
0
•
0
0
•
0
1
•
1
•
•
127
1
1
1
1
1
1
1
15
X
X
X
1
1
1
1
NOTES:
X = Don’t care condition
1. Divide ratio 0 to 127
2. B ꢀA
11-Bit Programmable Counter Divide Ratio (B Counter)
DIVIDE
N
N
N
N
N
N
N
N
N
N
9
N
8
RATIO A 18
17
16
15
14
13
12
11
10
3
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
1
0
•
1
0
•
4
•
2047
NOTES:
1
1
1
1
1
1
1
1
1
1
1
1. Divide ratio 3 to 2047 (divide ratios less than 3 are prohibited).
2. B ꢀA
Pulse Swallow Function
fVCO = [(P ꢁB) + A] ꢁfOSC/R
f
VCO: Output frequency of external voltage controlled oscillator (VCO)
B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (0ꢂAꢂ127 {RF}, 0ꢂAꢂ15 {IF}, AꢂB)
OSC: Output frequency of the external reference frequency oscillator
f
R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P: Preset modulus of dual modulus prescaler (for IF: P=8 or 16; for RF: P=64 or 128)
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢉ
ꢇ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
PRELIMINARY
Programmable Modes
Several modes of operation can be programmed with bits R16-R18 including the phase detector polarity and charge pump
High Z State. The prescaler and powerdown modes are selected with bits N19 and N20. The programmable modes and
truth table for the programmable modes are shown below.
C1
C2
R16
R17
R18
R19
R20
0
0
1
1
0
1
0
1
IF Phase Detector Polarity
IF ICPO
IF DO High Z
IF LD
RF LD
IF FO
RF Phase Detector Polarity
RF ICPO
RF DO High Z
RF FO
-
-
-
-
-
-
IF Prescaler
RF Prescaler
Powerdown IF
Powerdown RF
Mode Select Truth Table
PHASE DETECTOR
POLARITY
ICPO
RF
POWERDOWN
DO High Z STATE
IF PRESCALER
PRESCALER
(NOTE 1)
(NOTE 2)
0
Negative
Positive
Normal Operation
High Z State
LOW
8/9
64/65
Powered Up
1
HIGH
16/17
128/129
Powered Down
NOTES:
1. Activation of the IF PLL or RF PLL powerdown modes result in the disabling of the respective N counter divider and
debiasing of its respective fIN inputs (to a high impedance state). Powerdown forces the respective charge pump and
phase comparator logic to a High Z State condition. The R counter functionality does not become disabled until both IF
and RF powerdown bits are activated. The OSCIN pin reverts to a high impedance state when this condition exists. The
control register remains active and capable of loading and latching in data during all the powerdown modes.
FO LD (Pin 10) Output Truth Table
RF R[19]
(RF LD)
IF R[19]
(IF LD)
RF R[20]
(RF FO)
IF R[20]
(IF FO)
FO OUTPUT STATE
0
0
1
1
X
X
X
X
0
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
0
0
0
0
1
0
1
0
1
1
1
1
Disabled (Note1)
IF Lock Detect (Note2)
RF Lock Detect (Note2)
RF/IF Lock Detect (Note2)
IF Reference Divider Output
RF Reference Divider Output
IF Programmable Divider Output
RF Programmable Divider Output
For Internal Use Only
For Internal Use Only
For Internal Use Only
1
Counter Reset (Note4)
X = don’t care condition
NOTES:
1. When the FO LD output is disabled, it is actively pulled to a low logic state.
2. Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is
selected, the pins output is HIGH, with narrow pulse LOW. In the RF/IF lock detect mode a locked condition is indicated when RF and
IF are both locked.
3. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits then N counter resumes
counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R
counter is also forced to Reset, allowing smooth acquisition upon powering up.
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢊ
ꢇ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
PRELIMINARY
Phase Detector Polarity
ꢀꢁꢂꢃꢁꢄꢅꢆꢅꢇꢈꢉꢆꢊꢋꢈꢊꢇꢋ
ꢀꢁꢂ
Depending upon VCO characteristics, R16 bit should be
set accordingly:
When VCO characteristics are positive like (1), R16
should be set HIGH; When VCO characteristics are
negative like (2), R16 should be set LOW.
ꢄꢅꢆ
ꢆꢇꢈꢉꢇꢈ
ꢊꢋꢌꢍꢇꢌꢎꢏꢐ
ꢀꢃꢂ
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢃꢀꢉꢊꢈꢋꢌꢍ
Serial Data Input Timing
ꢞꢂꢋ,ꢒꢛ-.
ꢞꢁꢊ
&'&
ꢞꢁꢋ
ꢞꢊ
ꢀꢁ,ꢒ(-.
ꢀꢂ
ꢌꢃꢁꢊꢖ
ꢌꢃꢁꢋꢖ
ꢌꢃꢊꢖ
ꢌꢃꢉꢖ
ꢌꢃꢂꢋ,ꢒꢛ-.ꢖ
ꢌꢀꢂꢖ
ꢌꢀꢁ,ꢒ(-.ꢖ
ꢀ()ꢀ*
ꢏꢀꢄꢅ
(+
(+
ꢏꢀꢁ
ꢏꢃꢄ
ꢏꢀꢂ
ꢏꢀꢄꢂ
)ꢃ
ꢏꢃꢁ
NOTES:
1. Parenthesis data indicates programmable reference divider data.
2. Data shifted into register on clock rising edge.
3. Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VDD/2. The test waveform
has an edge rate of 0.6V/ns with amplitudes of 2.2V at VDD = 2.7V and 2.6V at VDD = 3.6V.
Phase Comparator and Internal Charge Pump Characteristics
"
ꢆ
"
ꢇ
(
ꢌ
ꢎ
ꢎ
ꢎ
ꢈ
ꢍ
ꢎ
ꢏ
"ꢆꢒ/ꢒ"ꢇ
"ꢆꢒ0ꢒ"ꢇ
"ꢆꢒ1ꢒ"ꢇ
"ꢆꢒ1ꢒ"ꢇ
"ꢆꢒ1ꢒ"ꢇ
NOTES:
1. Phase difference detection range: -2ꢃto +2ꢃ
2. The minimum width pump up and pump down current pulse occur at the DO pin when the loop is locked.
3. R16 = HIGH
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢋ
ꢇ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
PRELIMINARY
Powerdown Operation
Synchronous and asynchronous powerdown modes are both available. Synchronously powerdown occurs if the respective
loop’s R18 bit (Do High Z State) is LOW when its N20 bit (Powerdown) becomes HI. Asynchronous powerdown occurs if
the loop’s R18 bit is HI when its N20 bit becomes HI. In the synchronous powerdown mode, the powerdown function is
gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program bit N20 is loaded, the
part will go into powerdown mode when the charge pump reaches a High Z condition. In the asynchronous powerdown
mode, the device powers down immediately after the LE pin latches in a HI condition on the powerdown bit N20. Activation
of either the IF or RF PLL powerdown conditions in either synchronous or asynchronous modes forces the respective
loop’s R and N dividers to their load state condition and debiasing of its respective fin input to a high impedance state. The
oscillator circuitry function does not become disabled until both IF and RF powerdown bits are activated. The control
register remains active and capable of loading and latching data during all of the powerdown modes. The device returns to
an actively powered up condition in either synchronous or asynchronous modes immediately upon LE latching LOW data
into bit N20.
Powerdown Mode Select Table
R18
0
N20
0
Powerdown Status
PLL Active
1
0
1
0
1
1
PLL Active (Charge Pump High Z State)
Synchronous Powerdown Initiated
Asynchronous Powerdown Initiated
Physical Dimensions (unit : ꢀ)
Leadless Grid Array Package
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢐ
ꢇ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
PRELIMINARY
Physical Dimensions continued
(unit : ꢀ)
Thin Shrink Small Outline Package
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ
ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢇ ꢀꢑ
ꢇ
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
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