HMS77C1000A-XXXD [HYNIX]
Microcontroller, 8-Bit, 20MHz, CMOS, PDSO18, SOP-18;
| 型号： | HMS77C1000A-XXXD |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | Microcontroller, 8-Bit, 20MHz, CMOS, PDSO18, SOP-18 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总45页 (文件大小：549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-BIT SINGLE-CHIP MICROCONTROLLERS
HMS77C1000A
HMS77C1001A
User’s Manual (Ver. 2.0)
Version 1.1
Published by
MCU Application Team
2001 Hynix Semiconductor All right reserved.
Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed
at address directory.
Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice.
The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible
for any violations of patents or other rights of the third party generated by the use of this manual.
HMS77C1000A/HMS77C1001A
Contents of Table
Port RB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I/O Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . 24
I/O Successive Operations . . . . . . . . . . . . . . . 24
OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
TIMER0 MODULE AND TMR0 REGISTER 26
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 2
PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . 3
PACKAGE DIAGRAM . . . . . . . . . . . . . . . . . 4
PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . 6
PORT STRUCTURES . . . . . . . . . . . . . . . . . 7
ELECTRICAL CHARACTERISTICS . . . . . . 9
Timer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . 27
Using Timer0 with an External Clock . . . . . . . 28
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CONFIGURATION AREA . . . . . . . . . . . . . 30
OSCILLATOR CIRCUITS . . . . . . . . . . . . . 31
Absolute Maximum Ratings . . . . . . . . . . . . . . . 9
Recommended Operating Conditions . . . . . . . 9
DC Characteristics (1). . . . . . . . . . . . . . . . . . . 10
DC Electrical Characteristics (2) . . . . . . . . . . 11
AC Electrical Characteristics (1) . . . . . . . . . . 12
AC Electrical Characteristics (2) . . . . . . . . . . 13
Typical Characteristics . . . . . . . . . . . . . . . . . . 14
XT, HF or LF Mode . . . . . . . . . . . . . . . . . . . . 31
RC Oscillation Mode . . . . . . . . . . . . . . . . . . . 31
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 34
Internal Reset Timer (IRT) . . . . . . . . . . . . . . . 36
WATCHDOG TIMER (WDT) . . . . . . . . . . . 37
WDT Period . . . . . . . . . . . . . . . . . . . . . . . . . . 37
WDT Programming Considerations . . . . . . . . 37
ARCHITECTURE . . . . . . . . . . . . . . . . . . . 17
CPU Architecture . . . . . . . . . . . . . . . . . . . . . . 17
MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-Down Mode (SLEEP) . . . . . . . . . . 38
SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Wake-up From SLEEP . . . . . . . . . . . . . . . . . . 39
Minimizing Current Consumption . . . . . . . . . . 39
Program Memory . . . . . . . . . . . . . . . . . . . . . . 18
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . 18
Special Function Registers . . . . . . . . . . . . . . 19
TIME-OUT SEQUENCE AND POWER DOWN
STATUS BITS (TO/PD) . . . . . . . . . . . . . 41
I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . 24
Port RA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
POWER FAIL DETECTION PROCESSOR 42
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
HMS77C1000A / HMS77C1001A
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
1. OVERVIEW
1.1 Description
The HMS77C1000A and HMS77C1001A are an advanced CMOS 8-bit microcontroller with 0.5K/1K words(12-bit) of
EPROM. The Hynix Semiconductor HMS77C1000A and HMS77C1001A are a powerful microcontroller which provides a
high flexibility and cost effective solution to many small applications. The HMS77C1000A and HMS77C1001A provide the
following standard features: 0.5K/1K words of EPROM, 25 bytes of RAM, 8-bit timer/counter, power-on reset, on-chip os-
cillator and clock circuitry. In addition, the HMS77C1000A and HMS77C1001A supports power saving modes to reduce
power consumption.
Device name
HMS77C1000A
HMS77C1001A
ROM Size
RAM Size
25 bytes
25 bytes
Package
0.5K words(12-bit)
1K words(12-bit)
18 PDIP, SOP or 20 SSOP
18 PDIP, SOP or 20 SSOP
1.2 Features
• High-Performance RISC CPU:
-
-
Internal Reset Timer (IRT)
-
-
-
-
-
12-bit wide instructions and 8-bit wide data path
33 single word instructions
Watchdog Timer (WDT) with on-chip RC oscilla-
tor
-
-
-
Programmable code-protection
0.5K/1K words on-chip program memory
25 bytes on-chip data memory
Power saving SLEEP mode
Selectable oscillator options: Configuration word
Minimum instruction execution time
200ns @20MHz
RC: Low-cost RC oscillator (200KHz~4MHz)
XT: Standard crystal/resonator (455KHz~4MHz)
HF: High-speed crystal/resonator (4~20MHz)
LF: Power saving, low-frequency crystal/resonator
(32~200KHz)
-
-
-
Operating speed: DC - 20 MHz clock input
Seven special function hardware registers
Two-level hardware stack
• CMOS Technology:
• Peripheral Features:
-
Low-power, high-speed CMOS EPROM technol-
ogy
-
-
Twelve programmable I/O lines
One 8-bit timer/counter with 8-bit programmable
prescaler
-
-
Fully static design
Wide-operating range:
2.5V to 5.5V @ RC, XT, LF
4.5V to 5.5V @ HF
-
-
Power-On Reset (POR)
Power Fail Detector : noise immunity circuit
2 level detect ( 2.7V, 1.8V )
Oct. 2001 Ver. 2.0
1
HMS77C1000A/HMS77C1001A
2. BLOCK DIAGRAM
8-bit
Timer/
Counter
OPTION
STATUS
PC
STACK 1
STACK 2
ALU
W
Data
Memory
Power Fail Detector
System controller
Program
Memory
WDT/
TMR0
Prescaler
RESET
WDT time out
Xin
Clock Generator
Timing Control
Xout
Watch-dog
Timer
Instruction
Decoder
V
DD
Configuration Word
V
SS
Power
Supply
RA
TRISA
RB
TRISB
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
EC0
2
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
3. PIN ASSIGNMENT
18 PDIP or SOP
RA2
RA3
EC0
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RA1
RA0
Xin
RESET/V
Xout
PP
SS
V
V
DD
RB7
RB6
RB0
RB1
RB2
RB3
RB5
RB4
20 SSOP
RA2
RA3
EC0
1
20
19
18
17
16
15
14
13
12
11
RA1
RA0
Xin
2
3
RESET/V
4
Xout
PP
SS
SS
V
V
5
V
V
DD
DD
6
RB7
RB6
RB0
RB1
RB2
RB3
7
8
9
RB5
RB4
10
Oct. 2001 Ver. 2.0
3
HMS77C1000A/HMS77C1001A
4. PACKAGE DIAGRAM
unit: inch
MAX
18 PDIP
MIN
TYP 0.300
0.925
0.895
0.270
0.245
0.022
0.015
0 ~ 15°
0.065
0.045
TYP 0.10
18 SOP
0.461
0.451
0 ~ 8°
0.029
0.014
0.040
0.024
TYP 0.050
4
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
20 SSOP
unit: inch
MAX
MIN
0.289
0.278
0 ~ 8°
0.015
0.010
0.037
0.025
TYP 0.0256
Oct. 2001 Ver. 2.0
5
HMS77C1000A/HMS77C1001A
5. PIN FUNCTION
V
V
DD: Supply voltage.
SS: Circuit ground.
RA pins can be used as outputs or inputs according to “0”
or “1” written the their Port Direction Register(TRISA).
RB0~RB7
: RB is a 8-bit, CMOS, bidirectional I/O port.
RB pins can be used as outputs or inputs according to “0”
or “1” written the their Port Direction Register(TRISB).
RESET
: Reset the MCU.
X
IN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
EC0
: EC0 is an external clock input to Timer0. It should
X
OUT: Output from the inverting oscillator amplifier.
be tied to VSS or VDD, if not in use, to reduce current con-
sumption.
RA0~RA3
: RA is an 4-bit, CMOS, bidirectional I/O port.
DIP, SOP
Pin No.
SSOP
Pin No.
Input
Levels
PIN NAME
In/Out
Function
V
P
P
-
-
14
5
15,16
5,6
Supply voltage
DD
V
Circuit ground
SS
Reset signal input/programming voltage input. This pin is an active low
I
I
ST
ST
-
reset to the device. Voltage on the RESET pin must not exceed V to
avoid unintended entering of programming mode.
RESET
4
4
DD
X
16
15
18
17
Oscillator crystal input/external clock source input
IN
Oscillator crystal output. Connects to crystal or resonator in crystal oscilla-
tor mode. In RC mode, X
pin outputs CLKOUT which has 1/4 the fre-
X
O
OUT
OUT
quency of X , and denotes the instruction cycle rate.
IN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
17
18
1
19
20
1
4-bit bi-directional I/O ports
2
2
6
7
7
8
8
9
9
10
11
12
13
14
8-bit bi-directional I/O ports
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
10
11
12
13
Clock input to Timer0. Must be tied to V or V , if not in use, to reduce
current consumption.
DD
SS
I
ST
EC0
3
3
TABLE 5-1 PINOUT DESCRIPTION
Legend : I =input, O = output, I/O = input/output, P = power, - = Not used, TTL = TTL input, ST = Schmitt Trigger input
6
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
6. PORT STRUCTURES
• RESET
Internal RESET
V
SS
• Xin, Xout
( XT, HF, LF Mode )
V
DD
EN ( XT, HF, LF )
Xout
To Internal Clock
V
SS
R
F
Amplifier varies with
the oscillation mode
Xin
( RC Mode )
V
DD
EN ( RC )
Xout
÷ 4
V
SS
Internal
Capacitance ( appx. 6pF )
To Internal Clock
Xin
Oct. 2001 Ver. 2.0
7
HMS77C1000A/HMS77C1001A
• RA0~3/RB0~7
V
DD
Data Reg.
Data Bus
Direction Reg.
Data Bus
Data Bus
V
SS
Read
• EC0
V
DD
EC0
Timer Counter Clock Input
V
SS
8
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage.............................................. -0 to +7.5 V
Storage Temperature ................................-65 to +125 °C
Voltage on RESET with respect to VSS .......0.3 to 13.5V
Voltage on any pin with respect to VSS. -0.3 to VDD+0.3
Maximum current out of VSS pin........................150 mA
Maximum current into VDD pin ..........................100 mA
Maximum output current sunk by (IOL per I/O Pin)25 mA
Maximum current (ΣIOL).................................... 120 mA
Maximum current (ΣIOH)...................................... 80 mA
Note: Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional op-
eration of the device at any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect device reliability.
Maximum output current sourced by (IOH per I/O Pin)
...............................................................................20 mA
7.2 Recommended Operating Conditions
Specifications
Unit
Parameter
Symbol
Condition
Min.
Max.
fXIN=20MHz
fXIN=4MHz
RC Mode
XT Mode
HF Mode
LF Mode
4.5
2.5
0.2
0.455
4
5.5
5.5
4
VDD
Supply Voltage
V
4
MHz
fXIN
Operating Frequency
20
200
85
32
KHz
TOPR
Operating Temperature
-40
°C
Oct. 2001 Ver. 2.0
9
HMS77C1000A/HMS77C1001A
7.3 DC Characteristics (1)
• (TA=-40°C~+85°C)
Specification
Typ1
Parameter
Supply Voltage
Symbol
Test Condition
Unit
V
Min
Max
VDD
XT, RC, LF
HF
DD start voltage to ensure
2.5
4.5
5.5
5.5
V
VPOR
VSS
-
-
0.05
-
-
-
-
V
V/mS
V
Power-On Reset
2
VDD rise rate
SVDD
RAM Data Retention
Voltage
VDR
1.5
Power Fail Detection
VPFD
Normal Level
Low Level
-
-
2.7
1.8
-
-
V
Supply Current
XT, RC4
HF
XIN = 4MHz, VDD = 5V
-
-
-
-
-
1.8
9.0
17
4
3.3
20
40
14
5
mA
mA
uA
3
IDD
XIN = 20MHz, VDD = 5V
XIN = 32KHz, VDD = 3V, WDT Disabled
VDD = 3V, WDT Enabled
LF
5
Power Down Current
uA
IPD
VDD = 3V, WDT Disabled
0.4
1.
2.
3.
Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
This parameter is characterized but not tested.
The test conditions for all I measurements in NOP execution are:
DD
X
= external square wave; all I/O pins tristated, pulled to V , EC0 = V , RESET = V ; WDT disabled/enabled as specified.
SS DD DD
IN
4.
5.
Does not include current through R
Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V and V as
The current through the resistor can be estimated by the formula; I = V /2R (mA)
ext. R DD ext
DD
SS
like measurement conditions of supply current.
10
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
7.4 DC Electrical Characteristics (2)
• (TA=-40°C~+85°C)
Specification
Unit
Parameter
Symbol
Test Condition
Typ1
Min
Max
Input High Voltage
0.25VDD +0.8
0.85VDD
I/O Ports (TTL)
VDD
RESET, EC0, (ST)
XIN (ST)
VIH
V
V
0.85VDD
RC only
XIN (ST)
0.7VDD
XT, HF, LF
Input Low Voltage
0.15VDD
0.15VDD
0.15VDD
0.3VDD
I/O Ports (TTL)
RESET, EC0, (ST)
XIN (ST)
VSS
VIL
RC only
XIN (ST)
XT, HF, LF
Hysteresis of Schmitt
Trigger Inputs
2
VHYS
V
0.15VDD
VIN = VDD or VSS
XT, HF, LF
Input Leakage Current
IL
XIN (ST)
Other Pins
Output High Voltage
uA
-3.0
-1.0
0.5
0.2
3.0
1.0
IOH = -5.0mA, VDD = 4.5V
VDD - 0.9
VDD
I/O Ports
XOUT
VOH
V
V
IOH = -0.5mA, VDD = 4.5V, RC osc.
Output Low Voltage
IOL = 8.0mA, VDD = 4.5V
VSS
0.8
I/O Ports
XOUT
VOL
IOL = 0.6mA, VDD = 4.5V, RC osc.
1.
2.
Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
This parameter are characterized but not tested.
Oct. 2001 Ver. 2.0
11
HMS77C1000A/HMS77C1001A
7.5 AC Electrical Characteristics (1)
• (TA=-40°C~+85°C)
Specification
Parameter
Symbol
FXIN
Test Condition
XT osc mode
Unit
Min
DC
DC
DC
DC
0.1
4.0
5.0
250
50
5
Typ
Max
4.0
20
200
4.0
4.0
20
200
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MHz
MHz
KHz
MHz
MHz
MHz
KHz
nS
External Clock Input
Frequency
HF osc mode
LF osc mode
RC osc mode
XT osc mode
HF osc mode
LF osc mode
XT osc mode
HF osc mode
LF osc mode
RC osc mode
XT osc mode
HF osc mode
LF osc mode
XT osc mode
HF osc mode
LF osc mode
XT osc mode
HF osc mode
LF osc mode
Oscillator Frequency 1
FXIN
TXIN
TXIN
External Clock Input
Period
-
nS
-
uS
250
250
50
5
-
nS
10,000
250
200
-
nS
Oscillator Period 1
nS
uS
85
20
2
nS
Clock in XIN Pin 1
Low to High Time
TXINL
-
nS
TXINH
-
uS
-
25
25
50
nS
Clock in XIN Pin 1
Rise or Fall Time
TXIN
TXIN
R
F
-
nS
-
nS
1.
This parameter is characterized but not tested.
12
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
7.6 AC Electrical Characteristics (2)
• (TA=-40°C~+85°C)
Specification
Unit
Parameter 1
Symbol
Test Condition
Typ2
-
Min
100
Max
TRESET VDD = 5V
RESET Pulse Width (Low)
-
nS
mS
mS
Watchdog Timer Time-Out
Period ( No-prescaler )
TWDT
TIRT
VDD = 5V
VDD = 5V
9
9
18
18
30
30
Internal Reset Timer Period
EC0 High or Low Pulse Width
No Prescaler
TEC0
H
TCY = 4 X TXIN
10
-
-
-
-
nS
nS
TEC0L
0.5TCY + 20
With Prescaler
EC0 Period
N = Prescaler Value
( 1,2,4,......256 )
No Prescaler
TEC0P
20
-
-
-
-
(TCY+40) / N
With Prescaler
1.
2.
These parameters are characterized but not tested.
Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
T
H
XIN
T
L
XIN
T
XIN
0.85V
DD
XIN
0.15V
T
XIN
R
T
F
XIN
T
RESET
RESET
EC0
0.15V
DD
T
H
EC0
T
H
EC0
0.85V
DD
0.15V
DD
T
EC0
P
Oct. 2001 Ver. 2.0
13
HMS77C1000A/HMS77C1001A
7.7 Typical Characteristics
These graphs and tables are for design guidance only and
are not tested or guaranteed.
The data is a statistical summary of data collected on units
from different lots over a period of time. “Typical” repre-
sents the mean of the distribution while “max” or “min”
represents (mean + 3σ) and (mean − 3σ) respectively
where σ is standard deviation
In some graphs or tables the data presented are out-
side specified operating range (e.g. outside specified
V
DD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
Operating Area
Normal Operation
f
XIN
I
DD−VDD
(MHz)
I
DD
Ta= 25°C
Ta=25°C
(mA)
4
24
20
16
12
f
= 20MHz
XIN
3
2
4MHz
32KHz
5
8
4
0
1
0
V
(V)
6
DD
2
3
4
V
DD
(V)
2
3
6
4
5
I
OL−VOL, VDD=5V
I
OL−VOL, VDD=3V
I
I
OL
OL
(mA)
(mA)
Ta=25°C
Ta=25°C
40
18
32
24
16
12
6
0
8
0
V
(V)
V
OL
OL
(V)
1.2 1.6 2.0
0.4 0.8
1.2 1.6 2.0
0.4 0.8
14
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
I
OH−VOH, VDD=5V
I
OH−VOH, VDD=3V
I
I
OH
OH
(mA)
(mA)
Ta=25°C
Ta=25 C
°
-20
-8
-16
-12
-6
-4
-8
-4
0
-2
0
V
-V
(V)
DD OH
V
-V
(V)
DD OH
0.5
1.0
1.5
0.5
1.0
1.5
2.0
Typical RC Oscillator
Frequency VS. VDD
Typical RC Oscillator
Frequency VS. VDD
F
OSC
F
OSC
(MHz)
4.5
(MHz)
Cext=20pF
Cext=0pF
Ta=25°C
Ta=25°C
7.5
R=3.3K
R=5K
R=3.3K
R=5K
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
6.0
4.5
3.0
1.5
0
R=15K
R=15K
R=100K
R=100K
V
DD
V
6
(V)
DD
2.5
3
3.5
4
4.5
5
5.5
6
(V)
2.5
3
3.5
4
4.5
5
5.5
Typical RC Oscillator
Frequency VS. VDD
Typical RC Oscillator
Frequency VS. VDD
F
F
OSC
(MHz)
0.8
OSC
(MHz)
2.00
Cext=300pF
Ta=25°C
Cext=100pF
Ta=25°C
R=3.3K
R=3.3K
0.7
1.75
0.6
0.5
1.50
1.25
R=5K
R=5K
0.4
0.3
1.00
0.75
R=15K
R=15K
0.2
0.50
0.1
0
0.25
0
R=100K
R=100K
V
V
DD
DD
2.5
3
3.5
4
4.5
5
5.5
6
(V)
2.5
3
3.5
4
4.5
5
5.5
6
(V)
Oct. 2001 Ver. 2.0
15
HMS77C1000A/HMS77C1001A
Average
Fosc @ 5V,25°C
6.5MHz
Cext
Rext
3.3K
5K
5.4MHz
0pF
15K
100K
3.3K
5K
2.3MHz
400KHz
4.3MHz
3.5MHz
20pF
15K
100K
3.3K
5K
1.4MHz
240KHz
1.8MHz
1.5MHz
100pF
300pF
15K
100K
3.3K
5K
610KHz
100KHz
780KHz
630KHz
260KHz
42.5KHz
15K
100K
Table 7-1 RC Oscillator Frequencies
16
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
8. ARCHITECTURE
8.1 CPU Architecture
The HMS700 core is a RISC-based CPU and uses a modi-
fied Harvard architecture. This architecture uses two sepa-
rate memories with separate address buses, one for the
program memory and the other for the data memory. This
architecture adapts 33 single word instructions that are 12-
bit wide instruction and has an internal 2-stage pipeline
(fetch and execute), which results in execution of one in-
struction per single cycle(200ns @ 20MHz) except for pro-
gram branches.
The HMS77C100XA can address 1K x 12 Bits program
memory and 25 Bytes data memory. And it can directly or
indirectly address data memory.
The HMS700 core has three special function registers -
PC, STATUS and FSR - in data memory map and has ATU
(Address Translation Unit) to provide address for data
memory and has an 8-bit general purpose ALU and work-
ing register(W) as an accumulator. The W register consists
of 8-bit register and it can not be an addressed register.
Program Memory Address
Instruction
PC with 2-level Stack
STATUS
Immediate Data
FSR
Indirect Address
Instruction
Decode
&
Control
Unit
Address Translation
Unit
Control
Signals
W
ALU
Status
ALU
Data Bus
Data Memory Bus
FIGURE 8-1 HMS700 CPU BLOCK DIAGRAM
Oct. 2001 Ver. 2.0
17
HMS77C1000A/HMS77C1001A
9. MEMORY
The HMS77C100XA has separate memory maps for pro-
gram memory and data memory. Program memory can
only be read, not written to. It can be up to 1K words of
program memory. Data memory can be read and written to
32 bytes including special function registers.
PC<9:0>
Stack Level 1
Stack Level 2
9.1 Program Memory
The program memory is organized as 0.5K, 12-bit wide
words(HMS77C1000A) and 1K, 12-bit wide
words(HMS77C1001A). The program memory words are
addressed sequentially by a program counter. Increment-
ing at location 1FFH(HMS77C1000A) or 3FFH
(HMS77C1001A) will cause a wrap around to 000H.
000
H
On-chip
Program
Memory
(Page 0)
0FF
H
100
H
1FF
H
Figure 9-1 and Figure 9-2 show a map of program memo-
ry. After reset, CPU begins execution from reset vector
which is stored in address(1FFH: HMS77C1000A, 3FFH:
HMS77C1001A).
200
H
On-chip
Program
Memory
(Page 1)
2FF
H
H
300
PC<8:0>
3FF
H
Reset Vector
Stack Level 1
Stack Level 2
FIGURE 9-2 HMS77C1001A PROGRAM MEMORY MAP
AND STACK
000
H
9.2 Data Memory
The data memory consists of 25 bytes of RAM and seven
special function registers. The data memory locations are
addressed directly or indirectly by using FSR.
On-chip
Program
Memory
0FF
H
100
H
Figure 9-3 shows a map of data memory. The special func-
tion registers are mapped into the data memory..
1FF
H
Reset Vector
File Address
00
H
00
01
02
03
04
05
06
INDF
TMR0
PCL
Special
Function
Registers
H
H
H
H
H
H
H
FIGURE 9-1 HMS77C1000A PROGRAM MEMORY MAP
AND STACK
06
07
H
H
DATA
MEMORY
(SRAM)
STATUS
FSR
0F
H
RA
10
H
DATA
MEMORY
(SRAM)
RB
1F
H
FIGURE 9-3 HMS77C100XA DATA MEMORY MAP
18
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
9.3 Special Function Registers
This devices has seven special function register that are the
INDF register, the Program Counter(PC), the STATUS
register, File Select Register(FSR), 8-bit Timer(TMR0),
and I/O data register(RA, RB).
the device (Table 9-1).
TMR0, RA and RB are not in the G700 CPU. They are lo-
cated in each peripheral function blocks. All special func-
tion register are placed on data memory map. The INDF
register is not a physical register and this register is used
for indirect addressing mode...
The Special Function Registers are registers used by the
CPU and peripheral functions to control the operation of
Power-On
Reset
RESET and
WDT Reset
Name
TRIS
Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
N/A
N/A
I/O control registers (TRISA, TRISB)
1111 1111
0011 1111
1111 1111
0011 1111
Contains control bits to configure Timer0, Timer0/WDT
prescaler and PFD
OPTION
INDF
Uses contents of FSR to address data memory (not a
physical register)
00H
xxxx xxxx
uuuu uuuu
01H
02H
03H
04H
05H
06H
TMR0
PCL
8-bit real-time clock/counter
Low order 8bits of PC
xxxx xxxx
1111 1111
0001 1xxx
1xxx xxxx
---- xxxx
xxxx xxxx
uuuu uuuu
1111 1111
000q quuu
1uuu uuuu
---- uuuu
uuuu uuuu
STATUS
FSR
-
-
PA0
Indirect data memory address pointer
RA3 RA2 RA1 RA0
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
TO
PD
Z
DC
C
RA
-
-
-
-
RB
TABLE 9-1 SPECIAL FUNCTION REGISTER SUMMARY
Legend : Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’
x = unknown, u = unchanged, q = see the tables in Section 17 for possible values.
9.3.1 INDF Register
The INDF register is not physically implemented register,
Direct Addressing
(opcode)
Indirect Addressing
(FSR)
used for indirect addressing mode. If the INDF register
are accessed, CPU goes to indirect addressing mode. Then
CPU accesses the Data memory which address is the con-
tents of FSR.
4
0
4
0
location
select
location
00
H
select
If the INDF register are accessed in indirect addressing
mode(I.e., FSR=00H), 00H will be loaded into data bus.
This time, note the arithmetic status bits of STATUS reg-
ister may be affected.
0F
10
Data
Memory
H
The FSR<4:0> bits are used to select data memory ad-
dresses 00H to 1FH.
H
HMS77C1000A and HMS77C1001A do not use banking.
FSR<7:5> are unimplemented and read as '1's.
1F
H
FIGURE 9-4 DIRECT/INDIRECT ADDRESSING
Oct. 2001 Ver. 2.0
19
HMS77C1000A/HMS77C1001A
9.3.2 TMR0 Register
subroutine call instruction
The TMR0 register is a data register for 8-bit timer/
counter. In reset state, the TMR0 register is initialized with
“00H”.
8
7
0
PC
PCL
9.3.3 Program Counter (PC)
Instruction Word
The program counter contains the 10-bit address of the in-
struction to be executed(9-bit address for
HMS77C1000A).
Reset to ‘0’
FIGURE 9-5 LOADING OF BRANCH INSTRUCTION -
HMS77C1000A
The lower 8 bits of the program counter are contained in
the PCL register which can be provided by the instruction
word for a call instruction, or any instruction where the
PCL is the destination while the ninth bit of the program
counter comes from the page address bit - PA0 of the STA-
TUS register(HMS77C1001A only).
jump instruction
9
8
0
PC
PCL
This is necessary to cause program branches across pro-
gram memory page boundaries.
Instruction Word
PA0
Prior to the execution of a branch operation, the user must
initialize the PA0 bit of STATUS register.
subroutine call Instruction
The eighth bit of the program counter can come from the
instruction word by execution of goto instruction, or can be
cleared by execution of call or any instruction where the
PCL is the destination.
9
8
7
0
PC
PCL
In reset state, the program counter is initialized with
“1FFH”(HMS77C1000A) or “3FFH”(HMS77C1001A).
Instruction Word
Reset to ‘0’
PA0
Note: Because PC<8> is cleared in the subroutine call in-
struction, or any Modify PCL instruction, all subrou-
tine calls or computed jumps are limited to the first
256 locations of any program memory page (512
words long).
FIGURE 9-6 LOADING OF BRANCH INSTRUCTION -
HMS77C1001A
9.3.4 Stack Operation
jump instrunciton
The HMS77C100XA have a 2-level hardware stack. The
stack register consists of two 9-bit save regis-
ters(HMS77C1000A), 10-bit save regis-
ters(HMS77C1001A). A physical transfer of register
contents from the program counter to the stack or vice ver-
sa, and within the stack, occurs on call and return instruc-
tions. If more than two sequential call instructions are
executed, only the most recent two return address are
stored. If more than two sequential return instructions are
executed, the stack will be filled with the address previous-
ly stored in level 2. The stack cannot be read or written by
8
0
PC
PCL
Instruction Word
20
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
program.
RESET status, and the page select bit for program memo-
ries larger than 512 words.
The STATUS register can be the destination for any in-
struction, as with any other register. If the STATUS regis-
ter is the destination for an instruction that affects the Z,
DC or C bits, then the write to these three bits is disabled.
These bits are set or cleared according to the device logic.
Furthermore, the TO and PD bits are not writable. There-
fore, the result of an instruction with the STATUS register
as destination may be different than intended.
HMS77C1001A(HMS77C1000A)
9(8)
0
PC
subroutine call
return
STACK LEVEL1
STACK LEVEL2
subroutine call
return
It is recommended that only instructions that do not affect
status of CPU be used on STATUS register. Care should be
exercised when writing to the STATUS register as the
ALU status bits are updated upon completion of the write
operation, possibly leaving the STATUS register with a re-
sult that is different than intended. In reset state, the STA-
TUS register is initialized with “00011XXXB”.
FIGURE 9-7 OPERATION OF 2-LEVEL STACK
9.3.5 STATUS Register
This register contains the arithmetic status of the ALU, the
ADDRESS ; 03H
RESET VALUE : 0001_1XXX
R/W
PA0
R
R
R/W
Z
R/W
DC
R/W
C
-
-
TO
PD
R = Readable bit
W = Writable bit
bit7
bit0
PA0: Program memory page select bits
DC: Digit carry/borrow bit
0 = page 0 (000h - 1FFh) - HMS77C1000A/
1001A
(for addition and subtraction)
addition
1 = page 1 (200h - 3FFh) - HMS77C1001A
1 = A carry from the 4th low order bit of the result
occurred
0 = A carry from the 4th low order bit of the result
did not occur
subtraction
1 = A borrow from the 4th low order bit of the
result did not occur
TO: Time-overflow bit
1 = After power-up, watchdog clear instruction, or
entering power-down mode
0 = A watchdog timer time-overflow occurred
0 = A borrow from the 4th low order bit of the
result occurred
PD: Power-down bit
1 = After power-up or by the watchdog clear
instruction
0 = By execution of power-down mode
C: Carry/borrow bit
(for additon,subtraction and rotation)
addition
Z: Zero bit
1 = A carry occurred
0 = A carry did not occur
subtraction
1 = A borrow did not occur
0 = A borrow occurred
rotation
1 = The result of an arithmetic or logic operation
is zero
0 = The result of an arithmetic or logic operation
is not zero
Load bit with LSB or MSB, respectively
FIGURE 9-8 STATUS REGISTER
Oct. 2001 Ver. 2.0
21
HMS77C1000A/HMS77C1001A
9.3.6 FSR Register
dressing mode.
The FSR register is an 8-bit register. The lower 5 bits are
used to store indirect address for data memory. The upper
3 bits are unimplemented and read as “0”. Figure 9-9
shows how the FSR register can be used in indirect ad-
In reset state, the FSR register is initialized with
“1XXX_XXXXB”.
Instruction Word
11
5
4
0
8
4
0
Address : 04H
RESET Value: 1XXX_XXXX
-
-
-
OPCODE
FSR
B
Direct Addressing mode
Indirect Addressing mode
0
1
Data Memory Address
FIGURE 9-9 FSR REGISTER AND DIRECT/INDIRECT ADDRESSING MODE
9.3.7 OPTION Register
To modify the OPTION register, the content of W register
are transferred to the OPTION register by executing the
OPTION instruction.
The OPTION register consists of 8-bit write-only register
and can not addressed. This register is able to control the
status of PFD, TMR0/WDT prescaler and TMR0.
In reset state, the OPTION register is initialized with
“00111111B” .
22
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
ADDRESS ; N/A
RESET VALUE : 0011_1111
W
W
W
W
W
W
W
W
LOWOPT PFDEN
bit7
T0CS
5
T0SE
4
PSA
3
PS2
2
PS1
1
PS0
W = Writable bit
-n = Value at POR reset
6
bit0
LOWOPT: Power-fail detection level select bit.
PS2-PS0:
Prescaler rate select bits)
1 = Lowered detection level (1.8V @ 5V)
0 = Normal detection level (2.7V @ 5V)
Bit Value Timer 0 rate
WDT rate
1:1
000
001
010
011
100
101
110
111
1:2
1:4
PFDEN:
T0CS:
T0SE:
Power-fail detection enable bit
1 = Enable power-fail detection
0 = Disable power-fail detection
1:2
1:8
1:4
Timer 0 clock source select bit
1 = Transition on EC0 pin
0 = Internal instruction cycle clock
1:16
1:32
1:64
1:128
1:256
1:8
1:16
1:32
1:64
1:128
Timer 0 source edge select bit
1 = Increment on high-to-low transition on
EC0
0 = Increment on low-to-high transition on
EC0
PSA:
Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to the Timer 0
FIGURE 9-10 OPTION REGISTER
Oct. 2001 Ver. 2.0
23
HMS77C1000A/HMS77C1001A
10. I/O PORTS
The HMS77C100XA has a 4-bit I/O port(RA) and a 8-bit
I/O port(RB).
10.2 Port RB
RB is an 8-bit I/O register. Each I/O pin can independently
used as an input or an output through the port direction reg-
ister, TRISB. A “0” in the TRISB register configure the
corresponding port pin as output. Conversely, write “1”to
the corresponding bit to specify it as input pin.
All pin have data(RA,RB) and direction(TRISA,TRISB)
registers which can assign these ports as output or input.
A “0” in the port direction registers configure the corre-
sponding port pin as output. Conversely, write “1” to the
corresponding bit to specify it as input pin (Hi-Z state).
ADDRESS : 06H
RESET VALUE : Undefined
RB Data Register
For example, to use the even numbered bit of RB as output
ports and the odd numbered bits as input ports, write “55H”
to TRISB register during initial setting as shown in Figure
10-1.
3
2
1
0
7
6
5
4
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
RB
RB Direction Register ADDRESS : N/A
RESET VALUE : FFH
All the port direction registers in the HMS77C100XA have
“1” written to them by reset function. This causes all port
as input.
TRISB
Write “55H” to port RB direction register
FIGURE 10-3 RB PORT REGISTERS
7
6
5
4
3
2
1
0
TRISB
0
1
0
1
0
1
0
1
Note: A read of the ports reads the pins, not the output
data latches. That is, if an output driver on a pin is
enabled and driven high, but the external system is
holding it low, a read of the port will indicate that the
pin is low.
O UT IN O UT IN O UT IN O UT IN
PORT RB
FIGURE 10-1 EXAMPLE OF PORT I/O ASSIGNMENT
10.3 I/O Interfacing
10.1 Port RA
The equivalent circuit for an I/O port pin is shown in Fig-
ure 10-4. All ports may be used for both input and output
operation.
RA is a 4-bit I/O register. Each I/O pin can independently
used as an input or an output through the port direction reg-
ister, TRISA. A “0” in the TRISA register configure the
corresponding port pin as output. Conversely, write “1”to
the corresponding bit to specify it as input pin.
For input operations these ports are non-latching. Any in-
put must be present until read by an input instruction. The
outputs are latched and remain unchanged until the output
latch is rewritten. To use a port pin as output, the corre-
sponding direction control bit (in TRISA, TRISB) must be
cleared (= 0). For use as an input, the corresponding TRIS
bit must be set. Any I/O pin can be programmed individu-
ally as input or output..
Bits 7-4 are unimplemented and read as '0's.
RA Data Register
ADDRESS : 05H
RESET VALUE : Undefined
3
2
1
0
RA RA3 RA2 RA1 RA0
10.4 I/O Successive Operations
The actual write to an I/O port happens at the end of an in-
struction cycle, whereas for reading, the data must be valid
at the beginning of the instruction cycle (Figure 10-5).
Therefore, care must be exercised if a write followed by a
read operation is carried out on the same I/O port.
RA Direction Register ADDRESS : N/A
RESET VALUE : 0FH
TRISA
FIGURE 10-2 RA PORT REGISTERS
The sequence of instructions should allow the pin voltage
to stabilize (load dependent) before the next instruction,
which causes that file to be read into the CPU, is executed.
24
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
V
DD
Data Reg.
Data Bus
Direction Reg.
Data Bus
Data Bus
V
SS
Read
FIGURE 10-4 EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN
Power-On
Reset
RESET and
WDT Reset
Name
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TRIS
RA
N/A
05H
06H
I/O control registers (TRISA, TRISB)
1111 1111
---- xxxx
xxxx xxxx
1111 1111
---- uuuu
uuuu uuuu
-
-
-
-
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
RB
RB7
RB6
RB5
RB4
TABLE 10-1 SUMMARY OF PORT REGISTERS
Legend: Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’, x = unknown, u = unchanged.
Otherwise, the previous state of that pin may be read into
the CPU rather than the new state.
When in doubt, it is better to separate these instructions
with a NOP or another instruction not accessing this I/O
port.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
This example shows a write
to RB followed by a read
from RB.
PC
PC+1
PC+2
PC+3
Instruction
fetched
output RB
no operation
no operation
read RB port
RB7:RB0
Port pin
Port pin
written here
read here
FIGURE 10-5 SUCCESSIVE I/O OPERATION
Oct. 2001 Ver. 2.0
25
HMS77C1000A/HMS77C1001A
11. TIMER0 MODULE AND TMR0 REGISTER
The Timer0 module has the following features:
• Edge select for external clock
• 8-bit timer/counter register, TMR0
• 8-bit software programmable prescaler
• Internal or external clock select
Figure 11-1 is a simplified block diagram of the Timer0
module, while Figure 11-2 shows the electrical structure of
the Timer0 input.
T
( = F
/4)
OSC
CY
Data bus
0
1
8
1
0
MUX
Sync with
Internal
Clocks
MUX
PSA
TMR0 reg
EC0
pin
(2cycle delay)
T0SE
T0CS
0
1
clear
MUX
PSA
8-bit Prescaler
Watchdog
Timer
8
8 - to - 1 MUX
PS2:PS0
WDT Enable bit
0
1
MUX
PSA
WDT Time-Out
FIGURE 11-1 BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
P
R
IN
Noise Filter
(1)
ECO
pin
N
Schmitt Trigger
Input Buffer
Note 1: ESD protection circuits
FIGURE 11-2 ELECTRICAL STRUCTURE OF EC0 PIN
26
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
- With Prescaler (PSA=1)
11.1 Timer Mode
Timer will increment with prescaler division ratio.
@ PS2~PS0 = (1:2) ~ (1:256)Counter Mode
If the OPTION register bit5(T0CS) is cleared, the timer
mode is selected and is operated with internal system clock
(TCY). The Timer0 module will increment every instruc-
tion cycle (without prescaler). If TMR0 register is written,
the increment is inhibited for the following two cycles. The
user can work around this by writing an adjusted value to
the TMR0 register.
11.2 Counter Mode
If the OPTION register bit5(T0CS) is set, the counter
mode is selected and operates with event clock input.
In this mode, Timer0 will increment either on every rising
or falling edge of pin EC0. The incrementing edge is deter-
mined by the source edge select bit T0SE (OPTION<4>).
Clearing the T0SE bit selects the rising edge.
Figure 11-3 and Figure 11-4 show the timing diagram of
Timer.
- No Prescaler (PSA=0)
Timer will increment every instruction cycle(Q4).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
[ W ’ TMR0 ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
Instruction
Executed
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed
reads NT0
reads NT0
reads NT0
reads NT0+1 reads NT0+2
T0
T0+1
T0+2
NT0
NT0+1 NT0+2
TMR0
increment inhibited
Timer0
Clock
FIGURE 11-3 TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
[ W ’ TMR0 ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
Instruction
Executed
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed
reads NT0
reads NT0
reads NT0
reads NT0+1 reads NT0+2
T0
T0+1
NT0
NT0+1
TMR0
increment inhabited
Timer0
Clock
FIGURE 11-4 TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2
Oct. 2001 Ver. 2.0
27
HMS77C1000A/HMS77C1001A
Power-On RESET and
Reset WDT Reset
Name
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
01H
TMR0
8-bit real-time clock/counter
LOWOPT PFDEN T0CS T0SE PSA
xxxx xxxx uuuu uuuu
0011 1111 0011 1111
OPTION N/A
PS2
PS1
PS0
TABLE 11-1 REGISTERS ASSOCIATED WITH TIMER0
Legend: x = unknown, u = unchanged.
chronization and the increment of the counter mode.
11.3 Using Timer0 with an External Clock
• EC0 clock specification
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock requirement
is due to internal phase clock (TOSC) synchronization. Al-
so, there is a delay in the actual incrementing of Timer0 af-
ter synchronization.
- No Prescaler (PSA = 0)
High or low time(min) ≥ 2TXIN + 20ns
- With Prescaler (PSA = 1)
High or low time(min) ≥ 4TXIN + 40ns
But, there is a noise filter on the EC0 pin, the minimum low
or high time(10ns) should be required.
11.3.1 External Clock Synchronization
The synchronization of EC0 input with the internal phase
clocks is accomplished by sampling EC0 clock or the pres-
caler output on the Q2 and Q4 falling of the internal phase
clocks.
11.3.2 Timer0 Increment Delay
Since the prescaler output is synchronized with the internal
clocks, there is a small delay from the time the external
clock edge occurs to the time the Timer0 module is actual-
ly incrementing. Figure 11-5 shows the delay from the ex-
ternal clock edge to the timer incrementing.
After the synchronization, counter increments on the next
instruction cycle (Q4). There is a small delay from the time
the external clock edge occurs to the time the Timer0 mod-
ule is actually incrementing. Figure 11-5 shows the syn-
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small Pulse
misses sampling
External Clock Input or
Prescaler Output
(2)
(1)
(3)
External Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4)
TMR0
T0
T0+1
T0+2
Note 1: Delay from clock input change to TMR0 increment is 3T
to 7T
. (Duration of Q = T ).
XIN XIN
XIN
Therefore, the error in measuring the interval between two edges on TMR0 input = ±4T
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
max.
XIN
FIGURE 11-5 TIMER0 TIMING WITH EXTERNAL CLOCK
control bit PSA (OPTION<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is neither
readable nor writable.
11.4 Prescaler
The prescaler may be used by either the Timer0 module or
the Watchdog Timer, but not both. Thus, a prescaler as-
signment for the Timer0 module means that there is no
prescaler for the WDT, and vice-versa.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio. When the prescal-
er is assigned to the Timer0 module, prescale values of 1:2,
The prescaler assignment is controlled in software by the
28
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
1:4,..., 1:256 are selectable.
signed to WDT, a CLRWDT instruction will clear the
prescaler along with the WDT.
When assigned to the Timer0 module, all instructions writ-
ing to the TMR0 register will clear the prescaler. When as-
On a RESET, the prescaler contains all '0's.
Oct. 2001 Ver. 2.0
29
HMS77C1000A/HMS77C1001A
12. CONFIGURATION AREA
The device configuration area can be programmed or left
unprogrammed to select device configurations such as os-
cillator type, security bit or watchdog timer enable bit.
Four memory locations [AAAH ~ (AAA+3)H] are desig-
nated as customer ID recording locations where the user
can store check-sum or other customer identification num-
bers. These area are not accessible during normal execu-
tion but are readable and writable during program/verify
mode. It is recommended that only the 4 least significant
bits of ID recording locations are used.
bit11
4 3
bit0
AAA
-
-
-
-
ID0
ID1
ID2
ID3
H
AAA +1
H
AAA +2
H
AAA +3
H
Configuration Word
FFF
H
FIGURE 12-1 DEVICE CONFIGURATION AREA
bit11
4
3
2
1
bit0
Address : FFFH
Configuration Word
bit 3
-
CP
WDTE FOSC1 FOSC0
Unimplemented, read as ‘0’
CP : Code protection bit.
1 = Code protection disabled
0 = Code protection enabled
bit 2
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator selection bits
11 = RC oscillator
10 = HF oscillator
01 = XT oscillator
00 = LF oscillator
FIGURE 12-2 CONFIGURATION WORD FOR HMS77C100XA
30
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
13. OSCILLATOR CIRCUITS
HMS77C100XA supports four user-selectable oscillator
modes. The oscillator modes are selected by programming
the appropriate values into the configuration word.
Osc
Type
Resonator
Freq
Cap.Range
C1
Cap. Range
C2
XT
455 kHz
2.0 MHz
4.0 MHz
22-100 pF
15-68 pF
15-68 pF
22-100 pF
15-68 pF
15-68 pF
- XT : Crystal/Resonator
- HF : High Speed Crystal/Resonator
- LF : Low Speed and Low Power Crystal
- RC : External Resistor/Capacitor
HF
4.0 MHz
8.0 MHz
16.0 MHz
15-68 pF
10-68 pF
10-22 pF
15-68 pF
10-68 pF
10-22 pF
13.1 XT, HF or LF Mode
TABLE 13-1 CAPACITOR SELECTION FOR CERAMIC
RESONATORS
In XT, LF or HF modes, a crystal or ceramic resonator is
connected to the XIN and XOUT pins to establish oscillation
(Figure 13-1). The HMS77C100XA oscillator design re-
quires the use of a parallel cut crystal. Use of a series cut
crystal may give a frequency out of the crystal manufactur-
ers specifications. Bits 0 and 1 of the configuration register
(FOSC1:FOSC2) are used to configure the different exter-
nal resonator/crystal oscillator modes. These bits allow the
selection of the appropriate gain setting for the internal
driver to match the desired operating frequency. When in
XT, LF or HF modes, the device can have an external clock
source drive the XIN pin (Figure 13-2). In this case, the
Note: These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for ap-
propriate values of external components.
Osc
Type
Crystal
Freq
Cap.Range
C1
Cap. Range
C2
32 kHz1
100 kHz
200 kHZ
LF
15 pF
15-30 pF
15-30 pF
15 pF
30-47 pF
15-82 pF
XOUT pin should be left open.
XT
100 kHz
200 kHz
455 kHz
1 MHz
2 MHz
4 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-47 pF
200-300 pF
100-200 pF
15-100 pF
15-30 pF
15-30 pF
15-47 pF
(1)
C1
X
OUT
SLEEP
To internal
(2)
XTAL
RF
logic
X
IN
HF
4 MHz
8 MHz
20 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
(1)
C2
Note 1: See Capacitor Selection tables for recommended
values of C1 and C2.
TABLE 13-2 CAPACITOR SELECTION FOR CRYSTAL
2: RF varies with the crystal chosen
(approx. value = 9 MΩ).
1. For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended.
Note: These values are for design guidance only. Since
each crystal has its own characteristics, the user
should consult the crystal manufacturer for appropri-
ate values of external components.
FIGURE 13-1 CRYSTAL OR CERAMIC RESONATOR
(HF, XT OR LF OSC CONFIGURATION)
If you change from this device to another device,
please verify oscillator characteristics in your
application.
Clock from
ext. system
X
IN
HMS77C100XA
X
OUT
OPEN
13.2 RC Oscillation Mode
The external RC oscillator mode provides a cost-effective
approach for applications that do not require a precise op-
erating frequency. In this mode, the RC oscillator frequen-
FIGURE 13-2 EXTERNAL CLOCK INPUT OPERATION
(HF, XT OR LF OSC CONFIGURATION)
Oct. 2001 Ver. 2.0
31
HMS77C1000A/HMS77C1001A
cy is a function of the supply voltage, the resistor(R) and
capacitor(C) values, and the operating temperature.
The Electrical Specifications sections show R frequency
variation from part to part due to normal process variation.
In addition, the oscillator frequency will vary from unit to
unit due to normal manufacturing process variations. Fur-
thermore, the difference in lead frame capacitance between
package types also affects the oscillation frequency, espe-
cially for low C values. The external R and C component
tolerances contribute to oscillator frequency variation as
well.
Also, see the Electrical Specifications sections for variation of os-
cillator frequency due to VDD for given Rext/Cext values as well
as frequency variation due to operating temperature for given R,
C, and VDD values.
The oscillator frequency, divided by 4, is available on the
XOUT pin, and can be used for test purposes or to synchro-
nize other logic.
The user also needs to take into account variation due to
tolerance of external R and C components used.
V
DD
Figure 13-3 shows how the R is connected to the
HMS77C100XA. For Rext values below 2.2 kΩ, the oscil-
lator operation may become unstable, or stop completely.
For very high Rext values (e.g., 1 MΩ) the oscillator be-
comes sensitive to noise, humidity and leakage. Thus, we
recommend keeping Rext between 3 kΩ and 100 kΩ. Ta-
ble 13-3 shows recommended value of Rext and Cext.
R
ext
X
IN
Internal
Clock
N
C
ext
Although the oscillator will operate with no external ca-
pacitor (Cext = 0 pF), it is recommend using values above
20 pF for noise and stability reasons. With no or small ex-
ternal capacitance, the oscillation frequency can vary dra-
matically due to changes in external capacitances, such as
PCB trace capacitance or package lead frame capacitance.
F
/4
XIN
X
OUT
FIGURE 13-3 RC OSCILLATION MODE
Average FXIN @ 5V, 25°C
Cext
Rext
3.3K
5K
15K
100K
6.5MHz
5.4MHz
2.3MHz
400KHz
0pF
3.3K
5K
15K
100K
4.3MHz
3.5MHz
1.4MHz
240KHz
20pF
100pF
300pF
3.3K
5K
15K
100K
1.8MHz
1.5MHz
610KHz
100KHz
3.3K
5K
15K
100K
780KHz
630KHz
260KHz
42.5KHz
TABLE 13-3 RC OSCILLATION FREQUENCIES
32
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
14. RESET
HMS77C100XA devices may be reset in one of the follow-
ing ways:
Table 14-2 lists a full description of reset states of all reg-
isters. Figure 14-1 shows a simplified block diagram of the
on-chip reset circuit.
- Power-On Reset (POR)
- Power-Fail detect reset (PFDR)
- RESET (normal operation)
- RESET wake-up reset (from SLEEP)
- WDT reset (normal operation)
- WDT wake-up reset (from SLEEP)
PCL
Addr: 02H
STATUS
Addr: 03H
Condition
Power-On Reset
1111 1111
1111 1111
0001 1xxx
000u uuuu1
RESET reset or PFD
reset (normal operation)
Each one of these reset conditions causes the program
counter to branch to reset vector address. (HMS77C1000A
is 1FFH and HMS77C1001A is 3FFH ).
RESET wake-up or PFD
reset (from SLEEP)
1111 1111
1111 1111
1111 1111
0001 0uuu
Table 14-1 shows these reset conditions for the PCL and
STATUS registers.
WDT reset (normal
operation)
0000 uuuu2
0000 0uuu
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset state”
on Power-On Reset (POR), PFDR, RESET or WDT reset.
A RESET or WDT wake-up from SLEEP also results in a
device reset, and not a continuation of operation before
SLEEP.
WDT wake-up (from
SLEEP)
TABLE 14-1 RESET CONDITIONS FOR SPECIAL
REGISTERS
1. TO and PD bits retain their last value until one of the other
reset conditions occur.
2. The CLRWDT instruction will set the TO and PD bits.
The TO and PD bits (STATUS <4:3>) are set or cleared
depending on the different reset conditions. These bits may
be used to determine the nature of the reset.
Legend : x = unknown, u = unchanged.
Power-On
Reset
Wake-up
Reset
RESET, PFDR,
WDT Reset
Register
Address
W
N/A
N/A
N/A
00H
01H
02H
xxxx xxxx
1111 1111
0011 1111
xxxx xxxx
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
0011 1111
uuuu uuuu
uuuu uuuu
1111 1111
uuuu uuuu
1111 1111
0011 1111
uuuu uuuu
uuuu uuuu
1111 1111
TRIS
OPTION
INDF
TMR0
PCL1
STATUS1
FSR
03H
04H
0001 1xxx
1xxx xxxx
---- xxxx
xxxx xxxx
xxxx xxxx
100q quuu
1uuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
000q quuu
1uuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
05H
PORTA
PORTB
06H
07-1FH
General Purpose Register Files
TABLE 14-2 RESET CONDITIONS FOR ALL REGISTERS
1. See Table 14-1 for reset value for specific conditions.
Legend : - = unimplemented, read as ‘0’, x = unknown, u = unchanged.
q = see the tables in Section 17 for possible values.
Oct. 2001 Ver. 2.0
33
HMS77C1000A/HMS77C1001A
Power-On
RESET
WDT Time-Overflow
V
DD
Power-Fail
Detect
S
R
Q
Q
Internal RESET
Noise
Filter
RESET/V pin
PP
reset
clear
WDT
On-Chip
RC OSC
Internal RESET
Timer ( 8-bit asyn.
ripple counter )
FIGURE 14-1 SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
The Power-On Reset circuit and the Internal Reset Timer
circuit are closely related. On power-up, the reset latch is
set and the IRT is reset. The IRT timer begins counting
once it detects RESET to be high. After the time-out peri-
od, which is typically 7 ms (oscillation stabilization time),
it will reset the reset latch and thus end the on-chip reset
signal.
14.1 Power-On Reset (POR)
The HMS77C100XA family incorporates on-chip Power-
On Reset (POR) circuitry which provides an internal chip
reset for most power-up situations. To use this feature, the
user merely ties the RESET/VPP pin to VDD. A simplified
block diagram of the on-chip Power-On Reset circuit is
shown in Figure 14-1.
VDD
RESET
TIRT
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
FIGURE 14-2 TIME-OUT SEQUENCE ON POWER-UP (RESET NOT TIED TO VDD
)
34
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
VDD
RESET
TIRT
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
FIGURE 14-3 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): FAST VDD RISE TIME
VDD
RESET
TIRT
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
- When V rise slowly, the T
time-out expires long before V has reached its final value.
DD
DD
IRT
In this example, the chip will reset properly if, V1 ≥ V min.
DD
FIGURE 14-4 TIME-OUT SEQUENCE ON POWER-UP (RESET TIOED TO VDD): SLOW VDD RISE TIME
A power-up example where RESET is not tied to VDD is
shown in Figure 14-2. VDD is allowed to rise and stabilize
before bringing RESET high. The chip will actually come
out of reset TIRT after RESET goes high and POR, PFDR
is released.
when the internal reset timer times out, VDD has not
reached the VDD (min) value and the chip is, therefore, not
guaranteed to function correctly. For such situations, we
recommend that external R circuits be used to achieve
longer POR delay times (Figure 14-5).
In Figure 14-3, the on-chip Power-On Reset feature is be-
ing used (RESET and VDD are tied together). The VDD is
stable before the internal reset timer times out and there is
no problem in getting a proper reset. However, Figure 14-
4 depicts a problem situation where VDD rises too slowly.
The time between when the IRT senses a high on the RE-
SET/VPP pin, and when the RESET/VPP pin (and VDD)
actually reach their full value, is too long. In this situation,
Note: When the device starts normal operation (exits the
reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be meet to
ensure operation. If these conditions are not met,
the device must be held in reset until the operating
conditions are met.
Oct. 2001 Ver. 2.0
35
HMS77C1000A/HMS77C1001A
The POR circuit does not produce an internal reset when
VDD declines.
14.2 Internal Reset Timer (IRT)
The Internal Reset Timer (IRT) provides a fixed 7 ms nom-
inal time-out on reset. The IRT operates on an internal RC
oscillator. The processor is kept in RESET as long as the
IRT is active. The IRT delay allows VDD to rise above
VDD min., and for the oscillator to stabilize.
V
V
DD
DD
D
R
Oscillator circuits based on crystals or ceramic resonators
require a certain time after power-up to establish a stable
oscillation. The on-chip IRT keeps the device in a RESET
condition for approximately 7 ms after the voltage on the
RESET/VPP pin has reached a logic high (VIH) level and
POR released. Thus, external RC networks connected to
the RESET input are not required in most cases, allowing
for savings in cost-sensitive and/or space restricted appli-
cations. The Device Reset time delay will vary from chip
to chip due to VDD, temperature, and process variation.
R1
RESET
C
- External Power-On Reset circuit is required only if VDD
power-up is too slow. The diode D helps discharge the
capacitor quickly when VDD powers down.
- R < 40 kΩ is recommended to make sure that voltage
drop across R does not violate the device electrical specifi-
cation.
The IRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications us-
ing the WDT to wake the HMS77C100XA from SLEEP
mode automatically.
- R1 = 100W to 1 kW will limit any current flowing into
RESET from external capacitor C in the event of RESET
pin breakdown due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
FIGURE 14-5 EXTERNAL POWER-ON RESET
CIRCUIT (FOR SLOW VDD POWER- UP)
36
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
15. WATCHDOG TIMER (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC
oscillator which does not require any external components.
This RC oscillator is separate from the RC oscillator of the
XIN pin. That means that the WDT will run even if the
clock on the XIN and XOUT pins have been stopped, for ex-
ample, by execution of a SLEEP instruction. During nor-
mal operation or SLEEP, a WDT reset or wake-up reset
generates a device RESET.
caler with a division ratio of up to 1:256 can be assigned to
the WDT (under software control) by writing to the OP-
TION register. Thus, time-out a period of a nominal 3.5
seconds can be realized. These periods vary with tempera-
ture, VDD and part-to-part process variations (see DC
specs).
Under worst case conditions (VDD = Min., Temperature =
Max., max. WDT prescaler), it may take several seconds
before a WDT time-out occurs.
The TO bit (STATUS<4>) will be cleared upon a Watch-
dog Timer reset.
15.2 WDT Programming Considerations
The WDT can be permanently disabled by programming
the configuration bit WDTE as a '0' (Figure 12-2). Refer to
the HMS77C100XA Programming Specifications to deter-
mine how to access the configuration word.
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the postscaler,
if assigned to the WDT. This gives the maximum SLEEP
time before a WDT wake-up reset.
15.1 WDT Period
The WDT has a nominal time-out period of 14 ms, (with
no prescaler). If a longer time-out period is desired, a pres-
SLEEP
From TMR0 Clock Source
PSA
clearing WDT
Watchdog Timer
0
1
MUX
PSA
Postscaler
8-bit asynchronous
on-chip
RC-OSC
ripple counter
clear
8
8 - to - 1 MUX
PS2:PS0
To TMR0
enable
0
1
MUX
PSA
WDTE
WDT Time-Out
clearing WDT
SLEEP
FIGURE 15-1 WATCHDOG TIMER BLOCK DIAGRAM
Power-On
Reset
RESET and
WDT Reset
Name
Address
Bit7
Bit6
Bit5
Bit4
Bit3 Bit2 Bit1 Bit0
OPTION N/A
LOWOPT PFDEN T0CS T0SE PSA PS2 PS1 PS0
0011 1111
0011 1111
TABLE 15-1 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Oct. 2001 Ver. 2.0
37
HMS77C1000A/HMS77C1001A
16. Power-Down Mode (SLEEP)
For applications where power consumption is a critical
factor, device provides power down mode with Watchdog
operation. Executing of SLEEP Instruction is entrance to
SLEEP mode. In the SLEEP mode, oscillator is turn off
and system clock is disable and all functions is stop, but all
registers and RAM data is held. The wake-up sources from
SLEEP mode are external RESET pin reset and watchdog
time-overflow reset.
but keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had be-
fore the SLEEP instruction was executed (driving high,
driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT time-
out does not drive the RESET pin low.
For lowest current consumption while powered down, the
EC0 input should be at VDD or VSS and the RESET pin
must be at a logic high level .
16.1 SLEEP
The Power-Down mode is entered by executing a SLEEP
instruction. If enabled, the Watchdog Timer will be cleared
Oscillator
(X pin)
IN
Internal
System Clock
Fetch SLEEP
Execute SLEEP
Fetch RESET vector
Instruction
RESET
T
IRT
Internal
RESET
FIGURE 16-1 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO EXTERNAL RESET PIN RESET
Oscillator
(X pin)
IN
Internal
System Clock
Fetch SLEEP
Execute SLEEP
Fetch RESET vector
Instruction
WDT
Overflow
T
IRT
Internal
RESET
FIGURE 16-2 TIMING DIAGRAM OF WAKE-UP FROM SLEEP MODE DUE TO WATCHDOG TIME-OVERFLOW RESET
38
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
from external MCU is very high that the current doesn’t
flow.
16.2 Wake-up From SLEEP
The device can wake up from SLEEP through one of the
following events:
But input voltage level should be VSS or VDD. Be careful
that if unspecified voltage, i.e. if uncertain voltage level
(not VSSor VDD) is applied to input pin, there can be little
current (max. 1mA at around 2V) flow.
1. An external reset input on RESET pin.
2. A Watchdog Timer time-out reset (if WDT was en-
abled).
Note: In the SLEEP operation, the power dissipation asso-
ciated with the oscillator and the internal hardware
is lowered; however, the power dissipation associat-
ed with the pin interface (depending on the external
circuitry and program) is not directly determined by
the hardware operation of the SLEEP feature. This
point should be little current flows when the input
level is stable at the power voltage level (VDD/VSS);
however, when the input level becomes higher than
the power voltage level (by approximately 0.3V), a
current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal
into the high-impedance state, a current flow across
the ports input transistor, requiring it to fix the level
by pull-up or other means.
3. PFD reset
Both of these events cause a device reset. The TO and PD
bits can be used to determine the cause of device reset. The
TO bit is cleared if a WDT time-out occurred (and caused
wake-up). The PD bit, which is set on power-up, is cleared
when SLEEP is invoked.
The WDT is cleared when the device wakes from sleep, re-
gardless of the wake-up source.
16.3 Minimizing Current Consumption
The SLEEP mode is designed to reduce power consump-
tion. To minimize current drawn during SLEEP mode, the
user should turn-off output drivers that are sourcing or
sinking current, if it is practical.
If it is not appropriate to set as an input mode, then set to
output mode considering there is no current flow. Setting
to High or Low is decided considering its relationship with
external circuit. For example, if there is external pull-up re-
sistor then it is set to output mode, i.e. to high, and if there
is external pull-down register, it is set to low.
It should be set properly that current flow through port
doesn't exist.
First conseider the setting to input mode. Be sure that there
is no current flow after considering its relationship with
external circuit. In input mode, the pin impedance viewing
V
DD
INPUT PIN
INPUT PIN
V
DD
V
DD
internal
pull-up
i=0
V
DD
OPEN
O
O
i
O
i
Very weak current flows
V
DD
GND
i=0
X
GND
X
OPEN
Weak pull-up current flows
O
When port is configure as an input, input level should
be closed to 0V or 5V to avoid power consumption.
FIGURE 16-3 APPLICATION EXAMPLE OF UNUSED INPUT PORT
Oct. 2001 Ver. 2.0
39
HMS77C1000A/HMS77C1001A
OUTPUT PIN
ON
OUTPUT PIN
V
ON
OFF
DD
V
DD
OPEN
L
L
OFF
ON
ON
O
i=0
OFF
OFF
i
i
V
DD
GND
GND
GND
ON
X
O
X
OFF
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port.
O
In the left case, much current flows from port to GND.
FIGURE 16-4 APPLICATION EXAMPLE OF UNUSED OUTPUT PORT
40
Oct. 2001 Ver. 2.0
HMS77C1000A/HMS77C1001A
17. TIME-OUT SEQUENCE AND POWER DOWN STATUS BITS (TO/PD)
The TO and PD bits in the STATUS register can be tested
to determine if a RESET condition has been caused by a
power-up condition, a RESET or Watchdog Timer (WDT)
reset, or a RESET or WDT wake-up reset.
Table 17-2.
Event
TO
1
PD
1
Remarks
Power-up
WDT Time-out
SLEEP instruction
CLRWDT instruction
0
u
No effect on PD
TO
1
PD
1
RESET was caused by
Power-up(POR)
1
0
1
1
RESET or PFD reset (normal operation)1
u
u
RESET Wake-up or PFD reset
(from SLEEP)
TABLE 17-2 EVENTS AFFECTING TO/PD STATUS
BITS
1
0
0
0
1
0
WDT reset (normal operation)
WDT wake-up reset (from SLEEP)
Note: A WDT time-out will occur regardless of the status of
the TO bit. A SLEEP instruction will be executed,
regardless of the status of the PD bit.
TABLE 17-1 TO/PD STATUS AFTER RESET
1. The TO and PD bits maintain their status (u) until a reset
occurs. A low-pulse on the RESET input does not change the
TO and PD status bits.
Table 14-1 lists the reset conditions for the special function
registers, while Table 14-2 lists the reset conditions for all
the registers.
These STATUS bits are only affected by events listed in
Oct. 2001 Ver. 2.0
41
HMS77C1000A/HMS77C1001A
18. POWER FAIL DETECTION PROCESSOR
HMS77C100XA has an on-chip power fail detection cir-
cuitry to immunize against power noise.
If VDD falls below a level for longer 100ns, the power fail
detection processor may reset MCU and preserve the de-
vice from the malfunction due to Power Noise.
OPTION
Register
LOWOPT PFDEN
T0CS
5
T0SE
4
PSA
3
PS2
2
PS1
1
PS0
bit0
bit7
6
bit 7
LOWOPT: Power-fail detection level select bit.
1 = Lowered detection level (typ. 1.8V @ 5V)
0 = Normal detection level (typ. 2.7V @ 5V)
bit 6
PFDEN: Power-fail detection enable bit
1 = Enable power-fail detection
0 = Disable power-fail detection
FIGURE 18-1 POWER FAIL DETECTION PROCESSOR
The bit6(PFDEN) of OPTION register activates the PFD
Circuit, and bit7(LOWopt) lowers the detection level of
the Power Noise. The normal detection level is typically
2.7V and the lowered detection level is typically 1.8V. Fig-
ure 18-2 shows a Power Fail Detection Situations where
the detection level is selected by LOWOPT Bit.
Note: The PFD circuit is not implemented on the in circuit
emulator, user can not experiment with it. There
fore, after final development user program, this
function may be experimented on OTP
T
≥ 100nS
NVDD
V
DD
V
=2.7V
DR
T
IRT
PFDEN = 1
PFDR
LOWOPT = 0
Internal
RESET
T
≥ 100nS
NVDD
V
DD
V
=1.8V
DR
T
IRT
PFDEN = 1
LOWOPT = 1
PFDR
Internal
RESET
V
DD
V
=2.7 or 1.8V
DR
T
IRT
V
≤ V
DR
DD
PFDR
PFDEN = 1
LOWOPT = 0/1
Internal
RESET
POR
When V falls below approximately 1.5V level, Power-On Reset may occur.
DD
FIGURE 18-2 POWER FAIL DETECTION SITUATIONS
42
Oct. 2001 Ver. 2.0
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