HMS87C1304AD [HYNIX]
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER; CMOS单芯片8位微控制器
| 型号： | HMS87C1304AD |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER |
| 文件： | 总70页 (文件大小：947K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
HMS87C1304A / HMS87C1302A
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
1. OVERVIEW
1.1 Description
The HMS87C1304A and HMS87C1302A are an advanced CMOS 8-bit microcontroller with 4K/2K bytes of EPROM. The
HYUNDAI MicroElectronics HMS87C1304A and HMS87C1302A are powerful microcontroller which provides a highly
flexible and cost effective solution to many small applications such as controller for battery charger. The HMS87C1304A
and HMS87C1302A provide the following standard features: 4K/2K bytes of EPROM, 128bytes of RAM, 8-bit timer/
counter, 8-bit A/D converter, 10-bit high speed PWM output, programmable buzzer driving port, power-on reset circuit, on-
chip oscillator and clock circuitry. In addition, the HMS87C1304A and HMS87C1302A supports power saving modes to
reduce power consumption.
Operatind
Device name
EPROM Size
RAM Size
Package
Voltage
2.0 ~ 5.5V
2.0 ~ 5.5V
HMS87C1304A
HMS87C1302A
4K bytes
2K bytes
128bytes
128bytes
24 PDIP or SOP
24 PDIP or SOP
1.2 Features
• 4K/2K Bytes On-chip Program Memory
• Seven Interrupt sources
- External input: 2
- A/D Conversion: 1
- Timer: 4
• 128 Bytes of On-chip Data RAM
(Included stack memory)
• Instruction Cycle Time:
- 250nS at 8MHz
• One Programmable Buzzer Driving port
- 500Hz ~ 130kHz
• 19 Programmable I/O pins
(LED direct driving can be source and sink)
• Oscillator Type
- Crystal
- Ceramic Resonator
- RC-oscillation ( C can be omit )
Preliminary
• 2.0V to 5.5V Wide Operating Range
• One 8-bit A/D Converter
- 8 channels
• Power-On Reset
• Noise Immunity Circuit
- Power Fail Processor
• One 8-bit Basic Interval Timer
• Two 8-bit Timer / Counters
• One 10-bit High Speed PWM Outputs
• Watchdog timer
• Power Down Mode
- STOP mode
- Wake-up Timer mode
Jan. 2001
Preliminary
1
HMS87C1304A/HMS87C1302A
1.3 Development Tools
HYUNDAI MicroElectronics
The HMS87C1304A and HMS87C1302A are supported
by a full-featured macro assembler, an in-circuit emulator
In Circuit Emulators
Assembler
CHOICE-Dr.
CHOICE-DrTM
.
HME Macro Assembler
Single Writer : Dr. Writer
4-Gang Writer : Dr.Gang
OTP Writer
1.4 Ordering Information
ROM Size
Package Type
24 PDIP
Ordering Device Code
HMS87C1304A
Operating Temperature
4K bytes (OTP)
24 SOP
HMS87C1304A D
HMS87C1302A
-20 ~ +85°C
24 PDIP
2K bytes (OTP)
24 SOP
HMS87C1302A D
Preliminary
2
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
2. BLOCK DIAGRAM
HMS87C1304A/HMS87C1302A
PSW
ALU
PC
Accumulator
Stack Pointer
Data
Memory
Program
Memory
RESET
System controller
System
8-bit Basic
Interval
Timer
Data Table
Clock Controller
Interrupt Controller
Timing generator
Clock Generator
Xin
Xout
Instruction
Decoder
8-bit
A/D
Converter
8-bit
Timer/
Counter
High
Speed
PWM
Buzzer
Driver
Watch-dog
Timer
V
DD
RA
RB
RC
RD
V
SS
Power
Supply
RA0 / EC0
RB0 / AN0 / Avref
RB1 / BUZ
RB2 / INT0
RB3 / INT1
RB4 / CMP0 / PWM0
RC0
RC1
RD0
RD1
RD2
RD3
RA1 / AN1
RA2 / AN2
RA3 / AN3
RA4 / AN4
RA5 / AN5
Preliminary
RA6 / AN6
RA7 / AN7
Jan. 2001
Preliminary
3
HMS87C1304A/HMS87C1302A
3. PIN ASSIGNMENT
HYUNDAI MicroElectronics
24 PDIP
AN4 / RA4
1
24
23
22
21
20
19
18
17
16
15
14
13
RA3 / AN3
RA2 / AN2
RA1 / AN1
RA0 / EC0
RC1
AN5 / RA5
AN6 / RA6
AN7 / RA7
2
3
4
V
DD
5
RC0
RD0
RD1
6
V
7
SS
8
RESET
Xout
Xin
AN0 / AVref / RB0
BUZ / RB1
9
10
11
12
INT0 / RB2
RD3
RD2
INT1 / RB3
PWM0 / COMP0 / RB4
24 SOP
AN4 / RA4
AN5 / RA5
AN6 / RA6
1
2
3
24
23
22
RA3 / AN3
RA2 / AN2
RA1 / AN1
Preliminary
AN7 / RA7
4
21
20
19
18
17
16
15
14
13
RA0 / EC0
V
5
RC1
DD
RC0
6
RD0
RD1
V
SS
7
AN0 / AVref / RB0
BUZ / RB1
8
RESET
Xout
Xin
9
INT0 / RB2
10
11
12
INT1 / RB3
RD3
RD2
PWM0 / COMP0 / RB4
4
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
4. PACKAGE DIAGRAM
HMS87C1304A/HMS87C1302A
unit: inch
MAX
24 PDIP
MIN
TYP 0.300
1.265
1.160
0.300
0.250
0.021
0.015
0 ~ 15°
0.065
0.045
TYP 0.100
24 SOP
Preliminary
0.614
0.593
0 ~ 8°
0.019
0.0138
0.042
0.016
TYP 0.050
Jan. 2001
Preliminary
5
HMS87C1304A/HMS87C1302A
5. PIN FUNCTION
HYUNDAI MicroElectronics
V
V
RB0~RB7
: RB is a 8-bit, CMOS, bidirectional I/O port.
RB pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register(RBIO).
DD: Supply voltage.
SS: Circuit ground.
RESET
: Reset the MCU.
RB serves the functions of the various following special
features in Table 5-2
X
IN: Input to the inverting oscillator amplifier and input to
the internal main clock operating circuit.
Port pin
Alternate function
X
OUT: Output from the inverting oscillator amplifier.
RB0
AN0 ( Analog Input Port 0 )
RA0~RA7
: RA is an 8-bit, CMOS, bidirectional I/O port.
AVref ( External Analog Reference Pin )
BUZ ( Buzzer Driving Output Port )
INT0 ( External Interrupt Input Port 0 )
INT1 ( External Interrupt Input Port 1 )
PWM0 (PWM0 Output)
RA pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register(RAIO).
RB1
RB2
RB3
RB4
Port pin
Alternate function
COMP0 (Timer1 Compare Output)
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
EC0 ( Event Counter Input Source )
AN1 ( Analog Input Port 1 )
AN2 ( Analog Input Port 2 )
AN3 ( Analog Input Port 3 )
AN4 ( Analog Input Port 4 )
AN5 ( Analog Input Port 5 )
AN6 ( Analog Input Port 6 )
AN7 ( Analog Input Port 7 )
Table 5-2 RB Port
RC0, RC1
: RC is a 2-bit, CMOS, bidirectional I/O port.
RC pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register(RCIO).
RD0~RD3
: RD is a 4-bit, CMOS, bidirectional I/O port.
RC pins can be used as outputs or inputs according to “1”
or “0” written the their Port Direction Register(RDIO).
Table 5-1 RA Port
In addition, RA serves the functions of the various special
features in Table 5-1 .
Preliminary
6
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
PIN NAME
Pin No.
In/Out
Function
V
V
-
-
I
I
5
18
17
15
16
21
22
23
24
1
Supply voltage
Circuit ground
DD
SS
RESET
Reset signal input
X
IN
X
O
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Input)
I/O (Output)
I/O (Output/Output)
I/O
OUT
RA0 (EC0)
RA1 (AN1)
RA2 (AN2)
RA3 (AN3)
RA4 (AN4)
RA5 (AN5)
RA6 (AN6)
RA7 (AN7)
RB0 (AVref/AN0)
RB1 (BUZ)
RB2 (INT0)
RB3 (INT1)
RB4 (PWM0/COMP0)
RC0
External Event Counter input 0
Analog Input Port 1
Analog Input Port 2
Analog Input Port 3
8-bit general I/O ports
Analog Input Port 4
2
Analog Input Port 5
3
Analog Input Port 6
4
Analog Input Port 7
8
Analog Input Port 0 / Analog Reference
Buzzer Driving Output
9
10
11
12
19
20
6
5-bit general I/O ports
External Interrupt Input 0
External Interrupt Input 1
PWM0 Output or Timer1 Compare Output
2-bit general I/O ports
4-bit general I/O ports
I/O
RC1
I/O
RD0
I/O
RD1
7
I/O
RD2
13
14
I/O
RD3
Preliminary
Table 5-3 Pin Description
Jan. 2001
Preliminary
7
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
6. PORT STRUCTURES
• RESET
Internal RESET
V
SS
• Xin, Xout
Crystal or Ceramic
V
DD
Xout
V
SS
STOP
To System CLK
Xin
RC Oscillation
V
DD
Preliminary
Xout
STOP
V
SS
To System CLK
Xin
Internal Capacitor 6 pF
8
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
• RA0/EC0
Open Drain
Data Reg.
Data Bus
Direction Reg.
Data Bus
Data Bus
Read
EC0
Schmitt Trigger
• RA1/AN1 ~ RA7/AN7
V
DD
Data Reg.
Data Bus
Data Bus
Direction Reg.
V
SS
Data Bus
Read
Preliminary
To A/D Converter
Analog Input Mode
(ANSEL7 ~ 1)
Analog CH. Selection
(ADCM.4 ~ 2)
Jan. 2001
Preliminary
9
HMS87C1304A/HMS87C1302A
• RB0 / AN0 / AVref
HYUNDAI MicroElectronics
V
DD
Data Reg.
Data Bus
AVREFS
Data Bus
Direction Reg.
V
SS
Data Bus
Read
To A/D Converter
Analog Input Mode
(ANSEL0)
Analog CH0 Selection
(ADCM.4 ~ 2)
Internal V
DD
1
0
To Vref of A/D
AVREFS
• RB1/BUZ, RB4/PWM0/COMP0
PWM/COMP
BUZ
V
DD
Preliminary
1
Data Reg.
0
Data Bus
Function
Select
Direction Reg.
Data Bus
V
SS
Data Bus
Read
10
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
• RB2/INT0, RB3/INT1
HMS87C1304A/HMS87C1302A
Open Drain
Pull-up
Select
Weak Pull-up
Data Reg.
V
DD
Data Bus
Function
Select
Direction Reg.
Data Bus
V
SS
Data Bus
Read
Schmitt Trigger
INT0, INT1
• RC0, RD0, RD1, RD2, RD3
Data Reg.
Data Bus
Direction Reg.
Data Bus
Data Bus
Read
Preliminary
• RC1
Open Drain
V
DD
Data Reg.
Data Bus
Direction Reg.
Data Bus
Data Bus
V
SS
Read
Jan. 2001
Preliminary
11
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage........................................... -0.3 to +6.0 V
Maximum current (ΣIOH).................................... 100 mA
Storage Temperature ................................-40 to +125 °C
Note: Stresses above those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional op-
eration of the device at any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect device reliability.
Voltage on any pin with respect to Ground (VSS
)
............................................................... -0.3 to VDD+0.3
Maximum current out of VSS pin........................200 mA
Maximum current into VDD pin ..........................150 mA
Maximum current sunk by (IOL per I/O Pin) ........25 mA
Maximum output current sourced by (IOH per I/O Pin)
...............................................................................15 mA
Maximum current (ΣIOL) ....................................150 mA
7.2 Recommended Operating Conditions
Specifications
Unit
Parameter
Symbol
Condition
Min.
4.5
2.0
1
Max.
5.5
5.5
8
fXIN=8MHz
fXIN=4.2MHz
VDD=4.5~5.5V
VDD=2.0~5.5V
V
V
VDD
Supply Voltage
MHz
MHz
°C
fXIN
Operating Frequency
1
4.2
85
TOPR
Operating Temperature
-20
7.3 A/D Converter Characteristics
(TA=25°C, VSS=0V, VDD=5.12V @fXIN =8MHz, VDD=3.072V @fXIN =4MHz)
Specifications
Parameter
Symbol
Condition
Unit
Preliminary
Min.
Typ.
Max.
VDD
VREF
VDD
VDD
±1.5
±1.5
±1.5
±1.5
±0.5
±1.5
10
VSS
AVREFS=0
AVREFS=1
VDD=5V
-
-
VAIN
Analog Input Voltage Range
V
VSS
3
-
V
VREF
Analog Power Supply Input Voltage Range
VDD=3V
2.4
-
V
NACC
NNLE
NDNLE
NZOE
NFSE
NNLE
Overall Accuracy
Non-Linearity Error
Differential Non-Linearity Error
Zero Offset Error
Full Scale Error
-
-
-
-
-
-
-
-
-
±1.0
±1.0
±1.0
±0.5
±0.25
±1.0
-
LSB
LSB
LSB
LSB
LSB
LSB
Gain Error
fXIN=8MHz
fXIN=4MHz
AVREFS=1
TCONV
IREF
Conversion Time
µS
-
20
AVREF Input Current
0.5
1.0
mA
12
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
7.4 DC Electrical Characteristics
(TA=-20~85°C, VDD=2.0~5.5V, VSS=0V),
Specifications
Unit
Parameter
Symbol
Pin
Condition
Min.
Typ.
Max.
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
VOH
VOL
IP
XIN, RESET
0.8 VDD
VDD
-
Hysteresis Input1
Normal Input
XIN, RESET
0.8 VDD
VDD
Input High Voltage
-
V
V
0.7 VDD
VDD
-
0.2 VDD
0
-
Hysteresis Input1
Normal Input
0.2 VDD
Input Low Voltage
0
-
0.3 VDD
0
-
VDD=5V, IOH=-5mA
VDD=5V, IOL=10mA
VDD=5V
VDD -1
Output High Voltage
Output Low Voltage
Input Pull-up Current
All Output Port
-
-
1
V
-
-550
-
All Output Port
-
V
RB2, RB3, RD0, RD1
-420
-200
5
µA
µA
µA
µA
µA
V
IIH1
All Pins (except XIN) VDD=5V
XIN VDD=5V
All Pins (except XIN) VDD=5V
-
Input High
Leakage Current
IIH2
-
-
-
15
-
IIL1
-5
Input Low
Leakage Current
IIL2
XIN
VDD=5V
-15
0.5
2.5
2.0
40
95
-
-
-
Hysteresis Input1
| VT |
VDD=5V
Hysteresis
-
-
VPFD1 VDD
VPFD2 VDD
PFD Level = 0
PFD Level = 1
VDD=5V
3.0
2.5
3.5
3.0
120
280
6
PFD Voltage
V
Internal RC WDT
Period
TRCWDT
µS
mA
mA
V
DD=3V
VDD=5.5V, fXIN=8MHz
VDD=3.0V, fXIN=4MHz
5
2
IDD
VDD
Operating Current
-
3
Preliminary
VDD=5.5V, fXIN=8MHz
VDD=3.0V, fXIN=4MHz
VDD=5.5V
-
-
-
1
2
Wake-up Timer
Mode Current
IWKUP VDD
0.5
-
1
RCWDT Mode
Current at STOP
Mode
200
IRCWDT VDD
µA
µA
V
DD=3.0V
-
-
100
VDD=5.5V, fXIN=8MHz
VDD=3.0V, fXIN=4MHz
-
-
0.5
0.2
3
1
ISTOP
VDD
Stop Mode Current
1. Hysteresis Input: RB2, RB3
Jan. 2001
Preliminary
13
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
7.5 AC Characteristics
(TA=-20~+85°C, VDD=5V±10%, VSS=0V)
Specifications
Unit
Parameter
Symbol
Pins
Min.
Typ.
Max.
fCP
XIN
XIN
Operating Frequency
1
80
-
-
-
-
-
-
-
8
-
MHz
nS
tCPW
External Clock Pulse Width
External Clock Transition Time
Oscillation Stabilizing Time
External Input Pulse Width
RESET Input Width
tRCP, FCP
t
XIN
20
20
-
nS
tST
XIN, XOUT
INT0, INT1, EC0
RESET
-
mS
tSYS
tSYS
tEPW
tRST
2
8
-
t
t
CPW
CPW
1/f
CP
V
DD
-0.5V
XIN
0.5V
t
RCP
t
FCP
t
SYS
t
RST
RESET
0.2V
DD
t
t
EPW
EPW
Preliminary0.8V
DD
INT0, INT1
EC0
0.2V
DD
Figure 7-1 Timing Chart
14
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
7.6 Typical Characteristics
HMS87C1304A/HMS87C1302A
This graphs and tables provided in this section are for de-
sign guidance only and are not tested or guaranteed.
The data presented in this section is a statistical summary
of data collected on units from different lots over a period
of time. “Typical” represents the mean of the distribution
while “max” or “min” represents (mean + 3σ) and (mean −
3σ) respectively where σ is standard deviation
In some graphs or tables the data presented are out-
side specified operating range (e.g. outside specified
V
DD range). This is for information only and devices
are guaranteed to operate properly only within the
specified range.
Operating Area
Normal Operation
IDD−VDD
f
XIN
(MHz)
I
DD
Ta= 25°C
Ta=25°C
(mA)
8
10
8
6
4
f
= 8MHz
4MHz
XIN
6
4
2
0
2
0
V
DD
(V)
6
2
3
4
5
V
DD
(V)
2
3
6
4
5
STOP Mode
Wake-up Timer Mode
ISTOP−VDD
IWKUP−VDD
I
I
DD
DD
-25°C
25°C
85°C
f
= 8MHz
Ta=25°C
(µA)
0.8
XIN
(mA)
2.0
0.6
0.4
1.5
1.0
f
= 8MHz
XIN
Preliminary
0.2
0
0.5
4MHz
0
V
(V)
V
(V)
6
DD
DD
2
3
6
4
5
2
3
4
5
RC-WDT in Stop Mode
IRCWDT−VDD
I
DD
(µA)
20
Ta=25°C
15
10
T
= 80uS
RCWDT
5
0
V
DD
(V)
6
2
3
4
5
Jan. 2001
Preliminary
15
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
IOL−VOL, VDD=5V
IOH−VOH, VDD=5V
I
I
OL
OH
(mA)
(mA)
-25°C
25°C
85°C
-25°C
25°C
85°C
-20
40
-15
-10
30
20
-5
0
10
0
V
(V)
6
OH
V
(V)
5
OL
2
3
4
5
1
2
3
4
VDD−VIH1
XIN, RESET
VDD−VIH2
VDD−VIH3
Hysteresis input
Normal input
V
V
IH3
V
IH2
IH1
fXIN=4kHz
fXIN=4kHz
f
=4MHz
XIN
(V)
(V)
(V)
4
Ta=25°C
Ta=25°C
Ta=25°C
4
4
3
2
3
2
3
2
1
1
1
0
0
0
V
V
DD
V
DD
DD
1
(V)
(V)
6
2
3
6
2
3
(V)
6
4
5
4
5
2
3
4
5
Preliminary
VDD−VIL1
XIN, RESET
VDD−VIL2
VDD−VIL3
Hysteresis input
Normal input
V
V
IL3
V
IL2
IL1
fXIN=4kHz
fXIN=4kHz
f
=4MHz
XIN
(V)
(V)
(V)
Ta=25°C
Ta=25°C
Ta=25°C
4
4
4
3
2
3
2
3
2
1
1
1
0
0
0
V
V
DD
V
DD
DD
1
(V)
(V)
6
2
3
6
2
3
(V)
6
4
5
4
5
2
3
4
5
16
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
8. MEMORY ORGANIZATION
The HMS87C1304A and HMS87C1302A have separate
address spaces for Program memory and Data Memory.
Program memory can only be read, not written to. It can be
up to 4K /8K bytes of Program memory. Data memory can
be read and written to up to 192 bytes including the stack
area.
8.1 Registers
This device has six registers that are the Program Counter
(PC), a Accumulator (A), two index registers (X, Y), the
Stack Pointer (SP), and the Program Status Word (PSW).
The Program Counter consists of 16-bit register.
Generally, SP is automatically updated when a subroutine
call is executed or an interrupt is accepted. However, if it
is used in excess of the stack area permitted by the data
memory allocating configuration, the user-processed data
may be lost.
ACCUMULATOR
X REGISTER
A
X
The stack can be located at any position within 00H to 7FH
of the internal data memory. The SP is not initialized by
hardware, requiring to write the initial value (the location
with which the use of the stack starts) by using the initial-
ization routine. Normally, the initial value of “7FH” is
used.
Y
Y REGISTER
SP
STACK POINTER
PCH
PCL
PROGRAM COUNTER
Stack Address (000 ~ 07F )
H
H
PROGRAM STATUS
WORD
PSW
15
8
7
0
0
SP
Figure 8-1 Configuration of Registers
Hardware fixed
Accumulator:
The Accumulator is the 8-bit general pur-
pose register, used for data operation such as transfer, tem-
porary saving, and conditional judgement, etc.
Note: The Stack Pointer must be initialized by software be-
cause its value is undefined after RESET.
Example: To initialize the SP
The Accumulator can be used as a 16-bit register with Y
Register as shown below.
LDX
#07FH
TXSP
; SP ← 7FH
Y
Program Counter
: The Program Counter is a 16-bit wide
Preliminary
which consists of two 8-bit registers, PCH and PCL. This
Y
A
counter indicates the address of the next instruction to be
executed. In reset state, the program counter has reset rou-
tine address (PCH:0FFH, PCL:0FEH).
A
Two 8-bit Registers can be used as a “YA” 16-bit Register
Program Status Word
: The Program Status Word (PSW)
contains several bits that reflect the current state of the
CPU. The PSW is described in Figure 8-3 . It contains the
Negative flag, the Overflow flag, the Break flag the Half
Carry (for BCD operation), the Interrupt enable flag, the
Zero flag, and the Carry flag.
Figure 8-2 Configuration of YA 16-bit Register
X, Y Registers
: In the addressing mode which uses these
index registers, the register contents are added to the spec-
ified address, which becomes the actual address. These
modes are extremely effective for referencing subroutine
tables and memory tables. The index registers also have in-
crement, decrement, comparison and data transfer func-
tions, and they can be used as simple accumulators.
[Carry flag C]
This flag stores any carry or borrow from the ALU of CPU
after an arithmetic operation and is also changed by the
Shift Instruction or Rotate Instruction.
Stack Pointer
: The Stack Pointer is an 8-bit register used
[Zero flag Z]
for occurrence interrupts and calling out subroutines. Stack
Pointer identifies the location in the stack to be accessed
(save or restore).
This flag is set when the result of an arithmetic operation
or data transfer is “0” and is cleared by any other result.
Jan. 2001
Preliminary
17
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
MSB
N
LSB
C
V
-
B
H
I
Z
RESET VALUE: 00
PSW
H
CARRY FLAG RECEIVES
CARRY OUT
NEGATIVE FLAG
OVERFLOW FLAG
BRK FLAG
ZERO FLAG
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I]
dress.
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to “0”. This flag immedi-
ately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Overflow flag V]
This flag is set to “1” when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
ceeds +127(7FH) or -128(80H). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
[Half carry flag H]
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
Preliminary
18
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
8.2 Program Memory
HMS87C1304A/HMS87C1302A
A 16-bit program counter is capable of addressing up to
64K bytes, but these devices have 4K/2K bytes program
memory space only physically implemented. Accessing a
location above FFFFH will cause a wrap-around to 0000H.
Example: Usage of TCALL
LDA
#5
TCALL 0FH
;
;
;
1BYTE INSTRUCTION
INSTEAD OF 3 BYTES
NORM AL CALL
:
:
Figure 8-4 , shows a map of Program Memory. After reset,
the CPU begins execution from reset vector which is stored
in address FFFEH and FFFFH as shown in Figure 8-5 .
;
;TABLE CALL ROUTINE
;
FUNC_A: LDA
LRG0
RET
As shown in Figure 8-4 , each area is assigned a fixed lo-
cation in Program Memory. Program Memory area con-
tains the user program.
;
FUNC_B: LDA
LRG1
2
1
RET
;
;TABLE CALL ADD. AREA
;
F000H
ORG
DW
0FFC0H
FUNC_A
FUNC_B
;
TCALL ADDRESS AREA
DW
HMS87C1304A
F800H
The interrupt causes the CPU to jump to specific location,
where it commences the execution of the service routine.
The External interrupt 0, for example, is assigned to loca-
tion 0FFFAH. The interrupt service locations spaces 2-byte
interval: 0FFF8H and 0FFF9H for External Interrupt 1,
0FFFAH and 0FFFBH for External Interrupt 0, etc.
HMS87C1302A
PROGRAM
MEMORY
FEFFH
FF00H
FFC0H
PCALL
AREA
TCALL
AREA
FFDFH
FFE0H
INTERRUPT
VECTOR AREA
As for the area from 0FF00H to 0FFFFH, if any area of
them is not going to be used, its service location is avail-
able as general purpose Program Memory.
FFFFH
Address
0FFE0
Vector Area Memory
Figure 8-4 Program Memory Map
-
-
-
H
Page Call (PCALL) area contains subroutine program to
reduce program byte length by using 2 bytes PCALL in-
stead of 3 bytes CALL instruction. If it is frequently called,
it is more useful to save program byte length.
E2
E4
Preliminary
E6
E8
EA
EC
EE
F0
Basic Interval Interrupt Vector Area
Watchdog Timer Interrupt Vector Area
A/D Converter Interrupt Vector Area
Table Call (TCALL) causes the CPU to jump to each
TCALL address, where it commences the execution of the
service routine. The Table Call service area spaces 2-byte
for every TCALL: 0FFC0H for TCALL15, 0FFC2H for
TCALL14, etc., as shown in Figure 8-6 .
-
-
-
F2
F4
F6
F8
FA
FC
FE
-
Timer/Counter 1 Interrupt Vector Area
Timer/Counter 0 Interrupt Vector Area
External Interrupt 1 Vector Area
External Interrupt 0 Vector Area
-
RESET Vector Area
NOTE:
“-” means reserved area.
Figure 8-5 Interrupt Vector Area
Jan. 2001
Preliminary
19
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
Address
Program Memory
TCALL 15
TCALL 14
TCALL 13
TCALL 12
TCALL 11
TCALL 10
TCALL 9
0FFC0
C1
H
C2
C3
C4
C5
C6
C7
C8
C9
Address
0FF00
PCALL Area Memory
H
PCALL Area
(256 Bytes)
CA
CB
CC
CD
CE
CF
TCALL 8
0FFFF
H
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
TCALL 7
TCALL 6
TCALL 5
TCALL 4
TCALL 3
TCALL 2
TCALL 1
TCALL 0 / BRK *
NOTE:
* means that the BRK software interrupt is using
same address with TCALL0.
Figure 8-6 PCALL and TCALL Memory Area
Preliminary
PCALL→ rel
TCALL→ n
4F35
PCALL 35H
4A
TCALL 4
4A
01001010
4F
35
Reverse
þ
~
~
~
~
PC:
11111111
11010110
~
~
~
~
NEXT
0F125H
F
H
F
H
D
6
H H
0FF00H
0FF35H
Ã
0FF00H
À
NEXT
0FFD6H
0FFD7H
25
F1
0FFFFH
0FFFFH
20
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
Example: The usage software example of Vector address and the initialize part.
ORG
0FFE0H
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
NOT_USED
NOT_USED
NOT_USED
BIT_INT
WDT_INT
AD_INT
NOT_USED
NOT_USED
NOT_USED
NOT_USED
TMR1_INT
TMR0_INT
INT1
; (0FFEO)
; (0FFE2)
; (0FFE4)
; (0FFE6) Basic Interval Timer
; (0FFE8) Watchdog Timer
; (0FFEA) A/D
; (0FFEC)
; (0FFEE)
; (0FFF0)
; (0FFF2)
; (0FFF4) Timer-1
; (0FFF6) Timer-0
; (0FFF8) Int.1
; (0FFFA) Int.0
; (0FFFC)
INT0
NOT_USED
RESET
; (0FFFE) Reset
ORG
0F000H
;********************************************
;
MAIN
PROGRAM
*
;*******************************************
;
RESET: DI
;Disable All Interrupts
LDX
#0
#0
RAM_CLR:LDA
;RAM Clear(!0000H->!007FH)
STA
{X}+
#080H
RAM_CLR
CMPX
BNE
;
LDX
TXSP
;
#07FH
;Stack Pointer Initialize
CALL
;
INITIAL
RA, #0
;
LDM
LDM
LDM
LDM
:
;Normal Port A
RAIO,#1000_0010B ;Normal Port Direction
RB, #0
;Normal Port B
RBIO,#0000_0010B ;Normal Port Direction
Preliminary
:
LDM
:
PFDR,#0
;Enable Power Fail Detector
:
Jan. 2001
Preliminary
21
HMS87C1304A/HMS87C1302A
8.3 Data Memory
HYUNDAI MicroElectronics
Figure 8-7 shows the internal Data Memory space availa-
ble. Data Memory is divided into two groups, a user RAM
(including Stack) and control registers.
RESET
Value
Addressing
mode
Symbol
R/W
Address
0C0H
0C1H
0C2H
0C3H
0C4H
0C5H
0C6H
0C7H
0CAH
0CBH
0CCH
RA
RAIO
RB
RBIO
RC
RCIO
RD
RDIO
RAFUNC
RBFUNC
PUPSEL
R/W Undefined byte, bit1
byte2
byte, bit
byte
byte, bit
byte
byte, bit
byte
byte
W
0000_0000
R/W Undefined
0000_0000
R/W Undefined
----_--00
R/W Undefined
0000H
W
USER
MEMORY
(including STACK)
W
007FH
PAGE0
0080H
W
W
W
W
----_0000
0000_0000
0000_0000
----_--00
00BFH
byte
byte
00C0H
CONTROL
REGISTERS
00FFH
0D0H
0D1H
0D1H
0D1H
0D2H
0D3H
0D3H
0D4H
0D4H
0D4H
0D5H
TM0
T0
TDR0
CDR0
TM1
TDR1
T1PPR
T1
CDR1
T1PDR
PWM0HR
R/W --00_0000
byte, bit
byte
byte
byte
byte, bit
byte
byte
byte
byte
byte, bit
byte
R
W
R
0000_0000
1111_1111
0000_0000
Figure 8-7 Data Memory Map
User Memory
R/W 0000_0000
W
W
R
1111_1111
1111_1111
0000_0000
0000_0000
The HMS87C1304A and HMS87C1302A has 128 × 8 bits
for the user memory (RAM).
R
R/W 0000_0000
W
----_0000
Control Registers
0DEH
BUR
W
1111_1111
byte
The control registers are used by the CPU and Peripheral
function blocks for controlling the desired operation of the
device. Therefore these registers contain control and status
bits for the interrupt system, the timer/ counters, analog to
digital converters and I/O ports. The control registers are in
address range of 0C0H to 0FFH.
0E2H
0E3H
0E4H
0E5H
0E6H
0EAH
0EBH
0ECH
IENH
IENL
R/W 0000_----
R/W 000-_----
R/W 0000_----
R/W 000-_----
R/W ----_0000
R/W --00_0001
R
R
W
R
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte, bit
byte
byte
byte
byte
byte
IRQH
IRQL
IEDS
ADCM
ADCR
BITR
CKCTLR
WDTR
WDTR
PFDR
Note that unoccupied addresses may not be implemented
on the chip. Read accesses to these addresses will in gen-
eral return random data, and write accesses will have an in-
determinate effect.
Undefined
0000_0000
-001_0111
0000_0000
0111_1111
Preliminary
0ECH
0EDH
0EDH
0EFH
W
More detailed informations of each register are explained
in each peripheral section.
R/W ----_-100
byte, bit
Table 8-1 Control Registers
Note: Write only registers can not be accessed by bit ma-
nipulation instruction. Do not use read-modify-write
instruction. Use byte manipulation instruction.
1. “byte, bit” means that register can be addressed by not only bit
but byte manipulation instruction.
2. “byte” means that register can be addressed by only byte
manipulation instruction. On the other hand, do not use any
read-modify-write instruction such as bit manipulation for
clearing bit.
Example; To write at CKCTLR
LDM
CKCTLR,#09H;Divide ratio ÷16
22
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
Stack Area
Note: Several names are given at same address. Refer to
The stack provides the area where the return address is
saved before a jump is performed during the processing
routine at the execution of a subroutine call instruction or
the acceptance of an interrupt.
below table.
When read
When write
When returning from the processing routine, executing the
subroutine return instruction [RET] restores the contents of
the program counter from the stack; executing the interrupt
return instruction [RETI] restores the contents of the pro-
gram counter and flags.
Addr.
Timer
Mode
Capture
Mode
PWM
Mode
Timer
PWM
Mode
Mode
TDR0
TDR1
-
D1H
D3H
D4H
ECH
T0
CDR0
-
-
-
T1PPR
T1PDR
T1
CDR1 T1PDR
BITR
The save/restore locations in the stack are determined by
the stack pointed (SP). The SP is automatically decreased
after the saving, and increased before the restoring. This
means the value of the SP indicates the stack location
number for the next save.
CKCTLR
Table 8-2 Various Register Name in Same Address
Preliminary
Jan. 2001
Preliminary
23
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
Address
C0H
C1H
C2H
C3H
C4H
C5H
C6H
C7H
CAH
CBH
CCH
D0H
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA
RA Port Data Register
RA Port Direction Register
RB Port Data Register
RB Port Direction Register
RC Port Data Register
RC Port Direction Register
RD Port Data Register
RD Port Direction Register
RAIO
RB
RBIO
RC
RCIO
RD
RDIO
RAFUNC
RBFUNC
PUPSEL
TM0
ANSEL7
ANSEL6
ANSEL5
PWM1O
-
ANSEL4
PWM0O
-
ANSEL3
INT1I
ANSEL2
INT0I
ANSEL1
BUZO
ANSEL0
AVREFS
TMR2OV
EC1I
-
-
-
-
PUPSEL1 PUPSEL0
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
T0/TDR0/
CDR0
D1H
D2H
D3H
Timer0 Register / Timer0 Data Register / Capture0 Data Register
POL 16BIT PWM0E CAP1 T1CK1 T1CK0
Timer1 Data Register / PWM0 Period Register
TM1
T1CN
T1ST
TDR1/
T1PPR
T1/CDR1/
T1PDR
D4H
Timer1 Register / Capture1 Data Register / PWM0 Duty Register
PWM0 High Register
D5H
DEH
E2H
E3H
E4H
E5H
E6H
EAH
EBH
ECH
PWM0HR
BUR
BUCK1
INT0E
ADE
INT0IF
ADIF
-
BUCK0
INT1E
WDTE
INT1IF
WDTIF
BUR5
T0E
BUR4
BUR3
BUR2
BUR1
BUR0
IENH
T1E
-
-
-
-
-
-
-
IENL
BITE
T0IF
BITIF
-
T1IF
-
-
-
-
IRQH
IRQL
-
-
-
-
-
-
Preliminary
IEDS
-
-
-
IED1H
IED1L
IED0H
ADST
IED0L
ADSF
ADCM
ADCR
-
-
ADEN
ADS2
ADS1
ADS0
ADC Result Data Register
Basic Interval Timer Data Register
WAKEUP RCWDT
BITR1
CKCTLR1
WDTR
ECH
EDH
EFH
-
WDTON
BTCL
BTS2
BTS1
BTS0
PFDS
WDTCL 7-bit Watchdog Counter Register
PFDR2
-
-
-
-
-
PFDIS
PFDM
Table 8-3 Control Registers of HMS87C1304A and HMS87C1302A
These registers of shaded area can not be accessed by bit manipulation instruction as “SET1, CLR1”, but should be accessed by
register operation instruction as “LDM dp,#imm”.
1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR.
2.The register PFDR only be implemented on devices, not on In-circuit Emulator.
24
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
8.4 Addressing Mode
HMS87C1304A/HMS87C1302A
The HMS87C1304A and HMS87C1302A uses six ad-
dressing modes;
(3) Direct Page Addressing → dp
In this mode, a address is specified within direct page.
Example;
• Register addressing
C535
LDA
35H
;A ←RAM[35H]
• Immediate addressing
• Direct page addressing
• Absolute addressing
• Indexed addressing
0035
H
data
À
~
~
~
data → A
~
þ
• Register-indirect addressing
0F550
0F551
C5
35
H
H
(1) Register Addressing
Register addressing accesses the A, X, Y, C and PSW.
(2) Immediate Addressing → #imm
(4) Absolute Addressing → !abs
In this mode, second byte (operand) is accessed as a data
immediately.
Absolute addressing sets corresponding memory data to
Data, i.e. second byte(Operand I) of command becomes
lower level address and third byte (Operand II) becomes
upper level address.
With 3 bytes command, it is possible to access to whole
memory area.
Example:
0435
ADC
#35H
MEMORY
ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,
LDY, OR, SBC, STA, STX, STY
04
35
A+35H+C → A
Example;
0735F0 ADC
!0F035H
;A ←ROM[0F035H]
Preliminary
0F035
data
H
À
E45535 LDM
35H,#55H
~
~
~
~
A+data+C → A
þ
0F100
0F101
0F102
07
35
F0
H
H
H
address: 0F035
0035
H
data
data ← 55H
~
~
~
~
þ
H
À
0F100
E4
55
35
0F101
0F102
H
H
Jan. 2001
Preliminary
25
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
The operation within data memory (RAM)
ASL, BIT, DEC, INC, LSR, ROL, ROR
X indexed direct page, auto increment→ {X}+
In this mode, a address is specified within direct page by
the X register and the content of X is increased by 1.
Example; Addressing accesses the address 0135H.
983500 INC
!0035H
;A ←RAM[035H]
LDA, STA
Example; X=35H
DB
LDA
{X}+
0035
data
H
Ã
À
~
~
~
~
data+1 → data
35
H
data
À
0F100
0F101
0F102
98
35
00
H
þ
data → A
36H → X
~
~
~
H
H
address: 0035
~
þ
DB
(5) Indexed Addressing
X indexed direct page (no offset) → {X}
In this mode, a address is specified by the X register.
ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA
Example; X=15H
X indexed direct page (8 bit offset) → dp+X
This address value is the second byte (Operand) of com-
mand plus the data of ꢀ-register. And it assigns the mem-
ory in Direct page.
ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA
STY, XMA, ASL, DEC, INC, LSR, ROL, ROR
D4
LDA
{X}
;ACC←RAM[X].
Example; X=015H
C645
LDA
45H+X
15
H
data
À
data → A
~
~
~
~
Preliminary
þ
5A
H
data
D4
0E550
H
Ã
data → A
À
~
~
~
~
0E550
0E551
C6
45
þ
H
H
45H+15H=5AH
26
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
3F35
JMP
[35H]
Y indexed direct page (8 bit offset) → dp+Y
This address value is the second byte (Operand) of com-
mand plus the data of Y-register, which assigns Memory in
Direct page.
35
36
0A
E3
H
This is same with above (2). Use Y register instead of X.
H
À jump to address 0E30A
H
Y indexed absolute →!abs+Y
~
~
~
~
Sets the value of 16-bit absolute address plus Y-register
data as Memory. This addressing mode can specify mem-
ory in whole area.
0E30A
NEXT
H
H
~
~
~
~
þ
Example; Y=55H
0FA00
3F
35
D500FA LDA
!0FA00H+Y
0F100
H
D5
þ
0F101
0F102
00
H
H
X indexed indirect → [dp+X]
FA
0FA00H+55H=0FA55H
Processes memory data as Data, assigned by 16-bit pair
memory which is determined by pair data
[dp+X+1][dp+X] Operand plusꢁX-register data in Direct
page.
~
~
~
~
À
data
0FA55
H
data → A
Ã
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; X=10H
1625
ADC
[25H+X]
(6) Indirect Addressing
Direct page indirect → [dp]
Preliminary
35
05
H
E0
36
Assigns data address to use for accomplishing command
which sets memory data(or pair memory) by Operand.
Also index can be used with Index register X,Y.
H
0E005
H
À
~
~
~
~
25 + X(10) = 35
þ
H
0E005
data
H
JMP, CALL
Example;
~
~
~
~
0FA00
16
25
H
à A + data + C → A
Jan. 2001
Preliminary
27
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
Y indexed indirect → [dp]+Y
Absolute indirect → [!abs]
Processes memory data as Data, assigned by the data
[dp+1][dp] of 16-bit pair memory paired by Operand in Di-
rect pageꢁplus Y-register data.
The program jumps to address specified by 16-bit absolute
address.
JMP
ADC, AND, CMP, EOR, LDA, OR, SBC, STA
Example; Y=10H
Example;
1F25E0 JMP
[!0C025H]
1725
ADC
[25H]+Y
PROGRAM MEMORY
0E025
H
25
25
26
05
H
E7
0E026
H
E0
H
jump to
address 0E30A
À
0E005 + Y(10) = 0E015
H
À
H
~
~
~
~
~
~
~
~
H
þ
0E725
NEXT
H
0E015
data
H
H
þ
~
~
~
~
~
~
~
~
0FA00
1F
H
0FA00
17
25
25
à A + data + C → A
E0
Preliminary
28
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
9. I/O PORTS
The HMS87C1304A and HMS87C1302A has four ports,
RA, RB, RC and RD. These ports pins may be multiplexed
with an alternate function for the peripheral features on the
device. In general, when a initial reset state, all ports are
used as a general purpose input port.
Reading data register reads the status of the pins whereas
writing to it will write to the port latch.
WRITE “55H” TO PORT RA DIRECTION REGISTER
0
7
1
6
0
5
1
4
0
3
1
2
0
1
1
0
C0H
C1H
C2H
C3H
RA DATA
RA DIRECTION
RB DATA
BIT
All pins have data direction registers which can set these
ports as output or input. A “1” in the port direction register
defines the corresponding port pin as output. Conversely,
write “0” to the corresponding bit to specify as an input
pin. For example, to use the even numbered bit of RA as
output ports and the odd numbered bits as input ports, write
“55H” to address C1H (RA direction register) during initial
setting as shown in Figure 9-1 .
I
O
6
I
O
4
I
O
2
I
O
RB DIRECTION
7
5
3
1
0 PORT
I: INPUT PORT
O: OUTPUT PORT
Figure 9-1 Example of port I/O assignment
9.1 RA and RAIO registers
RA is an 8-bit bidirectional I/O port (address C0H). Each
port can be set individually as input and output through the
RAIO register (address C1H).
select alternate function. After reset, this value is “0”, port
may be used as general I/O ports. To select alternate func-
tion such as Analog Input or External Event Counter Input,
write “1” to the corresponding bit of RAFUNC.Regardless
of the direction register RAIO, RAFUNC is selected to use
as alternate functions, port pin can be used as a correspond-
ing alternate features (RA0/EC0 is controlled by RB-
FUNC)
RA7~RA1 ports are multiplexed with Analog Input Port
(AN7~AN1) and RA0 port is multiplexed with Event
Counter Input Port (EC0).
ADDRESS : C0H
RA Data Register
RESET VALUE : Undefined
RA
PORT
RAFUNC.7~0
Description
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
0
1
0
1
0
RA7 (Normal I/O Port)
AN7 (ADS2~0=111)
RA6 (Normal I/O Port)
AN6 (ADS2~0=110)
RA5 (Normal I/O Port)
AN5 (ADS2~0=101)
RA4 (Normal I/O Port)
AN4 (ADS2~0=100)
RA3 (Normal I/O Port)
AN3 (ADS2~0=011)
RA2 (Normal I/O Port)
AN2 (ADS2~0=010)
RA1 (Normal I/O Port)
AN1 (ADS2~0=001)
RA0 (Normal I/O Port)
EC0 (T0CK2~0=111)
RA7/AN7
INPUT / OUTPUT DATA
ADDRESS : C1H
RA Direction Register
RAIO
RESET VALUE : 00000000
RA6/AN6
Preliminary
RA5/AN5
RA4/AN4
RA3/AN3
RA2/AN2
RA1/AN1
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
1
0
1
0
1
0
1
0
1
RA Function Selection Register
RAFUNC
ADDRESS : CAH
RESET VALUE : 00000000
ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
0 : RA4
1 : AN4
0 : RB0
1 : AN0
0 : RA1
1 : AN1
0 : RA2
1 : AN2
0 : RA3
1 : AN3
0 : RA5
1 : AN5
0 : RA6
1 : AN6
0 : RA7
1 : AN7
1
RA0/EC0
1. This port is not an Analog Input port, but Event Counter clock
source input port. ECO is controlled by setting TOCK2~0 =
111. The bit RAFUNC.0 (ANSEL0) controls the RB0/AN0/AVref
port (Refer to Port RB).
Figure 9-2 Registers of Port RA
The control register RAFUNC (address CAH) controls to
Jan. 2001
Preliminary
29
HMS87C1304A/HMS87C1302A
9.2 RB and RBIO registers
HYUNDAI MicroElectronics
RB is a 5-bit bidirectional I/O port (address C2H). Each
pin can be set individually as input and output through the
RBIO register (address C3H). In addition, Port RB is mul-
tiplexed with various special features. The control register
RBFUNC (address CBH) controls to select alternate func-
tion. After reset, this value is “0”, port may be used as gen-
eral I/O ports. To select alternate function such as External
interrupt or Timer compare output, write “1” to the corre-
sponding bit of RBFUNC.
Pull-up Selection Register
RB Data Register
ADDRESS : C2H
RESET VALUE : Undefined
ADDRESS : CCH
RESET VALUE : ------00
RB
PUPSEL
-
-
-
PUP1
PUP0
RB4 RB3 RB2 RB1 RB0
-
-
-
-
-
-
RB1 / INT1 Pull-up
0 : No Pull-up
INPUT / OUTPUT DATA
RB0 / INT0 Pull-up
0 : No Pull-up
1 : With Pull-up
1 : With Pull-up
Interrupt Edge Selection Register
IEDS
RB Direction Register
RBIO
ADDRESS : E6H
RESET VALUE : ----0000
ADDRESS : C3H
RESET VALUE : ---00000
-
-
-
-
IED1H IED1L
INT1
IED0H
IED0L
INT0
External Interrupt Edge Select
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
00 : Normal I/O port
01 : Falling (1-to-0 transition)
10 : Rising (0-to-1 transition)
11 : Both (Rising & Falling)
RB Function Selection Register
RBFUNC
ADDRESS : CBH
RESET VALUE : ---00000
Preliminary
-
-
-
PWM0O INT1I
INT0I
BUZO AVREFS
0 : RB0 when ANSEL0 = 0
AN0 when ANSEL0 = 1
1 : AVref
0 : RB1
1 : BUZ Output
0 : RB2
1 : INT0
0 : RB3
1 : INT1
0 : RB4
1 : PWM0 Output or
Compare Output
Figure 9-3 Registers of Port RB
Regardless of the direction register RBIO, RBFUNC is se-
lected to use as alternate functions, port pin can be used as
a corresponding alternate features.
30
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
PORT
RBFUNC.4~0
Description
RB4 (Normal I/O Port)
PWM0 Output /
Timer1 Compare Output
RB3 (Normal I/O Port)
External Interrupt Input 1
RB2 (Normal I/O Port)
External Interrupt Input 0
RB1 (Normal I/O Port)
Buzzer Output
0
RB4/
PWM0/
COMP0
1
0
1
0
1
0
1
RB3/INT1
RB2/INT0
RB1/BUZ
RB0 (Normal I/O Port)/
AN0 (ANSEL0=1)
01
12
RB0/AN0/
AVref
External Analog Reference
Voltage
1. When ANSEL0 = “0”, this port is defined for normal I/O port
(RB0).
When ANSEL0 = “1” and ADS2~0 = “000”, this port
can be used Analog Input Port (AN0).
2. When this bit set to “1”, this port defined for AVref, so it can
not be used Analog Input Port AN0 and Normal I/O
Port RB0.
Preliminary
Jan. 2001
Preliminary
31
HMS87C1304A/HMS87C1302A
9.3 RC and RCIO registers
HYUNDAI MicroElectronics
RC is a 2-bit bidirectional I/O port (address C4H). Each
pin can be set individually as input and output through the
RCIO register (address C5H).
ADDRESS : C4H
RC Data Register
ADDRESS : C5H
RESET VALUE : ------00
RC Direction Register
RCIO
RESET VALUE : Undefined
-
-
-
-
-
-
RC
RC1 RC0
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
INPUT / OUTPUT DATA
Figure 9-4 Registers of Port RC
9.4 RD and RDIO registers
RD is a 4-bit bidirectional I/O port (address C6H). Each
pin can be set individually as input and output through the
RDIO register (address C7H).
RD Direction Register
RDIO
RD Data Register
ADDRESS : C7H
RESET VALUE : -----000
ADDRESS : C6H
RESET VALUE : Undefined
RD
-
-
-
-
RD2 RD1 RD0
RD3
DIRECTION SELECT
0 : INPUT PORT
1 : OUTPUT PORT
INPUT / OUTPUT DATA
Figure 9-5 Registers of Port RD
Preliminary
32
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
10. CLOCK GENERATOR
HMS87C1304A/HMS87C1302A
The clock generator produces the basic clock pulses which
provide the system clock to be supplied to the CPU and pe-
ripheral hardware. The main system clock oscillator oscillates
with a crystal resonator or a ceramic resonator connected to the
Xin and Xout pins. External clocks can be input to the main
system clock oscillator. In this case, input a clock signal to
the Xin pin and open the Xout pin.ꢀ
fxin
OSCILLATION
CIRCUIT
CLOCK PULSE
GENERATOR
Internal system clock
PRESCALER
STOP
WAKEUP
÷1
÷2
÷4
÷8
÷16
÷32
÷64
÷128 ÷256 ÷512 ÷1024 ÷2048
Peripheral clock
Figure 10-1 Block Diagram of Clock Pulse Generator
10.1 Oscillation Circuit
XIN and XOUT are the input and output, respectively, a in-
verting amplifier which can be set for use as an on-chip os-
cillator, as shown in Figure 10-2 .
values of external components.
OPEN
Xout
Xout
External
Clock
Source
C1
C2
Xin
R1
Vss
Xin
Preliminary
Vss
Figure 10-3 External Clock Connections
Recommended: C1, C2 = 30pF±10pF for Crystals
R1 = 1MΩ
Note: When using a system clock oscillator, carry out wir-
ing in the broken line area in Figure 10-2 to prevent
any effects from wiring capacities.
Figure 10-2 Oscillator Connections
- Minimize the wiring length.
- Do not allow wiring to intersect with other signal
conductors.
- Do not allow wiring to come near changing high
current.
- Set the potential of the grounding position of the
oscillator capacitor to that of VSS. Do not ground to
any ground pattern where high current is present.
- Do not fetch signals from the oscillator.
To drive the device from an external clock source, Xout
should be left unconnected while Xin is driven as shown in
Figure 10-3 . There are no requirements on the duty cycle
of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but
minimum and maximum high and low times specified on
the data sheet must be observed.
Oscillation circuit is designed to be used either with a ce-
ramic resonator or crystal oscillator. Since each crystal and
ceramic resonator have their own characteristics, the user
should consult the crystal manufacturer for appropriate
In addition, the HMS87C1304A and HMS87C1302A has
an ability for the external RC oscillated operation. It offers
timing insensitive applica-
additional cost savings for
Jan. 2001
Preliminary
33
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
Figure 10-4 RC Oscillator Connections
tions
. The RC oscillator frequency is a function of the sup-
ply voltage, the external resistor (Rext) and capacitor
(Cext) values, and the operating temperature.
The oscillator frequency, divided by 4, is output from the
Xout pin, and can be used for test purpose or to synchroze
other logic.
The user needs to take into account variation due to toler-
ance of external R and C components used. Figure 10-4
shows how the RC combination is connected to the
HMS87C1304A or HMS87C1302A.
To set the RC oscillation, it should be programmed
RCOPT bit to "1" to CONFIG (0FF0H). ( Refer to DE-
VICE CONFIGURATION AREA )
Vdd
Rext
Xin
Cext
Xout
fxin÷4
Preliminary
34
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
11. Basic Interval Timer
HMS87C1304A/HMS87C1302A
The HMS87C1304A and HMS87C1302A has one 8-bit
Basic Interval Timer that is free-run, can not stop. Block
diagram is shown in Figure 11-1 .The 8-bit Basic interval
timer register (BITR) is increased every internal count
pulse which is divided by prescaler. Since prescaler has di-
vided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of
the oscillator frequency. As the count overflows from FFH
to 00H, this overflow causes to generate the Basic interval
timer interrupt. The BITF is interrupt request flag of Basic
interval timer.
mode. In this mode, all of the block is halted except the os-
cillator, prescaler (only fxin÷2048) and Timer0.
If the STOP instruction executed after writing “1” to bit
RCWDT of CKCTLR, it goes into the internal RC oscillat-
ed watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON de-
cides Watchdog Timer or the normal 7-bit timer
When write “1” to bit BTCL of CKCTLR, BITR register is
cleared to “0” and restart to count-up. The bit BTCL be-
comes “0” after one machine cycle by hardware.
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR
(address ECH). Address ECH is read as BITR, writ-
ten to CKCTLR. Therefore, the CKCTLR can not be
accessed by bit manipulation instruction..
If the STOP instruction executed after writing “1” to bit
WAKEUP of CKCTLR, it goes into the wake-up timer
WAKEUP
RCWDT
STOP
BTS[2:0]
÷ 8
BTCL
Clear
3
To Watchdog Timer
÷ 16
÷ 32
8
÷ 64
0
fxin
MUX
÷ 128
÷ 256
÷ 512
÷ 1024
Basic Interval Timer
Interrupt
BITIF
BITR (8BIT)
1
Internal RC OSC
Figure 11-1 Block Diagram of Basic Interval Timer
Preliminary
Clock Control Register
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
-
WAKEUP RCWDT WDTON
BTCL
BTS2
BTS1
BTS0
CKCTLR
Basic Interval Timer Clock Selection
Symbol
Function Description
000 : fxin ÷ 8
001 : fxin ÷ 16
010 : fxin ÷ 32
011 : fxin ÷ 64
100 : fxin ÷ 128
101 : fxin ÷ 256
110 : fxin ÷ 512
111 : fxin ÷ 1024
1 : Enables Wake-up Timer
0 : Disables Wake-up Timer
WAKEUP
1 : Enables Internal RC Watchdog Timer
0 : Disables Internal RC Watchdog Time
RCWDT
WDTON
BTCL
1 : Enables Watchdog Timer
0 : Operates as a 7-bit Timer
1 : BITR is cleared and BTCL becomes “0” automatically
after one machine cycle, and BITR continue to count-up
Figure 11-2 CKCTLR: Clock Control Register
Jan. 2001
Preliminary
35
HMS87C1304A/HMS87C1302A
12. TIMER / COUNTER
HYUNDAI MicroElectronics
The HMS87C1304A and HMS87C1302A has two Timer/
Counter registers. Each module can generate an interrupt
to indicate that an event has occurred (i.e. timer match).
sponse to a 0-to-1 (rising edge) transition at its correspond-
ing external input pin, EC0(Timer 0).
In addition the “capture” function, the register is increased
in response external interrupt same with timer function.
When external interrupt edge input, the count register is
captured into capture data register CDRx.
Timer 0 and Timer 1 can be used either the two 8-bit Tim-
er/Counter or one 16-bit Timer/Counter by combining
them.
In the “timer” function, the register is increased every in-
ternal clock input. Thus, one can think of it as counting in-
ternal clock input. Since a least clock consists of 2 and
most clock consists of 2048 oscillator periods, the count
rate is 1/2 to 1/2048 of the oscillator frequency in Timer0.
And Timer1 can use the same clock source too. In addition,
Timer1 has more fast clock source (1/1 to 1/8).
Timer1 is shared with “PWM” function and “Compare
output” function
It has seven operating modes: “8-bit timer/counter”, “16-
bit timer/counter”, “8-bit capture”, “16-bit capture”, “8-bit
compare output”, “16-bit compare output” and “10-bit
PWM” which are selected by bit in Timer mode register
TMx as shown in Figure 12-1 and Table 12-1 .
In the “counter” function, the register is increased in re-
Timer 0 Mode Register
ADDRESS : D0H
RESET VALUE : --000000
-
-
CAP0
T0CK2
T0CK1
T0CK0
T0CN
T0ST
TM0
CAP0
Capture mode selection bit.
0 : Disables Capture
1 : Enables Capture
T0CN
T0ST
Continue control bit
0 : Stop counting
1 : Start counting continuously
T0CK[2:0]
Input clock selection
Start control bit
0 : Stop counting
1 : Counter start ( It must be stop before restart )
000 : fxin ÷ 2, 100 : fxin ÷ 128
001 : fxin ÷ 4, 101 : fxin ÷ 512
010 : fxin ÷ 8, 110 : fxin ÷ 2048
011 : fxin ÷ 32, 111 : External Event ( EC0 )
Timer 1 Mode Register
ADDRESS : D2H
RESET VALUE : 00000000
POL
16BIT
PWM0E
CAP1
T1CK1
T1CK0
T1CN
T1ST
TM1
Preliminary
POL
PWM Output Polarity
0 : Duty active low
1 : Duty active high
T1CK[2:0]
Input clock selection
00 : fxin
10 : fxin ÷ 8
11 : using the Timer 0 clock
01 : fxin ÷ 2
16BIT
16-bit mode selection
0 : 8-bit mode
T1CN
Continue control bit
0 : Stop counting
1 : 16-bit mode
1 : Start counting continuously
PWM0E
CAP1
PWM enable bit
0 : Disables PWM
1 : Enables PWM
T1ST
Start control bit
0 : Stop counting
1 : Counter start ( It must be stop before restart )
Capture mode selection bit.
0 : Disables Capture
1 : Enables Capture
Figure 12-1 Timer Mode Register (TM0, TM1)
36
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
16BIT
CAP0
CAP1
PWME T0CK[2:0] T1CK[1:0] PWMO
TIMER 0
8-bit Timer
TIMER1
8-bit Timer
0
0
0
0
1
1
1
1
0
0
1
0
1
0
0
0
0
X
0
0
0
0
1
0
0
0
0
XXX
111
XX
XX
XX
XX
11
11
0
0
1
1
0
0
0
1
8-bit Event Counter
8-bit Capture
8-bit Capture
XXX
XXX
XXX
111
8-bit Compare output
10-bit PWM
X1
0
8-bit Timer/Counter
16-bit Timer
0
16-bit Event Counter
16-bit Capture
1
XXX
XXX
11
0
11
16-bit Compare output
Table 12-1 Operating Modes of Timer 0 and Timer 1
1. X: The value “0” or “1” corresponding your operation.
12.1 8-bit Timer/Counter Mode
The HMS87C1304A and HMS87C1302A has four 8-bit
Timer/Counters, Timer 0 and Timer 1 as shown in Figure
12-2 .
isters TMx as shown in Figure 12-1 and Table 12-1 . To
use as an 8-bit timer/counter mode, bit CAP0 of TM0 is
cleared to “0” and bits 16BIT of TM1 should be cleared to
“0”(Table 12-1 ).
The “timer” or “counter” function is selected by mode reg-
ADDRESS : D0H
RESET VALUE : --000000
-
-
CAP0
0
T0CK2
X
T0CK1
X
T0CK0
X
T0CN
X
T0ST
X
TM0
TM1
-
-
ADDRESS : D2H
RESET VALUE : 00000000
POL
X
16BIT
0
PWME
0
CAP1
0
T1CK1
X
T1CK0
X
T1CN
X
T1ST
X
X: The value “0” or “1” corresponding your operation.
T0ST
T0CK[2:0]
Edge Detector
Preliminary
0 : Stop
1 : Start
1
CLEAR
EC0
T0 (8-bit)
MUX
÷ 2
÷ 4
TIMER 0
INTERRUPT
T0IF
÷ 8
COMPARATOR
÷ 32
÷ 128
÷ 512
T0CN
fxin
TDR0 (8-bit)
T1CK[1:0]
MUX
÷ 2048
T1ST
0 : Stop
1 : Start
COMP0 PIN
1
÷
÷
÷
1
2
8
F/F
CLEAR
T1 (8-bit)
TIMER 1
INTERRUPT
T1IF
T1CN
COMPARATOR
TDR1 (8-bit)
Figure 12-2 8-bit Timer / Counter Mode
Jan. 2001
Preliminary
37
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
These timers have each 8-bit count register and data regis-
ter. The count register is increased by every internal or ex-
ternal clock input. The internal clock has a prescaler divide
ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by con-
trol bits T0CK2, T0CK1 and T0CK0 of register TM0) and
1, 2, 8 (selected by control bits T1CK1 and T1CK0 of reg-
ister TM1). In the Timer 0, timer register T0 increases
from 00H until it matches TDR0 and then reset to 00H. The
match output of Timer 0 generates Timer 0 interrupt
(latched in T0F bit). As TDRx and Tx register are in same
address, when reading it as a Tx, written to TDRx.
In counter function, the counter is increased every 0-to 1
(rising edge) transition of EC0 pin. In order to use counter
function, the bit RA0 of the RA Direction Register RAIO
is set to “0”. The Timer 0 can be used as a counter by pin
EC0 input, but Timer 1 can not.
TDR1
n
n-1
P
CP
9
8
7
6
5
4
3
2
1
0
TIME
Interrupt period
= P x (n+1)
CP
Timer 1 (T1IF)
Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 12-3 Counting Example of Timer Data Registers
TDR1
enable
disable
Preliminary
clear & start
stop
TIME
Timer 1 (T1IF)
Interrupt
Occur interrupt
Occur interrupt
T1ST
Start & Stop
T1ST = 1
T1ST = 0
T1CN
Control count
T1CN = 0
T1CN = 1
Figure 12-4 Timer Count Operation
38
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
12.2 16-bit Timer/Counter Mode
The Timer register is being run with 16 bits. A 16-bit timer/
counter register T0, T1 are increased from 0000H until it
matches TDR0, TDR1 and then resets to 0000H. The
match output generates Timer 0 interrupt not Timer 1 in-
terrupt.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0SL0.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
ADDRESS : D0H
RESET VALUE : --000000
-
-
CAP0
0
T0CK2
X
T0CK1
X
T0CK0
X
T0CN
X
T0ST
X
TM0
TM1
-
-
ADDRESS : D2H
RESET VALUE : 00000000
POL
X
16BIT
1
PWME
0
CAP1
0
T1CK1
T1CK0
T1CN
X
T1ST
X
1
1
X: The value “0” or “1” corresponding your operation.
T0CK[2:0]
T0ST
0 : Stop
1 : Start
Edge Detector
1
EC0
T1 (8-bit)
T0 (8-bit)
CLEAR
MUX
÷ 2
÷ 4
÷ 8
TIMER 0
T0IF
T0CN
÷ 32
÷ 128
÷ 512
÷ 2048
fxin
INTERRUPT
COMPARATOR
F/F
TDR1 (8-bit)
TDR0 (8-bit)
COMP0 PIN
Figure 12-5 16-bit Timer / Counter Mode
Preliminary
12.3 8-bit Compare Output (16-bit)
The HMS87C1304A and HMS87C1302A has a function
of Timer Compare Output. To pulse out, the timer match
can goes to port pin(COMP0) as shown in Figure 12-2 and
Figure 12-5 . Thus, pulse out is generated by the timer
match. These operation is implemented to pin, RB4/
COMP0/PWM.
wave, and output frequency is same as below equation.
ꢀꢁꢂꢃꢄꢄꢅꢆꢃꢇꢈꢉꢊꢋꢌꢍꢎꢌꢈꢂꢏ
------------------------------------------------------------------------------------------
=
ꢀ
ꢐ × ꢑꢋꢌꢁꢂꢅꢄꢌꢋꢉꢒꢅꢄꢎꢌ × (ꢁꢂꢃ + ꢓ)
In this mode, the bit PWMO of RB function register (RB-
FUNC) should be set to “1”, and the bit PWME of timer1
mode register (TM1) should be set to “0”.
This pin output the signal having a 50: 50 duty square
In addition, 16-bit Compare output mode is available, also.
12.4 8-bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer
mode register TM0 (bit CAP1 of timer mode register TM1
for Timer 1) as shown in Figure 12-6 .
be used as a capture mode.
The Timer/Counter register is increased in response inter-
nal or external input. This counting function is same with
normal timer mode, and Timer interrupt is generated when
As mentioned above, not only Timer 0 but Timer 1 can also
Jan. 2001
Preliminary
39
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
timer register T0 (T1) increases and matches TDR0
(TDR1).
tured into registers CDRx (CDR0, CDR1), respectively.
After captured, Timer x register is cleared and restarts by
hardware.
This timer interrupt in capture mode is very useful when
the pulse width of captured signal is more wider than the
maximum period of Timer.
It has three transition modes: “falling edge”, “rising edge”,
“both edge” which are selected by interrupt edge selection
register IEDS (Refer to External interrupt section). In ad-
dition, the transition at INTx pin generate an interrupt.
For example, in Figure 12-8 , the pulse width of captured
signal is wider than the timer data value (FFH) over 2
times. When external interrupt is occurred, the captured
value (13H) is more little than wanted value. It can be ob-
tained correct value by counting the number of timer over-
flow occurrence.
Note: The CDRx, TDRx and Tx are in same address. In
the capture mode, reading operation is read the
CDRx, not Tx because path is opened to the CDRx,
and TDRx is only for writing operation.
Timer/Counter still does the above, but with the added fea-
ture that a edge transition at external input INTx pin causes
the current value in the Timer x register (T0,T1), to be cap-
ADDRESS : D0H
RESET VALUE : --000000
-
-
CAP0
1
T0CK2
X
T0CK1
X
T0CK0
X
T0CN
X
T0ST
X
TM0
TM1
-
-
ADDRESS : D2H
RESET VALUE : 00000000
POL
X
16BIT
0
PWME
0
CAP1
1
T1CK1
X
T1CK0
X
T1CN
X
T1ST
X
T0CK[2:0]
T0ST
0 : Stop
1 : Start
Edge Detector
1
CLEAR
EC0
T0 (8-bit)
MUX
÷ 2
÷ 4
TIMER 0
INTERRUPT
T0IF
÷ 8
T0CN
CAPTURE
÷ 32
÷ 128
÷ 512
÷ 2048
fxin
COMPARATOR
TDR0 (8-bit)
CDR0 (8-bit)
Preliminary
INT 0
INTERRUPT
INT0IF
INT0
T0ST
0 : Stop
1 : Start
IEDS[1:0]
1
÷
÷
÷
1
2
8
CLEAR
MUX
T1 (8-bit)
TIMER 1
INTERRUPT
T1IF
T1CN
COMPARATOR
T1CK[1:0]
CDR1 (8-bit)
TDR1 (8-bit)
IEDS[3:2]
CAPTURE
INT 1
INTERRUPT
INT1IF
INT1
Figure 12-6 8-bit Capture Mode
40
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
This value is loaded to CDR0
n
T0
n-1
9
8
7
6
5
4
3
2
1
0
TIME
Ext. INT0 Pin
Interrupt Request
(INT0F)
Interrupt Interval Period
Ext. INT0 Pin
Interrupt Request
(INT0F)
Delay
Clear & Start
Capture
(Timer Stop)
Figure 12-7 Input Capture Operation
Preliminary
Ext. INT0 Pin
Interrupt Request
(INT0F)
Interrupt Interval Period = FF + 01 + FF +01 + 13 = 213
H
H
H
H
H
H
Interrupt Request
(T0F)
FF
H
FF
H
T0
13
H
00
H
00
H
Figure 12-8 Excess Timer Overflow in Capture Mode
Jan. 2001
Preliminary
41
HMS87C1304A/HMS87C1302A
12.5 16-bit Capture Mode
HYUNDAI MicroElectronics
16-bit capture mode is the same as 8-bit capture, except
that the Timer register is being run will 16 bits.
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1
should be set to “1” respectively.
The clock source of the Timer 0 is selected either internal
or external clock by bit T0CK2, T0CK1 and T0CK0.
ADDRESS : D0H
RESET VALUE : --000000
-
-
CAP0
1
T0CK2
X
T0CK1
X
T0CK0
X
T0CN
X
T0ST
X
TM0
TM1
-
-
ADDRESS : D2H
RESET VALUE : 00000000
POL
X
16BIT
1
PWME
0
CAP1
X
T1CK1
1
T1CK0
1
T1CN
X
T1ST
X
X: The value “0” or “1” corresponding your operation.
T0CK[2:0]
T0ST
Edge Detector
0 : Stop
1 : Start
1
CLEAR
EC0
fxin
T0 + T1 (16-bit)
MUX
÷ 2
÷ 4
T0CN
TIMER 0
INTERRUPT
T0IF
÷ 8
÷ 32
÷ 128
÷ 512
÷ 2048
COMPARATOR
CAPTURE
CDR1
(8-bit)
TDR1
(8-bit)
CDR0
(8-bit)
TDR0
(8-bit)
INT 0
INTERRUPT
INT0IF
INT0
IEDS[1:0]
Figure 12-9 16-bit Capture Mode
12.6 PWM Mode
Preliminary
The HMS87C1304A and HMS87C1302A has a high speed
PWM (Pulse Width Modulation) functions which shared
with Timer1.
And writes duty value to the T1PDR and the
PWM0HR[1:0] same way.
The T1PDR is configure as a double buffering for glitch-
less PWM output. In Figure 12-10 , the duty data is trans-
ferred from the master to the slave when the period data
matched to the counted value. (i.e. at the beginning of next
duty cycle)
In PWM mode, pin RB4/COMP0/PWM0 outputs up to a
10-bit resolution PWM output. This pin should be config-
ure as a PWM output by setting “1” bit PWM0O in RB-
FUNC register.
PWM Period = [PWM0HR[3:2]T1PPR] X Source Clock
PWM Duty = [PWM0HR[1:0]T1PDR] X Source Clock
The period of the PWM output is determined by the
T1PPR (PWM0 Period Register) and PWM0HR[3:2]
(bit3,2 of PWM0 High Register) and the duty of the PWM
output is determined by the T1PDR (PWM0 Duty Regis-
ter) and PWM0HR[1:0] (bit1,0 of PWM0 High Register).
The relation of frequency and resolution is in inverse pro-
portion. Table 12-2 shows the relation of PWM frequency
vs. resolution.
The user writes the lower 8-bit period value to the T1PPR
and the higher 2-bit period value to the PWM0HR[3:2].
42
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
If it needed more higher frequency of PWM, it should be
reduced resolution.
It can be changed duty value when the PWM output. How-
ever the changed duty value is output after the current pe-
riod is over. And it can be maintained the duty value at
present output when changed only period value shown as
Figure 12-12 . As it were, the absolute duty time is not
changed in varying frequency. But the changed period val-
ue must greater than the duty value.
Frequency
Resolution
T1CK[1:0] = T1CK[1:0] = T1CK[1:0] =
00(125nS)
01(250nS)
10(1uS)
0.98KHZ
1.95KHz
3.90KHz
7.81KHz
10-bit
9-bit
8-bit
7-bit
7.8KHz
3.9KHz
15.6KHz
31.2KHz
62.5KHz
7.8KHz
Note: If changing the Timer1 to PWM function, it
should be stop the timer clock firstly, and then
set period and duty register value. If user
writes register values while timer is in opera-
tion, these register could be set with certain
values.
15.6KHz
31.2KHz
Table 12-2 PWM Frequency vs. Resolution at 8MHz
Ex)
LDM TM1,#00H
The bit POL of TM1 decides the polarity of duty cycle.
LDM T1PPR,#00H
LDM T1PDR,#00H
If the duty value is set same to the period value, the PWM
output is determined by the bit POL (1: High, 0: Low). And
if the duty value is set to “00H”, the PWM output is deter-
mined by the bit POL (1: Low, 0: High).
LDM PWM0HR,#00H
LDM RBFUNC,#0001_1100B
LDM TM1,#1010_1011B
ADDRESS : D2H
RESET VALUE : 00000000
POL
16BIT
PWME
CAP1
T1CK1
X
T1CK0
X
T1CN
T1ST
TM1
X
X
X
-
0
-
1
-
0
-
ADDRESS : D5H
RESET VALUE : ----0000
PWM0HR3 PWM0HR2 PWM0HR1 PWM0HR0
PWM0HR
Bit Manipulation Not Available
-
-
-
-
X
X
X
X
Period High
Duty High
X: The value “0” or “1” corresponding your operation.
PWM0HR[3:2]
T1ST
T1PPR(8-bit)
T0 clock source
0 : Stop
1 : Start
Preliminary
COMPARATOR
RB4/
PWM0
S
R
Q
CLEAR
1
MUX
T1 (8-bit)
PWM0O
[RBFUNC.4]
÷
÷
÷
1
2
8
fxin
POL
COMPARATOR
T1CN
T1CK[1:0]
Slave
T1PDR(8-bit)
PWM0HR[1:0]
Master
T1PDR(8-bit)
Figure 12-10 PWM Mode
Jan. 2001
Preliminary
43
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
fxin
T1
00 01
00 01
02
03
04
05
7F
80
81
3FF
02
03
PWM
POL=1
PWM
POL=0
Duty Cycle [80H x 125nS = 16uS]
Period Cycle [3FFH x 125nS = 127.875uS, 7.8KHz]
T1CK[1:0] = 00 (fxin)
PWM0HR = 0CH
T1PPR (8-bit)
PWM0HR3 PWM0HR2
Period
Duty
1
1
FFH
T1PPR = FFH
T1PDR = 80H
T1PDR (8-bit)
80H
PWM0HR1 PWM0HR0
0
0
Figure 12-11 Example of PWM at 8MHz
T1CK[1:0] = 10 (1uS)
PW M 0HR = 00H
T1PPR = 0EH
Write T1PPR to 0AH
Period changed
T1PDR = 05H
Source
clock
Preliminary
T1
01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 04 05
PWM
POL=1
Duty Cycle
[05H x 1uS = 5uS]
Duty Cycle
[05H x 1uS = 5uS]
Duty Cycle
[05H x 1uS = 5uS]
Period Cycle [0EH x 1uS = 14uS, 71KHz]
Period Cycle [0AH x 1uS = 10uS, 100KHz]
Figure 12-12 Example of Changing the Period in Absolute Duty Cycle (@8MHz)
44
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
13. Buzzer Output function
HMS87C1304A/HMS87C1302A
The buzzer driver consists of 6-bit binary counter, the
buzzer register BUR and the clock selector. It generates
square-wave which is very wide range frequency (480
Hz~250 KHz at fxin = 4 MHz) by user programmable
counter.
Also, it is cleared by counter overflow and count up to out-
put the square wave pulse of duty 50%.
The bit 0 to 5 of BUR determines output frequency for
buzzer driving. Frequency calculation is following as
shown below.
Pin RB1 is assigned for output port of Buzzer driver by set-
ting the bit BUZO of RBFUNC to “1”.
Oscillator Frequency
ꢐ × Prescaler Ratio × (ꢆꢇꢃ + ꢓ)
-------------------------------------------------------------------------------------
(ꢄꢅ) =
ꢀ
The 6-bit buzzer counter is cleared and start the counting
by writing signal to the register BUR. It is increased from
00H until it matches 6-bit register BUR.
The bits BUCK1, BUCK0 of BUR selects the source clock
from prescaler output.
ADDRESS : DEH
RESET VALUE : 11111111
BUCK1
BUCK0
BUR5
BUR4
BUR3
BUR2
BUR1
BUR0
BUR
Bit Manipulation Not Available
Input clock selection
Buzzer Period Data
00 : fxin ÷ 8
01 : fxin ÷ 16
10 : fxin ÷ 32
11 : fxin ÷ 64
÷ 8
÷ 16
MUX
÷ 32
COUNTER (6-bit)
fxin
÷ 64
F/F
COMPARATOR
BUCK[1:0]
RB1/BUZ PIN
BUZO
[RBFUNC.1]
BUR (6-bit)
Preliminary
Figure 13-1 Buzzer Driver
Jan. 2001
Preliminary
45
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
14. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a corresponding 8-bit digital
value. The A/D module has eight analog inputs, which are
multiplexed into one sample and hold. The output of the
sample and hold is the input into the converter, which gen-
erates the result via successive approximation.
To use analog inputs, each port is assigned analog input
port by setting the bit ANSEL[7:0] in RAFUNC register.
And selected the corresponding channel to be converted by
setting ADS[2:0].
The processing of conversion is start when the start bit
ADST is set to “1”. After one cycle, it is cleared by hard-
ware. The register ADCR contains the results of the A/D
conversion. When the conversion is completed, the result
is loaded into the ADCR, the A/D conversion status bit
ADSF is set to “1”, and the A/D interrupt flag ADIF is set.
The block diagram of the A/D module is shown in Figure
14-1 . The A/D status bit ADSF is set automatically when
A/D conversion is completed, cleared when A/D conver-
sion is in process. The conversion time takes maximum 10
uS (at fxin=8 MHz).
The analog reference voltage is selected to VDD or AVref
by setting of the bit AVREFS in RBFUNC register. If ex-
ternal analog reference AVref is selected, the bit ANSEL0
should not be set to “1”, because this pin is used to an an-
alog reference of A/D converter.
The A/D module has two registers which are the control
register ADCM and A/D result register ADCR. The
ADCM register, shown in Figure 14-2 , controls the oper-
ation of the A/D converter module. The port pins can be
configure as analog inputs or digital I/O.
ADS[2:0]
111
RA7/AN7
ANSEL7
110
RA6/AN6
A/D Result Register
ANSEL6
ADDRESS : EBH
ADCR(8-bit)
101
RA5/AN5
RESET VALUE : Undefined
ANSEL5
100
Sample & Hold
S/H
RA4/AN4
RA3/AN3
RA2/AN2
ANSEL4
Successive
Approximation
011
ADIF
Preliminary
Circuit
A/D Interrupt
ANSEL3
010
001
000
Resistor
Ladder
Circuit
ANSEL2
RA1/AN1
ANSEL1
RB0/AN0/AVref
ANSEL0 (RAFUNC.0)
1
0
V
Pin
DD
ADEN
AVREFS (RBFUNC.0)
Figure 14-1 A/D Converter Block Diagram
46
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
A/D Control Register
ADDRESS : EAH
RESET VALUE : --000001
-
-
ADEN
ADS2
ADS1
ADS0
ADST
ADSF
ADCM
Reserved
A/D Status bit
0 : A/D Conversion is in process
Analog Channel Select
1 : A/D Conversion is completed
000 : Channel 0 (RB0/AN0)
001 : Channel 1 (RA1/AN1)
010 : Channel 2 (RA2/AN2)
011 : Channel 3 (RA3/AN3)
100 : Channel 4 (RA4/AN4)
101 : Channel 5 (RA5/AN5)
110 : Channel 6 (RA6/AN6)
111 : Channel 7 (RA7/AN7)
A/D Start bit
1 : A/D Conversion is started
After 1 cycle, cleared to “0”
0 : Bit force to zero
A/D Enable bit
1 : A/D Conversion is enable
0 : A/D Converter module shut off
and consumes no operation current
A/D Result Data Register
ADCR7 ADCR6 ADCR5
ADDRESS : EBH
RESET VALUE : Undefined
ADCR4
ADCR3
ADCR2
ADCR1
ADCR0
ADCR
Figure 14-2 A/D Converter Registers
A/D Converter Cautions
ENABLE A/D CONVERTER
A/D INPUT CHANNEL SELECT
ANALOG REFERENCE SELECT
A/D START (ADST = 1)
NOP
(1) Input range of AN0 to AN7
The input voltage of AN0 to AN7 should be within the
specification range. In particular, if a voltage above VDD
(or AVref)or below VSS is input (even if within the absolute max-
imum rating range), the conversion value for that channel can not
be indeterminate. The conversion values of the other channels
may also be affected.
Preliminary
(2) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid to
noise on pins AVref(or VDD)and AN0 to AN7. Since the effect
increases in proportion to the output impedance of the an-
alog input source, it is recommended that a capacitor be con-
nected externally as shown in Figure 14-4 in order to reduce
noise.
ADSF = 1
YES
Analog
AN0~AN7
Input
NO
100~1000pF
READ ADCR
Figure 14-4 Analog Input Pin Connecting Capacitor
Figure 14-3 A/D Converter Operation Flow
Jan. 2001
Preliminary
47
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
(3) Pins AN0/RB0 and AN1/RA1 to AN7/RA7
noise. Therefore, avoid applying pulses to pins adjacent to
the pin undergoing A/D conversion.
The analog input pins AN0 to AN7 also function as input/
output port (PORT RA and RB0) pins. When A/D conver-
sion is performed with any of pins AN0 to AN7 selected,
be sure not to execute a PORT input instruction while con-
version is in progress, as this may reduce the conversion
resolution.
(4) AVref pin input impedance
A series resistor string of approximately 10KΩ is connected be-
tween the AVref pin and the VSS pin.
Therefore, if the output impedance of the reference voltage
source is high, this will result in parallel connection to the
series resistor string between the AVref pin and the VSS pin, and
there will be a large reference voltage error.
Also, if digital pulses are applied to a pin adjacent to the
pin in the process of A/D conversion, the expected A/D
conversion value may not be obtainable due to coupling
Preliminary
48
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
15. INTERRUPTS
HMS87C1304A/HMS87C1302A
The HMS87C1304A and HMS87C1302A interrupt cir-
cuits consist of Interrupt enable register (IENH, IENL), In-
terrupt request flags of IRQH, IRQL, Interrupt Edge
Selection Register (IEDS), priority circuit and Master en-
able flag(“I” flag of PSW). The configuration of interrupt
circuit is shown in Figure 15-1 and Interrupt priority is
shown in Table 15-1 .
by the hardware when the service routine is vectored to
only if the interrupt was transition-activated.
The Timer 0 and Timer 1 Interrupts are generated by T0IF
and T1IF, which are set by a match in their respective tim-
er/counter register. The AD converter Interrupt is generat-
ed by ADIF which is set by finishing the analog to digital
conversion. The Watch dog timer Interrupt is generated by
WDTIF which set by a match in Watch dog timer register
(when the bit WDTON is set to “0”). The Basic Interval
Timer Interrupt is generated by BITIF which is set by a
overflowing of the Basic Interval Timer Register(BITR).
The External Interrupts INT0 and INT1 can each be transi-
tion-activated (1-to-0, 0-to-1 and both transition).
The flags that actually generate these interrupts are bit
INT0IF and INT1IF in Register IRQH. When an external
interrupt is generated, the flag that generated it is cleared
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
Internal bus line
“1” by hardware.
Interrupt Enable
IENH
IRQH
Register (Higher byte)
Release STOP
7
INT0IF
INT1IF
T0IF
External Int. 0
External Int. 1
IEDS
6
To CPU
5
4
Timer 0
Timer 1
I Flag
T1IF
Interrupt Master
Enable Flag
7
6
ADIF
A/D Converter
WDT
Interrupt
Vector
Address
Preliminary
WDTIF
5
Generator
BIT
BITIF
Interrupt Enable
Register (Lower byte)
IRQL
IENL
Internal bus line
Figure 15-1 Block Diagram of Interrupt Function
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in IRQH,
IRQL) except Power-on reset and software BRK interrupt.
Interrupt enable registers are shown in Figure 15-2 . These
registers are composed of interrupt enable flags of each in-
terrupt source, these flags determines whether an interrupt
will be accepted or not. When enable flag is “0”, a corre-
Jan. 2001
Preliminary
49
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
sponding interrupt source is prohibited. Note that PSW
contains also a master enable bit, I-flag, which disables all
interrupts at once.
Reset/Interrupt
Symbol Priority Vector Addr.
FFFEH
Hardware Reset
External Interrupt 0 INT0
External Interrupt 1 INT1
Timer 0
Timer 1
A/D Converter
Watch Dog Timer
Basic Interval Timer BIT
RESET
-
FFFAH
FFF8H
FFF6H
FFF4H
FFEAH
FFE8H
FFE6H
1
2
3
4
5
6
7
Timer 0
Timer 1
A/D C
WDT
Table 15-1 Interrupt Priority
Interrupt Enable Register High
ADDRESS : E2H
RESET VALUE : 0000----
INT0E
INT1E
T0E
T1E
-
-
-
-
-
-
-
IENH
IENL
Interrupt Enable Register Low
ADE WDTE BITE
ADDRESS : E3H
RESET VALUE : 000-----
-
-
Enables or disables the interrupt individually
If flag is cleared, the interrupt is disabled.
0 : Disable
1 : Enable
Interrupt Request Register High
INT0IF INT1IF T0IF
ADDRESS : E4H
RESET VALUE : 0000----
T1IF
-
-
-
-
-
-
-
IRQH
IRQL
Interrupt Request Register Low
ADIF WDTIF BITIF
ADDRESS : E5H
RESET VALUE : 000-----
-
-
Preliminary
Shows the interrupt occurrence
0 : Not occurred
1 : Interrupt request is occurred
Figure 15-2 Interrupt Enable Registers and Interrupt Request Registers
When an interrupt is occurred, the I-flag is cleared and dis-
able any further interrupt, the return address and PSW are
pushed into the stack and the PC is vectored to. Once in the
interrupt service routine the source(s) of the interrupt can
be determined by polling the interrupt request flag bits.
The interrupt request flag bit(s) must be cleared by soft-
ware before re-enabling interrupts to avoid recursive inter-
rupts. The Interrupt Request flags are able to be read and
written.
15.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted
or the interrupt latch is cleared to “0” by a reset or an in-
struction. Interrupt acceptance sequence requires 8 fOSC (2
µs at fXIN=4MHz) after the completion of the current in-
struction execution. The interrupt service task is terminat-
ed upon execution of an interrupt return instruction
50
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
[RETI].
3. The contents of the program counter (return address)
and the program status word are saved (pushed) onto the
stack area. The stack pointer decreases 3 times.
Interrupt acceptance
1. The interrupt master enable flag (I-flag) is cleared to
“0” to temporarily disable the acceptance of any follow-
ing maskable interrupts. When a non-maskable inter-
rupt is accepted, the acceptance of any following
interrupts is temporarily disabled.
4. The entry address of the interrupt service program is
read from the vector table address and the entry address
is loaded to the program counter.
5. The instruction stored at the entry address of the inter-
rupt service program is executed.
2. Interrupt request flag for the interrupt source accepted is
cleared to “0”.
System clock
Instruction Fetch
SP-2
PSW
V.L.
V.H.
New PC
OP code
SP
SP-1
PC
Address Bus
Data Bus
Not used
PCH
PCL
V.L.
ADL
ADH
Internal Read
Internal Write
Interrupt Processing Step
Interrupt Service Task
V.L. and V.H. are vector addresses.
ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 15-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Preliminary
be set to “1” by “EI” instruction in the interrupt service
program. In this case, acceptable interrupt sources are se-
lectively enabled by the individual interrupt enable flags.
Basic Interval Timer
Vector Table Address
Entry Address
012
0FFE6
0FFE7
H
H
H
Saving/Restoring General-purpose Register
0E
2E
0E312
0E313
H
H
0E3
H
H
H
During interrupt acceptance processing, the program
counter and the program status word are automatically
saved on the stack, but accumulator and other registers are
not saved itself. These registers are saved by the software
if necessary. Also, when multiple interrupt services are
nested, it is necessary to avoid using the same data memory
area for saving registers.
Correspondence between vector table address for BIT interrupt
and the entry address of the interrupt service program.
A interrupt request is not accepted until the I-flag is set to
“1” even if a requested interrupt has higher priority than
that of the current interrupt being serviced.
The following method is used to save/restore the general-
purpose registers.
When nested interrupt service is required, the I-flag should
Jan. 2001
Preliminary
51
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
Example: Register save using push and pop instructions
main task
INTxx: PUSH
PUSH
A
X
Y
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
acceptance of
interrupt
interrupt
service task
PUSH
saving
registers
interrupt processing
POP
POP
POP
RETI
Y
X
A
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
restoring
registers
interrupt return
General-purpose register save/restore using push and pop
instructions;
15.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin-
guish BRK from TCALL 0.
=0
B-FLAG
=1
BRK
INTERRUPT
ROUTINE
BRK or
TCALL0
Each processing step is determined by B-flag as shown in
Figure 15-4 .
TCALL0
ROUTINE
RETI
RET
Figure 15-4 Execution of BRK/TCALL0
Preliminary
15.3 Multi Interrupt
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced.
However, multiple processing through software for special
features is possible. Generally when an interrupt is accept-
ed, the I-flag is cleared to disable any further interrupt. But
as user sets I-flag in interrupt routine, some further inter-
rupt can be serviced even if certain interrupt is in progress.
52
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
Example: Even though Timer1 interrupt is in progress,
INT0 interrupt serviced without any suspend.
Main Program
service
TIMER 1
service
TIMER1: PUSH
A
PUSH
PUSH
LDM
LDM
EI
X
INT0
service
Y
IENH,#80H
IENL,#0
;Enable INT0 only
;Disable other
;Enable Interrupt
enable INT0
disable other
EI
:
:
:
Occur
TIMER1 interrupt
Occur
INT0
:
:
:
enable INT0
enable other
LDM
LDM
POP
POP
POP
RETI
IENH,#0F0H ;Enable all interrupts
IENL,#0E0H
Y
X
A
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
Figure 15-5 Execution of Multi Interrupt
Preliminary
Jan. 2001
Preliminary
53
HMS87C1304A/HMS87C1302A
15.4 External Interrupt
HYUNDAI MicroElectronics
The external interrupt on INT0 and INT1 pins are edge
triggered depending on the edge selection register IEDS
(address 0E6H) as shown in Figure 15-6 .
Example: To use as an INT0 and INT1
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
:
:
;**** Set port as an input port RB2
LDM
;
RBIO,#1111_1011B
;**** Set port as an interrupt port
LDM
;
RBFUNC,#04H
INT0 pin
INT1 pin
INT0IF
INT1IF
INT0 INTERRUPT
INT1 INTERRUPT
;**** Set Falling-edge Detection
LDM
:
:
:
IEDS,#0000_0001B
Response Time
The INT0 and INT1 edge are latched into INT0IF and
INT1IF at every machine cycle. The values are not actually
polled by the circuitry until the next machine cycle. If a re-
quest is active and conditions are right for it to be acknowl-
edged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The
DIV itself takes twelve cycles. Thus, a minimum of twelve
complete machine cycles elapse between activation of an
external interrupt request and the beginning of execution
of the first instruction of the service routine.
IEDS
[0E6 ]
H
Figure 15-6 External Interrupt Block Diagram
ADDRESS : 0E6
RESET VALUE : 00000000
H
Ext. Interrupt Edge Selection
Register
W
W
W
W
W
W
W
W
shows interrupt response timings.
IEDS
INT0 edge select
INT1 edge select
Preliminary
00 : Int. disable
01 : falling
10 : rising
00 : Int. disable
01 : falling
10 : rising
11 : both
11 : both
max. 12 f
8 f
OSC
OSC
Interrupt
goes
active
Interrupt
latched
Interrupt
processing
Interrupt
routine
Figure 15-7 Interrupt Response Timing Diagram
54
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
16. WATCHDOG TIMER
HMS87C1304A/HMS87C1302A
The purpose of the watchdog timer is to detect the mal-
function (runaway) of program due to external noise or
other causes and return the operation to the normal condi-
tion.
The 7-bit binary counter is cleared by setting WDTCL(bit7
of WDTR) and the WDTCL is cleared automatically after
1 machine cycle.
The RC oscillated watchdog timer is activated by setting
the bit RCWDT as shown below.
The watchdog timer has two types of clock source.
:
The first type is an on-chip RC oscillator which does not
require any external components. This RC oscillator is sep-
arate from the external oscillator of the Xin pin. It means
that the watchdog timer will run, even if the clock on the
Xin pin of the device has been stopped, for example, by en-
tering the STOP mode.
LDM
LDM
STOP
NOP
NOP
:
CKCTLR,#3FH ; enable the RC-osc WDT
WDTR,#0FFH
; set the WDT period
; enter the STOP mode
; RC-osc WDT running
The RC oscillation period is vary with temperature, VDD
and process variations from part to part (approximately,
40~120uS). The following equation shows the RC oscillat-
ed watchdog timer time-out.
The other type is a prescaled system clock.
The watchdog timer consists of 7-bit binary counter and
the watchdog timer data register. When the value of 7-bit
binary counter is equal to the lower 7 bits of WDTR, the
interrupt request flag is generated. This can be used as
WDT interrupt or reset the CPU in accordance with the bit
WDTON.
TR C W D T= C LKR C ×28×[W D TR.6~0]+ (C LK R C ×28)/2
w here, C LK R C = 40~120uS
In addition, this watchdog timer can be used as a simple 7-
bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.
Note: Because the watchdog timer counter is enabled af-
ter clearing Basic Interval Timer, after the bit WD-
TON set to “1”, maximum error of timer is depend on
prescaler ratio of Basic Interval Timer.
T
WDT = [WDTR.6~0] × Interval of BIT
Clock Control Register
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
-
WAKEUP RCWDT WDTON
BTCL
X
BTS2
X
BTS1
X
BTS0
X
CKCTLR
-
0
X
1
Watchdog Timer Register
Preliminary
ADDRESS : EDH
RESET VALUE : 01111111
Bit Manipulation Not Available
WDTCL
7-bit Watchdog Counter Register
WDTR
WAKEUP
RCWDT
STOP
BTS[2:0]
3
WDTR (8-bit)
÷ 8
BTCL
WDTCL
WDTON
÷ 16
÷ 32
÷ 64
÷ 128
÷ 256
÷ 512
÷ 1024
Clear
8
0
1
fxin
MUX
1
0
CPU RESET
BITR (8-bit)
7-bit Counter
OFD
Overflow Detection
Watchdog Timer
Interrupt Request
Basic Interval Timer
Interrupt
BITIF
Internal RC OSC
Figure 16-1 Block Diagram of Watchdog Timer
Jan. 2001
Preliminary
55
HMS87C1304A/HMS87C1302A
17. Power Saving Mode
HYUNDAI MicroElectronics
For applications where power consumption is a critical
factor, device provides three kinds of power saving func-
tions, STOP mode, Wake-up Timer mode and internal RC-
oscillated watchdog timer mode.
Note: Before executing STOP instruction, clear all in-
terrupt request flag. Because if the interrupt re-
quest flag is set before STOP instruction, the MCU
runs as if it doesn’t perform STOP instruction, even
though the STOP instruction is completed. So insert
two lines to clear all interrupt request flags (IRQH,
IRQL) before STOP instruction as shown each ex-
ample.
The power saving function is activated by execution of
STOP instruction after setting the corresponding bit
(WAKEUP, RCWDT) of CKCTLR.
Table 17-1 shows the status of each Power Saving Mode
Peripheral
RAM
STOP
Retain
Retain
Retain
Stop
Wake-up Timer
Retain
Internal RC-WDT
Retain
Control Registers
I/O Ports
Retain
Retain
Retain
Retain
CPU
Stop
Stop
Timer0
Stop
Operation
Oscillation
÷ 2048 only
Stop
Stop
Oscillation
Prescaler
Stop
Stop
Stop
Stop
Internal RC oscillator
Stop
Oscillation
Entering Condition
CKCTLR[6,5]
00
1X
01
Power Saving Release
Source
RESET, INT0, INT1,
Timer0
RESET, INT0, INT1,
RC-WDT
RESET, INT0, INT1
Table 17-1 Power Saving Mode
17.1 Stop Mode
In the Stop mode, the on-chip oscillator is stopped. With
the clock frozen, all functions are stopped, but the on-chip
RAM and Control registers are held. The port pins out the
values held by their respective port data register, port di-
rection registers. Oscillator stops and the systems internal
operations are all held up.
to ensure that VDD is not reduced before the Stop mode is
invoked, and that VDD is restored to its normal operating
level, before the Stop mode is terminated.
Preliminary
The reset should not be activated before VDD is restored to
its normal operating level, and must be held active long
enough to allow the oscillator to restart and stabilize.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
Note: After STOP instruction, at least two or more NOP
instruction should be written
• The program counter stop the address of the
instruction to be executed after the instruction
“STOP” which starts the STOP operating mode.
Ex)
LDM CKCTLR,#0000_1110B
LDM IRQH,#0
LDM IRQL,#0
STOP
NOP
NOP
The Stop mode is activated by execution of STOP in-
struction after setting the bit WAKEUP and RCWDT
of CKCTLR to “00”. (This register should be written
by byte operation. If this register is set by bit manipu-
lation instruction, for example “set1” or “clr1” instruc-
tion, it may be undesired operation)
In the STOP operation, the dissipation of the power asso-
ciated with the oscillator and the internal hardware is low-
ered; however, the power dissipation associated with the
pin interface (depending on the external circuitry and pro-
gram) is not directly determined by the hardware operation
In the Stop mode of operation, VDD can be reduced to min-
imize power consumption. Care must be taken, however,
56
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
of the STOP feature. This point should be little current
flows when the input level is stable at the power voltage
level (VDD/VSS), however, when the input level gets high-
er than the power voltage level (by approximately 0.3 to
0.5V), a current begins to flow. Therefore, if cutting off the
output transistor at an I/O port puts the pin signal into the
high-impedance state, a current flow across the ports input
transistor, requiring to fix the level by pull-up or other
means.
To minimize the current consumption during Stop mode,
the user should turn-off output drivers that are sourcing or
sinking current, if it is practical. Weak pull-ups on port
pins should be turned off, if possible. All inputs should be
either as VSS or at VDD (or as close to rail as possible).
An intermediate voltage on an input pin causes the input
buffer to draw a significant amount of current.
Release the STOP mode
STOP
INSTRUCTION
The exit from STOP mode is hardware reset or external in-
terrupt. Reset re-defines all the Control registers but does
not change the on-chip RAM. External interrupts allow
both on-chip RAM and Control registers to retain their val-
ues.
STOP Mode
Interrupt Request
After releasing STOP mode, instruction execution is divid-
ed into two ways by I-flag(bit2 of PSW).
If I-flag = 1, the normal interrupt response takes place. If I-
flag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vec-
tor to interrupt service routine. (refer to )
=0
Corresponding Interrupt
IEXX
Enable Bit (IENH, IENL)
=1
STOP Mode Release
When exit from Stop mode by external interrupt, enough
oscillation stabilization time is required to normal opera-
tion. shows the timing diagram. When release the Stop
mode, the Basic interval timer is activated on wake-up. It
is increased from 00H until FFH. The count overflow is set
to start normal operation. Therefore, before STOP instruc-
tion, user must be set its relevant prescaler divide ratio to
have long enough time (more than 20msec). This guaran-
tees that oscillator has started and stabilized.
=0
Master Interrupt
Enable Bit PSW[2]
I-FLAG
=1
Interrupt Service Routine
Next
INSTRUCTION
By reset, exit from Stop mode is shown in .
Figure 17-1 STOP Releasing Flow by Interrupts
Preliminary
Minimizing Current Consumption in Stop Mode
The Stop mode is designed to reduce power consumption.
Oscillator
(X pin)
IN
Internal
Clock
External
Interrupt
Clear Basic Interval Timer
STOP Instruction Execution
BIT
Counter
N-1
N
N+1
N+2
N-2
00
01
FE FF 00
01
Normal Operation
Stabilization Time
> 20mS
STOP Mode
Normal Operation
t
ST
Figure 17-2 Timing of STOP Mode Release by External Interrupt
Jan. 2001
Preliminary
57
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
STOP Mode
Oscillator
(X pin)
IN
Internal
Clock
RESET
Internal
RESET
STOP Instruction Execution
Stabilization Time
= 64mS @4MHz
Time can not be controlled by software
t
ST
Figure 17-3 Timing of STOP Mode Release by RESET
17.2 Wake-up Timer Mode
In addition, the clock source of timer0 should be select-
ed to 2048 divided ratio. Otherwise, the wake-up func-
tion can not work. And the timer0 can be operated as
16-bit timer with timer1 (refer to timer function). The
period of wake-up function is varied by setting the tim-
er data register 0, TDR0.
In the Wake-up Timer mode, the on-chip oscillator is not
stopped. Except the Prescaler (only 2048 divided ratio) and
Timer0, all functions are stopped, but the on-chip RAM
and Control registers are held. The port pins out the values
held by their respective port data register, port direction
registers.
The Wake-up Timer mode is activated by execution of
STOP instruction after setting the bit WAKEUP of
CKCTLR to “1”. (This register should be written by
byte operation. If this register is set by bit manipulation
instruction, for example “set1” or “clr1” instruction, it
may be undesired operation)
Release the Wake-up Timer mode
The exit from Wake-up Timer mode is hardware reset,
Timer0 overflow or external interrupt. Reset re-defines all
the Control registers but does not change the on-chip
RAM. External interrupts and Timer0 overflow allow both
on-chip RAM and Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. If I-
flag = 0, the chip will resume execution starting with the
instruction following the STOP instruction. It will not vec-
tor to interrupt service routine (refer to ).
Note: After STOP instruction, at least two or more NOP in-
struction should be written
Ex) LDM TDR0,#0FFH
LDM TM0,#0001_1011B
Preliminary
LDM CKCTLR,#0100_1110B
When exit from Wake-up Timer mode by external inter-
rupt or timer0 overflow, the oscillation stabilization time is
not required to normal operation. Because this mode do not
stop the on-chip oscillator shown as .
LDM IRQH,#0
LDM IRQL,#0
STOP
NOP
NOP
Oscillator
(X pin)
IN
CPU
Clock
STOP Instruction
Execution
Interrupt
Request
Normal Operation
Wake-up Timer Mode
(stop the CPU clock)
Normal Operation
Do not need Stabilization Time
Figure 17-4 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt
58
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
17.3 Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the
on-chip oscillator is stopped. But internal RC oscillation
circuit is oscillated in this mode. The on-chip RAM and
Control registers are held. The port pins out the values held
by their respective port data register, port direction regis-
ters.
fines all the Control registers but does not change the on-
chip RAM. External interrupts allow both on-chip RAM
and Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. In
this case, if the bit WDTON of CKCTLR is set to “0” and
the bit WDTE of IENH is set to “1”, the device will exe-
cute the watchdog timer interrupt service routine.() How-
ever, if the bit WDTON of CKCTLR is set to “1”, the
device will generate the internal RESET signal and exe-
cute the reset processing. ()
The Internal RC-Oscillated Watchdog Timer mode is
activated by execution of STOP instruction after set-
ting the bit WAKEUP and RCWDT of CKCTLR to
“01”. (This register should be written by byte opera-
tion. If this register is set by bit manipulation instruc-
tion, for example “set1” or “clr1” instruction, it may be
undesired operation)
If I-flag = 0, the chip will resume execution starting with
the instruction following the STOP instruction. It will not
vector to interrupt service routine (refer to ).
When exit from Internal RC-Oscillated Watchdog Timer
mode by external interrupt, the oscillation stabilization
time is required for normal operation. shows the timing di-
agram. When release the Internal RC-Oscillated Watchdog
Timer mode, the basic interval timer is activated on wake-
up. It is increased from 00H until FFH. The count overflow
is set to start normal operation. Therefore, before STOP in-
struction, user must be set its relevant prescaler divide ratio
to have long enough time (more than 20msec). This guar-
antees that oscillator has started and stabilized.
Note: After STOP instruction, at least two or more NOP in-
struction should be written
Ex) LDM WDTR,#1111_1111B
LDM CKCTLR,#0010_1110B
LDM IRQH,#0
LDM IRQL,#0
STOP
NOP
NOP
By reset, exit from internal RC-Oscillated Watchdog Tim-
er mode is shown in .
Release the Internal RC-Oscillated Watchdog Timer mode
The exit from Internal RC-Oscillated Watchdog Timer
mode is hardware reset or external interrupt. Reset re-de-
Oscillator
(X pin)
IN
Preliminary
Internal
RC Clock
Internal
Clock
External
Interrupt
(or WDT Interrupt)
Clear Basic Interval Timer
STOP Instruction Execution
BIT
Counter
N-1
N
N+1
N+2
N-2
00
01
FE FF 00
00
Normal Operation
Stabilization Time
> 20mS
RCWDT Mode
Normal Operation
t
ST
Figure 17-5 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt
Jan. 2001
Preliminary
59
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
RCWDT Mode
Oscillator
(X pin)
IN
Internal
RC Clock
Internal
Clock
RESET
RESET by WDT
Internal
RESET
STOP Instruction Execution
Stabilization Time
= 64mS @4MHz
Time can not be controlled by software
t
ST
Figure 17-6 Internal RCWDT Mode Releasing by RESET.
INPUT PIN
V
INPUT PIN
DD
V
DD
V
DD
internal
pull-up
V
DD
OPEN
i=0
i=0
i
O
O
O
i
Very weak current flows
V
DD
GND
X
GND
X
OPEN
Weak pull-up current flows
O
When port is configured as an input, input level should
be closed to 0V or 5V to avoid power consumption.
Preliminary
Figure 17-7 Application Example of Unused Input Por
t
OUTPUT PIN
OUTPUT PIN
ON
V
ON
DD
V
DD
OPEN
L
L
OFF
ON
OFF
ON
O
i=0
OFF
OFF
i
i
V
DD
GND
GND
GND
ON
X
O
X
OFF
In the left case, Tr. base current flows from port to GND.
To avoid power consumption, there should be low output
to the port .
O
In the left case, much current flows from port to GND.
Figure 17-8 Application Example of Unused input Port
60
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
18. RESET
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, while the
oscillator running. After reset, 64ms (at 4 MHz) add with
7 oscillator periods are required to start execution as shown
in Figure 18-1 .
Internal RAM is not affected by reset. When VDD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before reading or testing it.
Initial state of each register is shown as Table 8-1 .
1
2
3
4
5
6
7
Oscillator
(X pin)
IN
RESET
ADDRESS
BUS
FFFE FFFF Start
?
?
?
?
DATA
BUS
OP
?
ADH
FE
ADL
?
?
?
MAIN PROGRAM
RESET Process Step
Stabilizing Time
= 64mS at 4MHz
t
ST
Figure 18-1 Timing Diagram after RESET
Preliminary
Jan. 2001
Preliminary
61
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
19. POWER FAIL PROCESSOR
The HMS87C1304A and HMS87C1302A has an on-chip
power fail detection circuitry to immunize against power
noise. A configuration register, PFDR, can enable (if clear/
programmed) or disable (if set) the Power-fail Detect cir-
cuitry. If VDD falls below 2.5~3.5V(2.0~3.0V) range for
longer than 50 nS, the Power fail situation may reset MCU
according to PFS bit of PFDR. And power fail detect level
is selectable by mask option. On the other hand, in the
OTP, power fail detect level is decided by setting the bit
PFDLEVEL of CONFIG register when program the OTP.
cuit emulator, user can not experiment with it. Therefore,
after final development of user program, this function may
be experimented.
Note: Power fail detect level is decided by mask option
checking the bit PFDLEVEL of MASK ORDER
SHEET (refer to MASK ORDER SHEET)
In thc case of OTP, Power fail detect level is decid-
ed by setting the bit PFDLEVEL of CONFIG register
(refer to Figure 20-1 .
As below PFDR register is not implemented on the in-cir-
Power Fail Detector Register
ADDRESS : EFH
RESET VALUE : -----100
-
-
-
-
-
PFDIS
PFDM
PFS
PFDR
Reserved
Power Fail Status
0 : Normal Operate
1 : This bit force to “1” when
Power fail was detected
Operation Mode
0 : System Clock Freeze during power fail
1 : MCU will be reset during power fail
Disable Flag
0 : Power fail detection enable
1 : Power fail detection disable
Figure 19-1 Power Fail Detector Register
Pre
R
l
ES
i
ET
m
VECTOR inary
YES
PFS =1
NO
RAM CLEAR
INITIALIZE RAM DATA
Skip the
initial routine
INITIALIZE ALL PORTS
INITIALIZE REGISTERS
FUNTION
EXECUTION
Figure 19-2 Example S/W of RESET by Power fail
62
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
V
DD
PFV MAX
DD
PFV MIN
DD
64mS
Internal
RESET
V
DD
PFV MAX
DD
PFV MIN
DD
When PFDM = 1
64mS
64mS
Internal
RESET
t < 64mS
V
DD
PFV MAX
DD
PFV MIN
DD
Internal
RESET
V
DD
PFV MAX
DD
PFV MIN
DD
System
Clock
When PFDM = 0
V
DD
PFV MAX
DD
PFV MIN
DD
System
Clock
Figure 19-3 Power Fail Processor Situations
Preliminary
Jan. 2001
Preliminary
63
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
20. DEVICE CONFIGURATION AREA
The Device Configuration Area can be programmed or left
unprogrammed to select device configuration such as secu-
rity bit.
Customer ID recording locations where the user can store
check-sum or other customer identification numbers.
This area is not accessible during normal execution but is
readable and writable during program / verify.
Ten memory locations (0F50H ~ 0FE0H) are designated as
0F50
H
ID
ID
0F50
0F60
0F70
0F80
0F90
H
H
H
H
H
DEVICE
CONFIGURATION
AREA
ID
Configuration Register
ID
0FF0
H
CONFIG
ID
PFD
LEVEL
-
LOCK
ADDRESS : 0FF0H
-
-
-
-
-
ID
0FA0
H
H
ID
0FB0
PFD Level Select
0 : PFD Level High (2.5~3.5V)
1 : PFD Level Low (2.0~3.0V)
ID
0FC0
0FD0
H
H
H
H
ID
ID
0FE0
0FF0
SECURITY BIT
0 Allow Code Read Out
1 : Prohibit Code Read Out
CONFIG
Figure 20-1 Device Configuration Area
Preliminary
64
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
A_D4
A_D3
A_D2
A_D1
A_D0
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A_D5
A_D6
A_D7
2
3
4
V
DD
5
CTL0
CTL1
CTL2
6
V
SS
7
V
PP
8
NC
9
EPROM Enable
10
11
12
13
14
Figure 20-2 Pin Assignment
User Mode
Pin Name
EPROM MODE
Pin No.
Pin Name
Description
1
2
RA4 (AN4)
A_D4
A12
A13
A14
A15
A4
A5
A6
A7
D4
D5
D6
D7
RA5 (AN5)
RA6 (AN6)
RA7 (AN7)
A_D5
A_D6
A_D7
Address Input
Data Input/Output
3
4
Preliminary
V
V
Connect to V (6.0V)
5
DD
DD
DD
6
RB0 (AVref/AN0)
RB1 (INT0)
CTL0
CTL1
CTL2
Read/Write Control
Address/Data Control
7
8
RB2 (INT1)
V
Connect to V (6.0V)
9~18
19
20
21
22
23, 24
RB3~7, RC3~6, RD2
DD
DD
X
EPROM Enable High Active, Latch Address in falling edge
IN
X
NC
V
No connection
OUT
RESET
Programming Power (0V, 12.75V)
PP
V
V
V
Connect to V (0V)
SS
SS
DD
SS
Connect to V (6.0V)
RC0, 1
DD
Table 20-1 Pin Description in EPROM Mode
Jan. 2001
Preliminary
65
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
25
26
27
28
RA0 (EC0)
RA1 (AN1)
RA2 (AN2)
RA3 (AN3)
A_D0
A_D1
A_D2
A_D3
A8
A9
A0
A1
A2
A3
D0
D1
D2
D3
Address Input
Data Input/Output
A10
A11
Table 20-1 Pin Description in EPROM Mode
Preliminary
66
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
T
T
SET1
T
HLD2
HLD1
T
DLY2
T
DLY1
EPROM
Enable
T
VPPS
V
IHP
T
VPPR
V
PP
T
VDDS
0V
0V
CTL0
CTL1
CTL2
V
DD1H
T
T
CD1
CD1
V
DD1H
T
CD1
T
CD1
0V
A_D7~
A_D0
DATA
OUT
DATA
HA
LA
LA
DATA IN
OUT
DATA IN
V
DD1H
V
DD
Write Mode
Verify
Low 8bit
Address
Input
Write Mode
Verify
Low 8bit
Address
Input
High 8bit
Address
Input
Figure 20-3 Timing Diagram in Program (Write & Verify) Mode
After input a high address,
output data following low address input
Another high address step
T
HLD1
T
SET1
T
DLY1
EPROM
Enable
T
VPPS
V
IHP
Preliminary
V
PP
T
VDDS
TVPPR
0V
0V
CTL0
CTL1
CTL2
V
DD2H
T
T
CD2
CD2
V
DD2H
T
CD1
T
CD1
0V
A_D7~
A_D0
HA
LA
LA
DATA
DATA
HA
DATA
LA
V
DD2H
V
DD
DATA
Output
DATA
Output
Low 8bit
Address
Input
Low 8bit
Address
Input
Low 8bit
Address
Input
DATA
Output
High 8bit
Address
Input
High 8bit
Address
Input
Figure 20-4 Timing Diagram in READ Mode
Jan. 2001
Preliminary
67
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
Parameter
Programming Supply Current
Supply Current in EPROM Mode
VPP Level during Programming
VDD Level in Program Mode
Symbol
IVPP
MIN
TYP
MAX
Unit
mA
mA
V
-
-
-
50
IVDDP
VIHP
-
20
11.5
12.0
6
12.5
VDD1H
VDD2H
VIHC
5
6.5
V
VDD Level in Read Mode
-
2.7
-
-
V
0.8VDD
CTL2~0 High Level in EPROM Mode
CTL2~0 Low Level in EPROM Mode
A_D7~A_D0 High Level in EPROM Mode
A_D7~A_D0 Low Level in EPROM Mode
VDD Saturation Time
-
V
VILC
0.2VDD
-
-
V
VIHAD
VILAD
TVDDS
TVPPR
TVPPS
TSET1
THLD1
TDLY1
THLD2
TDLY2
TCD1
0.9VDD
-
-
V
0.1VDD
-
1
-
-
V
-
-
1
-
mS
mS
mS
nS
nS
nS
nS
nS
nS
nS
VPP Setup Time
-
V
PP Saturation Time
1
-
EPROM Enable Setup Time after Data Input
EPROM Enable Hold Time after TSET1
200
500
200
100
200
100
100
EPROM Enable Delay Time after THLD1
EPROM Enable Hold Time in Write Mode
EPROM Enable Delay Time after THLD2
CTL2,1 Setup Time after Low Address input and Data input
CTL1 Setup Time before Data output in Read and Verify Mode
TCD2
Table 20-2 AC/DC Requirements for Program/Read Mode
Preliminary
68
Preliminary
Jan. 2001
HYUNDAI MicroElectronics
HMS87C1304A/HMS87C1302A
START
Set VDD=V
DD1H
Report
Verify failure
Verify for all address
Report
Set VPP=V
IHP
Programming failure
NO
Verify OK
YES
NO
Verify blank
YES
Report
First Address Location
Programming OK
Next address location
VDD=V =0v
pp
Report
Programming failure
N=1
END
NO
YES
EPROM Write
Verify pass
100uS program time
NO
Verify pass
YES
Apply 3N program cycle
NO
Last address
YES
Preliminary
Figure 20-5 Programming Flow Chart
Jan. 2001
Preliminary
69
HMS87C1304A/HMS87C1302A
HYUNDAI MicroElectronics
START
Set VDD=V
Verify for all address
DD2H
Set VPP=V
IHP
First Address Location
Next address location
NO
Last address
YES
Report Read OK
VDD=0V
VPP=0V
END
Figure 20-6 Reading Flow Chart
Preliminary
70
Preliminary
Jan. 2001
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