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HMT125U7AFR6C-H8 [HYNIX]

256M X 72 DDR DRAM MODULE, 20 ns, DMA204, HALOGEN FREE, UDIMM-204;
HMT125U7AFR6C-H8
型号： HMT125U7AFR6C-H8
厂家： HYNIX SEMICONDUCTOR    HYNIX SEMICONDUCTOR
描述：

256M X 72 DDR DRAM MODULE, 20 ns, DMA204, HALOGEN FREE, UDIMM-204

动态存储器 双倍数据速率
文件： 总57页 (文件大小：514K)
中文：  中文翻译
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240pin DDR3 SDRAM Unbuffered DIMMs  
DDR3 SDRAM Unbuffered DIMMs  
Based on 1Gb A version  
HMT164U6AFP(R)6C  
HMT112U6AFP(R)8C  
HMT112U7AFP(R)8C  
HMT125U6AFP(R)8C  
HMT125U7AFP(R)8C  
** Contents are subject to change without prior notice.  
Rev. 0.1 / Dec 2008  
1
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Revision History  
Revision No.  
History  
Draft Date  
Remark  
Preliminary  
Preliminary  
0.01  
0.02  
0.1  
Initial draft for internal review  
Added IDD & Halogen-free products  
Initial Specification Release.  
Nov. 2007  
Mar. 2008  
Dec 2008  
Corrected typo on package ball feature.  
Rev. 0.1 / Dec 2008  
2
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table of Contents  
1. Description  
1.1 Device Features and Ordering Information  
1.1.1 Features  
1.1.2 Ordering Information  
1.2 Speed Grade & Key Parameters  
1.3 Address Table  
2. Pin Architecture  
2.1 Pin Definition  
2.2 Input/Output Functional Description  
2.3 Pin Assignment  
3. Functional Block Diagram  
3.1 512MB, 64Mx64 Module(1Rank of x16)  
3.2 1GB, 128Mx64 Module(1Rank of x8)  
3.3 1GB, 128Mx72 ECC Module(1Rank of x8)  
3.4 2GB, 256Mx64 Module(2Rank of x8)  
3.5 2GB, 256Mx72 ECC Module(2Rank of x8)  
4. Address Mirroring Feature  
4.1 DRAM Pin Wiring for Mirroring  
5. Absolute Maximum Ratings  
5.1 Absolute Maximum DC Ratings  
5.2 Operating Temperature Range  
6. AC & DC Operating Conditions  
6.1 Recommended DC Operating Conditions  
6.2 DC & AC Logic Input Levels  
6.2.1 For Single-ended Signals  
6.2.2 For Differential Signals  
6.2.3 Differential Input Cross Point  
6.3 Slew Rate Definition  
6.3.1 For Ended Input Signals  
6.3.2 For Differential Input Signals  
6.4 DC & AC Output Buffer Levels  
6.4.1 Single Ended DC & AC Output Levels  
6.4.2 Differential DC & AC Output Levels  
6.4.3 Single Ended Output Slew Rate  
6.4.4 Differential Ended Output Slew Rate  
6.5 Overshoot/Undershoot Specification  
6.6 Input/Output Capacitance & AC Parametrics  
6.7 IDD Specifications & Measurement Conditions  
7. Electrical Characteristics and AC Timing  
7.1 Refresh Parameters by Device Density  
7.2 DDR3 Standard speed bins and AC para  
8. DIMM Outline Diagram  
8.1 512MB, 64Mx64 Module(1Rankx16)  
8.2 1GB, 128Mx64 Module(1Rank of x8)  
8.3 1GB, 128Mx72 ECC Module(1Rank of x8)  
8.4 2GB, 256Mx64 Module(2Rank of x8)  
8.5 2GB, 256Mx72 ECC Module(2Rank of x8)  
Rev. 0.1 / Dec 2008  
3
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
1. Description  
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb A version. DDR3 SDRAMs in Fine  
Ball Grid Array(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffered DIMM series based on 1Gb  
A ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable  
for easy interchange and addition.  
1.1 Device Features & Ordering Information  
1.1.1 Features  
• VDD=VDDQ=1.5V  
• Programmable burst length 4/8 with both nibble  
sequential and interleave mode  
• VDDSPD=3.3V to 3.6V  
• BL switch on the fly  
• 8banks  
• Fully differential clock inputs (CK, /CK) operation  
• Differential Data Strobe (DQS, /DQS)  
• 8K refresh cycles /64ms  
• On chip DLL align DQ, DQS and /DQS transition with  
CK transition  
• DDR3 SDRAM Package: JEDEC standard 78ball  
FBGA(x4/x8), 96ball FBGA(x16) with support balls  
• DM masks write data-in at the both rising and falling  
edges of the data strobe  
• Driver strength selected by EMRS  
• Dynamic On Die Termination supported  
• Asynchronous RESET pin supported  
• ZQ calibration supported  
• All addresses and control inputs except data, data  
strobes and data masks latched on the rising edges of  
the clock  
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)  
supported  
• TDQS (Termination Data Strobe) supported (x8 only)  
• Write Levelization supported  
• P r o g ra m m a b l e a d d i t i ve l a t e n c y 0 , C L- 1 , a n d C L- 2 s u p  
ported  
• Auto Self Refresh supported  
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8  
• On Die Thermal Sensor supported (JEDEC optional)  
Rev. 0.1 / Dec 2008  
4
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
1.1.2 Ordering Information  
Part Name  
# of  
DRAMs ranks  
# of  
Density  
Org.  
Materials  
ECC  
TS  
HMT164U6AFP6C-S6/S5/G8/G7/H9/H8  
HMT164U6AFR6C-S6/S5/G8/G7/H9/H8  
HMT112U6AFP8C-S6/S5/G8/G7/H9/H8  
HMT112U6AFR8C-S6/S5/G8/G7/H9/H8  
HMT112U7AFP8C-S6/S5/G8/G7/H9/H8  
HMT112U7AFR8C-S6/S5/G8/G7/H9/H8  
HMT125U6AFP8C-S6/S5/G8/G7/H9/H8  
HMT125U6AFR8C-S6/S5/G8/G7/H9/H8  
HMT125U7AFP8C-S6/S5/G8/G7/H9/H8  
HMT125U7AFR8C-S6/S5/G8/G7/H9/H8  
512MB 64Mx64  
512MB 64Mx64  
4
4
1
1
1
1
1
1
2
2
2
2
Lead-free  
None  
No  
No  
Halogen-free None  
Lead free None  
Halogen-free None  
Lead free ECC  
Halogen-free ECC  
Lead free None  
Halogen-free None  
Lead free ECC  
Halogen-free ECC  
1GB  
1GB  
1GB  
1GB  
2GB  
2GB  
2GB  
2GB  
128Mx64  
128Mx64  
128Mx72  
128Mx72  
256Mx64  
256Mx64  
256Mx72  
256Mx72  
8
No  
8
No  
9
Yes  
Yes  
No  
9
16  
16  
18  
18  
No  
Yes  
Yes  
Rev. 0.1 / Dec 2008  
5
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
1.2 Speed Grade & Key Parameters  
MT/S  
DDR3-800  
-S6 -S5  
DDR3-1066  
-G8 -G7  
DDR3-1333  
-H9 -H8  
DDR3-1600  
Unit  
Grade  
-P1  
-P9  
tCK(min)  
CAS Latency  
tRCD(min)  
tRP(min)  
2.5  
1.875  
1.5  
1.25  
ns  
tCK  
ns  
6
5
8
7
9
8
12  
10  
12.5  
12.5  
35  
9
15  
12.5  
12.5  
37.5  
50  
15  
13.125  
13.125  
37.5  
13.5  
13.5  
36  
11.25  
11.25  
35  
15  
15  
12  
ns  
tRAS(min)  
tRC(min)  
37.5  
52.5  
6-6-6  
37.5  
52.5  
8-8-8  
36  
ns  
50.625  
7-7-7  
49.5  
9-9-9  
48  
47.25  
46.25  
9-9-9  
ns  
CL-tRCD-tRP  
5-5-5  
8-8-8  
10-10-10  
tCK  
1.3 Address Table  
512MB  
1GB  
1GB  
2GB  
2GB  
Organization  
Refresh Method  
Row Address  
Column Address  
Bank Address  
Page Size  
64M x 64  
8K/64ms  
A0-A12  
A0-A9  
BA0-BA2  
2KB  
128M x 64  
8K/64ms  
A0-A13  
A0-A9  
BA0-BA2  
1KB  
128M x 72  
8K/64ms  
A0-A13  
A0-A9  
BA0-BA2  
1KB  
256M x 64  
8K/64ms  
A0-A13  
A0-A9  
BA0-BA2  
1KB  
256M x 72  
8K/64ms  
A0-A13  
A0-A9  
BA0-BA2  
1KB  
# of Rank  
1
1
1
2
2
# of Device  
4
8
9
16  
18  
Rev. 0.1 / Dec 2008  
6
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
2. Pin Architecture  
2.1 Pin Definition  
Pin Name  
Description  
Pin Name  
SCL  
Description  
I2C serial bus clock for EEPROM  
A0–A13  
SDRAM address bus  
SDRAM bank select  
I2C serial bus data line for EEPROM  
BA0–BA2  
SDA  
I2C slave address select for EEPROM  
SDRAM core power supply  
RAS  
CAS  
SDRAM row address strobe  
SDRAM column address strobe  
SDRAM write enable  
SA0–SA2  
VDD  
*
VDDQ*  
WE  
SDRAM I/O Driver power supply  
SDRAM I/O reference supply  
S0–S1  
DIMM Rank Select Lines  
VREFDQ  
SDRAM command/address reference  
supply  
CKE0–CKE1  
SDRAM clock enable lines  
VREFCA  
ODT0–ODT1  
DQ0–DQ63  
CB0–CB7  
On-die termination control lines  
DIMM memory data bus  
DIMM ECC check bits  
VSS  
VDDSPD  
NC  
Power supply return (ground)  
Serial EEPROM positive power supply  
Spare pins (no connect)  
SDRAM data strobes  
(positive line of differential pair)  
Memory bus analysis tools  
(unused on memory DIMMS)  
DQS0–DQS8  
DQS0–DQS8  
DM0–DM8  
CK0–CK1  
TEST  
SDRAM data strobes  
(negative line of differential pair)  
RESET  
Set DRAMs to Known State  
SDRAM I/O termination supply  
Reserved for future use  
-
SDRAM data masks/high data strobes  
(x8-based x72 DIMMs)  
VTT  
SDRAM clocks  
(positive line of differential pair)  
RFU  
-
SDRAM clocks  
(negative line of differential pair)  
CK0–CK1  
*The VDD and VDDQ pins are tied common to a single power-plane on these designs  
Rev. 0.1 / Dec 2008  
7
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
2.2 Input/Output Functional Description  
Symbol  
Type  
Polarity  
Function  
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl  
Differential inputs are sampled on the crossing of positive edge of CK and negative  
CK0–CK1  
CK0–CK1  
SSTL  
crossing  
edge of CK. Output (read) data is reference to the crossing of CK and CK  
(Both directions of crossing).  
Activates the SDRAM CK signal when high and deactivates the CK signal  
CKE0–CKE1  
S0–S1  
SSTL  
SSTL  
Active High when low. By deactivating the clocks, CKE low initiates the Power Down  
mode, or the Self Refresh mode.  
Enables the associated SDRAM command decoder when low and disables  
the command decoder when high. When the command decoder is dis-  
abled, new commands are ignored but previous operations continue. This  
Active Low  
signal provides for external rank selection on systems with multiple ranks.  
RAS, CAS, WE  
ODT0–ODT1  
SSTL  
SSTL  
Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered.  
When high, termination resistance is enabled for all DQ, DQS, DQS and DM  
Active High  
pins, assuming this function is enabled in the Mode Register 1 (MR1).  
VREFDQ  
VREFCA  
Supply  
Supply  
Reference voltage for SSTL15 I/O inputs.  
Reference voltage for SSTL 15 command/address inputs.  
Power supply for the DDR3 SDRAM output buffers to provide improved  
noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ  
shares the same power plane as VDD pins.  
VDDQ  
Supply  
SSTL  
BA0–BA2  
—
—
Selects which SDRAM bank of eight is activated.  
During a Bank Activate command cycle, Address input defines the row  
address (RA0–RA15).  
During a Read or Write command cycle, Address input defines the column  
address. In addition to the column address, AP is used to invoke autopre-  
charge operation at the end of the burst read or write cycle. If AP is high,  
autoprecharge is selected and BA0, BA1, BA2 defines the bank to be pre-  
charged. If AP is low, autoprecharge is disabled. During a Precharge com-  
mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which  
bank(s) to precharge. If AP is high, all banks will be precharged regardless  
of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to  
define which bank to precharge. A12(BC) is sampled during READ and  
WRITE commands to determine if burst chop (on-the-fly) will be per-  
formed (HIGH, no burst chop; LOW, burst chopped).  
A0–A13  
SSTL  
DQ0–DQ63,  
CB0–CB7  
SSTL  
SSTL  
—
Data and Check Bit Input/Output pins.  
DM is an input mask signal for write data. Input data is masked when DM  
is sampled High coincident with that input data during a write access. DM  
is sampled on both edges of DQS. Although DM pins are input only, the DM  
loading matches the DQ and DQS loading.  
DM0–DM8  
VDD, VSS  
Active High  
Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD  
and VDDQ pins are tied to VDD/VDDQ planes on these modules.  
Supply  
Rev. 0.1 / Dec 2008  
8
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Symbol  
Type  
Polarity  
Function  
Data strobe for input and output data.  
DQS0–DQS8  
DQS0–DQS8  
Differential  
crossing  
SSTL  
These signals are tied at the system planar to either VSS or VDDSPD to con-  
figure the serial SPD EEPROM address range.  
SA0–SA2  
—
This bidirectional pin is used to transfer data into or out of the SPD  
EEPROM. An external resistor may be connected from the SDA bus line to  
VDDSPD to act as a pullup on the system board.  
SDA  
—
This signal is used to clock data into and out of the SPD EEPROM. An  
external resistor may be connected from the SCL bus time to VDDSPD to act  
as a pullup on the system board.  
SCL  
—
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ  
power plane. EEPROM supply is operable from 3.0V to 3.6V.  
VDDSPD  
Supply  
2.3 Pin Assignment  
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
1
2
VREFDQ  
VSS  
VREFDQ 121  
V
SS  
V
SS  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
A2  
VDD  
A2  
181  
182  
183  
184  
185  
186  
A1  
VDD  
VDD  
CK0  
CK0  
VDD  
NC  
A1  
VDD  
VDD  
CK0  
CK0  
VDD  
NC  
V
SS  
122  
123  
124  
125  
DQ4  
DQ5  
DQ4  
DQ5  
VDD  
CK1  
CK1  
VDD  
VDD  
3
DQ0  
DQ0  
DQ1  
CK1  
CK1  
VDD  
4
DQ1  
VSS  
VSS  
5
VSS  
VSS  
DM0  
NC  
DM0  
NC  
6
DQS0  
DQS0  
DQS0 126  
DQS0 127  
VDD  
7
VSS  
VSS  
VREFCA  
NC  
VREFCA 187  
8
VSS  
V
SS  
128  
129  
130  
DQ6  
DQ7  
DQ6  
DQ7  
NC  
VDD  
A10  
188  
189  
190  
A0  
A0  
9
DQ2  
DQ3  
DQ2  
DQ3  
VDD  
VDD  
VDD  
BA12  
VDD  
RAS  
S0  
BA12  
VDD  
RAS  
S0  
10  
VSS  
VSS  
A10  
BA02  
VDD  
WE  
BA02  
VDD  
WE  
11  
12  
13  
14  
15  
16  
VSS  
V
SS  
131  
132  
133  
134  
DQ12  
DQ13  
DQ12  
DQ13  
71  
72  
73  
74  
75  
76  
191  
192  
193  
194  
195  
196  
DQ8  
DQ9  
DQ8  
DQ9  
VSS  
VSS  
VSS  
VSS  
DM1  
NC  
DM1  
NC  
CAS  
VDD  
S1  
CAS  
VDD  
S1  
VDD  
ODT0  
A13  
VDD  
ODT0  
A13  
DQS1  
DQS1  
DQS1 135  
DQS1 136  
VSS  
VSS  
NC = No Connect; RFU = Reserved Future Use  
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.  
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more  
information on mirrored addresses.  
Rev. 0.1 / Dec 2008  
9
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
V
SS  
V
SS  
137  
DQ14  
DQ15  
DQ14  
DQ15  
77  
78  
ODT1  
VDD  
NC  
ODT1  
VDD  
NC  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
VDD  
NC  
VDD  
NC  
DQ10  
DQ11  
DQ10 138  
DQ11 139  
VSS  
VSS  
79  
VSS  
VSS  
VSS  
VSS  
140  
141  
DQ20  
DQ21  
DQ20  
DQ21  
80  
VSS  
VSS  
DQ36  
DQ37  
DQ36  
DQ37  
DQ16  
DQ17  
DQ16  
81  
DQ32  
DQ33  
DQ32  
DQ33  
DQ17 142  
143  
VSS  
VSS  
82  
VSS  
VSS  
VSS  
VSS  
DM2  
NC  
DM2  
NC  
83  
VSS  
VSS  
DM4  
NC  
DM4  
NC  
DQS2  
DQS2  
DQS2 144  
DQS2 145  
84  
DQS4  
DQS4  
DQS4  
DQS4  
VSS  
VSS  
85  
VSS  
VSS  
VSS  
VSS  
146  
DQ22  
DQ23  
DQ22  
DQ23  
86  
VSS  
VSS  
DQ38  
DQ39  
DQ38  
DQ39  
DQ18  
DQ19  
DQ18 147  
DQ19 148  
87  
DQ34  
DQ35  
DQ34  
DQ35  
VSS  
VSS  
88  
VSS  
VSS  
VSS  
VSS  
149  
DQ28  
DQ29  
DQ28  
DQ29  
89  
VSS  
VSS  
DQ44  
DQ45  
DQ44  
DQ45  
DQ24  
DQ25  
DQ24 150  
DQ25 151  
90  
DQ40  
DQ41  
DQ40  
DQ41  
VSS  
VSS  
91  
VSS  
VSS  
VSS  
VSS  
152  
DM3  
NC  
DM3  
NC  
92  
VSS  
VSS  
DM5  
NC  
DM5  
NC  
DQS3  
DQS3  
DQS3 153  
DQS3 154  
93  
DQS5  
DQS5  
DQS5  
DQS5  
VSS  
VSS  
94  
VSS  
VSS  
VSS  
VSS  
155  
DQ30  
DQ31  
DQ30  
DQ31  
95  
VSS  
VSS  
DQ46  
DQ47  
DQ46  
DQ47  
DQ26  
DQ27  
DQ26 156  
DQ27 157  
96  
DQ42  
DQ43  
DQ42  
DQ43  
VSS  
VSS  
97  
VSS  
VSS  
VSS  
VSS  
158  
159  
160  
161  
NC  
NC  
CB4  
CB5  
98  
VSS  
VSS  
DQ52  
DQ53  
DQ52  
DQ53  
NC  
NC  
CB0  
CB1  
99  
DQ48  
DQ49  
DQ48  
DQ49  
VSS  
VSS  
100  
101  
102  
103  
104  
105  
106  
107  
VSS  
VSS  
VSS  
VSS  
DM8  
NC  
DM8  
NC  
VSS  
VSS  
DM6  
NC  
DM6  
NC  
NC  
NC  
DQS8 162  
DQS8 163  
DQS6  
DQS6  
DQS6  
DQS6  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
164  
165  
166  
167  
NC  
NC  
CB6  
CB7  
VSS  
VSS  
DQ54  
DQ55  
DQ54  
DQ55  
NC  
NC  
CB2  
CB3  
DQ50  
DQ51  
DQ50  
DQ51  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
NC  
VSS  
VSS  
DQ60  
DQ60  
NC = No Connect; RFU = Reserved Future Use  
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.  
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more  
information on mirrored addresses.  
Rev. 0.1 / Dec 2008  
10  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
48  
NC  
KEY  
NC  
NC  
168  
Reset  
Reset  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
DQ56  
DQ57  
DQ56  
DQ57  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
DQ61  
DQ61  
KEY  
VSS  
VSS  
49  
50  
51  
52  
53  
54  
55  
56  
NC  
CKE0  
VDD  
BA2  
NC  
169 CKE1/NC  
CKE1/NC  
VDD  
NC  
VSS  
VSS  
DM7  
NC  
DM7  
NC  
CKE0  
VDD  
BA2  
NC  
170  
171  
172  
173  
174  
175  
176  
VDD  
NC  
DQS7  
DQS7  
DQS7  
DQS7  
VSS  
VSS  
NC  
NC  
VSS  
VSS  
DQ62  
DQ63  
DQ62  
DQ63  
VDD  
A12  
A9  
VDD  
A12  
A9  
DQ58  
DQ59  
DQ58  
DQ59  
VDD  
All  
VDD  
All  
VSS  
VSS  
VSS  
VSS  
VDDSPD  
SA1  
VDDSPD  
SA1  
A72  
VDD  
A72  
VDD  
VDD  
VDD  
SA0  
SCL  
SA2  
VTT  
SA0  
SCL  
SA2  
VTT  
A82  
A62  
VDD  
A82  
57  
58  
59  
60  
177  
178  
179  
180  
118  
119  
120  
238  
239  
240  
SDA  
SDA  
A52  
A42  
VDD  
A52  
A42  
VDD  
A62  
VDD  
VSS  
VSS  
VTT  
VTT  
A32  
A32  
NC = No Connect; RFU = Reserved Future Use  
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.  
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more  
information on mirrored addresses.  
Rev. 0.1 / Dec 2008  
11  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
3. Functional Block Diagram  
3.1 512MB, 64Mx64 Module(1Rank of x16)  
S0  
CS  
CS  
DQS4  
DQS4  
DM4  
DQS0  
DQS0  
DM0  
LDQS  
LDQS  
LDM  
LDQS  
LDQS  
LDM  
D2  
D0  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS5  
DQS5  
DM5  
UDQS  
UDQS  
UDM  
I/O 8  
I/O 9  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
DQS1  
DQS1  
DM1  
UDQS  
UDQS  
UDM  
I/O 8  
I/O 9  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ8  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
ZQ  
ZQ  
CS  
CS  
DQS6  
DQS6  
DM6  
DQS2  
DQS2  
DM2  
LDQS  
LDQS  
LDM  
LDQS  
LDQS  
LDM  
D1  
D3  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS7  
DQS7  
DM7  
UDQS  
UDQS  
UDM  
I/O 8  
I/O 9  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
DQS3  
DQS3  
DM3  
UDQS  
UDQS  
UDM  
I/O 8  
I/O 9  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
ZQ  
ZQ  
Notes:  
Serial PD  
1. DQ-to-I/O wiring is shown as recom-  
mended but may be changed.  
SCL  
2. DQ/DQS/DQS/ODT/DM/CKE/S relation-  
ships must be maintained as shown.  
3. DQ,DM,DQS,DQS resistors;Refer to asso-  
ciated topology diagram.  
SDA  
WP  
A0  
BA0–BA2  
BA0–BA2: SDRAMs D0–D3  
A1  
A2  
A0–A14  
RAS  
A0–A14: SDRAMs D0–D3  
RAS: SDRAMs D0–D3  
CAS: SDRAMs D0–D3  
CKE: SDRAMs D0–D3  
SA0 SA1 SA2  
4. Refer to the appropriate clock wiring  
topology under the DIMM wiring details  
section of this document.  
CAS  
VDDSPD  
SPD  
5. The pair CK1 and CK1# is terminated in  
75ohm but is not used on the module.  
6. A15 is not routed on the module.  
7. For each DRAM, a unique ZQ resistor is  
connected to ground.The ZQ resistor is  
240ohm+-1%  
CKE0  
V
DD/VDD  
Q
D0–D3  
WE: SDRAMs D0–D3  
ODT: SDRAMs D0–D3  
WE  
ODT0  
V
REFDQ  
SS  
REFCA  
D0–D3  
D0–D3  
V
CK0  
CK0  
RESET  
CK: SDRAMs D0–D3  
CK: SDRAMs D0–D3  
RESET:SDRAMs D0-D3  
8. One SPD exists per module.  
D0–D3  
V
Rev. 0.1 / Dec 2008  
12  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
3.2 1GB, 128Mx64 Module(1Rank of x8)  
S0  
DQS0  
DQS0  
DM0  
DQS4  
DQS4  
DM4  
DM CS  
DQS DQS  
DM CS DQS DQS  
I/O 0  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D4  
D0  
ZQ  
ZQ  
DQS5  
DQS5  
DM5  
DQS1  
DQS1  
DM1  
DQS  
DQS  
DM CS  
DM CS DQS DQS  
I/O 0  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ8  
DQ9  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D5  
D1  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
ZQ  
ZQ  
DQS6  
DQS6  
DM6  
DQS2  
DQS2  
DM2  
DQS DQS  
DM CS  
DM CS DQS DQS  
I/O 0  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
D6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D2  
ZQ  
ZQ  
DQS7  
DQS7  
DM7  
DQS3  
DQS3  
DM3  
CS DQS DQS  
D7  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DM CS DQS DQS  
I/O 0  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D3  
ZQ  
ZQ  
Serial PD  
Notes:  
SCL  
1. DQ-to-I/O wiring is shown as recom-  
mended but may be changed.  
2. DQ/DQS/DQS/ODT/DM/CKE/S relation-  
ships must be maintained as shown.  
3. DQ,DM,DQS/DQS resistors;Refer to  
associated topology diagram.  
4. Refer to the appropriate clock wiring  
topology under the DIMM wiring details  
section of this document.  
5. Refer to Section 3.1 of this document for  
details on address mirroring.  
SDA  
WP  
A0  
A1  
A2  
BA0–BA2  
BA0–BA2: SDRAMs D0–D7  
SA0 SA1 SA2  
A0–A15  
RAS  
A0–A15: SDRAMs D0–D7  
RAS: SDRAMs D0–D7  
CAS: SDRAMs D0–D7  
CKE: SDRAMs D0–D7  
CAS  
V
DDSPD  
SPD  
CKE0  
V
DD/VDD  
Q
D0–D7  
WE: SDRAMs D0–D7  
ODT: SDRAMs D0–D7  
CK: SDRAMs D0–D7  
CK: SDRAMs D0–D7  
WE  
ODT0  
CK0  
VREFDQ  
6. For each DRAM, a unique ZQ resistor is  
connected to ground.The ZQ resistor is  
240ohm+-1%  
D0–D7  
D0–D7  
V
SS  
CK0  
D0–D7  
VREFCA  
7. One SPD exists per module.  
RESET  
RESET:SDRAMs D0-D7  
Rev. 0.1 / Dec 2008  
13  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
3.3 1GB, 128Mx72 Module(1Rank of x8)  
S0  
DQS0  
DQS0  
DM0  
DQS4  
DQS4  
DM4  
DM CS  
DQS DQS  
DQS  
DQS  
CS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
D4  
D0  
ZQ  
ZQ  
DQS5  
DQS5  
DM5  
DQS1  
DQS1  
DM1  
DQS  
DQS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
CS  
CS DQS DQS  
D1  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ8  
DQ9  
D5  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
ZQ  
ZQ  
DQS6  
DQS6  
DM6  
DQS2  
DQS2  
DM2  
DQS DQS  
D6  
DM CS  
I/O 0  
DQS  
CS DQS  
D2  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
ZQ  
ZQ  
DQS7  
DQS7  
DM7  
DQS3  
DQS3  
DM3  
CS  
D7  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS  
DQS  
DQS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
CS  
D3  
DQS  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
ZQ  
ZQ  
DQS8  
DQS8  
DM8  
SPD(TS integrated)  
EVENT  
DQS  
DQS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
CS  
Notes:  
SCL  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
1. DQ-to-I/O wiring is shown as recom-  
mended but may be changed.  
2. DQ/DQS/DQS/ODT/DM/CKE/S rela-  
tionships must be maintained as  
shown.  
D8  
SDA  
EVENT  
A0  
A1  
A2  
SA0 SA1  
SA2  
ZQ  
3. DQ,CB,DM,DQS/DQS resistors;Refer  
to associated topology diagram.  
4. Refer to the appropriate clock wiring  
topology under the DIMM wiring  
details section of this document.  
5. For each DRAM, a unique ZQ resistor  
is connected to ground.The ZQ resis-  
tor is 240ohm+-1%  
BA0–BA2  
BA0–BA2: SDRAMs D0–D8  
A0–A15: SDRAMs D0–D8  
RAS: SDRAMs D0–D8  
CAS: SDRAMs D0–D8  
CKE: SDRAMs D0–D8  
WE: SDRAMs D0–D8  
ODT: SDRAMs D0–D8  
CK: SDRAMs D0–D8  
CK: SDRAMs D0–D8  
A0–A15  
RAS  
VDDSPD  
VDD/VDDQ  
SPD  
D0–D8  
CAS  
CKE0  
WE  
ODT0  
CK0  
CK0  
VREFDQ  
D0–D8  
D0–D8  
VSS  
6. One SPD exists per module.  
VREFCA  
D0–D8  
RESET  
RESET:SDRAMs D0-D8  
Rev. 0.1 / Dec 2008  
14  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
3.4 2GB, 256Mx64 Module(2Rank of x8)  
S1  
S0  
DQS0  
DQS0  
DM0  
DQS4  
DQS4  
DM4  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D4  
D12  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D8  
D0  
ZQ  
ZQ  
ZQ  
ZQ  
DQS1  
DQS1  
DM1  
DQS5  
DQS5  
DM5  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ8  
DQ9  
DQ10  
DQ11  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D13  
D5  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D9  
D1  
DQ12  
DQ13  
DQ14  
DQ15  
ZQ  
ZQ  
ZQ  
ZQ  
DQS6  
DQS6  
DM6  
DQS2  
DQS2  
DM2  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D14  
D6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D10  
D2  
ZQ  
ZQ  
ZQ  
ZQ  
DQS3  
DQS3  
DM3  
DQS7  
DQS7  
DM7  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D15  
D7  
D11  
D3  
ZQ  
Serial PD  
ZQ  
ZQ  
ZQ  
Notes:  
BA0–BA2  
A0–A15  
CKE1  
CKE0  
RAS  
BA0–BA2: SDRAMs D0–D15  
A0-A15: SDRAMs D0–D15  
CKE: SDRAMs D8–D15  
CKE: SDRAMs D0–D7  
SCL  
1. DQ-to-I/O wiring is shown as recom-  
mended but may be changed.  
2. DQ/DQS/DQS/ODT/DM/CKE/S relation-  
ships must be maintained as shown.  
3. DQ,DM,DQS,DQS resistors;Refer to  
associated topology diagram.  
SDA  
WP  
A0  
A1  
A2  
SA0 SA1 SA2  
RAS: SDRAMs D0–D15  
CAS: SDRAMs D0–D15  
CAS  
VDDSPD  
SPD  
WE  
WE: SDRAMs D0–D15  
4. Refer to Section 3.1 of this document for  
details on address mirroring.  
V
DD/VDD  
Q
D0–D15  
ODT0  
ODT1  
CK0  
ODT: SDRAMs D0–D7  
ODT: SDRAMs D8–D15  
CK: SDRAMs D0–D7  
CK: SDRAMs D0–D7  
CK: SDRAMs D8–D15  
CK: SDRAMs D8–D15  
VREFDQ  
5. For each DRAM, a unique ZQ resistor is  
connected to ground.The ZQ resistor is  
240ohm+-1%  
D0–D15  
D0–D15  
VSS  
CK0  
VREFCA  
6. One SPD exists per module.  
CK1  
D0–D15  
CK1  
RESET  
RESET:SDRAMs D0-D3  
Rev. 0.1 / Dec 2008  
15  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
3.5 2GB, 256Mx72 Module(2Rank of x8)  
S1  
S0  
DQS0  
DQS0  
DM0  
DQS4  
DQS4  
DM4  
DM CS DQS DQS  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
D13  
D4  
D9  
D0  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
ZQ  
ZQ  
ZQ  
ZQ  
DQS1  
DQS1  
DM1  
DQS5  
DQS5  
DM5  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ8  
DQ9  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D14  
D5  
I/O 1  
D10  
D1  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
ZQ  
ZQ  
ZQ  
ZQ  
DQS6  
DQS6  
DM6  
DQS2  
DQS2  
DM2  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D15  
D2  
D11  
D6  
ZQ  
ZQ  
ZQ  
ZQ  
DQS3  
DQS3  
DM3  
DQS7  
DQS7  
DM7  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D16  
D7  
D12  
D3  
ZQ  
ZQ  
ZQ  
ZQ  
VDDSPD  
SPD  
DQS8  
DQS8  
DM8  
SPD(TS integrated)  
VDD/VDDQ  
D0–D17  
D0–D17  
SCL  
V
REFDQ  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
SDA  
EVENT  
EVENT  
Vss  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
D0–D17  
D0–D17  
A0  
A1  
A2  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D17  
D8  
VREFCA  
SA0 SA1  
SA2  
Notes:  
1. DQ-to-I/O wiring is shown as recom-  
mended but may be changed.  
2. DQ/DQS/DQS/ODT/DM/CKE/S relation-  
ships must be maintained as shown.  
3. DQ,CB,DM/DQS/DQS resistors;Refer to  
associated topology diagram.  
ZQ  
ZQ  
BA0–BA2  
A0–A15  
CKE0  
CKE1  
RAS  
BA0-BA2: SDRAMs D0–D17  
A0-A15: SDRAMs D0–D17  
CKE: SDRAMs D0–D8  
CKE: SDRAMs D9–D17  
RAS: SDRAMs D0–D17  
CAS: SDRAMs D0–D17  
4. Refer to Section 3.1 of this document for  
details on address mirroring.  
ODT0  
ODT: SDRAMs D0–D8  
ODT: SDRAMs D9–D17  
CK: SDRAMs D0–D8  
CK: SDRAMs D0–D8  
CK: SDRAMs D9–D17  
CK: SDRAMs D9–D17  
RESET:SDRAMs D0-D17  
ODT1  
CK0  
CK0  
CK1  
CK1  
5. For each DRAM, a unique ZQ resistor is  
connected to ground.The ZQ resistor is  
240ohm+-1%  
6. One SPD exists per module.  
CAS  
WE  
WE: SDRAMs D0–D17  
RESET  
Rev. 0.1 / Dec 2008  
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HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
4. Address Mirroring Feature  
There is a via grid located under the SDRAMs for wiring the CA signals (address, bank address, command, and control  
lines) to the SDRAM pins. The length of the traces from the via to the SDRAMs places limitations on the bandwidth of  
the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3  
modules, a scheme was defined to reduce the length of these traces.The pins on the SDRAM are defined in a manner  
that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins,  
do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are  
address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 SDRAM pins are  
wired straight, with no mismatch between the connector pin assignment and the SDRAM pin assignment. Some of the  
Rank 1 SDRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.  
4.1 DRAM Pin Wiring for Mirroring  
SDRAM Pin  
Connector Pin  
Rank 0  
A3  
Rank 1  
A4  
A3  
A4  
A4  
A3  
A5  
A5  
A6  
A6  
A6  
A5  
A7  
A7  
A8  
A8  
A8  
A7  
BA0  
BA1  
BA0  
BA1  
BA1  
BA0  
<Table 4.1: SDRAM Pin Wiring for Mirroring >  
The table 4.1 illustrates the wiring in both the mirrored and non-mirrored case.  
The lengths of the traces to the SDRAM pins, is obviously shorter. The via grid is smaller as well.  
Rev. 0.1 / Dec 2008  
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HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Mirroring  
No Mirroring  
< Figure 4.1: Wiring Differences for Mirrored and Non-Mirrored Addresses >  
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is  
read the same way. There are limitations however. When writing to the internal registers with a "load mode" opera-  
tion, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a  
few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement  
that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been  
designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller  
must read the SPD and have the capability of de-mirroring the address when accessing the second rank.  
Rev. 0.1 / Dec 2008  
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HMT125U6(7)AFP(R)8C  
5. ABSOLUTE MAXIMUM RATINGS  
5.1 Absolute Maximum DC Ratings  
Symbol  
Parameter  
Voltage on VDD pin relative to Vss  
Voltage on VDDQ pin relative to Vss  
Voltage on any pin relative to Vss  
Storage Temperature  
Rating  
Units  
Notes  
VDD  
- 0.4 V ~ 1.975 V  
V
,3  
VDDQ  
VIN, VOUT  
TSTG  
- 0.4 V ~ 1.975 V  
- 0.4 V ~ 1.975 V  
-55 to +100 ℃  
V
V
,3  
, 2  
℃
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to  
the device. This is a stress rating only and functional operation of the device at these or any other conditions  
above those indicated in the operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect reliability.  
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement  
conditions, please refer to JESD51-2 standard.  
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than  
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.  
5.2 DRAM Component Operating Temperature Range  
Symbol  
Parameter  
Normal Temperature Range  
Extended Temperature Range  
Rating  
Units  
℃
Notes  
0 to 85  
,2  
TOPER  
85 to 95  
1,3  
℃
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM.  
For measurement conditions, please refer to the JEDEC document JESD51-2.  
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.  
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating  
conditions  
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85°… and  
95°… case temperature.  
Full specifications are guaranteed in this range, but the following additional conditions apply:  
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.  
(This double refresh requirement may not apply for some devices.) It is also possible to specify a component  
with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to supplier data sheet and/  
or the DIMM SPD for option avail ability.  
b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the  
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or  
enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).  
Rev. 0.1 / Dec 2008  
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HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
6. AC & DC Operating Conditions  
6.1 Recommended DC Operating Conditions  
Rating  
Symbol  
Parameter  
Units  
Notes  
Min.  
Typ.  
Max.  
VDD  
1.425  
1.500  
1.575  
V
V
1,2  
1,2  
Supply Voltage  
VDDQ  
1.425  
1.500  
1.575  
Supply Voltage for Output  
1. Under all conditions, VDDQ must be less than or equal to VDD.  
2. VDDQ tracks with VDD. AC parameters are measured with VDD abd VDDQ tied together.  
6.2 DC & AC Logic Input Levels  
6.2.1 DC & AC Logic Input Levels for Single-Ended Signals  
DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600  
Symbol  
Parameter  
Unit  
Notes  
Min  
Max  
VIH(DC)  
VIL(DC)  
VIH(AC)  
VIL(AC)  
DC input logic high  
DC input logic low  
AC input logic high  
AC input logic low  
Vref + 0.100  
-
V
V
V
V
1, 2  
1, 2  
1, 2  
1, 2  
Vref - 0.100  
-
Vref + 0.175  
Vref - 0.175  
Reference Voltage for  
DQ, DM inputs  
VRefDQ(DC)  
VRefCA(DC)  
VTT  
0.49 * VDD  
0.49 * VDD  
0.51 * VDD  
0.51 * VDD  
V
V
V
3, 4  
3, 4  
Reference Voltage for  
ADD, CMD inputs  
Termination voltage for  
DQ, DQS outputs  
VDDQ/2 - TBD  
VDDQ/2 + TBD  
1. For DQ and DM, Vref = VrefDQ. For input ony pins except RESET#, Vref = VrefCA.  
2. The “t.b.d.” entries might change based on overshoot and undershoot specification.  
3. The ac peak noise on VRef may not allow VRef to deviate from VRef(DC) by more than +/-1% VDD  
(for reference: approx. +/- 15 mV).  
For reference: approx. VDD/2 +/- 15 mV.  
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure  
6.2.1. It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ like-  
wise).VRef(DC) is the linear average of VRef(t) over a very long period of time (e.g. 1 sec). This average has to meet  
the min/max requirements in Table 1. Furthermore VRef(t) may temporarily deviate from VRef(DC) by no more than  
+/- 1% VDD.  
Rev. 0.1 / Dec 2008  
20  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
voltage  
VDD  
V
(t)  
Ref  
V
ac-noise  
Ref  
V
Ref(DC)max  
V
Ref(DC)  
VDD/2  
V
Ref(DC)min  
VSS  
time  
< Figure 6.2.1: Illustration of Vref(DC) tolerance and Vref AC-noise limits >  
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on  
VRef. "VRef " shall be understood as VRef(DC), as defined in Figure 6.2.1  
This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low  
level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account  
for VRef(DC) deviations from the optimum position within the data-eye of the input signals.  
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associ-  
ated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD)  
are included in DRAM timings and their associated deratings.  
6.2.2 DC & AC Logic Input Levels for Differential Signals  
DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600  
Symbol  
Parameter  
Unit Notes  
Min  
Max  
VIHdiff  
VILdiff  
Differential input logic high  
Differential input logic low  
+ 0.200  
-
V
V
1
1
- 0.200  
Note1:  
Refer to “Overshoot and Undershoot Specification section 6.5 on 26 page  
Rev. 0.1 / Dec 2008  
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HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
6.2.3 Differential Input Cross Point Voltage  
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each  
cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table 6.2.3  
The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to  
the midlevel between of VDD and VSS.  
VDD  
CK#, DQS#  
V
IX  
VDD/2  
V
IX  
V
IX  
CK, DQS  
VSS  
< Figure 6.2.3 Vix Definition >  
DDR3-800, DDR3-1066, DDR3-1333, DDR3-1600  
Symbol  
Parameter  
Unit Notes  
Min  
Max  
Differential Input Cross Point  
Voltage relative to VDD/2  
VIX  
- 150  
+ 150  
mV  
< Table 6.2.3: Cross point voltage for differential input signals (CK, DQS) >  
Rev. 0.1 / Dec 2008  
22  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
6.3 Slew Rate Definitions  
6.3.1 For Single Ended Input Signals  
- Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)  
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef  
and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew  
rate between the last crossing of VRef and the first crossing of VIL(AC)max.  
- Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)  
Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and  
the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate  
between the last crossing of VIH(DC)min and the first crossing of VRef.  
Measured  
Description  
Defined by  
Applicable for  
Min  
Max  
VIH(AC)min-Vref  
Delta TRS  
Vref-VIL(AC)max  
Delta TFS  
Vref-VIL(DC)max  
Delta TFH  
VIH(DC)min-Vref  
Delta TRH  
Input slew rate for rising edge  
Input slew rate for falling edge  
Input slew rate for rising edge  
Input slew rate for falling edge  
Vref  
VIH(AC)min  
Setup  
(tIS, tDS)  
Vref  
VIL(AC)max  
Vref  
VIL(DC)max  
VIH(DC)min  
Hold  
(tIH, tDH)  
Vref  
< Table 6.3.1: Single-Ended Input Slew Rate Definition >  
Part A: Set up  
Delta TRS  
vIH(AC)min  
vIH(DC)min  
vRefDQ or  
vRefCA  
vIL(DC)max  
vIL(AC)max  
Delta TFS  
Rev. 0.1 / Dec 2008  
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HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Part B: Hold  
Delta TRH  
vIH(AC)m in  
vIH(DC)m in  
vRefDQ or  
vRefCA  
vIL(DC)m ax  
vIL(AC)m ax  
Delta TFH  
< Figure 6.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals >  
6.3.2 Differential Input Signals  
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table  
and Figure .  
Measured  
Description  
Defined by  
Min  
Max  
VIHdiffmin-VILdiffmax  
Differential input slew rate for rising edge  
(CK-CK and DQS-DQS)  
VILdiffmax  
VIHdiffmin  
DeltaTRdiff  
VIHdiffmin-VILdiffmax  
Differential input slew rate for falling edge  
(CK-CK and DQS-DQS)  
VIHdiffmin  
VILdiffmax  
DeltaTFdiff  
Note:  
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.  
Rev. 0.1 / Dec 2008  
24  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Delta  
TRdiff  
vIHdiffmin  
0
vILdiffmax  
Delta  
TFdiff  
< Figure 6.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# >  
6.4 DC & AC Output Buffer Levels  
6.4.1 Single Ended DC & AC Output Levels  
Below table shows the output levels used for measurements of single ended signals.  
Symbol  
Parameter  
DC output high measurement level  
(for IV curve linearity)  
DDR3-800, 1066, 1333 and 1600  
Unit  
Notes  
VOH(DC)  
0.8 x VDDQ  
V
DC output mid measurement level  
(for IV curve linearity)  
VOM(DC)  
VOL(DC)  
VOH(AC)  
VOL(AC)  
0.5 x VDDQ  
0.2 x VDDQ  
V
V
V
V
DC output low measurement level  
(for IV curve linearity)  
AC output high measurement level  
(for output SR)  
VTT + 0.1 x VDDQ  
VTT - 0.1 x VDDQ  
1
1
AC output low measurement level  
(for output SR)  
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing  
with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2.  
Rev. 0.1 / Dec 2008  
25  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
6.4.2 Differential DC & AC Output Levels  
Below table shows the output levels used for measurements of differential signals.  
Symbol  
Parameter  
DDR3-800, 1066, 1333 and 1600  
Unit  
Notes  
VOHdiff  
(AC)  
AC differential output high  
measurement level (for output SR)  
+ 0.2 x VDDQ  
V
1
VOLdiff  
(AC)  
AC differential output low  
measurement level (for output SR)  
- 0.2 x VDDQ  
V
1
1. The swing of °æ 0.2 x VDDQ is based on approximately 50% of the static differential output high  
or low swingwith a driver impedance of 40ߟ and an effective test load of 25ߟ to VTT = VDDQ/2 at each of  
the differential output  
6.4.3 Single Ended Output Slew Rate  
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and  
measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 6.4.3.  
Measured  
Description  
Defined by  
From  
To  
VOH(AC)-VOL(AC)  
DeltaTRse  
Single ended output slew rate for rising edge  
VOL(AC)  
VOH(AC)  
VOH(AC)-VOL(AC)  
DeltaTFse  
Single ended output slew rate for falling edge  
VOH(AC)  
VOL(AC)  
Note:  
Output slew rate is verified by design and characterization, and may not be subject to production test.  
D elta T R se  
vO H (A C )  
V ∏  
vO L(A C )  
D elta T F se  
< Figure 6.4.3: Single Ended Output Slew Rate Definition >  
Rev. 0.1 / Dec 2008  
26  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
DDR3-800  
DDR3-1066  
DDR3-1333  
DDR3-1600  
Parameter  
Symbol  
Units  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Single-ended Output Slew Rate SRQse  
2.5  
5
2.5  
5
2.5  
5
TBD  
5
V/ns  
*** Description:  
SR: Slew Rate  
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)  
For Ron = RZQ/7 setting  
< Table 6.4.3: Output Slew Rate (single-ended) >  
6.4.4 Differential Output Slew Rate  
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and mea-  
sured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below Table and Figure 6.4.4  
Measured  
Description  
Defined by  
From  
To  
VOHdiff(AC)-VOLdiff(AC)  
Differential output slew rate for rising edge  
Differential output slew rate for falling edge  
VOLdiff(AC)  
VOHdiff(AC)  
DeltaTRdiff  
VOHdiff(AC)-VOLdiff(AC)  
VOHdiff(AC)  
VOLdiff(AC)  
DeltaTFdiff  
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.  
Delta  
TRdiff  
vOHdiff(AC)  
O
vOLdiff(AC)  
Delta  
TFdiff  
< Figure 6.4.4: Differential Output Slew Rate Definition >  
Rev. 0.1 / Dec 2008  
27  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
DDR3-800  
DDR3-1066  
DDR3-1333  
DDR3-1600  
Parameter  
Symbol  
Units  
Max  
Max  
Max  
Max  
Min  
Min  
Min  
Min  
Differential Output Slew Rate  
SRQdiff  
5
10  
5
10  
5
10  
TBD  
10  
V/ns  
***Description:  
SR: Slew Rate  
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)  
diff: Differential Signals  
For Ron = RZQ/7 setting  
< Table 6.6.4: Differential Output Slew Rate >  
6.5 Overshoot and Undershoot Specifications  
6.5.1 Address and Control Overshoot and Undershoot Specifications  
Specification  
Description  
DDR3-800  
DDR3-1066  
DDR3-1333  
DDR3-1600  
Maximum peak amplitude allowed for  
overshoot area (see Figure)  
0.4V  
0.4V  
0.4V  
0.4V  
Maximum peak amplitude allowed for  
undershoot area (see Figure)  
0.4V  
0.4V  
0.4V  
0.4V  
Maximum overshoot area above VDD  
(See Figure)  
0.67 V-ns  
0.5 V-ns  
0.4 V-ns  
0.33 V-ns  
Maximum undershoot area below VSS  
(See Figure)  
0.67 V-ns  
0.5 V-ns  
0.4 V-ns  
0.33 V-ns  
< Table 6.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins >  
< Figure 6.5.1: Address and Control Overshoot and Undershoot Definition >  
Maximum Amplitude  
Overshoot Area  
VDD  
VSS  
Volts  
(V)  
Undershoot Area  
Maximum Amplitude  
Time (ns)  
Rev. 0.1 / Dec 2008  
28  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
6.5.2 Clock,Data,Strobe and Mask Overshoot and Undershoot Specifications  
Specification  
Description  
DDR3-800  
DDR3-1066  
DDR3-1333  
DDR3-1600  
Maximum peak amplitude allowed for  
overshoot area (see Figure)  
Maximum peak amplitude allowed for  
undershoot area (see Figure)  
Maximum overshoot area above VDDQ  
(See Figure)  
0.4V  
0.4V  
0.4V  
0.4V  
0.4V  
0.4V  
0.4V  
0.4V  
0.25 V-ns  
0.25 V-ns  
0.19 V-ns  
0.19 V-ns  
0.15 V-ns  
0.15 V-ns  
0.13 V-ns  
0.13 V-ns  
Maximum undershoot area below VSSQ  
(See Figure)  
< Table 6.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask >  
Maximum Amplitude  
Overshoot Area  
VDDQ  
Volts  
(V)  
VSSQ  
Undershoot Area  
Maximum Amplitude  
Time (ns)  
Clock, Data Strobe and Mask Overshoot and Undershoot Definition  
< Figure 6.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition >  
Rev. 0.1 / Dec 2008  
29  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
6.6 Pin Capacitance  
Parameter  
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600  
Symbol  
Units Notes  
Min Max Min Max Min Max Min Max  
Input/output capacitance  
(DQ, DM, DQS, DQS#, TDQS,  
TDQS#)  
CIO  
1.5  
3.0  
1.5  
3.0  
1.6  
1.5  
2.5  
TBD TBD  
pF  
1,2,3  
Input capacitance, CK and  
CK#  
CCK  
CDCK  
TBD  
0
1.6  
0.15  
1.5  
TBD  
0
TBD TBD TBD TBD  
pF  
pF  
pF  
2,3,5  
2,3,4  
2,3,6  
Input capacitance delta  
CK and CK#  
0.15 TBD TBD TBD TBD  
1.5 TBD TBD TBD TBD  
0.20 TBD TBD TBD TBD  
Input capacitance  
(All other input-only pins)  
CI  
TBD  
0
TBD  
0
Input capacitance delta, DQS  
and DQS#  
CDDQS  
CDI_CTRL  
0.20  
0.3  
pF 2,3,12  
pF 2,3,7,8  
Input capacitance delta  
(All CTRL input-only pins)  
-0.5  
-0.5  
-0.5  
-0.5  
-0.5  
-0.5  
0.3  
0.5  
0.3  
TBD TBD TBD TBD  
TBD TBD TBD TBD  
TBD TBD TBD TBD  
Input capacitance delta  
(All ADD/CMD input-only pins)  
CDI_ADD_  
2,3,9,  
0.5  
pF  
10  
CMD  
Input/output capacitance delta  
(DQ, DM, DQS, DQS#)  
CDIO  
0.3  
pF 2,3,11  
Notes:  
1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic  
characterization of TDQS/TDQS# should be close as much as possible, Cio&Cdio requirement is applied  
(recommend deleting note or changing to “Although the DM, TDQS and TDQS# pins have different functions,  
the loading matches DQ and DQS.”)  
2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is  
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK  
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,  
RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.  
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here  
4. Absolute value of CCK-CCK#.  
5. The minimum CCK will be equal to the minimum CI.  
6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#.  
7. CTRL pins defined as ODT, CS and CKE.  
8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#))  
9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#.  
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#))  
11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#))  
12. Absolute value of CIO(DQS) - CIO(DQS#)  
Rev. 0.1 / Dec 2008  
30  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
o
6.7 IDD Specifications(T  
: 0 to 95 C)  
CASE  
512MB, 64M x 64 U-DIMM: HMT164U6AFP6C  
Symbol  
IDD0  
DDR3 800  
360  
480  
100  
40  
DDR3 1066  
420  
DDR3 1333  
480  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
note  
IDD1  
540  
580  
IDD2P(F)  
IDD2P(S)  
IDD2Q  
IDD2N  
IDD3P  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6(D)  
IDD6(S)  
IDD7  
120  
140  
40  
40  
180  
200  
140  
220  
700  
700  
740  
40  
240  
280  
240  
300  
180  
200  
280  
340  
880  
1060  
1020  
840  
860  
780  
40  
40  
1
1
24  
24  
24  
1300  
1420  
1720  
1GB, 128M x 64 U-DIMM: HMT112U6AFP8C  
Symbol  
IDD0  
DDR3 800  
640  
DDR3 1066  
760  
DDR3 1333  
840  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
note  
IDD1  
760  
880  
960  
IDD2P(F)  
IDD2P(S)  
IDD2Q  
IDD2N  
IDD3P  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6(D)  
IDD6(S)  
IDD7  
200  
240  
280  
80  
80  
80  
360  
480  
560  
400  
480  
600  
280  
360  
400  
440  
560  
680  
1120  
1040  
1480  
80  
1440  
1320  
1560  
80  
1560  
1680  
1720  
80  
1
1
48  
48  
48  
1800  
2000  
2440  
Rev. 0.1 / Dec 2008  
31  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
1GB, 128M x 72 U-DIMM: HMT112U7AFP8C  
Symbol  
IDD0  
DDR3 800  
720  
DDR3 1066  
855  
DDR3 1333  
945  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
note  
IDD1  
855  
990  
1080  
315  
IDD2P(F)  
IDD2P(S)  
IDD2Q  
IDD2N  
IDD3P  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6(D)  
IDD6(S)  
IDD7  
225  
270  
90  
90  
90  
405  
540  
630  
450  
540  
675  
315  
405  
450  
495  
630  
765  
1260  
1170  
1665  
90  
1620  
1485  
1755  
90  
1755  
1890  
1935  
90  
1
1
54  
54  
54  
2025  
2250  
2745  
2GB, 256M x 64 U-DIMM: HMT125U6AFP8C  
Symbol  
IDD0  
DDR3 800  
1040  
1160  
400  
DDR3 1066  
1240  
1360  
480  
DDR3 1333  
1440  
1560  
560  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
note  
IDD1  
IDD2P(F)  
IDD2P(S)  
IDD2Q  
IDD2N  
IDD3P  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6(D)  
IDD6(S)  
IDD7  
160  
160  
160  
720  
960  
1120  
1200  
800  
800  
960  
560  
720  
880  
1120  
1920  
1800  
2040  
160  
1360  
2160  
2280  
2320  
160  
1520  
1440  
1880  
160  
1
1
96  
96  
96  
2200  
2480  
3040  
Rev. 0.1 / Dec 2008  
32  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
2GB, 256M x 72 U-DIMM: HMT125U7AFP8C  
Symbol  
IDD0  
DDR3 800  
1170  
1305  
450  
DDR3 1066  
1395  
1530  
540  
DDR3 1333  
1620  
1755  
630  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
note  
IDD1  
IDD2P(F)  
IDD2P(S)  
IDD2Q  
IDD2N  
IDD3P  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6(D)  
IDD6(S)  
IDD7  
180  
180  
180  
810  
1080  
1080  
810  
1260  
1350  
900  
900  
630  
990  
1260  
2160  
2025  
2295  
180  
1530  
2430  
2565  
2610  
180  
1710  
1620  
2115  
180  
1
1
108  
108  
108  
2475  
2790  
3420  
6.7 IDD Measurement Conditions  
Within the tables provided further down, an overview about the IDD measurement conditions is  
provided as follows:  
Table 1 — Overview of Tables providing IDD Measurement Conditions and DRAM Behavior  
Table number  
Table 5 on page 33  
Table 6 on page 36  
Table 7 on page 38  
Table 8 on page 39  
Table 9 on page 42  
Table 10 on page 43  
Table 11 on page 44  
Measurement Conditions  
IDD0 and IDD1  
IDD2N, IDD2Q, IDD2P(0), IDD2P(1)  
IDD3N and IDD3P  
IDD4R, IDD4W, IDD7  
IDD7 for different Speed Grades and different tRRD, tFAW conditions  
IDD5B  
IDD6, IDD6ET  
Within the tables about IDD measurement conditions, the following definitions are used:  
- LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.).  
- STABLE is defined as inputs are stable at a HIGH or LOW level.  
- FLOATING is defined as inputs are VREF = VDDQ / 2.  
- SWITCHING is defined as described in the following 2 tables.  
Rev. 0.1 / Dec 2008  
33  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 2 —  
Definition of SWITCHING for Address and Command Input Signals  
SWITCHING for Address (row, column) and Command Signals (CS, RAS, CAS, WE) is defined as:  
If not otherwise mentioned the inputs are stable at HIGH or LOW during 4 clocks and change  
Address  
then to the opposite value  
(row, column):  
(e.g. Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax Ax.....  
please see each IDDx definition for details  
If not otherwise mentioned the bank addresses should be switched like the row/column  
addresses - please see each IDDx definition for details  
Bank address:  
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}  
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH,HIGH,HIGH}  
Define Command Background Pattern = D D D D D D D D D D D D...  
Command  
(CS, RAS, CAS, WE):  
If other commands are necessary (e.g. ACT for IDD0 or Read for IDD4R), the Background  
Pattern Command is substituted by the respective CS, RAS, CAS, WE levels of the necessary  
command.  
See each IDDx definition for details and figures 1,2,3 as examples.  
Table 3 — Definition of SWITCHING for Data (DQ)  
SWITCHING for Data (DQ) is defined as  
Data DQ is changing between HIGH and LOW every other data transfer (once per clock)  
for DQ signals, which means that data DQ is stable during one clock; see each IDDx  
definition for exceptions from this rule and for further details.  
See figures 1,2,3 as examples.  
Data (DQ)  
Data Masking (DM)  
NO Switching; DM must be driven LOW all the time  
Rev. 0.1 / Dec 2008  
34  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Timing parameters are listed in the following table:  
Table 4 — For IDD testing the following parameters are utilized.  
Parameter  
Bin  
DDR3-800  
DDR3-1066  
DDR3-1333  
DDR3-1600  
Unit  
5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 7-7-7 8-8-8 9-9-9 8-8-8 9-9-9 101010  
tCKmin(IDD)  
CL(IDD)  
2.5  
1.875  
7
1.5  
8
1.25  
9
ns  
clk  
ns  
ns  
ns  
ns  
5
6
6
8
7
9
8
10  
12.5  
tbd  
tRCDmin(IDD)  
tRCmin(IDD)  
tRASmin(IDD)  
tRPmin(IDD)  
12.5  
50  
15  
11.25 13.13  
15  
10.5  
12  
48  
36  
12  
13.5  
49.5  
36  
10  
11.25  
tbd  
52.5 48.75 50.63 52.50 46.5  
tbd  
tbd  
10  
37.5  
12.5  
37.5  
15  
37.5  
37.5  
37.5  
15  
36  
tbd  
tbd  
11.25 13.13  
10.5  
13.5  
11.25  
12.5  
x4/  
x8  
40  
50  
10  
10  
90  
40  
50  
10  
10  
90  
37.5  
50  
37.5  
50  
37.5  
50  
30  
45  
30  
45  
30  
45  
30  
40  
30  
40  
30  
40  
ns  
ns  
ns  
ns  
ns  
tFAW(IDD)  
tRRD(IDD)  
x16  
x4/  
x8  
7.5  
10  
7.5  
10  
7.5  
10  
6.0  
7.5  
90  
6.0  
7.5  
90  
6.0  
7.5  
90  
6.0  
7.5  
90  
6.0  
7.5  
90  
6.0  
7.5  
90  
x16  
tRFC(IDD) -  
512Mb  
90  
90  
90  
tRFC(IDD) - 1  
Gb  
110  
160  
tbd  
110  
160  
tbd  
110  
160  
tbd  
110  
160  
tbd  
110  
160  
tbd  
110  
160  
tbd  
110  
160  
tbd  
110  
160  
tbd  
110  
160  
tbd  
110  
160  
tbd  
110  
160  
tbd  
ns  
ns  
ns  
tRFC(IDD) - 2  
Gb  
tRFC(IDD) - 4  
Gb  
The following conditions apply:  
- IDD specifications are tested after the device is properly initialized.  
- Input slew rate is specified by AC Parametric test conditions.  
- IDD parameters are specified with ODT and output buffer disabled (MR1 Bit A12).  
Rev. 0.1 / Dec 2008  
35  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 5 — IDD Measurement Conditions for IDD0 and IDD1  
Current  
IDD0  
IDD1  
Operating Current 1  
Operating Current 0  
-> One Bank Activate  
-> Precharge  
-> One Bank Activate  
-> Read  
Name  
-> Precharge  
Measurement Condition  
Timing Diagram Example  
Figure 1  
CKE  
HIGH  
HIGH  
External Clock  
on  
on  
tCK  
tCKmin(IDD)  
tCKmin(IDD)  
tRC  
tRAS  
tRCD  
tRRD  
CL  
tRCmin(IDD)  
tRCmin(IDD)  
tRASmin(IDD)  
tRASmin(IDD)  
n.a.  
tRCDmin(IDD)  
n.a.  
n.a.  
n.a.  
CL(IDD)  
AL  
n.a.  
0
HIGH between. Activate and Precharge  
Commands  
HIGH between Activate, Read and  
Precharge  
CS  
Command Inputs  
SWITCHING as described in Table 2  
only exceptions are Activate and  
SWITCHING as described in Table 2; only  
exceptions are Activate, Read and  
(CS,RAS, CAS, WE)  
Precharge commands; example of IDD0 Precharge commands; example of IDD1  
pattern:  
pattern:  
A0DDDDDDDDDDDDDD P0  
A0DDDDR0DDDDDDDDD P0  
(DDR3-800: tRAS = 37.5ns between  
(A)ctivate and (P)recharge to bank 0;  
(DDR3-800 -555: tRCD = 12.5ns between  
(A)ctivate and (R)ead to bank 0;  
Definition of D and D: see Table 2  
Definition of D and D: see Table 2)  
Rev. 0.1 / Dec 2008  
36  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 5 — IDD Measurement Conditions for IDD0 and IDD1  
Current  
IDD0  
IDD1  
Operating Current 1  
Operating Current 0  
-> One Bank Activate  
-> Precharge  
-> One Bank Activate  
-> Read  
Name  
-> Precharge  
Row, Column Addresses  
Row addresses SWITCHING as described Row addresses SWITCHING as described  
in Table 2; in Table 2;  
Address Input A10 must be LOW all the Address Input A10 must be LOW all the  
time!  
time!  
Bank Addresses  
Data I/O  
bank address is fixed (bank 0)  
SWITCHING as described in Table 3  
bank address is fixed (bank 0)  
Read Data: output data switches every  
clock, which means that Read data is  
stable during one clock cycle.  
To achieve Iout = 0mA, the output buffer  
should be switched off by MR1 Bit A12 set  
to “1”.  
When there is no read data burst from  
DRAM, the DQ I/O should be FLOATING.  
off / 1  
Output Buffer DQ,DQS  
/ MR1 bit A12  
ODT  
off / 1  
disabled  
/ [0,0]  
disabled  
/ MR1 bits [A6, A2]  
Burst length  
/ [0,0]  
n.a.  
8 fixed / MR0 Bits [A1, A0] = {0,0}  
Active banks  
one  
one  
ACT-PRE loop  
all other  
ACT-RD-PRE loop  
all other  
Idle banks  
PrechargePowerDown Mode/ n.a.  
Mode Register Bit 12  
n.a.  
Rev. 0.1 / Dec 2008  
37  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
T10  
T12  
T14  
T16  
T18  
CK  
000  
BA[2:0]  
ADDR_a[9:0]  
ADDR_b[10]  
000  
00  
3FF  
11  
000  
00  
3FF  
11  
000  
00  
3F  
ADDR_c[12:11]  
CS  
RAS  
CAS  
WE  
ACT  
D
D# D#  
D
RD  
D# D#  
D
D
D# D#  
D
D
D# PRE  
D
D
D#  
CMD  
DQ  
DM  
0
0
1
1
0
0 1 1  
IDD1 Measurment Loop  
< Figure 1. IDD1 Example > (DDR3-800-555, 512Mb x8): Data DQ is shown but the output buffer  
should be switched off (per MR1 Bit A12 =”1”) to achieve Iout = 0mA. Address inputs are split into 3  
parts.  
a. In DDR3, the MRS Bit 12 defines DLL on/off behaviour ONLY for precharge power down. There are 2 different  
Precharge Power Down states possible: one with DLL on (fast exit, bit 12 = 1) and one with DLL off  
(slow exit, bit 12 = 0).  
b. Because it is an exit after precharge power down, the valid commands are: Activate, Refresh, Mode-Register Set,  
Enter - Self Refresh  
Rev. 0.1 / Dec 2008  
38  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 6 —  
IDD Measurement Conditions for IDD2N, IDD2P(1), IDD2P(0) and IDD2Q  
Current  
IDD2N  
IDD2P(1) a  
IDD2P(0)  
IDD2Q  
Precharge Power  
Precharge Standby Down Current  
Precharge Power  
Down Current  
Slow Exit -  
Precharge Quiet  
Standby Current  
Name  
Current  
Fast Exit -  
MRS A12 Bit = 1  
MRS A12 Bit = 0  
Measurement Condition  
Timing Diagram  
Example  
Figure 2  
CKE  
HIGH  
LOW  
on  
LOW  
on  
HIGH  
on  
External Clock  
on  
tCK  
tCKmin(IDD)  
n.a.  
tCKmin(IDD)  
n.a.  
tCKmin(IDD)  
n.a.  
tCKmin(IDD)  
n.a.  
tRC  
tRAS  
n.a.  
n.a.  
n.a.  
n.a.  
tRCD  
n.a.  
n.a.  
n.a.  
n.a.  
tRRD  
n.a.  
n.a.  
n.a.  
n.a.  
CL  
n.a.  
n.a.  
n.a.  
n.a.  
AL  
n.a.  
n.a.  
n.a.  
n.a.  
CS  
HIGH  
STABLE  
STABLE  
HIGH  
Bank Address, Row  
SWITCHING as  
Addr. and Command described in  
STABLE  
FLOATING  
off / 1  
STABLE  
FLOATING  
off / 1  
STABLE  
FLOATING  
off / 1  
Inputs  
Table 2  
Data inputs  
SWITCHING  
Output Buffer  
DQ,DQS  
off / 1  
/ MR1 bit A12  
ODT  
disabled  
/ [0,0]  
disabled  
/ [0,0]  
disabled  
/ [0,0]  
disabled  
/ [0,0]  
/ MR1 bits [A6, A2]  
Burst length  
Active banks  
Idle banks  
n.a.  
none  
all  
n.a.  
none  
all  
n.a.  
none  
all  
n.a.  
none  
all  
Slow Exit / 0  
Precharge Power  
Down Mode /  
Fast Exit / 1  
Slow exit (RD and  
ODT commands must  
satisfy tXPDLL-AL)  
n.a.  
n.a.  
(any valid command  
Mode Register Bit a  
after tXPb)  
a.  
b.  
Rev. 0.1 / Dec 2008  
39  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
T0  
T1  
T2  
T3  
T4  
T5  
T6  
T7  
T8  
T9  
CK  
BA[2:0]  
0
7
0
0
ADDR[12:0]  
0
7
CS  
RAS  
CAS  
WE  
D#  
D#  
D
D
D#  
D#  
D
D
D#  
D#  
CMD  
DQ[7:0]  
DM  
FF 00  
00  
FF  
FF 00  
00  
FF  
FF 00  
00  
FF  
FF 00  
00  
FF  
FF 00  
00  
FF  
FF  
<Figure 2. IDD2N / IDD3N Example > (DDR3-800-555, 512Mb x8)  
Rev. 0.1 / Dec 2008  
40  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 7 — IDD Measurement Conditions for IDD3N and IDD3P(fast exit)  
Current  
IDD3N  
IDD3P  
Active Power-Down Currenta  
Name  
Active Standby Current  
Always Fast Exit  
Measurement Condition  
Timing Diagram Example  
Figure 2  
CKE  
HIGH  
LOW  
on  
External Clock  
on  
tCK  
tCKmin(IDD)  
tCKmin(IDD)  
n.a.  
tRC  
n.a.  
tRAS  
n.a.  
n.a.  
tRCD  
tRRD  
n.a.  
n.a.  
n.a.  
n.a.  
CL  
n.a.  
n.a.  
AL  
n.a.  
n.a.  
CS  
HIGH  
STABLE  
STABLE  
FLOATING  
Addr. and cmd Inputs  
Data inputs  
SWITCHING as described in Table 2  
SWITCHING as described in Table 3  
Output Buffer DQ,DQS  
/ MR1 bit A12  
ODT  
off / 1  
off / 1  
disabled  
/ [0,0]  
n.a.  
disabled  
/ MR1 bits [A6, A2]  
Burst length  
Active banks  
Idle banks  
/ [0,0]  
n.a.  
all  
all  
none  
none  
Precharge Power Down Mode /  
Mode Register Bit a  
n.a. (Active Power Down Mode is always  
“Fast Exit” with DLL on  
n.a.  
a. DDR3 will offer only ONE active power down mode with DLL on (-> fast exit). MRS bit 12 will not be used for active  
power down. Instead bit 12 will be used to switch between two different precharge power down modes.  
Rev. 0.1 / Dec 2008  
41  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 8 —  
IDD Measurement Conditions for IDD4R, IDD4W and IDD7  
Current  
IDD4R  
IDD4W  
IDD7  
Name  
Operating Current  
Burst Read  
Operating Current  
Burst Write  
All Bank Interleave Read  
Current  
Measurement Condition  
Timing Diagram  
Example  
Figure 3  
CKE  
HIGH  
HIGH  
HIGH  
on  
External Clock  
on  
on  
tCK  
tRC  
tCKmin(IDD)  
tCKmin(IDD)  
tCKmin(IDD)  
n.a.  
n.a.  
tRCmin(IDD)  
tRAS  
tRCD  
tRRD  
CL  
n.a.  
n.a.  
tRASmin(IDD)  
tRCDmin(IDD)  
tRRDmin(IDD)  
CL(IDD)  
n.a.  
n.a.  
n.a.  
n.a.  
CL(IDD)  
CL(IDD)  
AL  
0
0
tRCDmin - 1 tCK  
HIGH btw. valid cmds  
For patterns see Table 9  
CS  
HIGH btw. valid cmds  
HIGH btw. valid cmds  
SWITCHING as described in  
CommandInputs(CS, SWITCHING as described in  
RAS, CAS, WE)  
Table 2; exceptions are Read Table 2; exceptions are Write  
commands => IDD4R  
Pattern:  
commands => IDD4W  
Pattern:  
R0DDDR1DDDR2DDDR3.DD W0DDDW1DDDW2DDDW3  
D R4.....  
Rx = Read from bank x;  
Definition of D and D: see  
Table 2  
DDD W4...  
Wx = Write to bank x;  
Definition of D and D: see  
Table 2  
Rev. 0.1 / Dec 2008  
42  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 8 —  
IDD Measurement Conditions for IDD4R, IDD4W and IDD7  
Current  
IDD4R  
IDD4W  
IDD7  
Name  
Operating Current  
Burst Read  
Operating Current  
Burst Write  
All Bank Interleave Read  
Current  
column addresses  
SWITCHING as described in  
Table 2;  
column addresses  
SWITCHING as described in  
Table 2;  
Row, Column  
Addresses  
STABLE during DESELECTs  
Address Input A10 must be  
LOW all the time!  
Address Input A10 must be  
LOW all the time!  
bank address cycling (0 -> 1 -  
> 2 -> 3...), see pattern in  
Table 9  
bank address cycling (0 -> 1 - bank address cycling (0 -> 1 -  
Bank Addresses  
> 2 -> 3...)  
> 2 -> 3...)  
Seamless Read Data Burst  
(BL8): output data switches  
every clock, which means that  
Read data is stable during one  
clock cycle.  
Seamless Write Data Burst Read Data (BL8): output data  
(BL8): input data switches  
switches every clock, which  
means that Read data is  
every clock, which means that  
Write data is stable during one stable during one clock cycle.  
clock cycle.  
DQ I/O  
To achieve Iout = 0mA the  
To achieve Iout = 0mA the  
output buffer should be  
switched off by MR1 Bit A12  
set to “1”.  
DM is low all the time.  
output buffer should be  
switched off by MR1 Bit A12  
set to “1”.  
Output Buffer  
DQ,DQS  
off / 1  
off / 1  
off / 1  
/ MR1 bit A12  
ODT  
disabled  
/ [0,0]  
disabled  
/ [0,0]  
disabled  
/ [0,0]  
/ MR1 bits [A6, A2]  
8 fixed / MR0 Bits [A1, A0] = 8 fixed / MR0 Bits [A1, A0] = 8 fixed / MR0 Bits [A1, A0] =  
Burst length  
{0,0}  
all  
{0,0}  
all  
{0,0}  
all, rotational  
none  
Active banks  
Idle banks  
none  
none  
Precharge Power  
Down Mode /  
n.a.  
n.a.  
n.a.  
Mode Register Bit  
Rev. 0.1 / Dec 2008  
43  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
CK  
000  
000  
001  
3FF  
010  
000  
011  
3FF  
BA[2:0]  
ADDR[12:0]  
ADDR_b[10]  
ADDR_c[12:11]  
11  
00  
11  
00  
CS  
RAS  
CAS  
WE  
CMD[2:0]  
RD  
D
D#  
D#  
RD  
D
D#  
D#  
RD  
D
D#  
D#  
RD  
DQ[7:0]  
DM  
00 00 FF FF 00 00 FF FF 00 00 FF FF 00 00 FF FF  
-> Start of Measurement Loop  
< Figure 3. IDD4R Example > (DDR3-800-555, 512Mb x8): data DQ is shown but the output buffer  
should be switched off (per MR1 Bit A12=”1”) to achieve Iout = 0mA. Address inputs are split into 3  
parts.  
Rev. 0.1 / Dec 2008  
44  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 9 —  
Speed  
IDD7 Pattern for different Speed Grades and different tRRD, tFAW conditions  
Bin  
Org.  
tFAW tFAW tRRD tRRD  
IDD7 Patterna  
Mb/s  
[ns]  
[CLK]  
[ns]  
[CLK] (Note this entire sequence is repeated.)  
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D A4  
RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D  
all  
all  
x4/x8  
x16  
40  
16  
10  
4
800  
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D  
D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D  
D D D D  
50  
37.5  
50  
20  
20  
27  
20  
30  
24  
10  
7.5  
10  
6
4
4
6
4
5
5
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D  
D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D  
D D D D  
all  
all  
all  
all  
all  
x4/x8  
x16  
1066  
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3  
RA3 D D D D D D D A4 RA4 D D D D A5 RA5 D D D D  
A6 RA6 D D D D A7 RA7 D D D D D D D  
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D  
D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D  
D D D D  
x4/x8  
x16  
30  
1333  
1600  
A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D  
D D D D D D D D D D D D A4 RA4 D D D A5 RA5 D D  
D A6 RA6 D D D A7 RA7 D D D D D D D D D D D D D  
45  
7.5  
6
A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D  
D D D D D D A4 RA4 D D D A5 RA5 D D D A6 RA6 D D  
D A7 RA7 D D D D D D D  
x4/x8  
30  
A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3  
RA3 D D D D D D D D D D D D A4 RA4 D D D D A5 RA5  
D D D D A6 RA6 D D D D A7 RA7 D D D D D D D D D  
D D D  
all  
x16  
40  
32  
7.5  
6
a. A0 = Activation of Bank 0; RA0 = Read with Auto-Precharge of Bank 0; D = Deselect  
Rev. 0.1 / Dec 2008  
45  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 10 — IDD Measurement Conditions for IDD5B  
Current  
IDD5B  
Name  
Burst Refresh Current  
Measurement Condition  
CKE  
HIGH  
External Clock  
on  
tCK  
tCKmin(IDD)  
tRC  
n.a.  
tRAS  
n.a.  
tRCD  
n.a.  
tRRD  
n.a.  
tRFC  
tRFCmin(IDD)  
CL  
n.a.  
AL  
n.a.  
CS  
HIGH btw. valid cmds  
Addr. and cmd Inputs  
Data inputs  
SWITCHING  
SWITCHING  
Output Buffer DQ,DQS / MR1 bit A12  
ODT / MR1 bits [A6, A2]  
Burst length  
off / 1  
disabled / [0,0]  
n.a.  
Active banks  
Refresh command every tRFC=tRFCmin  
Idle banks  
none  
n.a.  
Precharge Power Down Mode / Mode Register Bit  
Rev. 0.1 / Dec 2008  
46  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
Table 11 — IDD Measurement Conditions for IDD6 and IDD6ET  
Current  
IDD6  
IDD6ET  
Self-Refresh Current  
Normal Temperature Range  
TCASE = 0. 85 °C  
Self-Refresh Current  
Extended Temperature Range a  
TCASE = 0. 95 °C  
Name  
Measurement Condition  
Temperature  
TCASE = 85 °C  
TCASE = 95 °C  
Disabled / “0”  
Auto Self Refresh (ASR) /  
MR2 Bit A6  
Disabled / “0”  
Self Refresh Temperature  
Range (SRT) /  
Normal / “0”  
Extended / “1”  
MR2 Bit A7  
CKE  
LOW  
LOW  
External Clock  
OFF; CK and CK at LOW  
OFF; CK and CK at LOW  
tCK  
tRC  
n.a.  
n.a.  
n.a.  
n.a.  
tRAS  
tRCD  
tRRD  
CL  
n.a.  
n.a.  
n.a.  
n.a.  
n.a.  
n.a.  
n.a.  
n.a.  
AL  
n.a.  
n.a.  
CS  
FLOATING  
FLOATING  
Command Inputs  
(RAS, CAS, WE)  
FLOATING  
FLOATING  
Row, Column Addresses  
Bank Addresses  
Data I/O  
FLOATING  
FLOATING  
FLOATING  
FLOATING  
FLOATING  
FLOATING  
Output Buffer DQ,DQS  
/ MR1 bit A12  
off / 1  
off / 1  
ODT  
disabled  
/ [0,0]  
disabled  
/ [0,0]  
/ MR1 bits [A6, A2]  
Burst length  
Active banks  
Idle banks  
n.a.  
n.a.  
all during self-refresh actions  
all btw. Self-Refresh actions  
all during self-refresh actions  
all btw. Self-Refresh actions  
Precharge Power Down Mode  
/ MR0 bit A12  
n.a.  
n.a.  
a. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM  
devices support the following options or requirements referred to in this material.  
Rev. 0.1 / Dec 2008  
47  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
7. Electrical Characteristics and AC Timing  
7.1 Refresh Parameters by Device Density  
Parameter  
Symbol  
512Mb 1Gb 2Gb 4Gb 8Gb  
Units  
REF command to  
ACT or REF  
tRFC  
90  
110  
160  
300  
350  
ns  
command time  
0 ×C < TCASE < 85 ×C  
85 ×C < TCASE < 95 ×C  
7.8  
3.9  
7.8  
3.9  
7.8  
3.9  
7.8  
3.9  
7.8  
3.9  
ms  
ms  
Average periodic  
refresh interval  
tREFI  
7.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC  
for each corresponding bin  
DDR3 800 Speed Bin  
DDR3-800D  
5-5-5  
DDR3-800E  
6-6-6  
Unit Notes  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
max  
min  
max  
tAA  
12.5  
12.5  
12.5  
50  
20  
15  
15  
20  
ns  
ns  
ns  
ns  
ns  
Internal read command to first data  
ACT to internal read or write delay time  
PRE command period  
tRCD  
—
—
—
—
tRP  
15  
tRC  
—
52.5  
37.5  
—
ACT to ACT or REF command period  
ACT to PRE command period  
tRAS  
37.5  
9 * tREFI  
9 * tREFI  
tCK(AVG)  
tCK(AVG)  
2.5  
2.5  
3.3  
3.3  
Reserved  
3.3  
ns  
ns  
CL = 5  
CL = 6  
CWL = 5  
CWL = 5  
1)2)3)4)  
1)2)3)  
2.5  
5, 6  
6
5
nCK  
nCK  
Supported CL Settings  
Supported CWL Settings  
5
Rev. 0.1 / Dec 2008  
48  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
DDR3 1066 Speed Bin  
CL - nRCD - nRP  
DDR3-1066E  
DDR3-1066F  
7-7-7  
DDR3-1066G  
8-8-8  
Unit  
Note  
6-6-6  
max  
Parameter  
Symbol min  
min  
max  
min  
max  
Internal read command to  
first data  
tAA  
tRCD  
tRP  
11.25  
11.25  
11.25  
48.75  
20  
—
—
—
13.125  
20  
15  
20  
ns  
ns  
ns  
ns  
ns  
ACT to internal read or  
write delay time  
13.125  
13.125  
50.625  
—
—
—
15  
15  
—
—
—
PRE command period  
ACT to ACT or REF  
command period  
tRC  
52.5  
ACT to PRE command  
period  
tRAS  
37.5 9 * tREFI 37.5 9 * tREFI 37.5 9 * tREFI  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 5  
CL = 5  
2.5  
3.3  
Reserved  
Reserved  
Reserved  
Reserved  
ns 1)2)3)4)6)  
ns 4)  
CWL = 6  
Reserved  
CWL = 5  
2.5  
3.3  
2.5  
3.3  
2.5  
3.3  
ns 1)2)3)6)  
CL = 6  
tCK(AVG)  
CWL = 6  
1.875  
Reserved  
Reserved  
Reserved  
ns 1)2)3)4)  
< 2.5  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 5  
CL = 7  
Reserved  
Reserved  
Reserved  
Reserved  
ns 4)  
ns 1)2)3)4)  
ns 4)  
ns 1)2)3)  
nCK  
CWL = 6  
1.875  
< 2.5  
< 2.5  
1.875  
Reserved  
1.875 < 2.5  
< 2.5  
CWL = 5  
CL = 8  
Reserved  
CWL = 6  
1.875  
1.875  
< 2.5  
Supported CL Settings  
Supported CWL Settings  
5, 6, 7, 8  
5, 6  
6, 7, 8  
5, 6  
6, 8  
5, 6  
nCK  
Rev. 0.1 / Dec 2008  
49  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
DDR3-1333F  
(optional)  
DDR3-1333J  
(optional)  
DDR3 1333 Speed Bin  
CL - nRCD - nRP  
DDR3-1333G DDR3-1333H  
Unit  
Note  
7-7-7  
8-8-8  
9-9-9  
10-10-10  
Parameter  
Symbol min  
max  
min  
max  
min  
max  
min  
max  
Internal read  
command to first  
tAA  
10.5  
10.5  
10.5  
46.5  
20  
12  
12  
12  
48  
20  
13.5  
13.5  
13.5  
49.5  
36  
20  
15  
20  
—
—
—
ns  
ns  
ns  
ns  
ns  
ACT to internal read  
tRCD  
—
—
—
—
—
—
—
—
—
15  
15  
51  
36  
or write delay time  
tRP  
PRE command period  
ACT to ACT or REF  
command period  
tRC  
ACT to PRE  
command period  
9 *  
tREFI  
9 *  
tREFI  
9 *  
tREFI  
9 *  
tREFI  
tRAS  
36  
36  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 5  
CL = 5  
2.5  
3.3  
2.5  
3.3  
Reserved  
Reserved  
2.5 3.3  
Reserved  
Reserved  
2.5 3.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1,2,3,4,7  
4
CWL = 6, 7  
Reserved  
Reserved  
CWL = 5  
CL = 6 CWL = 6  
CWL = 7  
2.5  
3.3  
2.5  
3.3  
1,2,3,7  
1,2,3,4,7  
4
1.875 < 2.5  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
CWL = 5  
Reserved  
4
CL = 7 CWL = 6  
CWL = 7  
1.875 < 2.5 1.875 < 2.5  
1,2,3,4,7  
1,2,3,4  
4
1.5  
<1.875  
Reserved  
Reserved  
CWL = 5  
Reserved  
CL = 8 CWL = 6  
CWL = 7  
1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5  
1,2,3,7  
1,2,3,4  
4
1.5  
<1.875 1.5 <1.875  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
CWL = 5, 6  
CL = 9  
Reserved  
CWL = 7  
1.5  
<1.875 1.5 <1.875 1.5 <1.875  
Reserved Reserved  
<1.875 1.5 <1.875 1.5 <1.875  
1,2,3,4  
CWL = 5, 6  
Reserved  
1.5  
(Optional)  
ns  
ns  
4
1,2,3  
5
CL = 10  
CWL = 7  
tCK(AVG)  
1.5 <1.875  
(Optional)  
5, 6, 7, 8, 9  
5, 6, 7  
(Optional)  
6, 8, 9  
ns  
nCK  
Supported CL Settings  
Supported CWL Settings  
5, 6, 7, 8, 9  
5, 6, 7  
6, 8, 10  
5, 6, 7  
nCK  
5, 6, 7  
Rev. 0.1 / Dec 2008  
50  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
DDR3-1600G  
(optional)  
DDR3-1600K  
(optional)  
DDR3 1600 Speed Bin  
DDR3-1600H DDR3-1600J  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
8-8-8  
9-9-9  
10-10-10  
min max  
11-11-11  
min max  
Symbol min  
max  
min  
max  
Internal read command  
tAA  
10  
10  
10  
45  
20  
11.25  
11.25  
11.25  
46.25  
20  
12.5  
12.5  
12.5  
47.5  
20  
—
—
—
13.75  
13.75  
13.75  
48.75  
35  
20  
—
—
—
ns  
ns  
ns  
ns  
ns  
to first data  
ACT to internal read or  
write delay time  
tRCD  
—
—
—
—
—
—
tRP  
PRE command period  
ACT to ACT or REF  
command period  
tRC  
ACT to PRE command  
period  
9 *  
tREFI  
9 *  
tREFI  
9 *  
tREFI  
9 *  
tREFI  
tRAS  
35  
35  
35  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
tCK(AVG)  
CWL = 5  
CL = 5  
2.5  
3.3  
2.5  
3.3  
2.5  
3.3  
3.3  
Reserved  
Reserved  
2.5 3.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1,2,3,4,8  
4
CWL = 6, 7, 8  
Reserved  
Reserved  
Reserved  
CWL = 5  
2.5  
3.3  
2.5  
3.3  
2.5  
1,2,3,8  
1,2,3,4,8  
4
CL = 6  
CL = 7  
CWL = 6  
CWL = 7, 8  
CWL = 5  
CWL = 6  
CWL = 7  
CWL = 8  
CWL = 5  
CWL = 6  
CWL = 7  
CWL = 8  
CWL = 5, 6  
CWL = 7  
CWL = 8  
CWL = 5, 6  
CWL = 7  
CWL = 8  
1.875 < 2.5 1.875 < 2.5  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
4
1.875 < 2.5 1.875 < 2.5 1.875 < 2.5  
1,2,3,4,8  
1,2,3,4,8  
4
1.5 <1.875  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
4
1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5  
1,2,3,8  
1,2,3,4,8  
1,2,3,4  
4
CL = 8  
1.5 <1.875 1.5 <1.875  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
1.25  
< 1.5  
Reserved  
Reserved  
Reserved  
CL = 9  
1.5 <1.875 1.5 <1.875 1.5 <1.875  
1,2,3,4,8  
1,2,3,4  
4
1.25  
< 1.5  
1.25  
< 1.5  
Reserved  
Reserved  
Reserved  
Reserved  
CL = 10  
1.5 <1.875 1.5 <1.875 1.5 <1.875 1.5 <1.875  
1.25 < 1.5 1.25 < 1.5 1.25 < 1.5 Reserved  
1,2,3,8  
1,2,3,4  
Rev. 0.1 / Dec 2008  
51  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
tCK(AVG)  
CWL = 5, 6, 7  
CWL = 8  
Reserved  
1.25 < 1.5  
(Optional)  
5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 5, 6, 7, 8, 9, 10 6, 8, 10, 11  
5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8  
Reserved  
1.25 < 1.5  
(Optional)  
Reserved  
1.25 < 1.5  
(Optional)  
Reserved  
ns  
ns  
4
1,2,3  
5
CL = 11  
tCK(AVG)  
1.25  
< 1.5  
ns  
nCK  
nCK  
Supported CL Settings  
Supported CWL Settings  
*Speed Bin Table Notes*  
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);  
Notes:  
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection  
of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.  
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the  
DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC  
standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],  
rounding up to the next ‘Supported CL’.  
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CLSELECTED and round the resulting tCK(AVG) down to the  
next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to  
CLSELECTED.  
4. ‘Reserved’ settings are not allowed. User must program a different value.  
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory  
feature. Refer to supplier’s data sheet and SPD information if and how this setting is supported.  
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are  
not subject to Production Tests but verified by Design/Characterization.  
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are  
not subject to Production Tests but verified by Design/Characterization.  
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are  
not subject to Production Tests but verified by Design/Characterization.  
Rev. 0.1 / Dec 2008  
52  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
8. Dimm Outline Diagram  
8.1 164Mx64 - HMT164U6AFP(R)6C  
Front  
2.10±0.15  
Max R0.70  
30.00  
Min 1.45  
SPD  
4x3.00±0.10  
17.30  
2xφ2.50±0.10  
DETAIL-B  
DETAIL-A  
9.50  
2x2.30±0.10  
47.00  
71.00  
5.175  
128.95  
133.35  
Back  
Side  
Detail - A  
Detail - B  
3.18  
FULL R  
2.50  
0.80±0.05  
2.50±0.20  
1.00  
1.27  
± 0.10  
0.3~1.0  
1.50±0.10  
5.00  
Note) All dimensions are in millimeters unless otherwise stated.  
Rev. 0.1 / Dec 2008  
53  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
8.2 128Mx64 - HMT112U6AFP(R)8C  
Front  
2.10±0.15  
Min 1.45  
Max R0.70  
30.00  
SPD  
4x3.00±0.10  
17.30  
2xφ2.50±0.10  
DETAIL-B  
DETAIL-A  
9.50  
2x2.30±0.10  
47.00  
71.00  
5.175  
128.95  
133.35  
Back  
Side  
Detail - A  
Detail - B  
3.18  
FULL R  
2.50  
0.80±0.05  
2.50±0.20  
1.00  
1.27  
± 0.10  
0.3~1.0  
1.50±0.10  
5.00  
Note) All dimensions are in millimeters unless otherwise stated.  
Rev. 0.1 / Dec 2008  
54  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
8.3 128Mx72 - HMT112U7AFP(R)8C  
Front  
2.10±0.15  
Min 1.45  
SPD  
Max R0.70  
30.00  
4x3.00±0.10  
17.30  
2xφ2.50±0.10  
DETAIL-B  
DETAIL-A  
9.50  
2x2.30±0.10  
47.00  
71.00  
5.175  
128.95  
133.35  
Back  
Side  
Detail - A  
Detail - B  
3.18  
FULL R  
2.50  
0.80±0.05  
2.50±0.20  
1.00  
1.27  
± 0.10  
0.3~1.0  
1.50±0.10  
5.00  
Note) All dimensions are in millimeters unless otherwise stated.  
Rev. 0.1 / Dec 2008  
55  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
8.4 256Mx64 - HMT125U6AFP(R)8C  
Front  
2.10±0.15  
Min 1.45  
Max R0.70  
30.00  
SPD  
4x3.00±0.10  
17.30  
2xφ2.50±0.10  
DETAIL-B  
DETAIL-A  
9.50  
2x2.30±0.10  
47.00  
71.00  
5.175  
128.95  
133.35  
Back  
Side  
Detail - A  
Detail - B  
4.00  
FULL R  
2.50  
0.80±0.05  
2.50±0.20  
1.00  
1.27  
± 0.10  
0.3~1.0  
1.50±0.10  
5.00  
Note) All dimensions are in millimeters unless otherwise stated.  
Rev. 0.1 / Dec 2008  
56  
HMT164U6AFP(R)6C  
HMT112U6(7)AFP(R)8C  
HMT125U6(7)AFP(R)8C  
8.5 256Mx72 - HMT125U7AFP(R)8C  
Front  
2.10±0.15  
Min 1.45  
Max R0.70  
30.00  
SPD  
4x3.00±0.10  
17.30  
2xφ2.50±0.10  
DETAIL-B  
DETAIL-A  
9.50  
2x2.30±0.10  
47.00  
71.00  
5.175  
128.95  
133.35  
Back  
Side  
Detail - A  
Detail - B  
4.00  
FULL R  
2.50  
0.80±0.05  
2.50±0.20  
1.00  
1.27  
± 0.10  
0.3~1.0  
1.50±0.10  
5.00  
Note) All dimensions are in millimeters unless otherwise stated.  
Rev. 0.1 / Dec 2008  
57  

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