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HMT325U7EFR8C-PB [HYNIX]

DDR3 SDRAM Unbuffered DIMMs Based on 2Gb E-Die; 基于2Gb的E-模具DDR3 SDRAM非缓冲DIMM
HMT325U7EFR8C-PB
型号： HMT325U7EFR8C-PB
厂家： HYNIX SEMICONDUCTOR    HYNIX SEMICONDUCTOR
描述：

DDR3 SDRAM Unbuffered DIMMs Based on 2Gb E-Die
基于2Gb的E-模具DDR3 SDRAM非缓冲DIMM

动态存储器 双倍数据速率
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中文：  中文翻译
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240pin DDR3 SDRAM Unbuffered DIMM  
DDR3 SDRAM  
Unbuffered DIMMs  
Based on 2Gb E-Die  
HMT325U6EFR8C  
HMT325U7EFR8C  
HMT351U6EFR8C  
HMT351U7EFR8C  
*SK hynix reserves the right to change products or specifications without notice.  
Rev. 1.3 / Jul. 2013  
1
Revision History  
Revision No.  
History  
Draft Date  
May. 2012  
Jun. 2012  
Jul. 2012  
Remark  
0.1  
1.0  
Initial Release  
Latest JEDEC Spec  
Preliminary  
1.1  
1.2  
1.3  
Module Dimension Updated  
IDD5B spec modified  
Nov. 2012  
Jul. 2013  
Changed module maximum thickness  
to reflect the measured maximum  
Rev. 1.3 / Jul. 2013  
2
Description  
SK hynix Unbuffered DDR3 SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-Line  
Memory Modules) are low power, high-speed operation memory modules that use DDR3 SDRAM devices.  
These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as  
PCs and workstations.  
Feature  
• VDD=1.5V +/- 0.075V  
• VDDQ=1.5V +/- 0.075V  
• VDDSPD=3.0V to 3.6V  
• 8 internal banks  
• Data transfer rates: PC3-14900, PC3-12800, PC3-10600  
• Bi-directional Differential Data Strobe  
• 8 bit pre-fetch  
• Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4  
• Supports ECC error correction and detection  
• On Die Termination (ODT) supported  
• Temperature sensor with integrated SPD (Serial Presence Detect) EEPROM  
• This product is in Compliance with the RoHS directive  
Ordering Information  
# of  
ranks  
Part Number  
Density Organization  
Component Composition  
FDHS  
HMT325U6EFR8C-H9/PB/RD  
HMT325U7EFR8C-H9/PB/RD  
HMT351U6EFR8C-H9/PB/RD  
HMT351U7EFR8C-H9/PB/RD  
2GB  
2GB  
4GB  
4GB  
256Mx64  
256Mx72  
512Mx64  
512Mx72  
256Mx8(H5TQ2G83EFR)*8  
256Mx8(H5TQ2G83EFR)*9  
256Mx8(H5TQ2G83EFR)*16  
256Mx8(H5TQ2G83EFR)*18  
1
1
2
2
X
X
X
X
Rev. 1.3 / Jul. 2013  
3
Key Parameters  
CAS  
Latency  
(tCK)  
tCK  
(ns)  
tRCD  
(ns)  
tRP  
(ns)  
tRAS  
(ns)  
tRC  
(ns)  
MT/s  
Grade  
CL-tRCD-tRP  
DDR3-1066  
DDR3-1333  
1.875  
1.5  
7
9
13.125  
13.5  
13.125  
13.5  
37.5  
36  
50.625  
7-7-7  
9-9-9  
-G7  
-H9  
49.5  
(49.125)*  
(13.125)* (13.125)*  
13.75 13.75  
48.75  
(48.125)*  
DDR3-1600  
DDR3-1866  
-PB  
1.25  
1.07  
11  
13  
35  
34  
11-11-11  
13-13-13  
(13.125)* (13.125)*  
13.91 13.91  
47.91  
(47.125)*  
-RD  
(13.125)* (13.125)*  
*SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.  
Speed Grade  
Frequency [MHz]  
Grade  
Remark  
CL6  
CL7  
CL8  
CL9  
CL10  
CL11  
CL12  
CL13  
-G7  
-H9  
-PB  
-RD  
800  
800  
800  
800  
1066  
1066  
1066  
1066  
1066  
1066  
1066  
1066  
1333  
1333  
1333  
1333  
1333  
1333  
1600  
1600  
1866  
Address Table  
2GB(1Rx8)  
2GB(1Rx8)  
4GB(2Rx8)  
4GB(2Rx8)  
Refresh Method  
Row Address  
Column Address  
Bank Address  
Page Size  
8K/64ms  
A0-A14  
A0-A9  
8K/64ms  
A0-A14  
A0-A9  
8K/64ms  
A0-A14  
A0-A9  
8K/64ms  
A0-A14  
A0-A9  
BA0-BA2  
1KB  
BA0-BA2  
1KB  
BA0-BA2  
1KB  
BA0-BA2  
1KB  
Rev. 1.3 / Jul. 2013  
4
Pin Descriptions  
Pin Name  
Description  
SDRAM address bus  
SDRAM bank select  
Pin Name  
SCL  
Description  
I2C serial bus clock for EEPROM  
A0–A15  
I2C serial bus data line for EEPROM  
BA0–BA2  
SDA  
I2C slave address select for EEPROM  
SDRAM core power supply  
RAS  
CAS  
SDRAM row address strobe  
SDRAM column address strobe  
SDRAM write enable  
SA0–SA2  
VDD  
*
VDDQ*  
WE  
SDRAM I/O Driver power supply  
SDRAM I/O reference supply  
S0–S1  
DIMM Rank Select Lines  
VREFDQ  
SDRAM command/address reference  
supply  
CKE0–CKE1  
SDRAM clock enable lines  
VREFCA  
ODT0–ODT1  
DQ0–DQ63  
CB0–CB7  
On-die termination control lines  
DIMM memory data bus  
DIMM ECC check bits  
VSS  
VDDSPD  
NC  
Power supply return (ground)  
Serial EEPROM positive power supply  
Spare pins (no connect)  
SDRAM data strobes  
(positive line of differential pair)  
Memory bus analysis tools  
(unused on memory DIMMS)  
DQS0–DQS8  
DQS0–DQS8  
DM0–DM8  
CK0–CK1  
TEST  
SDRAM data strobes  
(negative line of differential pair)  
RESET  
Set DRAMs to Known State  
SDRAM I/O termination supply  
Reserved for future use  
-
SDRAM data masks/high data strobes  
(x8-based x72 DIMMs)  
VTT  
SDRAM clocks  
(positive line of differential pair)  
RSVD  
-
SDRAM clocks  
(negative line of differential pair)  
CK0–CK1  
*The VDD and VDDQ pins are tied common to a single power-plane on these designs  
Rev. 1.3 / Jul. 2013  
5
Input/Output Functional Descriptions  
Symbol  
Type  
Polarity  
Function  
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl  
CK0–CK1  
CK0–CK1  
Differential inputs are sampled on the crossing of positive edge of CK and negative  
SSTL  
crossing  
edge of CK. Output (read) data is reference to the crossing of CK and CK  
(Both directions of crossing).  
Activates the SDRAM CK signal when high and deactivates the CK signal  
CKE0–CKE1  
S0–S1  
SSTL  
SSTL  
Active High when low. By deactivating the clocks, CKE low initiates the Power Down  
mode, or the Self Refresh mode.  
Enables the associated SDRAM command decoder when low and disables  
the command decoder when high. When the command decoder is dis-  
abled, new commands are ignored but previous operations continue. This  
Active Low  
signal provides for external rank selection on systems with multiple ranks.  
RAS, CAS, WE  
ODT0–ODT1  
SSTL  
SSTL  
Active Low RAS, CAS, and WE (ALONG WITH S) define the command being entered.  
When high, termination resistance is enabled for all DQ, DQS, DQS and DM  
Active High  
pins, assuming this function is enabled in the Mode Register 1 (MR1).  
VREFDQ  
VREFCA  
Supply  
Supply  
Reference voltage for SSTL15 I/O inputs.  
Reference voltage for SSTL 15 command/address inputs.  
Power supply for the DDR3 SDRAM output buffers to provide improved  
noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ  
shares the same power plane as VDD pins.  
VDDQ  
Supply  
SSTL  
BA0–BA2  
—
—
Selects which SDRAM bank of eight is activated.  
During a Bank Activate command cycle, Address input defines the row  
address (RA0–RA15).  
During a Read or Write command cycle, Address input defines the column  
address. In addition to the column address, AP is used to invoke autopre-  
charge operation at the end of the burst read or write cycle. If AP is high,  
autoprecharge is selected and BA0, BA1, BA2 defines the bank to be pre-  
charged. If AP is low, autoprecharge is disabled. During a Precharge com-  
mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which  
bank(s) to precharge. If AP is high, all banks will be precharged regardless  
of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to  
define which bank to precharge. A12(BC) is sampled during READ and  
WRITE commands to determine if burst chop (on-the-fly) will be per-  
formed (HIGH, no burst chop; LOW, burst chopped).  
A0–A15  
SSTL  
DQ0–DQ63,  
CB0–CB7  
SSTL  
SSTL  
—
Data and Check Bit Input/Output pins.  
DM is an input mask signal for write data. Input data is masked when DM  
is sampled High coincident with that input data during a write access. DM  
is sampled on both edges of DQS. Although DM pins are input only, the DM  
loading matches the DQ and DQS loading.  
DM0–DM8  
VDD, VSS  
Active High  
Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD  
and VDDQ pins are tied to VDD/VDDQ planes on these modules.  
Supply  
Rev. 1.3 / Jul. 2013  
6
Symbol  
Type  
Polarity  
Function  
Data strobe for input and output data.  
DQS0–DQS8  
DQS0–DQS8  
Differential  
crossing  
SSTL  
These signals are tied at the system planar to either VSS or VDDSPD to con-  
figure the serial SPD EEPROM address range.  
SA0–SA2  
—
This bidirectional pin is used to transfer data into or out of the SPD  
EEPROM. An external resistor may be connected from the SDA bus line to  
VDDSPD to act as a pullup on the system board.  
SDA  
—
This signal is used to clock data into and out of the SPD EEPROM. An  
external resistor may be connected from the SCL bus time to VDDSPD to act  
as a pullup on the system board.  
SCL  
—
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ  
power plane. EEPROM supply is operable from 3.0V to 3.6V.  
VDDSPD  
Supply  
Rev. 1.3 / Jul. 2013  
7
Pin Assignments  
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
1
2
VREFDQ  
VSS  
VREFDQ 121  
V
SS  
V
SS  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
A2  
VDD  
CK1  
CK1  
VDD  
VDD  
VREFCA  
NC  
A2  
181  
182  
183  
184  
185  
186  
A1  
VDD  
VDD  
CK0  
CK0  
VDD  
NC  
A1  
VDD  
VDD  
CK0  
CK0  
VDD  
EVENT  
A0  
V
SS  
122  
123  
124  
125  
DQ4  
DQ5  
DQ4  
DQ5  
VDD  
CK1  
CK1  
VDD  
VDD  
3
DQ0  
DQ0  
DQ1  
4
DQ1  
VSS  
VSS  
5
VSS  
VSS  
DM0  
NC  
DM0  
NC  
6
DQS0  
DQS0  
DQS0 126  
DQS0 127  
7
VSS  
VSS  
VREFCA 187  
8
VSS  
V
SS  
128  
129  
130  
DQ6  
DQ7  
DQ6  
DQ7  
NC  
VDD  
A10  
188  
189  
190  
A0  
9
DQ2  
DQ3  
DQ2  
DQ3  
VDD  
A10  
VDD  
VDD  
BA12  
VDD  
BA12  
VDD  
10  
VSS  
VSS  
BA02  
VDD  
WE  
BA02  
VDD  
WE  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VSS  
V
SS  
131  
132  
133  
134  
DQ12  
DQ13  
DQ12  
DQ13  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
209  
210  
DQ8  
DQ9  
DQ8  
DQ9  
RAS  
S0  
RAS  
S0  
VSS  
VSS  
VSS  
VSS  
DM1  
NC  
DM1  
NC  
CAS  
VDD  
S1  
CAS  
VDD  
S1  
VDD  
ODT0  
A13  
VDD  
NC  
VDD  
ODT0  
A13  
VDD  
NC  
DQS1  
DQS1  
DQS1 135  
DQS1 136  
VSS  
VSS  
VSS  
VSS  
137  
DQ14  
DQ15  
DQ14  
DQ15  
ODT1  
VDD  
NC  
ODT1  
VDD  
NC  
DQ10  
DQ11  
DQ10 138  
DQ11 139  
VSS  
VSS  
VSS  
VSS  
VSS  
V
SS  
140  
141  
DQ20  
DQ21  
DQ20  
DQ21  
VSS  
VSS  
DQ36  
DQ37  
DQ36  
DQ37  
DQ16  
DQ17  
DQ16  
DQ32  
DQ33  
DQ32  
DQ33  
DQ17 142  
143  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
DM2  
NC  
DM2  
NC  
VSS  
VSS  
DM4  
NC  
DM4  
NC  
DQS2  
DQS2  
DQS2 144  
DQS2 145  
DQS4  
DQS4  
DQS4  
DQS4  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
146  
DQ22  
DQ23  
DQ22  
DQ23  
VSS  
VSS  
DQ38  
DQ39  
DQ38  
DQ39  
DQ18  
DQ19  
DQ18 147  
DQ19 148  
DQ34  
DQ35  
DQ34  
DQ35  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
149  
DQ28  
DQ29  
DQ28  
DQ29  
VSS  
VSS  
DQ44  
DQ45  
DQ44  
DQ45  
DQ24  
DQ24 150  
DQ40  
DQ40  
NC = No Connect; RFU = Reserved Future Use  
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.  
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.  
Rev. 1.3 / Jul. 2013  
8
Front Side(left 1–60) Back Side(right 121–180) Front Side(left 61–120) Back Side(right 181–240)  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
Pin  
#
x64  
Non-ECC  
x72  
ECC  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
DQ25  
DQ25 151  
152  
V
SS  
V
SS  
91  
92  
DQ41  
DQ41  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
V
SS  
VSS  
VSS  
VSS  
DM3  
NC  
DM3  
NC  
VSS  
VSS  
DM5  
NC  
DM5  
NC  
DQS3  
DQS3  
DQS3 153  
DQS3 154  
93  
DQS5  
DQS5  
DQS5  
DQS5  
VSS  
VSS  
94  
VSS  
VSS  
VSS  
VSS  
155  
DQ30  
DQ31  
DQ30  
DQ31  
95  
VSS  
VSS  
DQ46  
DQ47  
DQ46  
DQ47  
DQ26  
DQ27  
DQ26 156  
DQ27 157  
96  
DQ42  
DQ43  
DQ42  
DQ43  
VSS  
VSS  
97  
VSS  
VSS  
VSS  
V
SS  
158  
159  
160  
161  
NC  
NC  
CB4  
CB5  
98  
VSS  
VSS  
DQ52  
DQ53  
DQ52  
DQ53  
NC  
NC  
CB0  
CB1  
99  
DQ48  
DQ49  
DQ48  
DQ49  
VSS  
VSS  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
VSS  
VSS  
VSS  
VSS  
DM8  
NC  
DM8  
NC  
VSS  
VSS  
DM6  
NC  
DM6  
NC  
NC  
NC  
DQS8 162  
DQS8 163  
DQS6  
DQS6  
DQS6  
DQS6  
VSS  
VSS  
VSS  
VSS  
VSS  
V
SS  
164  
165  
166  
167  
168  
NC  
NC  
CB6  
CB7  
VSS  
VSS  
DQ54  
DQ55  
DQ54  
DQ55  
NC  
NC  
CB2  
CB3  
DQ50  
DQ51  
DQ50  
DQ51  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
NC  
NC  
VSS  
VSS  
DQ60  
DQ61  
DQ60  
DQ61  
NC  
KEY  
NC  
Reset  
Reset  
DQ56  
DQ57  
DQ56  
DQ57  
KEY  
169 CKE1/NC  
VSS  
VSS  
49  
50  
51  
52  
53  
54  
55  
56  
NC  
CKE0  
VDD  
BA2  
NC  
NC  
CKE0  
VDD  
BA2  
NC  
CKE1/NC  
VDD  
NC  
VSS  
VSS  
DM7  
NC  
DM7  
NC  
170  
171  
172  
173  
174  
175  
176  
VDD  
NC  
DQS7  
DQS7  
DQS7  
DQS7  
VSS  
VSS  
A14  
VDD  
A12  
A9  
A14  
VDD  
A12  
A9  
VSS  
VSS  
DQ62  
DQ63  
DQ62  
DQ63  
DQ58  
DQ59  
DQ58  
DQ59  
VDD  
All  
VDD  
All  
VSS  
VSS  
VSS  
VSS  
VDDSPD  
SA1  
VDDSPD  
SA1  
A72  
VDD  
A72  
VDD  
VDD  
VDD  
SA0  
SCL  
SA2  
VTT  
SA0  
SCL  
SA2  
VTT  
A82  
A62  
VDD  
A82  
57  
58  
59  
60  
177  
178  
179  
180  
118  
119  
120  
238  
239  
240  
SDA  
SDA  
A52  
A42  
VDD  
A52  
A42  
VDD  
A62  
VDD  
VSS  
VSS  
VTT  
VTT  
A32  
A32  
NC = No Connect; RFU = Reserved Future Use  
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.  
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored.  
Rev. 1.3 / Jul. 2013  
9
On DIMM Thermal Sensor  
The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal  
sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.  
Connection of Thermal Sensor  
EVENT  
SCL  
SDA  
SA0  
SA1  
SA2  
EVENT  
SCL  
SPD with  
Integrated  
TS  
SA0  
SA1  
SA2  
SDA  
Temperature-to-Digital Conversion Performance  
Parameter  
Temperature Sensor Accuracy (Grade B)  
Resolution  
Condition  
Min  
Typ  
Max  
Unit  
Active Range,  
75°C < TA < 95°C  
-
± 0.5  
± 1.0  
± 1.0  
°C  
Monitor Range,  
40°C < TA < 125°C  
-
-
± 2.0  
± 3.0  
°C  
-20°C < TA < 125°C  
± 2.0  
°C  
°C  
0.25  
Rev. 1.3 / Jul. 2013  
10  
Functional Block Diagram  
2GB, 256Mx64 Module(1Rank of x8)  
S0  
DQS0  
DQS4  
DQS4  
DM4  
DQS0  
DM0  
DM CS  
DQS DQS  
DM CS DQS DQS  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D4  
D0  
ZQ  
ZQ  
DQS5  
DQS5  
DM5  
DQS1  
DQS1  
DM1  
DQS  
DQS  
DM CS  
DM CS DQS DQS  
I/O 0  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ8  
DQ9  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D5  
D1  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
ZQ  
ZQ  
DQS6  
DQS6  
DM6  
DQS2  
DQS2  
DM2  
DQS DQS  
DM CS  
DM CS DQS DQS  
I/O 0  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
D6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D2  
ZQ  
ZQ  
DQS7  
DQS7  
DM7  
DQS3  
DQS3  
DM3  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D7  
D3  
ZQ  
ZQ  
Serial PD  
Notes:  
SCL  
1. DQ-to-I/O wiring is shown as recom-  
mended but may be changed.  
2. DQ/DQS/DQS/ODT/DM/CKE/S relation-  
ships must be maintained as shown.  
3. DQ,DM,DQS/DQS resistors;Refer to  
associated topology diagram.  
SDA  
WP  
A0  
A1  
A2  
BA0–BA2  
BA0–BA2: SDRAMs D0–D7  
SA0 SA1 SA2  
A0–A15  
RAS  
A0–A15: SDRAMs D0–D7  
RAS: SDRAMs D0–D7  
CAS: SDRAMs D0–D7  
CKE: SDRAMs D0–D7  
4. Refer to the appropriate clock wiring  
topology under the DIMM wiring details  
section of this document.  
5. Refer to Section 3.1 of this document for  
details on address mirroring.  
CAS  
V
DDSPD  
SPD  
CKE0  
V
DD/VDD  
Q
D0–D7  
WE: SDRAMs D0–D7  
ODT: SDRAMs D0–D7  
WE  
ODT0  
CK0  
VREFDQ  
6. For each DRAM, a unique ZQ resistor is  
connected to ground.The ZQ resistor is  
240ohm+-1%  
D0–D7  
D0–D7  
CK: SDRAMs D0–D7  
CK: SDRAMs D0–D7  
VSS  
CK0  
D0–D7  
VREFCA  
7. One SPD exists per module.  
RESET  
RESET: SDRAMs D0-D7  
Rev. 1.3 / Jul. 2013  
11  
2GB, 256Mx72 Module(1Rank of x8)  
S0  
DQS0  
DQS0  
DM0  
DQS4  
DQS4  
DM4  
DM CS  
I/O 0  
DQS DQS  
DQS  
DQS  
CS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D4  
D0  
ZQ  
ZQ  
DQS5  
DQS5  
DM5  
DQS1  
DQS1  
DM1  
DQS  
DQS  
DM CS  
CS DQS DQS  
D1  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ8  
DQ9  
D5  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
ZQ  
ZQ  
DQS6  
DQS6  
DM6  
DQS2  
DQS2  
DM2  
DQS DQS  
DM CS  
DQS  
CS DQS  
D2  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
D6  
ZQ  
ZQ  
DQS7  
DQS7  
DM7  
DQS3  
DQS3  
DM3  
DM CS DQS DQS  
I/O 0  
DQS  
CS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D7  
D3  
ZQ  
ZQ  
DQS8  
DQS8  
DM8  
SPD(TS integrated)  
EVENT  
DQS  
DQS  
DM  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
CS  
Notes:  
SCL  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
1. DQ-to-I/O wiring is shown as recom-  
mended but may be changed.  
2. DQ/DQS/DQS/ODT/DM/CKE/S rela-  
tionships must be maintained as  
shown.  
D8  
SDA  
EVENT  
A0  
A1  
A2  
SA0 SA1  
SA2  
ZQ  
3. DQ,CB,DM,DQS/DQS resistors;Refer  
to associated topology diagram.  
4. Refer to the appropriate clock wiring  
topology under the DIMM wiring  
details section of this document.  
5. For each DRAM, a unique ZQ resistor  
is connected to ground.The ZQ resis-  
tor is 240ohm+-1%  
BA0–BA2  
BA0–BA2: SDRAMs D0–D8  
A0–A15: SDRAMs D0–D8  
RAS: SDRAMs D0–D8  
A0–A15  
RAS  
VDDSPD  
SPD  
VDD/VDDQ  
D0–D8  
CAS  
CKE0  
WE  
ODT0  
CK0  
CK0  
CAS: SDRAMs D0–D8  
CKE: SDRAMs D0–D8  
WE: SDRAMs D0–D8  
ODT: SDRAMs D0–D8  
CK: SDRAMs D0–D8  
CK: SDRAMs D0–D8  
VREFDQ  
VSS  
D0–D8  
D0–D8  
6. One SPD exists per module.  
VREFCA  
D0–D8  
RESET  
RESET: SDRAMs D0-D8  
Rev. 1.3 / Jul. 2013  
12  
4GB, 512Mx64 Module(2Rank of x8)  
S1  
S0  
DQS0  
DQS0  
DM0  
DQS4  
DQS4  
DM4  
DM CS DQS DQS  
DM CS DQS DQS  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D12  
D4  
D8  
D0  
ZQ  
ZQ  
ZQ  
ZQ  
DQS1  
DQS1  
DM1  
DQS5  
DQS5  
DM5  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ8  
DQ9  
DQ10  
DQ11  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D13  
D5  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D9  
D1  
DQ12  
DQ13  
DQ14  
DQ15  
ZQ  
ZQ  
ZQ  
ZQ  
DQS6  
DQS6  
DM6  
DQS2  
DQS2  
DM2  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D14  
D6  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D10  
D2  
ZQ  
ZQ  
ZQ  
ZQ  
DQS3  
DQS3  
DM3  
DQS7  
DQS7  
DM7  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D15  
D7  
D11  
D3  
ZQ  
Serial PD  
ZQ  
ZQ  
ZQ  
Notes:  
BA0–BA2  
A0–A15  
CKE1  
CKE0  
RAS  
BA0–BA2: SDRAMs D0–D15  
A0-A15: SDRAMs D0–D15  
CKE: SDRAMs D8–D15  
CKE: SDRAMs D0–D7  
RAS: SDRAMs D0–D15  
CAS: SDRAMs D0–D15  
WE: SDRAMs D0–D15  
SCL  
1. DQ-to-I/O wiring is shown as recom-  
mended but may be changed.  
2. DQ/DQS/DQS/ODT/DM/CKE/S relation-  
ships must be maintained as shown.  
3. DQ,DM,DQS,DQS resistors;Refer to  
associated topology diagram.  
SDA  
WP  
A0  
A1  
A2  
SA0 SA1 SA2  
CAS  
VDDSPD  
SPD  
WE  
4. Refer to Section 3.1 of this document for  
details on address mirroring.  
VDD/VDDQ  
D0–D15  
ODT0  
ODT1  
CK0  
ODT: SDRAMs D0–D7  
ODT: SDRAMs D8–D15  
CK: SDRAMs D0–D7  
CK: SDRAMs D0–D7  
CK: SDRAMs D8–D15  
CK: SDRAMs D8–D15  
VREFDQ  
VSS  
5. For each DRAM, a unique ZQ resistor is  
connected to ground.The ZQ resistor is  
240ohm+-1%  
D0–D15  
D0–D15  
CK0  
VREFCA  
6. One SPD exists per module.  
CK1  
D0–D15  
CK1  
RESET  
RESET: SDRAMs D0-D3  
Rev. 1.3 / Jul. 2013  
13  
4GB, 512Mx72 Module(2Rank of x8)  
S1  
S0  
DQS0  
DQS0  
DM0  
DQS4  
DQS4  
DM4  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
D13  
D4  
D9  
D0  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
ZQ  
ZQ  
ZQ  
ZQ  
DQS1  
DQS1  
DM1  
DQS5  
DQS5  
DM5  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ8  
DQ9  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D14  
D5  
I/O 1  
D10  
D1  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
ZQ  
ZQ  
ZQ  
ZQ  
DQS6  
DQS6  
DM6  
DQS2  
DQS2  
DM2  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D15  
D2  
D11  
D6  
ZQ  
ZQ  
ZQ  
ZQ  
DQS3  
DQS3  
DM3  
DQS7  
DQS7  
DM7  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D16  
D7  
D12  
D3  
ZQ  
ZQ  
ZQ  
ZQ  
VDDSPD  
SPD  
DQS8  
DQS8  
DM8  
SPD(TS integrated)  
VDD/VDDQ  
D0–D17  
D0–D17  
SCL  
V
REFDQ  
DM CS DQS DQS  
I/O 0  
DM CS DQS DQS  
I/O 0  
SDA  
EVENT  
EVENT  
Vss  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
D0–D17  
D0–D17  
A0  
A1  
A2  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D17  
D8  
VREFCA  
SA0 SA1  
SA2  
Notes:  
1. DQ-to-I/O wiring is shown as recom-  
mended but may be changed.  
2. DQ/DQS/DQS/ODT/DM/CKE/S relation-  
ships must be maintained as shown.  
3. DQ,CB,DM/DQS/DQS resistors;Refer to  
associated topology diagram.  
ZQ  
ZQ  
BA0–BA2  
A0–A15  
CKE0  
CKE1  
RAS  
BA0-BA2: SDRAMs D0–D17  
A0-A15: SDRAMs D0–D17  
CKE: SDRAMs D0–D8  
CKE: SDRAMs D9–D17  
RAS: SDRAMs D0–D17  
CAS: SDRAMs D0–D17  
4. Refer to Section 3.1 of this document for  
details on address mirroring.  
ODT0  
ODT: SDRAMs D0–D8  
ODT: SDRAMs D9–D17  
CK: SDRAMs D0–D8  
CK: SDRAMs D0–D8  
CK: SDRAMs D9–D17  
CK: SDRAMs D9–D17  
RESET: SDRAMs D0-D17  
ODT1  
CK0  
CK0  
CK1  
CK1  
5. For each DRAM, a unique ZQ resistor is  
connected to ground.The ZQ resistor is  
240ohm+-1%  
6. One SPD exists per module.  
CAS  
WE  
WE: SDRAMs D0–D17  
RESET  
Rev. 1.3 / Jul. 2013  
14  
Absolute Maximum Ratings  
Absolute Maximum DC Ratings  
Absolute Maximum DC Ratings  
Symbol  
Parameter  
Voltage on VDD pin relative to Vss  
Voltage on VDDQ pin relative to Vss  
Voltage on any pin relative to Vss  
Storage Temperature  
Rating  
Units  
Notes  
VDD  
- 0.4 V ~ 1.80 V  
V
1, 3  
VDDQ  
VIN, VOUT  
TSTG  
- 0.4 V ~ 1.80 V  
- 0.4 V ~ 1.80 V  
-55 to +100  
V
1, 3  
1
V
oC  
1, 2  
Notes:  
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional operation of the device at these or any other conditions above  
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-  
ing conditions for extended periods may affect reliability.  
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement  
conditions, please refer to JESD51-2 standard.  
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than  
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.  
DRAM Component Operating Temperature Range  
Temperature Range  
Symbol  
Parameter  
Rating  
Units  
Notes  
0 to 85  
oC  
1,2  
Normal Operating Temperature Range  
Extended Temperature Range  
TOPER  
85 to 95  
oC  
1,3  
Notes:  
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-  
surement conditions, please refer to the JEDEC document JESD51-2.  
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-  
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.  
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC  
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:  
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It  
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.  
Please refer to the DIMM SPD for option availability  
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use  
the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b)  
or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). DDR3 SDRAMs support Auto  
Self-Refresh and Extended Temperature Range and please refer to component datasheet and/or the DIMM  
SPD for tREFI requirements in the Extended Temperature Range.  
Rev. 1.3 / Jul. 2013  
15  
AC & DC Operating Conditions  
Recommended DC Operating Conditions  
Recommended DC Operating Conditions  
Rating  
Symbol  
Parameter  
Units Notes  
Min.  
Typ.  
Max.  
VDD  
1.425  
1.500  
1.575  
V
V
1,2  
1,2  
Supply Voltage  
Supply Voltage for Output  
VDDQ  
1.425  
1.500  
1.575  
Notes:  
1. Under all conditions, VDDQ must be less than or equal to VDD.  
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.  
Rev. 1.3 / Jul. 2013  
16  
AC & DC Input Measurement Levels  
AC and DC Logic Input Levels for Single-Ended Signals  
AC and DC Input Levels for Single-Ended Command and Address Signals  
Single Ended AC and DC Input Levels for Command and ADDress  
DDR3-800/1066/1333/1600  
DDR3-1866  
Symbol  
Parameter  
Unit  
Notes  
Min  
Max  
Min  
Max  
VIH.CA(DC100)  
VIL.CA(DC100)  
VIH.CA(AC175)  
VIL.CA(AC175)  
VIH.CA(AC150)  
VIL.CA(AC150)  
VIH.CA(AC135)  
VIL.CA(AC135)  
VIH.CA(AC125)  
VIL.CA(AC125)  
DC input logic high  
DC input logic low  
AC input logic high  
AC input logic low  
AC Input logic high  
AC input logic low  
AC input logic high  
AC input logic low  
AC Input logic high  
AC input logic low  
Vref + 0.100  
VDD  
Vref + 0.100  
VDD  
V
V
1, 5  
VSS  
Vref - 0.100  
VSS  
Vref - 0.100  
1, 6  
Vref + 0.175  
Note2  
-
-
V
1, 2, 7  
1, 2, 8  
1, 2, 7  
1, 2, 8  
1, 2, 7  
1, 2, 8  
1, 2, 7  
1, 2, 8  
Note2  
Vref - 0.175  
-
-
V
Vref + 0.150  
Note2  
-
-
V
Note2  
Vref - 0.150  
-
-
V
-
-
-
-
-
-
-
-
Vref + 0.135  
Note2  
Note2  
V
Vref - 0.135  
Note2  
V
Vref + 0.125  
Note2  
mV  
mV  
Vref - 0.125  
Reference Voltage for  
ADD, CMD inputs  
VRefCA(DC  
)
0.49 * VDD  
0.51 * VDD  
0.49 * VDD  
0.51 * VDD  
V
3, 4  
Notes:  
1. For input only pins except RESET, Vref = VrefCA (DC).  
2. Refer to "Overshoot and Undershoot Specifications" on page 30.  
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for  
ence: approx. +/- 15 mV).  
refer-  
4. For reference: approx. VDD/2 +/- 15 mV.  
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)  
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)  
7. VIH(ac) is used as simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125);  
VIH.CA(AC175) value is used when Vref + 0.175V is referenced, VIH.CA(AC150) value is used when Vref +  
0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value  
is used when Vref + 0.125V is referenced.  
8. VIL(ac) is used as simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135), and VIL.CA(AC125);  
VIL.CA(AC175) value is used when Vref - 0.175V is referenced, VIL.CA(AC150) value is used when Vref - 0.150V is  
referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and VIL.CA(AC125) value is used  
when Vref - 0.125V is referenced.  
Rev. 1.3 / Jul. 2013  
17  
AC and DC Input Levels for Single-Ended Signals  
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table  
below. DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 51 in “ DDR3 Device  
Operation”) as well as derating tables in Table 46 of “DDR3 Device Operation” depending on Vih/Vil AC lev-  
els.  
Single Ended AC and DC Input Levels for DQ and DM  
DDR3-800/1066  
DDR3-1333/1600  
DDR3-1866  
Symbol  
Parameter  
Unit Notes  
Min  
VIH.DQ(DC100) DC input logic high Vref + 0.100  
VIL.DQ(DC100) DC input logic low VSS  
Max  
Min  
Max  
Min  
Max  
VDD  
Vref + 0.100  
VDD  
Vref + 0.100  
VDD  
V
V
V
V
V
V
1, 5  
Vref - 0.100  
VSS  
Vref - 0.100  
VSS  
Vref - 0.100  
1, 6  
VIH.DQ(AC175) AC input logic high Vref + 0.175 Note2  
VIL.DQ(AC175) AC input logic low Note2 Vref - 0.175  
-
-
-
-
-
-
-
-
1, 2, 7  
1, 2, 8  
1, 2, 7  
1, 2, 8  
VIH.DQ(AC150) AC Input logic high Vref + 0.150 Note2 Vref + 0.150 Note2 Vref + 0.150 Note2  
VIL.DQ(AC150) AC input logic low  
VIH.CA(AC135) AC input logic high  
VIL.CA(AC135) AC input logic low  
Reference Voltage  
Note2  
Vref - 0.150  
Note2  
Vref - 0.150  
Note2  
Vref + 0.135 Note2  
Note2 Vref - 0.135 mV 1, 2, 8  
Vref - 0.150  
-
-
-
-
-
-
-
-
mV 1, 2, 7  
VRefDQ(DC  
)
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD  
V
3, 4  
for DQ, DM inputs  
Notes:  
1. Vref = VrefDQ (DC).  
2. Refer to "Overshoot and Undershoot Specifications" on page 30.  
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference:  
approx. +/- 15 mV).  
4. For reference: approx. VDD/2 +/- 15 mV.  
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)  
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)  
7. VIH(ac) is used as simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175)  
value is used when Vref + 0.175V is referenced, VIH.DQ(AC150) value is used when Vref + 0.150V is referenced,  
and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.  
8. VIL(ac) is used as simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175)  
value is used when Vref - 0.175V is referenced, VIL.DQ(AC150) value is used when Vref - 0.150V is referenced,  
and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.  
Rev. 1.3 / Jul. 2013  
18  
Vref Tolerances  
The dc-tolerance limits and ac-noise limits for the reference voltages  
and V  
are illustrated in  
RefDQ  
VRefCA  
figure below. It shows a valid reference voltage V (t) as a function of time. (V stands for V and  
RefCA  
Ref  
Ref  
V
likewise).  
RefDQ  
V
(DC) is the linear average of V (t) over a very long period of time (e.g. 1 sec). This average has to  
Ref  
Ref  
meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 25. Further-  
more V (t) may temporarily deviate from V  
by no more than +/- 1% VDD.  
Ref  
Ref (DC)  
voltage  
VDD  
V
(t)  
Ref  
V
ac-noise  
Ref  
V
Ref(DC)max  
V
Ref(DC)  
VDD/2  
V
Ref(DC)min  
VSS  
time  
Illustration of V  
tolerance and V  
ac-noise limits  
Ref  
Ref(DC)  
The voltage levels for setup and hold time measurements V  
, V  
, V  
, and V  
are depen-  
IL(DC)  
IH(AC)  
IH(DC)  
IL(AC)  
dent on V  
.
Ref  
“V ” shall be understood as V  
, as defined in figure above.  
Ref  
Ref(DC)  
This clarifies that dc-variations of V affect the absolute voltage a signal has to reach to achieve a valid  
Ref  
high or low level and therefore the time to which setup and hold is measured. System timing and voltage  
budgets need to account for V  
deviations from the optimum position within the data-eye of the input  
Ref(DC)  
signals.  
This also clarifies that the DRAM setup/hold specification and derating values need to include time and  
voltage associated with V ac-noise. Timing and voltage effects due to ac-noise on V up to the speci-  
Ref  
Ref  
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.  
Rev. 1.3 / Jul. 2013  
19  
AC and DC Logic Input Levels for Differential Signals  
Differential signal definition  
t
DVAC  
VIL.DIFF.AC.MIN  
VIL.DIFF.MIN  
0
half cycle  
V
IL.DIFF.MAX  
VIL.DIFF.AC.MAX  
t
DVAC  
time  
Definition of differential ac-swing and “time above ac-level” t  
DVAC  
Rev. 1.3 / Jul. 2013  
20  
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)  
Differential AC and DC Input Levels  
DDR3-800, 1066, 1333, 1600, 1866  
Symbol  
Parameter  
Unit Notes  
Min  
Max  
VIHdiff  
VILdiff  
Differential input high  
Differential input logic low  
Differential input high ac  
Differential input low ac  
+ 0.180  
Note 3  
Note 3  
- 0.180  
V
V
V
V
1
1
2
2
VIHdiff (ac)  
VILdiff (ac)  
2 x (VIH (ac) - Vref)  
Note 3  
Note 3  
2 x (VIL (ac) - Vref)  
Notes:  
1. Used to define a differential signal slew-rate.  
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL  
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level  
applies also here.  
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU  
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-  
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 30.  
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS  
DDR3-800/1066/1333/1600  
tDVAC [ps]  
DDR3-1866  
Slew  
Rate  
[V/ns]  
tDVAC [ps]  
@ VIH/Ldiff (ac) @ VIH/Ldiff (ac)  
= 350mV = 300mV  
tDVAC [ps]  
@ VIH/Ldiff (ac)  
= 270mV  
(DQS-DQS)only  
(Optional)  
tDVAC [ps]  
@ VIH/Ldiff (ac)| @ VIH/Ldiff (ac)|  
= 300mV = (CK-CK)only  
tDVAC [ps]  
min  
max  
min  
max  
min  
214  
214  
191  
146  
131  
113  
88  
max  
min  
max  
min  
139  
139  
118  
77  
max  
> 4.0  
4.0  
75  
57  
50  
38  
34  
29  
22  
13  
0
-
-
-
-
-
-
-
-
-
-
175  
170  
167  
119  
102  
81  
-
-
-
-
-
-
134  
134  
112  
67  
-
-
-
-
-
-
3.0  
2.0  
1.8  
-
-
-
-
-
-
-
-
-
-
-
-
52  
-
-
-
-
-
-
63  
-
-
-
-
-
-
1.6  
33  
45  
1.4  
54  
9
23  
1.2  
19  
56  
note  
note  
note  
note  
note  
note  
1.0  
note  
note  
11  
< 1.0  
0
note  
note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling  
input differential signal shall become equal to or less than VIL(ac) level.  
Rev. 1.3 / Jul. 2013  
21  
Single-ended requirements for differential signals  
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) also  
has to comply with certain requirements for single-ended signals.  
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH  
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.  
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)  
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.  
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if  
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the single-  
ended signals CK and CK.  
VDD or VDDQ  
VSEHmin  
VSEH  
VDD/2 or VDDQ/2  
CK or DQS  
VSELmax  
VSEL  
VSS or VSSQ  
time  
Single-ended requirements for differential signals.  
Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo-  
nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the  
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended  
components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing,  
but adds a restriction on the common mode characteristics of these signals.  
Rev. 1.3 / Jul. 2013  
22  
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU  
DDR3-800, 1066, 1333, 1600, 1866  
Parameter  
Unit Notes  
Min  
Max  
Single-ended high level for strobes  
Single-ended high level for Ck, CK  
Single-ended low level for strobes  
Single-ended low level for CK, CK  
(VDD / 2) + 0.175  
(VDD /2) + 0.175  
Note 3  
Note 3  
V
V
V
V
1,2  
1,2  
1,2  
1,2  
VSEH  
VSEL  
Note 3  
(VDD / 2) - 0.175  
(VDD / 2) - 0.175  
Note 3  
Notes:  
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)  
of DQs.  
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced  
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.  
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU  
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-  
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 30.  
Rev. 1.3 / Jul. 2013  
23  
Differential Input Cross Point Voltage  
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and  
strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the  
requirements in table below. The differential input cross point voltage VIX is measured from the actual  
cross point of true and complement signals to the midlevel between of VDD and VSS  
Vix Definition  
Cross point voltage for differential input signals (CK, DQS)  
DDR3-800, 1066, 1333, 1600, 1866  
Parameter  
Unit Notes  
Min  
Max  
-150  
-175  
150  
175  
mV  
mV  
2
1
Differential Input Cross Point Voltage  
relative to VDD/2 for CK, CK  
VIX(CK)  
Differential Input Cross Point Voltage  
relative to VDD/2 for DQS, DQS  
VIX(DQS)  
-150  
150  
mV  
2
Notes:  
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic  
with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -  
CK is larger than 3 V/ns.  
2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.  
(VDD/2) + Vix (Min) - VSEL 25mV   
VSEH - ((VDD/2) + Vix (Max)) 25mV  
Rev. 1.3 / Jul. 2013  
24  
Slew Rate Definitions for Single-Ended Input Signals  
See 7.5 “Address / Command Setup, Hold and Derating” in “DDR3 Device Operation” for single-ended slew  
rate definitions for address and command signals.  
See 7.6 “Data Setup, Hold and Slew Rate Derating” in “DDR3 Device Operation” for single-ended slew rate  
definition for data signals.  
Slew Rate Definitions for Differential Input Signals  
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table  
and figure below.  
Differential Input Slew Rate Definition  
Measured  
Description  
Defined by  
Max  
Min  
Differential input slew rate for rising edge  
(CK-CK and DQS-DQS)  
V
V
[V -V  
] / DeltaTRdiff  
[V -V ] / DeltaTFdiff  
IHdiffmin ILdiffmax  
ILdiffmax  
IHdiffmin  
IHdiffmin ILdiffmax  
Differential input slew rate for falling edge  
(CK-CK and DQS-DQS)  
V
V
IHdiffmin  
ILdiffmax  
Notes:  
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.  
Delta  
TRdiff  
VIHdiffmin  
0
VILdiffmax  
Delta  
TFdiff  
Differential Input Slew Rate Definition for DQS, DQS and CK, CK  
Rev. 1.3 / Jul. 2013  
25  
AC & DC Output Measurement Levels  
Single Ended AC and DC Output Levels  
Table below shows the output levels used for measurements of single ended signals.  
Single-ended AC and DC Output Levels  
DDR3-800, 1066,  
Symbol  
Parameter  
Unit  
Notes  
1333 and 1600  
VOH(DC)  
VOM(DC)  
VOL(DC)  
VOH(AC)  
VOL(AC)  
0.8 x VDDQ  
V
V
V
V
V
DC output high measurement level (for IV curve linearity)  
DC output mid measurement level (for IV curve linearity)  
DC output low measurement level (for IV curve linearity)  
AC output high measurement level (for output SR)  
AC output low measurement level (for output SR)  
0.5 x VDDQ  
0.2 x VDDQ  
V
TT + 0.1 x VDDQ  
1
1
VTT - 0.1 x VDDQ  
Notes:  
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with  
a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2.  
Differential AC and DC Output Levels  
Table below shows the output levels used for measurements of single ended signals.  
Differential AC and DC Output Levels  
DDR3-800, 1066,  
Symbol  
Parameter  
Unit  
Notes  
1333 and 1600  
VOHdiff (AC)  
VOLdiff (AC)  
Notes:  
+ 0.2 x VDDQ  
V
V
1
1
AC differential output high measurement level (for output SR)  
AC differential output low measurement level (for output SR)  
- 0.2 x VDDQ  
1. The swing of ±0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with  
a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the differential outputs.  
Rev. 1.3 / Jul. 2013  
26  
Single Ended Output Slew Rate  
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined  
and measured between V  
and V  
for single ended signals are shown in table and figure below.  
OL(AC)  
OH(AC)  
Single-ended Output slew Rate Definition  
Measured  
Description  
Defined by  
From  
VOL(AC)  
VOH(AC)  
To  
VOH(AC)  
VOL(AC)  
[VOH(AC)-VOL(AC)] / DeltaTRse  
[VOH(AC)-VOL(AC)] / DeltaTFse  
Single-ended output slew rate for rising edge  
Single-ended output slew rate for falling edge  
Notes:  
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.  
Delta TRse  
VOH(AC)  
V∏  
VOl(AC)  
Delta TFse  
Single Ended Output slew Rate Definition  
Output Slew Rate (single-ended)  
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866  
Units  
Parameter  
Symbol Min Max Min Max Min Max Min Max Min Max  
SRQse 2.5 2.5 2.5 2.5 2.5  
51)  
Single-ended Output Slew Rate  
Description: SR; Slew Rate  
5
5
5
5
V/ns  
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)  
se: Single-ended Signals  
For Ron = RZQ/7 setting  
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.  
Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high  
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).  
Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high  
to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from  
low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular  
maximum limite of 5 V/ns applies.  
Rev. 1.3 / Jul. 2013  
27  
Differential Output Slew Rate  
With the reference load for timing measurements, output slew rate for falling and rising edges is defined  
and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure  
below.  
Differential Output Slew Rate Definition  
Measured  
Description  
Defined by  
From  
To  
VOHdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff  
VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff  
VOLdiff (AC)  
VOHdiff (AC)  
Differential output slew rate for rising edge  
Differential output slew rate for falling edge  
Notes:  
1. Output slew rate is verified by design and characterization, and may not be subject to production test.  
Delta  
TRdiff  
VOHdiff(AC)  
O
VOLdiff(AC)  
Delta  
TFdiff  
Differential Output slew Rate Definition  
Differential Output Slew Rate  
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866  
Units  
Parameter  
Symbol Min Max Min Max Min Max Min Max Min Max  
Differential Output Slew Rate SRQdiff  
5
12  
5
12  
5
12  
5
12  
5
12  
V/ns  
Description: SR; Slew Rate  
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)  
se: Single-ended Signals  
For Ron = RZQ/7 setting  
Rev. 1.3 / Jul. 2013  
28  
Reference Load for AC Timing and Output Slew Rate  
Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing  
parameters of the device as well as output slew rate measurements.  
It is not intended as a precise representation of any particular system environment or a depiction of the  
actual load presented by a production tester. System designers should use IBIS or other simulation tools to  
correlate the timing reference load to a system environment. Manufacturers correlate to their production  
test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.  
VDDQ  
25 Ohm  
CK, CK  
DQ  
DQS  
DQS  
VTT = VDDQ/2  
DUT  
Reference Load for AC Timing and Output Slew Rate  
Rev. 1.3 / Jul. 2013  
29  
Overshoot and Undershoot Specifications  
Address and Control Overshoot and Undershoot Specifications  
AC Overshoot/Undershoot Specification for Address and Control Pins  
DDR3- DDR3- DDR3- DDR3- DDR3-  
Parameter  
Units  
800 1066 1333 1600 1866  
Maximum peak amplitude allowed for overshoot area. (See Figure below)  
0.4  
0.4  
0.4  
0.5  
0.5  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
V
V
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4  
Maximum overshoot area above VDD (See Figure below)  
Maximum undershoot area below VSS (See Figure below)  
0.67  
0.67  
0.33 0.28 V-ns  
0.33 0.28 V-ns  
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)  
See figure below for each parameter definition  
Maximum Amplitude  
Overshoot Area  
VDD  
VSS  
Volts  
(V)  
Undershoot Area  
Maximum Amplitude  
Time (ns)  
Address and Control Overshoot and Undershoot Definition  
Rev. 1.3 / Jul. 2013  
30  
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications  
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask  
DDR3-DDR3-DDR3-DDR3-DDR3-  
Parameter  
Units  
800 1066 1333 1600 1866  
Maximum peak amplitude allowed for overshoot area. (See Figure below)  
Maximum peak amplitude allowed for undershoot area. (See Figure below)  
Maximum overshoot area above VDD (See Figure below)  
Maximum undershoot area below VSS (See Figure below)  
(CK, CK, DQ, DQS, DQS, DM)  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
0.4  
V
V
0.25 0.19 0.15 0.13 0.11 V-ns  
0.25 0.19 0.15 0.13 0.11 V-ns  
See figure below for each parameter definition  
Maximum Amplitude  
Overshoot Area  
VDDQ  
VSSQ  
Volts  
(V)  
Undershoot Area  
Maximum Amplitude  
Time (ns)  
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition  
Rev. 1.3 / Jul. 2013  
31  
Refresh parameters by device density  
Refresh parameters by device density  
Parameter  
RTT_Nom Setting  
512Mb  
90  
1Gb  
2Gb  
4Gb  
8Gb  
Units Notes  
REF command ACT or  
REF command time  
tRFC  
110  
160  
260  
350  
ns  
0 C T  
85 C T  
85 C  
7.8  
7.8  
3.9  
7.8  
3.9  
7.8  
3.9  
7.8  
3.9  
us  
us  
Average periodic  
refresh interval  
CASE  
tREFI  
95 C 3.9  
CASE  
Notes:  
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices  
support the following options or requirements referred to in this materia.  
Rev. 1.3 / Jul. 2013  
32  
Standard Speed Bins  
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.  
DDR3-800 Speed Bins  
For specific Notes See "Speed Bin Table Notes" on page 38.  
Speed Bin  
DDR3-800E  
6-6-6  
Unit  
Notes  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
max  
t
15  
20  
ns  
ns  
ns  
ns  
AA  
Internal read command to first data  
ACT to internal read or write delay time  
PRE command period  
t
15  
15  
—
—
—
RCD  
t
RP  
t
52.5  
RC  
ACT to ACT or REF command period  
ACT to PRE command period  
t
37.5  
2.5  
9 * tREFI  
3.3  
ns  
ns  
RAS  
t
CK(AVG)  
CL = 6  
CWL = 5  
1, 2, 3  
n
6
5
CK  
Supported CL Settings  
Supported CWL Settings  
n
CK  
Rev. 1.3 / Jul. 2013  
33  
DDR3-1066 Speed Bins  
For specific Notes See "Speed Bin Table Notes" on page 38.  
Speed Bin  
DDR3-1066F  
7-7-7  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
max  
Internal read command to  
first data  
t
13.125  
20  
ns  
ns  
ns  
ns  
ns  
AA  
ACT to internal read or  
write delay time  
t
13.125  
13.125  
50.625  
—
—
—
RCD  
t
PRE command period  
RP  
ACT to ACT or REF  
command period  
t
RC  
ACT to PRE command  
period  
t
37.5  
2.5  
9 * tREFI  
3.3  
RAS  
t
CWL = 5  
CL = 6  
ns  
ns  
ns  
ns  
ns  
ns  
1, 2, 3, 6  
1, 2, 3, 4  
4
CK(AVG)  
t
CWL = 6  
Reserved  
Reserved  
CK(AVG)  
t
CWL = 5  
CL = 7  
CK(AVG)  
t
CWL = 6  
1.875  
1.875  
< 2.5  
< 2.5  
1, 2, 3, 4  
4
CK(AVG)  
t
CWL = 5  
CL = 8  
Reserved  
CK(AVG)  
t
CWL = 6  
1, 2, 3  
CK(AVG)  
n
Supported CL Settings  
Supported CWL Settings  
6, 7, 8  
5, 6  
CK  
n
CK  
Rev. 1.3 / Jul. 2013  
34  
DDR3-1333 Speed Bins  
For specific Notes See "Speed Bin Table Notes" on page 38.  
Speed Bin  
DDR3-1333H  
9-9-9  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
13.5  
(13.125)5,10  
max  
Internal read command  
to first data  
t
20  
ns  
ns  
ns  
ns  
ns  
AA  
13.5  
ACT to internal read or  
write delay time  
t
—
—
—
RCD  
(13.125)5,10  
13.5  
(13.125)5,10  
t
PRE command period  
RP  
49.5  
(49.125)5,10  
ACT to ACT or REF  
command period  
t
RC  
ACT to PRE command  
period  
t
36  
9 * tREFI  
3.3  
RAS  
t
t
t
t
CWL = 5  
2.5  
ns  
ns  
ns  
ns  
1, 2, 3, 7  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CL = 6  
CL = 7  
CL = 8  
CWL = 6  
CWL = 7  
CWL = 5  
Reserved  
Reserved  
Reserved  
1, 2, 3, 4, 7  
4
4
1.875  
1.875  
< 2.5  
t
CWL = 6  
ns  
1, 2, 3, 4, 7  
CK(AVG)  
(Optional)5,10  
Reserved  
t
t
t
t
t
t
t
CWL = 7  
CWL = 5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1, 2, 3, 4  
4
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
Reserved  
CWL = 6  
< 2.5  
1, 2, 3, 7  
1, 2, 3, 4  
4
CWL = 7  
Reserved  
Reserved  
CWL = 5, 6  
CWL = 7  
CL = 9  
1.5  
1.5  
<1.875  
<1.875  
1, 2, 3, 4  
CWL = 5, 6  
Reserved  
Reserved  
4
CL = 10  
ns  
ns  
1, 2, 3  
t
CWL = 7  
CK(AVG)  
n
Supported CL Settings  
Supported CWL Settings  
6, (7), 8, 9, (10)  
5, 6, 7  
CK  
n
CK  
Rev. 1.3 / Jul. 2013  
35  
DDR3-1600 Speed Bins  
For specific Notes See "Speed Bin Table Notes" on page 38.  
Speed Bin  
DDR3-1600K  
11-11-11  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
13.75  
(13.125)5,10  
max  
Internal read command to  
first data  
t
20  
ns  
ns  
ns  
ns  
ns  
AA  
13.75  
(13.125)5,10  
ACT to internal read or  
write delay time  
t
—
—
—
RCD  
13.75  
(13.125)5,10  
t
PRE command period  
RP  
48.75  
(48.125)5,10  
ACT to ACT or REF  
command period  
t
RC  
ACT to PRE command  
period  
t
35  
9 * tREFI  
3.3  
RAS  
t
CWL = 5  
2.5  
ns  
ns  
ns  
ns  
1,2,3,8  
CK(AVG)  
t
CL = 6  
CWL = 6  
CWL = 7  
CWL = 5  
Reserved  
Reserved  
Reserved  
1,2,3,4,8  
CK(AVG)  
t
4
4
CK(AVG)  
t
CK(AVG)  
1.875  
< 2.5  
t
CWL = 6  
ns  
1,2,3,4,8  
CK(AVG)  
(Optional)5,10  
Reserved  
CL = 7  
t
CWL = 7  
CWL = 8  
CWL = 5  
CWL = 6  
CWL = 7  
CWL = 8  
CWL = 5, 6  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1,2,3,4,8  
CK(AVG)  
t
Reserved  
4
4
CK(AVG)  
t
Reserved  
CK(AVG)  
t
1.875  
1.5  
< 2.5  
1,2,3,8  
1,2,3,4,8  
1,2,3,4  
4
CK(AVG)  
CL = 8  
CL = 9  
t
Reserved  
Reserved  
Reserved  
CK(AVG)  
t
CK(AVG)  
t
CK(AVG)  
<1.875  
t
CWL = 7  
ns  
1,2,3,4,8  
CK(AVG)  
(Optional)5,10  
Reserved  
t
CWL = 8  
CWL = 5, 6  
CWL = 7  
ns  
ns  
ns  
ns  
ns  
ns  
1,2,3,4  
4
CK(AVG)  
t
Reserved  
CK(AVG)  
t
CL = 10  
CL = 11  
1.5  
<1.875  
<1.5  
1,2,3,8  
1,2,3,4  
4
CK(AVG)  
t
CWL = 8  
Reserved  
Reserved  
CK(AVG)  
t
CWL = 5, 6,7  
CWL = 8  
CK(AVG)  
t
1.25  
1,2,3  
CK(AVG)  
n
Supported CL Settings  
Supported CWL Settings  
5, 6, 7, 8, 9, 10, 11  
5, 6, 7, 8  
CK  
n
CK  
Rev. 1.3 / Jul. 2013  
36  
DDR3-1866 Speed Bins  
For specific Notes See "Speed Bin Table Notes" on page 38.  
Speed Bin  
DDR3-1866M  
13-13-13  
Unit  
Note  
CL - nRCD - nRP  
Parameter  
Symbol  
min  
13.91  
(13.125)5,11  
13.91  
(13.125)5,11  
13.91  
(13.125)5,11  
max  
Internal read command  
to first data  
t
20  
ns  
ns  
ns  
ns  
ns  
AA  
ACT to internal read or  
write delay time  
t
—
—
RCD  
t
PRE command period  
RP  
ACT to PRE command  
period  
t
34  
9 * tREFI  
RAS  
47.91  
(47.125)5,11  
2.5  
ACT to ACT or PRE  
command period  
t
-
RC  
t
t
t
t
CWL = 5  
3.3  
ns  
ns  
ns  
ns  
1, 2, 3, 9  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CL = 6  
CWL = 6  
CWL = 7,8,9  
CWL = 5  
Reserved  
Reserved  
Reserved  
1, 2, 3, 4, 9  
4
4
1.875  
1.875  
1.5  
< 2.5  
< 2.5  
t
CL = 7  
CWL = 6  
ns  
1, 2, 3, 4, 9  
CK(AVG)  
(Optional)  
Reserved  
Reserved  
t
t
t
t
t
t
CWL = 7,8,9  
CWL = 5  
ns  
ns  
ns  
ns  
ns  
ns  
4
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
4
CWL = 6  
1, 2, 3, 9  
CL = 8  
CL = 9  
CWL = 7  
Reserved  
Reserved  
Reserved  
1, 2, 3, 4, 9  
CWL = 8,9  
CWL = 5, 6  
4
4
<1.875  
t
CWL = 7  
ns  
1, 2, 3, 4, 9  
CK(AVG)  
(Optional)  
Reserved  
Reserved  
Reserved  
t
t
t
t
t
t
CWL = 8  
CWL = 9  
ns  
ns  
ns  
ns  
ns  
ns  
1, 2, 3, 4, 9  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
4
CWL = 5, 6  
CWL = 7  
4
CL = 10  
CL = 11  
1.5  
<1.875  
<1.5  
1, 2, 3, 9  
1, 2, 3, 4, 9  
4
CWL = 8  
Reserved  
Reserved  
CWL = 5,6,7  
1.25  
t
CWL = 8  
ns  
1, 2, 3, 4, 9  
CK(AVG)  
(Optional)  
Reserved  
Reserved  
Reserved  
Reserved  
t
t
t
t
t
CWL = 9  
CWL = 5,6,7,8  
CWL = 9  
ns  
ns  
ns  
ns  
ns  
1, 2, 3, 4  
4
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CK(AVG)  
CL = 12  
CL = 13  
1,2,3,4  
4
CWL = 5,6,7,8  
CWL = 9  
1.07  
<1.25  
1, 2, 3  
n
Supported CL Settings  
Supported CWL Settings  
6, 7, 8, 9, 10, 11, 13  
5, 6, 7, 8, 9  
CK  
n
CK  
Rev. 1.3 / Jul. 2013  
37  
Speed Bin Table Notes  
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);  
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-  
ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require-  
ments from CWL setting.  
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-  
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should  
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-  
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =  
3.0 ns should only be used for CL = 5 calculation.  
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)  
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is  
tCK(AVG).MAX corresponding to CL SELECTED.  
4. ‘Reserved’ settings are not allowed. User must program a different value.  
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-  
datory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is  
supported.  
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the  
table which are not subject to Production Tests but verified by Design/Characterization.  
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the  
table which are not subject to Production Tests but verified by Design/Characterization.  
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the  
table which are not subject to Production Tests but verified by Design/Characterization.  
9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the  
table which are not subject to Production Tests but verified by Design/Characterization.  
10. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must  
be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H  
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin  
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to  
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin  
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)  
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125  
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.  
11. DDR3 SDRAM devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be  
13.125ns. SPD setting must be programed to match. For example, DDR3-1866 devices supporting down binning  
to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte 16), tRCDmin(byte  
18) and tRPmin(byte 20) is programmed to 13.125ns, tRCmin(byte 21,23) also should be programmed accord-  
ingly. For example, 47.125ns (tRASmin + tRPmin = 34ns + 13.125ns)  
Rev. 1.3 / Jul. 2013  
38  
Environmental Parameters  
Symbol  
Parameter  
Rating  
Units  
Notes  
o
T
0 to +55  
C
3
OPR  
Operating temperature (ambient)  
Operating humidity (relative)  
H
10 to 90  
-50 to +100  
5 to 95  
%
1
1
OPR  
o
T
Storage temperature  
C
STG  
H
Storage humidity (without condensation)  
Barometric Pressure (operating & storage)  
%
1
STG  
P
105 to 69  
K Pascal  
1, 2  
BAR  
Note:  
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and  
device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum  
rating conditions for extended periods may affect reliablility.  
2. Up to 9850 ft.  
3. The designer must meet the case temperature specifications for individual module components.  
Rev. 1.3 / Jul. 2013  
39  
IDD and IDDQ Specification Parameters and Test Conditions  
IDD and IDDQ Measurement Conditions  
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure  
below (Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements) shows the setup  
and test load for IDD and IDDQ measurements.  
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,  
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls  
of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.  
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all  
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-  
rents.  
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can  
be used to support correlation of simulated IO power to actual IO power as outlined in the Figure  
below (Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ  
Measurement). In DRAM module application, IDDQ cannot be measured separately since VDD and  
VDDQ are using on merged-power layer in Module PCB.  
For IDD and IDDQ measurements, the following definitions apply:  
•
•
”0” and “LOW” is defined as VIN <= VILAC(max).  
”1” and “HIGH” is defined as VIN >= VIHAC(max).  
•
•
•
•
•
“MID_LEVEL” is defined as inputs are VREF = VDD/2.  
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.  
Basic IDD and IDDQ Measurement Conditions are described in Table 2.  
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.  
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-  
ited to setting  
RON = RZQ/7 (34 Ohm in MR1);  
Qoff = 0B (Output Buffer enabled in MR1);  
RTT_Nom = RZQ/6 (40 Ohm in MR1);  
RTT_Wr = RZQ/2 (120 Ohm in MR2);  
TDQS Feature disabled in MR1  
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time  
before actual IDD or IDDQ measurement is started.  
•
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}  
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}  
Rev. 1.3 / Jul. 2013  
40  
IDDQ (optional)  
IDD  
VDD  
RESET  
CK/CK  
VDDQ  
DDR3  
SDRAM  
RTT = 25 Ohm  
CKE  
CS  
DQS, DQS  
DQ, DM,  
VDDQ/2  
RAS, CAS, WE  
TDQS, TDQS  
A, BA  
ODT  
ZQ  
VSS  
VSSQ  
Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements  
[Note: DIMM level Output test load condition may be different from above  
Application specific  
memory channel  
environment  
IDDQ  
Test Load  
Channel  
IO Power  
Simulation  
IDDQ  
Simulation  
IDDQ  
Simulation  
Correction  
Channel IO Power  
Number  
Correlation from simulated Channel IO Power to actual Channel IO Power supported  
by IDDQ Measurement  
Rev. 1.3 / Jul. 2013  
41  
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns  
DDR3-1333  
DDR3-1600  
DDR3-1866  
Symbol  
Unit  
9-9-9  
1.5  
9
11-11-11  
13-13-13  
1.07  
13  
t
1.25  
11  
11  
39  
28  
11  
24  
32  
5
ns  
CK  
CL  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
nCK  
n
n
n
n
9
13  
RCD  
RC  
33  
24  
9
45  
32  
RAS  
RP  
13  
1KB page size  
2KB page size  
1KB page size  
2KB page size  
20  
30  
4
26  
n
FAW  
33  
5
n
RRD  
5
6
6
n
n
n
n
n
RFC -512Mb  
60  
74  
107  
174  
234  
72  
88  
128  
208  
280  
85  
RFC-1 Gb  
103  
150  
243  
328  
RFC- 2 Gb  
RFC- 4 Gb  
RFC- 8 Gb  
Table 2 -Basic IDD and IDDQ Measurement Conditions  
Symbol  
Description  
Operating One Bank Active-Precharge Current  
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and  
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;  
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-  
IDD0  
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.  
Operating One Bank Active-Precharge Current  
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,  
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:  
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and  
IDD1  
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.  
Rev. 1.3 / Jul. 2013  
42  
Symbol  
Description  
Precharge Standby Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank  
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all  
IDD2N  
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:  
see Table 5.  
Precharge Standby ODT Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank  
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all  
IDD2NT  
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;  
Pattern Details: see Table 6.  
Precharge Power-Down Current Slow Exit  
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank  
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-  
IDD2P0  
IDD2P1  
IDD2Q  
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc)  
Precharge Power-Down Current Fast Exit  
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank  
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-  
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)  
Precharge Quiet Standby Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank  
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-  
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0  
Active Standby Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank  
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all  
IDD3N  
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see  
Table 5.  
Active Power-Down Current  
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank  
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer  
IDD3P  
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0  
Rev. 1.3 / Jul. 2013  
43  
Symbol  
Description  
Operating Burst Read Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,  
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different  
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,  
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode  
IDD4R  
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.  
Operating Burst Write Current  
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,  
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different  
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,  
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode  
IDD4W  
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.  
Burst Refresh Current  
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,  
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;  
IDD5B  
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);  
ODT Signal: stable at 0; Pattern Details: see Table 9.  
Self-Refresh Current: Normal Temperature Range  
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:  
IDD6  
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank  
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer  
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL  
Self-Refresh Current: Extended Temperature Range  
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);  
IDD6ET  
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank  
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh  
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL  
Rev. 1.3 / Jul. 2013  
44  
Symbol  
Description  
Operating Bank Interleave Read Current  
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS:  
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table  
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;  
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-  
IDD7  
ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern  
Details: see Table 10.  
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B  
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;  
RTT_Wr enable: set MR2 A[10,9] = 10B  
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit  
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable  
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range  
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B  
Rev. 1.3 / Jul. 2013  
45  
a)  
Table 3 - IDD0 Measurement-Loop Pattern  
Datab)  
0
ACT  
D, D  
D, D  
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00  
00  
00  
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2  
3,4  
...  
repeat pattern 1...4 until nRAS - 1, truncate if necessary  
nRAS  
PRE  
0
0
1
0
0
0
00  
0
0
0
0
-
...  
repeat pattern 1...4 until nRC - 1, truncate if necessary  
1*nRC+0  
1*nRC+1, 2  
1*nRC+3, 4  
...  
ACT  
D, D  
D, D  
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00  
00  
00  
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary  
PRE 00  
1*nRC+nRAS  
...  
0
0
1
0
0
0
0
0
F
0
-
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary  
repeat Sub-Loop 0, use BA[2:0] = 1 instead  
repeat Sub-Loop 0, use BA[2:0] = 2 instead  
repeat Sub-Loop 0, use BA[2:0] = 3 instead  
repeat Sub-Loop 0, use BA[2:0] = 4 instead  
repeat Sub-Loop 0, use BA[2:0] = 5 instead  
repeat Sub-Loop 0, use BA[2:0] = 6 instead  
repeat Sub-Loop 0, use BA[2:0] = 7 instead  
1
2
3
4
5
6
7
2*nRC  
4*nRC  
6*nRC  
8*nRC  
10*nRC  
12*nRC  
14*nRC  
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.  
b) DQ signals are MID-LEVEL.  
Rev. 1.3 / Jul. 2013  
46  
a)  
Table 4 - IDD1 Measurement-Loop Pattern  
Datab)  
0
ACT  
D, D  
D, D  
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00  
00  
00  
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2  
3,4  
...  
repeat pattern 1...4 until nRCD - 1, truncate if necessary  
RD 00  
repeat pattern 1...4 until nRAS - 1, truncate if necessary  
nRCD  
...  
0
1
0
1
0
0
0
0
0
0
0
0
00000000  
-
nRAS  
PRE  
0
0
1
0
0
0
00  
0
0
...  
repeat pattern 1...4 until nRC - 1, truncate if necessary  
1*nRC+0  
1*nRC+1,2  
1*nRC+3,4  
...  
ACT  
D, D  
D, D  
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00  
00  
00  
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary  
RD 00  
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary  
PRE 00  
1*nRC+nRCD  
...  
0
1
0
1
0
0
0
0
F
0
00110011  
-
1*nRC+nRAS  
...  
0
0
1
0
0
0
0
0
F
0
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary  
repeat Sub-Loop 0, use BA[2:0] = 1 instead  
repeat Sub-Loop 0, use BA[2:0] = 2 instead  
repeat Sub-Loop 0, use BA[2:0] = 3 instead  
repeat Sub-Loop 0, use BA[2:0] = 4 instead  
repeat Sub-Loop 0, use BA[2:0] = 5 instead  
repeat Sub-Loop 0, use BA[2:0] = 6 instead  
repeat Sub-Loop 0, use BA[2:0] = 7 instead  
1
2
3
4
5
6
7
2*nRC  
4*nRC  
6*nRC  
8*nRC  
10*nRC  
12*nRC  
14*nRC  
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.  
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.  
Rev. 1.3 / Jul. 2013  
47  
a)  
Table 5 - IDD2N and IDD3N Measurement-Loop Pattern  
Datab)  
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
-
-
-
-
0
1
2
3
1
2
3
4
5
6
7
4-7  
repeat Sub-Loop 0, use BA[2:0] = 1 instead  
repeat Sub-Loop 0, use BA[2:0] = 2 instead  
repeat Sub-Loop 0, use BA[2:0] = 3 instead  
repeat Sub-Loop 0, use BA[2:0] = 4 instead  
repeat Sub-Loop 0, use BA[2:0] = 5 instead  
repeat Sub-Loop 0, use BA[2:0] = 6 instead  
repeat Sub-Loop 0, use BA[2:0] = 7 instead  
8-11  
12-15  
16-19  
20-23  
24-17  
28-31  
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.  
b) DQ signals are MID-LEVEL.  
a)  
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern  
Datab)  
0
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
1
0
F
F
0
0
0
2
3
1
2
3
4
5
6
7
4-7  
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1  
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2  
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3  
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4  
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5  
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6  
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7  
8-11  
12-15  
16-19  
20-23  
24-17  
28-31  
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.  
b) DQ signals are MID-LEVEL.  
Rev. 1.3 / Jul. 2013  
48  
a)  
Table 7 - IDD4R and IDDQ4R Measurement-Loop Pattern  
Datab)  
0
RD  
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000  
0
1
-
2,3  
D,D  
RD  
D
-
4
00110011  
5
-
-
6,7  
D,D  
1
2
3
4
5
6
7
8-15  
16-23  
24-31  
32-39  
40-47  
48-55  
56-63  
repeat Sub-Loop 0, but BA[2:0] = 1  
repeat Sub-Loop 0, but BA[2:0] = 2  
repeat Sub-Loop 0, but BA[2:0] = 3  
repeat Sub-Loop 0, but BA[2:0] = 4  
repeat Sub-Loop 0, but BA[2:0] = 5  
repeat Sub-Loop 0, but BA[2:0] = 6  
repeat Sub-Loop 0, but BA[2:0] = 7  
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.  
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.  
a)  
Table 8 - IDD4W Measurement-Loop Pattern  
Datab)  
0
0
1
2,3  
4
5
6,7  
WR  
D
D,D  
WR  
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
00  
00  
00  
00  
00  
00  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000  
-
-
00110011  
-
-
D,D  
1
2
3
4
5
6
7
8-15  
16-23  
24-31  
32-39  
40-47  
48-55  
56-63  
repeat Sub-Loop 0, but BA[2:0] = 1  
repeat Sub-Loop 0, but BA[2:0] = 2  
repeat Sub-Loop 0, but BA[2:0] = 3  
repeat Sub-Loop 0, but BA[2:0] = 4  
repeat Sub-Loop 0, but BA[2:0] = 5  
repeat Sub-Loop 0, but BA[2:0] = 6  
repeat Sub-Loop 0, but BA[2:0] = 7  
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.  
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.  
Rev. 1.3 / Jul. 2013  
49  
a)  
Table 9 - IDD5B Measurement-Loop Pattern  
Datab)  
0
1
REF  
D, D  
D, D  
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
0
0
0
-
-
-
0
1.2  
00  
00  
3,4  
5...8  
repeat cycles 1...4, but BA[2:0] = 1  
repeat cycles 1...4, but BA[2:0] = 2  
repeat cycles 1...4, but BA[2:0] = 3  
repeat cycles 1...4, but BA[2:0] = 4  
repeat cycles 1...4, but BA[2:0] = 5  
repeat cycles 1...4, but BA[2:0] = 6  
repeat cycles 1...4, but BA[2:0] = 7  
9...12  
13...16  
17...20  
21...24  
25...28  
29...32  
33...nRFC-1  
2
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.  
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.  
b) DQ signals are MID-LEVEL.  
Rev. 1.3 / Jul. 2013  
50  
a)  
Table 10 - IDD7 Measurement-Loop Pattern  
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9  
Datab)  
0
1
0
1
2
...  
ACT  
RDA  
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00  
00  
00  
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000  
-
repeat above D Command until nRRD - 1  
nRRD  
nRRD+1  
nRRD+2  
...  
2*nRRD  
3*nRRD  
4*nRRD  
ACT  
RDA  
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00  
00  
00  
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011  
-
repeat above D Command until 2* nRRD - 1  
repeat Sub-Loop 0, but BA[2:0] = 2  
repeat Sub-Loop 1, but BA[2:0] = 3  
2
3
D
1
0
0
0
0
3
00  
0
0
F
0
-
4
Assert and repeat above D Command until nFAW - 1, if necessary  
repeat Sub-Loop 0, but BA[2:0] = 4  
repeat Sub-Loop 1, but BA[2:0] = 5  
repeat Sub-Loop 0, but BA[2:0] = 6  
repeat Sub-Loop 1, but BA[2:0] = 7  
5
6
7
8
nFAW  
nFAW+nRRD  
nFAW+2*nRRD  
nFAW+3*nRRD  
nFAW+4*nRRD  
D
1
0
0
0
0
7
00  
0
0
F
0
-
9
Assert and repeat above D Command until 2* nFAW - 1, if necessary  
2*nFAW+0  
2*nFAW+1  
ACT  
RDA  
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00  
00  
00  
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011  
-
10  
2&nFAW+2  
Repeat above D Command until 2* nFAW + nRRD - 1  
2*nFAW+nRRD  
2*nFAW+nRRD+1  
ACT  
RDA  
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00  
00  
00  
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000  
-
11  
2&nFAW+nRRD+2  
Repeat above D Command until 2* nFAW + 2* nRRD - 1  
repeat Sub-Loop 10, but BA[2:0] = 2  
repeat Sub-Loop 11, but BA[2:0] = 3  
12 2*nFAW+2*nRRD  
13 2*nFAW+3*nRRD  
D
1
0
0
0
0
3
00  
0
0
0
0
-
14 2*nFAW+4*nRRD  
Assert and repeat above D Command until 3* nFAW - 1, if necessary  
repeat Sub-Loop 10, but BA[2:0] = 4  
15 3*nFAW  
16 3*nFAW+nRRD  
17 3*nFAW+2*nRRD  
18 3*nFAW+3*nRRD  
repeat Sub-Loop 11, but BA[2:0] = 5  
repeat Sub-Loop 10, but BA[2:0] = 6  
repeat Sub-Loop 11, but BA[2:0] = 7  
D
1
0
0
0
0
7
00  
0
0
0
0
-
19 3*nFAW+4*nRRD  
Assert and repeat above D Command until 4* nFAW - 1, if necessary  
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.  
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.  
Rev. 1.3 / Jul. 2013  
51  
IDD Specifications (Tcase: 0 to 95oC)  
* Module IDD values in the datasheet are only a calculation based on the component IDD spec.  
The actual measurements may vary according to DQ loading cap.  
2GB, 256M x 64 U-DIMM: HMT325U6EFR8C  
Symbol  
IDD0  
DDR3 1066  
224  
DDR3 1333  
232  
DDR3 1600  
240  
DDR3 1866  
256  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
note  
IDD1  
272  
288  
296  
304  
IDD2N  
IDD2NT  
IDD2P0  
IDD2P1  
IDD2Q  
IDD3N  
IDD3P  
IDD4R  
IDD4W  
IDD5B  
IDD6  
120  
128  
136  
144  
144  
160  
168  
192  
96  
96  
96  
96  
120  
120  
120  
136  
120  
136  
144  
144  
144  
152  
168  
176  
120  
120  
120  
136  
464  
544  
640  
728  
480  
560  
656  
744  
1280  
96  
1280  
96  
1280  
96  
1280  
96  
IDD6ET  
IDD7  
112  
112  
112  
112  
888  
992  
1008  
1144  
2GB, 256M x 72 U-DIMM: HMT325U7EFR8C  
Symbol  
IDD0  
DDR3 1066  
252  
DDR3 1333  
261  
DDR3 1600  
270  
DDR3 1866  
288  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
note  
IDD1  
306  
324  
333  
342  
IDD2N  
IDD2NT  
IDD2P0  
IDD2P1  
IDD2Q  
IDD3N  
IDD3P  
IDD4R  
IDD4W  
IDD5B  
IDD6  
135  
144  
153  
162  
162  
180  
189  
216  
108  
108  
108  
108  
135  
135  
135  
153  
135  
153  
162  
162  
162  
171  
189  
198  
135  
135  
135  
153  
522  
612  
720  
819  
540  
630  
738  
837  
1440  
108  
1440  
108  
1440  
108  
1440  
108  
IDD6ET  
IDD7  
126  
126  
126  
126  
999  
1116  
1134  
1287  
Rev. 1.3 / Jul. 2013  
52  
4GB, 512M x 64 U-DIMM: HMT351U6EFR8C  
Symbol  
IDD0  
DDR3 1066  
344  
DDR3 1333  
360  
DDR3 1600  
408  
DDR3 1866  
432  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
note  
IDD1  
392  
416  
464  
480  
IDD2N  
IDD2NT  
IDD2P0  
IDD2P1  
IDD2Q  
IDD3N  
IDD3P  
IDD4R  
IDD4W  
IDD5B  
IDD6  
240  
256  
272  
288  
288  
320  
336  
384  
192  
192  
192  
192  
240  
240  
240  
272  
240  
272  
288  
288  
288  
304  
336  
352  
240  
240  
240  
272  
584  
682  
808  
904  
600  
688  
824  
920  
1400  
192  
1408  
192  
1448  
192  
1456  
192  
IDDET  
IDD7  
224  
224  
224  
224  
1008  
1120  
1176  
1320  
4GB, 512M x 72 U-DIMM: HMT351U7EFR8C  
Symbol  
IDD0  
DDR3 1066  
387  
DDR3 1333  
405  
DDR3 1600  
459  
DDR3 1866  
486  
Unit  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
note  
IDD1  
441  
468  
522  
540  
IDD2N  
IDD2NT  
IDD2P0  
IDD2P1  
IDD2Q  
IDD3N  
IDD3P  
IDD4R  
IDD4W  
IDD5B  
IDD6  
270  
288  
306  
324  
324  
360  
378  
432  
216  
216  
216  
216  
270  
270  
270  
306  
270  
306  
324  
324  
324  
342  
378  
396  
270  
270  
270  
306  
657  
756  
909  
1017  
1035  
1638  
216  
675  
774  
927  
1575  
216  
1584  
216  
1629  
216  
IDDET  
IDD7  
252  
252  
252  
252  
1134  
1260  
1323  
1485  
Rev. 1.3 / Jul. 2013  
53  
Module Dimensions  
256Mx64 - HMT325U6EFR8C  
Front  
2.100.15  
Min 1.45  
Max R0.70  
30.00  
SPD  
4x3.000.10  
17.30  
DETAIL-B  
DETAIL-A  
2x2.500.10  
9.50  
2x2.300.10  
47.00  
71.00  
5.175  
128.95  
133.35  
Back  
Side  
Detail - A  
Detail - B  
2.51mm max  
FULL R  
2.50  
0.800.05  
2.500.20  
1.00  
0.3~1.0  
1.27±0.10  
1.500.10  
5.00  
Note:  
1. 0.13tolerance on all dimensions unless otherwise stated.  
Units: millimeters  
Rev. 1.3 / Jul. 2013  
54  
256Mx72 - HMT325U7EFR8C  
Front  
2.100.15  
Min 1.45  
Max R0.70  
30.00  
SPD  
4x3.000.10  
17.30  
DETAIL-B  
DETAIL-A  
2x2.500.10  
9.50  
2x2.300.10  
47.00  
5.175  
71.00  
128.95  
133.35  
Back  
Side  
Detail - A  
Detail - B  
2.51mm Max  
FULL R  
2.50  
0.800.05  
2.500.20  
1.00  
0.3~1.0  
1.27±0.10  
1.500.10  
5.00  
Note:  
1. 0.13tolerance on all dimensions unless otherwise stated.  
Units: millimeters  
Rev. 1.3 / Jul. 2013  
55  
512Mx64 - HMT351U6EFR8C  
Front  
2.100.15  
Min 1.45  
Max R0.70  
30.00  
4x3.000.10  
SPD  
17.30  
DETAIL-A  
2x2.500.10  
DETAIL-B  
9.50  
2x2.300.10  
47.00  
71.00  
5.175  
128.95  
133.35  
Back  
Side  
Detail - A  
Detail - B  
3.64mm Max  
FULL R  
2.50  
0.800.05  
2.500.20  
1.00  
0.3~1.0  
1.27±0.10  
1.500.10  
5.00  
Note:  
1. 0.13tolerance on all dimensions unless otherwise stated.  
Units: millimeters  
Rev. 1.3 / Jul. 2013  
56  
512Mx72 - HMT351U7EFR8C  
Front  
2.100.15  
Min 1.45  
Max R0.70  
30.00  
SPD  
4x3.000.10  
17.30  
DETAIL-B  
DETAIL-A  
2x2.500.10  
9.50  
2x2.300.10  
47.00  
5.175  
71.00  
128.95  
133.35  
Back  
Side  
Detail - A  
Detail - B  
3.64mm Max  
FULL R  
2.50  
0.800.05  
2.500.20  
1.00  
0.3~1.0  
1.27±0.10  
1.500.10  
5.00  
Note:  
1. 0.13tolerance on all dimensions unless otherwise stated.  
Units: millimeters  
Rev. 1.3 / Jul. 2013  
57  

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