HMTA8GL7AHR4A [HYNIX]
DDR3(L) SDRAM Load Reduced DIMM Based on 4Gb A-die; DDR3 （ L） SDRAM负载降低的DIMM基于4Gb的A-模
| 型号： | HMTA8GL7AHR4A |
| 厂家： | 
HYNIX SEMICONDUCTOR |
| 描述： | DDR3(L) SDRAM Load Reduced DIMM Based on 4Gb A-die |
| 文件： | 总35页 (文件大小：555K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
240pin Load Reduced DDR3(L) SDRAM DIMM
DDR3(L) SDRAM Load Reduced DIMM
Based on 4Gb A-die
HMTA8GL7AHR4A
HMTA8GL7AHR4C
*SK hynix reserves the right to change products or specifications without notice.
Rev. 0.1 / Jun. 2013
1
Revision History
Revision No.
History
Draft Date
Remark
0.1
Initial Release
Jun.2013
Rev. 0.1 / Jun. 2013
2
Description
SK hynix Load Reduced DDR3(L) SDRAM DIMMs are low power, high-speed operation memory modules
that use SK hynix DDR3(L) SDRAM devices. These Load Reduced DIMMs are intended for use as main
memory when installed in systems such as servers and workstations.
Features
• 240 pin Load Reduced DDR3(L) DRAM Dual In-Line Memory Module
• Buffer performance by LRDIMM presenting less load to system
• Compatible with RDIMM systems with appropriate BIOS changes
• Backward Compatible with 1.5V DDR3 Memory Module
(1.35V could not support the upper 1.5V speed)
• Built with 4Gb DDR3 SDRAM 78ball
• Data transfer rates: Up to PC3L-10600 / PC3-12800
• JEDEC standard Double Data Rate3 Synchronous DRAMs(DDR3 SDRAMs) with 1.5V nominal
• JEDEC standard Double Data Rate3L Synchronous DRAMs(DDR3L SDRAMs) with 1.35V nominal
• Functionality and operations are same with DDR3 & DDR3L about same speed bin
• Host interface and MB(Memory Buffer) component industry standard compliant
• MB provides “address multiplication” to generate additional chips selects
• Address mirroring
• ODT (On-Die Termination)
• 133.35 x 30.35 mm form factor
• Full DIMM Heat Spreader
• This product is in compliance with the RoHS directive.
Ordering Information
MB
# of
Part Number
Density Organization Component Composition
FDHS Height
ranks
Vendor version
Montage
Inphi
C1
HMTA8GL7AHR4A-H9
HMTA8GL7AHR4C-PB
QDP 4Gx4(H5TCAG43AHR)*36
GS02B
C1
64GB
8Gx72
8
O
30.35mm
Montage
Inphi
QDP 4Gx4(H5TQAG43AHR)*36
GS02B
* In order to uninstall FDHS, please contact sales administrator
Rev. 0.1 / Jun. 2013
3
Key Parameters
CAS
Latency
(tCK)
tCK
(ns)
tRCD
(ns)
tRP
(ns)
tRAS
(ns)
tRC
(ns)
MT/s
Grade
CL-tRCD-tRP
DDR3-1066
DDR3-1333
-G7
-H9
1.875
1.5
7
9
13.125
13.5
13.125
13.5
37.5
36
50.625
7-7-7
9-9-9
49.5
(49.125)*
(13.125)* (13.125)*
13.75 13.75
(13.125)* (13.125)*
48.75
(48.125)*
DDR3-1600
-PB
1.25
11
35
11-11-11
*SK hynix DRAM devices support optional downbinning to CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [MHz]
Grade
Remark
CL6
CL7
CL8
CL9
CL10
CL11
-G7
-H9
-PB
800
800
800
1066
1066
1066
1066
1066
1066
1333
1333
1333
1333
1600
Address Table
64GB(8Rx4)
Refresh Method
Row Address
Column Address
Bank Address
Page Size
8K/64ms
A0-A15
A0-A9,A11
BA0-BA2
1KB
Rev. 0.1 / Jun. 2013
4
Pin Descriptions
Num
ber
Num
ber
Pin Name
CK0
Description
Pin Name
Par_In
Description
Parity bit for the Address and Con-
trol bus
Clock Input, positive line
Clock Input, negative line
1
1
1
1
Parity error found on the Address
and Control bus
CK0
Err_Out
CK1
CK1
Clock Input, positive line
Clock Input, negative line
Clock Enables
1
1
2
ODT[0]
DQ[63:0]
CB[7:0]
On Die Termination Inputs
Data Input/Output
1
64
8
CKE[1:0]
Data check bits Input/Output
Clock Enables
On Die Termination
CKE[3:2],
ODT[1], TEST
2
DQS[8:0]
DQS[8:0]
Data strobes
9
Memory bus tool (Not Con-
nected and Not Useable on
DIMMs)
RAS
CAS
Row Address Strobe
1
1
Data strobes, negative line
9
9
DM[8:0]/
DQS[17:9],
TDQS[17:9]
Data Masks / Data strobes,
Termination data strobes
Column Address Strobe
Data Masks / Data strobes,
Termination data strobes
DQS[17:9],
TDQS[17:9]
WE
Write Enable
Chip Selects
1
2
9
1
1
1
Reserved for optional hardware
temperature sensing
S[1:0]
EVENT
TEST
Chip Selects
S[3:2], A17,
A16
Memory bus test tool (Not Con-
nected and Not Usable on DIMMs)
2
Address Inputs
A[9:0],A11,
A[15:13]
Address Inputs
14
RESET
Register and SDRAM control pin
VDD
VSS
A10/AP
A12/BC
BA[2:0]
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
1
1
3
Power Supply
22
59
1
Ground
VREFDQ
Reference Voltage for DQ
Serial Presence Detect (SPD)
Clock Input
VREFCA
SCL
1
Reference Voltage for CA
1
VTT
SDA
SPD Data Input/Output
SPD Address Inputs
1
3
Termination Voltage
SPD Power
4
1
VDDSPD
SA[2:0]
Rev. 0.1 / Jun. 2013
5
Input/Output Functional Descriptions
Symbol
Type
Polarity
Function
Positive
Line
Positive line of the differential pair of system clock inputs that drives input to the on-
DIMM Clock Driver.
CK0
IN
Negative Negative line of the differential pair of system clock inputs that drives the input to the
CK0
CK1
CK1
IN
IN
IN
Line
on-DIMM Clock Driver.
Positive
Line
Terminated but not used on RDIMMs.
Negative
Line
Terminated but not used on RDIMMs.
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN
(row ACTIVE in any bank)
Active
High
CKE[1:0]
IN
Enables the command decoders for the associated rank of SDRAM when low and dis-
ables decoders when high. When decoders are disabled, new commands are ignored
and previous operations continue. Other combinations of these input signals perform
unique functions, including disabling all outputs (except CKE and ODT) of the register(s)
on the DIMM or accessing internal control words in the register device(s). For modules
with two registers, S[3:2] operate similarly to S[1:0] for the second set of register out-
puts or register control words.
Active
Low
S[3:0]
IN
IN
Active
High
ODT[1:0]
On-Die Termination control signals
Active
Low
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
RAS, CAS, WE
VREFDQ
IN
Supply
Supply
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In,
ODT0 and ODT1.
VREFCA
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
applied. Bank address also determines mode register is to be accessed during an MRS
cycle.
BA[2:0]
IN
IN
—
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a Precharge command to deter-
mine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL
4/8 identification for ‘’BL on the fly’’ during CAS command. The address inputs also pro-
vide the op-code during Mode Register Set commands.
A[15:13,
12/BC,11,
10/AP,[9:0]
—
—
DQ[63:0],
CB[7:0]
I/O
IN
Data and Check Bit Input/Output pins
Active
High
DM[8:0]
Masks write data when high, issued concurrently with input data.
V
DD, VSS
VTT
Supply
Supply
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Rev. 0.1 / Jun. 2013
6
Symbol
Type
Polarity
Function
Positive
Edge
DQS[17:0]
I/O
Positive line of the differential data strobe for input and output data.
Negative
Edge
DQS[17:0]
I/O
Negative line of the differential data strobe for input and output data.
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is
applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will
provide the data mask function and TDQS is not used. X4 DRAMs must disable the TDQS
function via mode register A11=0 in MR1
TDQS[17:9]
TDQS[17:9]
OUT
These signals are tied at the system planar to either VSS or VDDSPD to configure the
serial SPD EEPROM address range.
SA[2:0]
SDA
IN
I/O
IN
—
—
—
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to VDDSPD on the system planar to act as a
pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
SCL
This signal indicates that a thermal event has been detected in the thermal sensing
device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
OUT
(open
drain)
EVENT
VDDSPD
Active Low
No pull-up resister is provided on DIMM.
Serial EEPROM positive power supply wired to a separate power pin at the connector
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
Supply
The RESET pin is connected to the RESET pin on the register and to the RESET pin on
the DRAM.
RESET
Par_In
IN
IN
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
OUT
(open
drain)
Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out bus line to VDD on the system planar to act as a pull up.
Err_Out
TEST
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Rev. 0.1 / Jun. 2013
7
Pin Assignments
Front Side
(left 1–60)
Back Side
(right 121–180)
Front Side
(left 61–120)
Back Side
(right 181–240)
Pin #
Pin #
Pin #
Pin #
1
2
3
4
VREFDQ
121
122
123
124
V
SS
61
62
63
64
A2
181
182
183
184
A1
VSS
DQ4
DQ5
VDD
VDD
VDD
CK0
DQ0
DQ1
NC, CK1
NC, CK1
VSS
DM0,DQS9,
TDQS9
5
6
V
SS
125
126
65
66
VDD
VDD
185
186
CK0
VDD
NC,DQS9,
TDQS9
DQS0
DQS0
7
8
127
128
129
130
131
132
133
VSS
67
68
69
70
71
72
73
VREFCA
Par_In, NC
VDD
187
188
189
190
191
192
193
EVENT, NC
A0
VSS
DQ6
DQ7
9
DQ2
DQ3
VDD
10
11
12
13
VSS
A10 / AP
BA0
BA1
VSS
DQ12
DQ13
VDD
DQ8
DQ9
VDD
RAS
VSS
WE
S0
DM1,DQS10,
TDQS10
14
15
V
SS
134
135
74
75
CAS
VDD
194
195
VDD
NC,DQS10,
TDQS10
DQS1
DQS1
ODT0
16
17
18
19
20
21
22
136
137
138
139
140
141
142
VSS
76
77
78
79
80
81
82
S1, NC
ODT1, NC
VDD
196
197
198
199
200
201
202
A13
VDD
VSS
DQ14
DQ15
DQ10
DQ11
S3, NC
VSS
S2, NC
VSS
VSS
DQ20
DQ21
VSS
DQ36
DQ37
DQ16
DQ17
DQ32
DQ33
VSS
VSS
DM2,DQS11,
TDQS11
DM4,DQS13,
TDQS13
23
24
V
SS
143
144
83
84
V
SS
203
204
NC,DQS11,
TDQS11
NC,DQS13,
TDQS13
DQS2
DQS2
DQS4
DQS4
25
26
27
28
29
30
31
145
146
147
148
149
150
151
VSS
85
86
87
88
89
90
91
205
206
207
208
209
210
211
VSS
VSS
DQ22
DQ23
VSS
DQ38
DQ39
DQ18
DQ19
DQ34
DQ35
VSS
VSS
VSS
DQ28
DQ29
VSS
DQ44
DQ45
DQ24
DQ25
DQ40
DQ41
VSS
VSS
NC = No Connect; RFU = Reserved Future Use
Rev. 0.1 / Jun. 2013
8
Front Side
(left 1–60)
Back Side
Front Side
Back Side
Pin #
32
Pin #
152
Pin #
92
Pin #
212
(right 121–180)
(left 61–120)
(right 181–240)
DM3,DQS12,
TDQS12
DM5,DQS14,
TDQS14
VSS
VSS
NC,DQS12,
TDQS12
NC,DQS14,
TDQS14
33
DQS3
DQS3
153
93
DQS5
DQS5
213
34
35
36
37
38
39
40
154
155
156
157
158
159
160
VSS
94
95
214
215
216
217
218
219
220
VSS
VSS
DQ30
DQ31
VSS
DQ46
DQ47
DQ26
DQ27
96
DQ42
DQ43
VSS
97
VSS
VSS
CB4, NC
CB5, NC
98
VSS
DQ52
DQ53
CB0, NC
CB1, NC
99
DQ48
DQ49
VSS
100
VSS
NC,DM8,DQS17,
TDQS17
DM6,DQS15,
TDQS15
41
42
V
SS
161
162
101
102
V
SS
221
222
NC,DQS17,
TDQS17
NC,DQS15,
TDQS15
DQS8
DQS8
DQS6
DQS6
43
44
45
46
47
48
163
164
165
166
167
168
VSS
103
104
105
106
107
108
109
223
224
225
226
227
228
229
VSS
VSS
CB6, NC
CB7, NC
VSS
DQ54
DQ55
CB2, NC
CB3, NC
DQ50
DQ51
VSS
VSS
VSS
NC(TEST)
RESET
VSS
DQ60
DQ61
VTT, NC
KEY
DQ56
DQ57
KEY
VSS
DM7,DQS16,
TDQS16
49
50
VTT, NC
CKE0
169
170
CKE1, NC
VDD
110
111
V
SS
230
231
NC,DQS16,
TDQS16
DQS7
DQS7
51
52
53
54
55
56
57
58
59
60
VDD
BA2
171
172
173
174
175
176
177
178
179
180
A15
A14
VDD
A12 / BC
A9
112
113
114
115
116
117
118
119
120
232
233
234
235
236
237
238
239
240
VSS
VSS
DQ62
DQ63
Err_Out, NC
VDD
DQ58
DQ59
VSS
A11
VSS
VDDSPD
SA1
A7
VDD
A8
SA0
SCL
SA2
VTT
VDD
SDA
A5
A6
VSS
A4
VDD
A3
VTT
VDD
NC = No Connect; RFU = Reserved Future Use
Rev. 0.1 / Jun. 2013
9
Functional Block Diagram
64GB, 8Gx72 Module(8Rank of x4) - page1
QCKE2A
QCKE0A
QODT0A
QCS6
QCKE3A
QCKE1A
QODT1A
QCS7
QCS4
QCS5
QCS2
QCS0
QCS3
QCS1
VDD
VDD
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MDQS11
MDQS11
MDQ [20:23]
D0
D27
DQS
DQS
DQS
DQS
DQS11
DQS11
DQ [20:23]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS2
MDQS2
MDQ [16:19]
D1
D28
DQS
DQS
DQS
DQS
DQS2
DQS2
DQ [16:19]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS17
MDQS17
MCB [4:7]
D2
D29
DQS
DQS
DQS
DQS
DQS17
DQS17
CB [4:7]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS1
MDQS1
MDQ [8:11]
D3
D30
DQS
DQS
DQS
DQS
DQS1
DQS1
DQ [8:11]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS10
MDQS10
MDQ [12:15]
D4
D31
DQS
DQS
DQS
DQS
DQS10
DQS10
DQ [12:15]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS15
MDQS15
MDQ [52:55]
D5
D32
DQS
DQS
DQS
DQS
DQS15
DQS15
DQ [52:55]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS6
MDQS6
MDQ [48:51]
D6
D33
DQS
DQS
DQS
DQS
DQS6
DQS6
DQ [48:51]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS14
MDQS14
MDQ [44:47]
D7
D34
DQS
DQS
DQS
DQS
DQS14
DQS14
DQ [44:47]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS5
MDQS5
MDQ [40:43]
D8
D35
DQS
DQS
DQ [0:3]
DQS
DQS
DQ [0:3]
DQS5
DQS5
DQ [40:43]
Notes:
1. Unless otherwise noted, resistor values are 10 Ohms ±5%.
2. This Design uses SDRAMz in DDP. There are four ZQ resistors per DDP. The ZQ resistors are 240 Ohms ±1%.
3. DM pins on SDRAMs are wired to VSS.
4. The DQ and MDQ labels reflect the byte lanes as defined at the edge connector not which Memory Buffer pins are used.
Rev. 0.1 / Jun. 2013
10
32GB, 4Gx72 Module(4Rank of x4) - page2
QCKE2B
QCKE0B
QODT0B
QCS6
QCKE3B
QCKE1B
QODT1B
QCS7
QCS4
QCS5
QCS2
QCS0
QCS3
QCS1
VDD
VDD
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MDQS12
MDQS12
MDQ [28:31]
D9
D18
DQS
DQS
DQS
DQS
DQS12
DQS21
DQ [28:31]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS3
MDQS3
MDQ [24:27]
D10
D19
DQS
DQS
DQS
DQS
DQS3
DQS3
DQ [24:27]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS8
MDQS8
MCB [0:3]
D11
D20
DQS
DQS
DQS
DQS
DQS8
DQS8
CB [0:3]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS0
MDQS0
MDQ [0:3]
D12
D21
DQS
DQS
DQS
DQS
DQS0
DQS0
DQ [0:3]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS9
MDQS9
MDQ [4:7]
D13
D22
DQS
DQS
DQS
DQS
DQS9
DQS9
DQ [4:7]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS16
MDQS16
MDQ [60:63]
D14
D23
DQS
DQS
DQS
DQS
DQS16
DQS16
DQ [60:63]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1 CS2 CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS7
MDQS7
MDQ [56:59]
D15
D24
DQS
DQS
DQS
DQS
DQS7
DQS7
DQ [56:59]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS13
MDQS13
MDQ [36:39]
D16
D25
DQS
DQS
DQS
DQS
DQS13
DQS13
DQ [36:39]
DQ [0:3]
DQ [0:3]
VDD
VDD
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
CS0 CS1CS2CS3 ODT0 ODT1 CKE0 CKE1
ZQ
MDQS4
MDQS4
MDQ [32:35]
D17
D26
DQS
DQS
DQ [0:3]
DQS
DQS
DQ [0:3]
DQS4
DQS4
DQ [32:35]
V
SPD
DDSPD
SCL
EVENT
V
DD
D0–D35
EVENT
SDA
V
TT
VREFCA
VREFDQ
A0 A1 A2
D0–D35
D0–D35
SA0 SA1 SA2
Serial PD w/ stand alone Thermal sensor
VSS
D0–D35
Rev. 0.1 / Jun. 2013
11
32GB, 4Gx72 Module(4Rank of x4) - page3
CS[3:0]
CS0 -> CS0: SDRAMs D[17:0]
CS2 -> CS1: SDRAMs D[17:0]
CS4 -> CS2: SDRAMs D[17:0]
CS6 -> CS3: SDRAMs D[17:0]
CS1-> CS0: SDRAMs D[35:18]
CS3-> CS1: SDRAMs D[35:18]
CS5-> CS2: SDRAMs D[35:18]
CS7-> CS3: SDRAMs D[35:18]
M
e
m
o
r
y
BA[2:0]A -> BA[2:0]: SDRAMs D[8:0], D[35:27]
BA[2:0]B -> BA[2:0]: SDRAMs D[26:9]
BA[2:0]
A[15:0]
A[15:0]A -> A[15:0]: SDRAMs D[8:0], D[35:27]
A[15:0]B -> A[15:0]: SDRAMs D[26:9]
RASA -> RAS: SDRAMs D[8:0], D[35:27]
RASB -> RAS: SDRAMs D[26:9]
RAS
CAS
CASA -> CAS: SDRAMs D[8:0], D[35:27]
CASB -> CAS: SDRAMs D[26:9]
B
u
f
f
e
r
WEA -> WE: SDRAMs D[8:0], D[35:27]
WEB -> WE: SDRAMs D[26:9]
WE
CKE[1:0]
CKE0A -> CKE0: D[8:0]
CKE1B -> CKE0: D[35:27]
CKE0A -> CKE0: D[17:9]
CKE1B -> CKE0: D[26:18]
CKE2A -> CKE1: D[8:0]
CKE2B -> CKE1: D[35:27]
CKE2A -> CKE1: D[17:9]
CKE2B -> CKE1: D[26:18]
ODT[1:0]
ODT0A -> ODT1: SDRAMs D[8:0]
ODT1A -> ODT1: SDRAMs D[35:27]
ODT0B -> ODT1: SDRAMs D[17:9]
ODT1B -> ODT1: SDRAMs D[26:18]
CK0 -> CK: SDRAMs D[8:0]
CK1 -> CK: SDRAMs D[35:27]
CK2 -> CK: SDRAMs D[17:9]
CK3 -> CK: SDRAMs D[26:18]
CK0
CK0
CK0 -> CK: SDRAMs D[8:0]
CK1 -> CK: SDRAMs D[35:27]
CK2 -> CK: SDRAMs D[17:9]
CK3 -> CK: SDRAMs D[26:18]
CK1
CK1
PAR_IN
RESET
Err_Out
QRESET: All SDRAMs
1. CK0 and CK0 are terminated with 120 Ohms ±5% resistor.
2. CK1 and CK1 are terminated with 120 Ohms ±5% resistor, but is not used.
3. Unless othersiwe noted resistors are 22 Ohms ±5%
Rev. 0.1 / Jun. 2013
12
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
Parameter
Voltage on VDD pin relative to Vss
Voltage on VDDQ pin relative to Vss
Voltage on any pin relative to Vss
Storage Temperature
Rating
Units
Notes
VDD
- 0.4 V ~ 1.80 V
V
1,3
VDDQ
VIN, VOUT
TSTG
- 0.4 V ~ 1.80 V
- 0.4 V ~ 1.80 V
-55 to +100
V
1,3
1
V
oC
1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
Parameter
Normal Operating Temperature Range
Extended Temperature Range
Rating
Units
oC
Notes
0 to 85
1,2
TOPER
85 to 95
oC
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).
DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the
DIMM SPD for tREFI requirements in the Extended Temperature Range
Rev. 0.1 / Jun. 2013
13
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Rating
Symbol
Parameter
Units
Notes
Min.
Typ.
Max.
VDD
1.283
1.35
1.45
V
V
1,2,3,4
1,2,3,4
Supply Voltage
Supply Voltage for Output
VDDQ
1.283
1.35
1.45
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - - DDR3 (1.5V) operation
Rating
Symbol
Parameter
Units
Notes
Min.
Typ.
Max.
VDD
1.425
1.5
1.575
V
V
1,2,3
1,2,3
Supply Voltage
Supply Voltage for Output
VDDQ
1.425
1.5
1.575
Notes:
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 0.1 / Jun. 2013
14
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
Tj
Tk
CK,CK#
tCKSRX
Tmin = 10ns
VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
Tmin = 10ns
Tmin = 200us
T = 500us
RESET#
Tmin = 10ns
CKE
VALID
VALID
tDLLK
tIS
tXPR
tMRD
tMRD
tMRD
tMOD
tZQinit
1)
COMMAND
BA
READ
READ
1)
MRS
MR2
MRS
MR3
MRS
MR1
MRS
MR0
ZQCL
VALID
tIS
tIS
ODT
RTT
READ
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
between MRS and ZQCL commands.
DON’T CARE
TIME BREAK
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
Rev. 0.1 / Jun. 2013
15
Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 20.
Speed Bin
DDR3-800E
6-6-6
Unit
Notes
CL - nRCD - nRP
Parameter
Symbol
min
max
tAA
15
20
—
—
—
ns
ns
ns
ns
ns
Internal read command to first data
ACT to internal read or write delay time
PRE command period
tRCD
15
15
tRP
tRC
52.5
ACT to ACT or REF command period
ACT to PRE command period
tRAS
37.5
2.5
9 * tREFI
3.3
tCK(AVG)
ns
CL = 6
CWL = 5
1,2,3
nCK
nCK
6
5
Supported CL Settings
Supported CWL Settings
Rev. 0.1 / Jun. 2013
16
DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 20.
Speed Bin
DDR3-1066F
7-7-7
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
max
Internal read command to
first data
tAA
13.125
20
ns
ns
ns
ns
ns
ACT to internal read or
write delay time
tRCD
13.125
13.125
50.625
—
—
—
tRP
PRE command period
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
37.5
2.5
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
CL = 6
ns
ns
1,2,3,6
1,2,3,4
4
CWL = 6
Reserved
Reserved
CWL = 5
CL = 7
ns
CWL = 6
1.875
1.875
< 2.5
< 2.5
ns
1,2,3,4
4
CWL = 5
CL = 8
Reserved
ns
CWL = 6
ns
1,2,3
nCK
nCK
Supported CL Settings
Supported CWL Settings
6, 7, 8
5, 6
Rev. 0.1 / Jun. 2013
17
DDR3-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 20.
Speed Bin
DDR3-1333H
9-9-9
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
13.5
max
Internal read
command to first data
tAA
tRCD
tRP
20
ns
ns
ns
ns
ns
(13.125)5,9
13.5
(13.125)5,9
ACT to internal read or
write delay time
—
—
—
13.5
(13.125)5,9
PRE command period
49.5
(49.125)5,9
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
36
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
2.5
ns
ns
ns
ns
1,2,3,7
CL = 6
CL = 7
CL = 8
CWL = 6
CWL = 7
CWL = 5
Reserved
Reserved
Reserved
1,2,3,4,7
4
4
1.875
1.875
< 2.5
< 2.5
tCK(AVG)
CWL = 6
ns
1,2,3,4,7
(Optional)5,9
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
CWL = 5
ns
ns
ns
ns
ns
ns
ns
1,2,3,4
4
Reserved
CWL = 6
1,2,3,7
1,2,3,4
4
CWL = 7
Reserved
Reserved
CWL = 5, 6
CWL = 7
CL = 9
1.5
1.5
<1.875
<1.875
1,2,3,4
4
CWL = 5, 6
Reserved
CL = 10
ns
ns
1,2,3
5
tCK(AVG)
CWL = 7
(Optional)
nCK
Supported CL Settings
Supported CWL Settings
6, 7, 8, 9, 10
nCK
5, 6, 7
Rev. 0.1 / Jun. 2013
18
DDR3-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 20.
Speed Bin
DDR3-1600K
11-11-11
Unit
Note
CL - nRCD - nRP
Parameter
Symbol
min
13.75
max
Internal read
command to first data
tAA
tRCD
tRP
20
ns
ns
ns
ns
ns
(13.125)5,9
13.75
(13.125)5,9
ACT to internal read or
write delay time
—
—
—
13.75
(13.125)5,9
PRE command period
48.75
(48.125)5,9
ACT to ACT or REF
command period
tRC
ACT to PRE command
period
tRAS
35
9 * tREFI
3.3
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 5
2.5
ns
ns
ns
ns
1,2,3,8
CL = 6
CWL = 6
CWL = 7
CWL = 5
Reserved
Reserved
Reserved
1,2,3,4,8
4
4
1.875
< 2.5
tCK(AVG)
CWL = 6
ns
1,2,3,4,8
(Optional)5,9
Reserved
Reserved
Reserved
CL = 7
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
ns
ns
ns
ns
ns
ns
ns
1,2,3,4,8
4
4
1.875
1.5
< 2.5
1,2,3,8
1,2,3,4,8
1,2,3,4
4
CL = 8
CL = 9
Reserved
Reserved
Reserved
<1.875
tCK(AVG)
CWL = 7
ns
1,2,3,4,8
(Optional)5,9
Reserved
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
CWL = 8
ns
ns
1,2,3,4
4
CWL = 5, 6
Reserved
CL = 10 CWL = 7
CWL = 8
1.5
<1.875
<1.5
ns
1,2,3,8
1,2,3,4
4
Reserved
Reserved
ns
CWL = 5, 6,7
CL = 11
ns
CWL = 8
1.25
ns
1,2,3
nCK
nCK
Supported CL Settings
Supported CWL Settings
5, 6, 7, 8, 9, 10, 11
5, 6, 7, 8
Rev. 0.1 / Jun. 2013
19
Speed Bin Table Notes
Absolute Specification (T
; V
= V = 1.35V +1.000/- 0.067 V);
OPER
DDQ DD
(T
; V
= V = 1.5V +/- 0.075 V);
DDQ DD
OPER
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-
ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require-
ments from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-
datory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is
supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must
be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
Rev. 0.1 / Jun. 2013
20
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
•
”0” and “LOW” is defined as VIN <= V
ILAC(max).
”1” and “HIGH” is defined as VIN >= V
IHAC(max).
•
•
•
•
•
“MID_LEVEL” is defined as inputs are VREF = VDD/2.
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
Basic IDD and IDDQ Measurement Conditions are described in Table 2.
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0 (Output Buffer enabled in MR1);
B
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
•
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 0.1 / Jun. 2013
21
IDDQ (optional)
IDD
VDD
RESET
CK/CK
VDDQ
DDR3(L)
SDRAM
RTT = 25 Ohm
CKE
CS
DQS, DQS
DQ, DM,
VDDQ/2
RAS, CAS, WE
TDQS, TDQS
A, BA
ODT
ZQ
VSS
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Application specific
memory channel
environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
Rev. 0.1 / Jun. 2013
22
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3-1066
DDR3-1333
DDR3-1600
Symbol
Unit
7-7-7
1.875
7
9-9-9
1.5
9
11-11-11
tCK
1.25
11
11
39
28
11
24
32
5
ns
CL
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nRCD
nRC
nRAS
nRP
7
9
27
20
7
33
24
9
1KB page size
2KB page size
1KB page size
2KB page size
20
27
4
20
30
4
nFAW
nRRD
6
5
6
nRFC -512Mb
nRFC-1 Gb
nRFC- 2 Gb
nRFC- 4 Gb
nRFC- 8 Gb
48
59
86
139
187
60
74
107
174
234
72
88
128
208
280
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-
IDD0
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
IDD1
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 0.1 / Jun. 2013
23
Symbol
Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
IDD2N
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
IDD2NT
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
IDD2P0
IDD2P1
IDD2Q
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
IDD3N
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 5.
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
IDD3P
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Rev. 0.1 / Jun. 2013
24
Symbol
Description
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
IDD4R
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
IDD4W
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
IDD5B
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
IDD6
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
IDD6ET
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Rev. 0.1 / Jun. 2013
25
Symbol
Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-
IDD7
ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 0.1 / Jun. 2013
26
a)
Table 3 - IDD0 Measurement-Loop Pattern
Datab)
0
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2
3,4
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE
0
0
1
0
0
0
00
0
0
0
0
-
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
1*nRC+1, 2
1*nRC+3, 4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE 00
1*nRC+nRAS
...
0
0
1
0
0
0
0
0
F
0
-
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 0.1 / Jun. 2013
27
a)
Table 4 - IDD1 Measurement-Loop Pattern
Datab)
0
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
0
1,2
3,4
...
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD 00
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRCD
...
0
1
0
1
0
0
0
0
0
0
0
0
00000000
-
nRAS
PRE
0
0
1
0
0
0
00
0
0
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
1*nRC+1,2
1*nRC+3,4
...
ACT
D, D
D, D
0
1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F
0
0
0
-
-
-
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
RD 00
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE 00
1*nRC+nRCD
...
0
1
0
1
0
0
0
0
F
0
00110011
-
1*nRC+nRAS
...
0
0
1
0
0
0
0
0
F
0
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
1
2
3
4
5
6
7
2*nRC
4*nRC
6*nRC
8*nRC
10*nRC
12*nRC
14*nRC
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
Rev. 0.1 / Jun. 2013
28
a)
Table 5 - IDD2N and IDD3N Measurement-Loop Pattern
Datab)
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
0
0
0
0
-
-
-
-
0
1
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
repeat Sub-Loop 0, use BA[2:0] = 2 instead
repeat Sub-Loop 0, use BA[2:0] = 3 instead
repeat Sub-Loop 0, use BA[2:0] = 4 instead
repeat Sub-Loop 0, use BA[2:0] = 5 instead
repeat Sub-Loop 0, use BA[2:0] = 6 instead
repeat Sub-Loop 0, use BA[2:0] = 7 instead
8-11
12-15
16-19
20-23
24-17
28-31
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
a)
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern
Datab)
0
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
0
1
0
F
F
0
0
0
2
3
1
2
3
4
5
6
7
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
8-11
12-15
16-19
20-23
24-17
28-31
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 0.1 / Jun. 2013
29
a)
Table 7 - IDD4R and IDDQ4R Measurement-Loop Pattern
Datab)
0
RD
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
0
1
-
2,3
D,D
RD
D
-
4
00110011
5
-
-
6,7
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
a)
Table 8 - IDD4W Measurement-Loop Pattern
Datab)
0
WR
D
D,D
WR
D
0
1
1
0
1
1
1
0
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
0
0
0
00000000
0
1
2,3
4
5
6,7
-
-
00110011
-
-
D,D
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
repeat Sub-Loop 0, but BA[2:0] = 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 0, but BA[2:0] = 3
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 0, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 0.1 / Jun. 2013
30
a)
Table 9 - IDD5B Measurement-Loop Pattern
Datab)
0
1
REF
D, D
D, D
0
1
1
0
0
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
0
0
0
-
-
-
0
1.2
00
00
3,4
5...8
repeat cycles 1...4, but BA[2:0] = 1
repeat cycles 1...4, but BA[2:0] = 2
repeat cycles 1...4, but BA[2:0] = 3
repeat cycles 1...4, but BA[2:0] = 4
repeat cycles 1...4, but BA[2:0] = 5
repeat cycles 1...4, but BA[2:0] = 6
repeat cycles 1...4, but BA[2:0] = 7
9...12
13...16
17...20
21...24
25...28
29...32
33...nRFC-1
2
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 0.1 / Jun. 2013
31
a)
Table 10 - IDD7 Measurement-Loop Pattern
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
Datab)
0
1
0
1
2
...
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
repeat above D Command until nRRD - 1
nRRD
nRRD+1
nRRD+2
...
2*nRRD
3*nRRD
4*nRRD
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
repeat above D Command until 2* nRRD - 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
2
3
D
1
0
0
0
0
3
00
0
0
F
0
0
-
-
4
Assert and repeat above D Command until nFAW - 1, if necessary
repeat Sub-Loop 0, but BA[2:0] = 4
repeat Sub-Loop 1, but BA[2:0] = 5
repeat Sub-Loop 0, but BA[2:0] = 6
repeat Sub-Loop 1, but BA[2:0] = 7
5
6
7
8
nFAW
nFAW+nRRD
nFAW+2*nRRD
nFAW+3*nRRD
nFAW+4*nRRD
D
1
0
0
0
0
7
00
0
0
F
9
Assert and repeat above D Command until 2* nFAW - 1, if necessary
2*nFAW+0
2*nFAW+1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
0
1
0
0
0
0
F
F
F
0
0
0
-
00110011
-
10
2&nFAW+2
Repeat above D Command until 2* nFAW + nRRD - 1
2*nFAW+nRRD
2*nFAW+nRRD+1
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
1
1
1
00
00
00
0
1
0
0
0
0
0
0
0
0
0
0
-
00000000
-
11
2&nFAW+nRRD+2
Repeat above D Command until 2* nFAW + 2* nRRD - 1
repeat Sub-Loop 10, but BA[2:0] = 2
repeat Sub-Loop 11, but BA[2:0] = 3
12 2*nFAW+2*nRRD
13 2*nFAW+3*nRRD
D
1
0
0
0
0
3
00
0
0
0
0
-
14 2*nFAW+4*nRRD
Assert and repeat above D Command until 3* nFAW - 1, if necessary
repeat Sub-Loop 10, but BA[2:0] = 4
15 3*nFAW
16 3*nFAW+nRRD
17 3*nFAW+2*nRRD
18 3*nFAW+3*nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
repeat Sub-Loop 10, but BA[2:0] = 6
repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
0
0
-
19 3*nFAW+4*nRRD
Assert and repeat above D Command until 4* nFAW - 1, if necessary
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 0.1 / Jun. 2013
32
IDD Specifications (Tcase: 0 to 95oC)
*Module IDD values in the datasheet are only a calculation based on the component IDD spec and register
power. The actual measurements may vary according to DQ loading cap.
64GB, 8G x 72 LR-DIMM: HMTA8GL7AHR4A
Symbol
IDD0
DDR3L 1333
10692
10818
10404
10980
1522
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
1984
1810
10548
11700
2818
11466
11556
2098
IDD6ET
IDD7
2674
12456
64GB, 8G x 72 LR-DIMM: HMTA8GL7AHR4C
Symbol
IDD0
DDR3 1600
11472
11616
11166
13038
2050
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
note
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
2338
11310
12606
3490
12498
12588
14388
2626
IDD6ET
IDD7
3202
14748
Rev. 0.1 / Jun. 2013
33
Module Dimensions
8Gx72 - HMTA8GL7AHR4A(C)
Front
133.35
128.95
Detail B
2.20
Detail A
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
Memory
Buffer
4X3.00±0.10
1
120
1
2X2.30±0.10
47.00
71.00
Detail D
5.175
5.0
Detail C
Back
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
121
240
1
Side
4.70mm max
Detail of Contacts D
Detail of Contacts A
Detail of Contacts B
Detail of Contacts C
1.45± 0.10
0.80± 0.05
2.50
10.00±
0.10
0.75
± 0.10
8.40
3
± 0.1
0.3~0.1
1.00
1.50
±0.10
5.00
1.27±010mm
max
Note:
1. 0.13tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 0.1 / Jun. 2013
34
8Gx72 - HMTA8GL7AHR4A(C) - Heat Spreader
Front
133.4
126.4
42.3
26.1
2.7
5.7
10.8
7.9
3.1
14
16
120
1
34
76.6
69.25
119.2
Back
120
1
Side
7.90mm max
1.27±010mm
Note:
max
1. 0.13tolerance on all dimensions unless otherwise stated.
2.In order to uninstall FDHS, please contact sales administrator.
Units: millimeters
Rev. 0.1 / Jun. 2013
35
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